tree f6ae8646f59090ef368a2df99d0f01084f84ff6d
parent 904b2e2e882e1d6f01fc5ff2061fd809b048b7bd
author Jit Loon Lim <jit.loon.lim@intel.com> 1684297571 +0800
committer Jit Loon Lim <jit.loon.lim@intel.com> 1688519301 +0800

feat(intel): clock manager support for Agilex5 SoC FPGA

This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
	1. Added clock manager support.
	2. Updated product name -> Agilex5
	3. Updated register address based on y22ww52.2 RTL
	4. Standardized handoff handler.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b