Merge pull request #1333 from jeenu-arm/icfg-fix
GIC: Fix interrupt setting interrupt configuration
diff --git a/Makefile b/Makefile
index 94ae63e..ca91e69 100644
--- a/Makefile
+++ b/Makefile
@@ -275,13 +275,6 @@
endif
################################################################################
-# Include libraries' Makefile that are used in all BL
-################################################################################
-
-include lib/stack_protector/stack_protector.mk
-
-
-################################################################################
# Include the platform specific Makefile after the SPD Makefile (the platform
# makefile may use all previous definitions in this file)
################################################################################
@@ -441,6 +434,12 @@
endif
################################################################################
+# Include libraries' Makefile that are used in all BL
+################################################################################
+
+include lib/stack_protector/stack_protector.mk
+
+################################################################################
# Auxiliary tools (fiptool, cert_create, etc)
################################################################################
diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h
index 6ac3b8c..42a74d2 100644
--- a/bl1/bl1_private.h
+++ b/bl1/bl1_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,18 +8,16 @@
#define __BL1_PRIVATE_H__
#include <types.h>
+#include <utils_def.h>
/*******************************************************************************
* Declarations of linker defined symbols which will tell us where BL1 lives
* in Trusted ROM and RAM
******************************************************************************/
-extern uintptr_t __BL1_ROM_END__;
-#define BL1_ROM_END (uintptr_t)(&__BL1_ROM_END__)
+IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END);
-extern uintptr_t __BL1_RAM_START__;
-extern uintptr_t __BL1_RAM_END__;
-#define BL1_RAM_BASE (uintptr_t)(&__BL1_RAM_START__)
-#define BL1_RAM_LIMIT (uintptr_t)(&__BL1_RAM_END__)
+IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
+IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT);
/******************************************
* Function prototypes
diff --git a/common/runtime_svc.c b/common/runtime_svc.c
index 0ea4cd0..de80f30 100644
--- a/common/runtime_svc.c
+++ b/common/runtime_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,8 +19,6 @@
* 'rt_svc_descs_indices' array. This gives the index of the descriptor in the
* 'rt_svc_descs' array which contains the SMC handler.
******************************************************************************/
-#define RT_SVC_DESCS_START ((uintptr_t) (&__RT_SVC_DESCS_START__))
-#define RT_SVC_DESCS_END ((uintptr_t) (&__RT_SVC_DESCS_END__))
uint8_t rt_svc_descs_indices[MAX_RT_SVCS];
static rt_svc_desc_t *rt_svc_descs;
diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst
index c30110e..b7879a8 100644
--- a/docs/plat/rpi3.rst
+++ b/docs/plat/rpi3.rst
@@ -247,6 +247,11 @@
- ``LOAD_IMAGE_V2=0``: Only version 2 is supported.
+- ``MULTI_CONSOLE_API=0``: The multi console API must be enabled. Note that the
+ crash console uses the internal 16550 driver functions directly in order to be
+ able to print error messages during early crashes before setting up the
+ multi console API.
+
AArch64 kernel build instructions
---------------------------------
@@ -300,7 +305,7 @@
The instructions assume that you have an SD card with a fresh install of
`Raspbian`_ (or that, at least, the ``boot`` partition is untouched, or nearly
-untouched). They have been tested with the image available in 2017-09-07.
+untouched). They have been tested with the image available in 2018-03-13.
1. Insert the SD card and open the ``boot`` partition.
diff --git a/drivers/auth/img_parser_mod.c b/drivers/auth/img_parser_mod.c
index 6a01071..6316014 100644
--- a/drivers/auth/img_parser_mod.c
+++ b/drivers/auth/img_parser_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,11 +12,10 @@
#include <limits.h>
#include <stdint.h>
#include <string.h>
+#include <utils_def.h>
-extern uintptr_t __PARSER_LIB_DESCS_START__;
-extern uintptr_t __PARSER_LIB_DESCS_END__;
-#define PARSER_LIB_DESCS_START ((uintptr_t) (&__PARSER_LIB_DESCS_START__))
-#define PARSER_LIB_DESCS_END ((uintptr_t) (&__PARSER_LIB_DESCS_END__))
+IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_START__, PARSER_LIB_DESCS_START);
+IMPORT_SYM(uintptr_t, __PARSER_LIB_DESCS_END__, PARSER_LIB_DESCS_END);
static unsigned int parser_lib_indices[IMG_MAX_TYPES];
static img_parser_lib_desc_t *parser_lib_descs;
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S
index b02209d..56e7e5c 100644
--- a/drivers/ti/uart/aarch64/16550_console.S
+++ b/drivers/ti/uart/aarch64/16550_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,10 +17,11 @@
.globl console_16550_core_init
.globl console_16550_core_putc
.globl console_16550_core_getc
+ .globl console_16550_core_flush
.globl console_16550_putc
.globl console_16550_getc
-
+ .globl console_16550_flush
/* -----------------------------------------------
* int console_16550_core_init(uintptr_t base_addr,
@@ -119,6 +120,7 @@
.equ console_core_init,console_16550_core_init
.equ console_core_putc,console_16550_core_putc
.equ console_core_getc,console_16550_core_getc
+ .equ console_core_flush,console_16550_core_flush
#endif
/* --------------------------------------------------------
@@ -222,8 +224,7 @@
endfunc console_16550_getc
/* ---------------------------------------------
- * int console_core_flush(uintptr_t base_addr)
- * DEPRECATED: Not used with MULTI_CONSOLE_API!
+ * int console_16550_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
@@ -231,8 +232,36 @@
* Clobber list : x0, x1
* ---------------------------------------------
*/
-func console_core_flush
- /* Placeholder */
+func console_16550_core_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+
+ /* Loop until the transmit FIFO is empty */
+1: ldr w1, [x0, #UARTLSR]
+ and w1, w1, #(UARTLSR_TEMT | UARTLSR_THRE)
+ cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE)
+ b.ne 1b
+
mov w0, #0
ret
-endfunc console_core_flush
+endfunc console_16550_core_flush
+
+ /* ---------------------------------------------
+ * int console_16550_flush(console_pl011_t *console)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - pointer to console_t structure
+ * Out : return -1 on error else return 0.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_16550_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ ldr x0, [x0, #CONSOLE_T_16550_BASE]
+ b console_16550_core_flush
+endfunc console_16550_flush
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 4ef916f..09a394d 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -64,33 +64,41 @@
#include <types.h>
#include <utils_def.h> /* To retain compatibility */
+
/*
* Declarations of linker defined symbols to help determine memory layout of
* BL images
*/
#if SEPARATE_CODE_AND_RODATA
-extern uintptr_t __TEXT_START__;
-extern uintptr_t __TEXT_END__;
-extern uintptr_t __RODATA_START__;
-extern uintptr_t __RODATA_END__;
+IMPORT_SYM(unsigned long, __TEXT_START__, BL_CODE_BASE);
+IMPORT_SYM(unsigned long, __TEXT_END__, BL_CODE_END);
+IMPORT_SYM(unsigned long, __RODATA_START__, BL_RO_DATA_BASE);
+IMPORT_SYM(unsigned long, __RODATA_END__, BL_RO_DATA_END);
#else
-extern uintptr_t __RO_START__;
-extern uintptr_t __RO_END__;
+IMPORT_SYM(unsigned long, __RO_START__, BL_CODE_BASE);
+IMPORT_SYM(unsigned long, __RO_END__, BL_CODE_END);
#endif
#if defined(IMAGE_BL2)
-extern uintptr_t __BL2_END__;
+IMPORT_SYM(unsigned long, __BL2_END__, BL2_END);
#elif defined(IMAGE_BL2U)
-extern uintptr_t __BL2U_END__;
+IMPORT_SYM(unsigned long, __BL2U_END__, BL2U_END);
#elif defined(IMAGE_BL31)
-extern uintptr_t __BL31_END__;
+IMPORT_SYM(unsigned long, __BL31_END__, BL31_END);
#elif defined(IMAGE_BL32)
-extern uintptr_t __BL32_END__;
+IMPORT_SYM(unsigned long, __BL32_END__, BL32_END);
#endif /* IMAGE_BLX */
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned. It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
+ * page-aligned addresses.
+ */
#if USE_COHERENT_MEM
-extern uintptr_t __COHERENT_RAM_START__;
-extern uintptr_t __COHERENT_RAM_END__;
+IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE);
+IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL_COHERENT_RAM_END);
#endif
/*******************************************************************************
diff --git a/include/common/runtime_svc.h b/include/common/runtime_svc.h
index d12af22..5d9fa39 100644
--- a/include/common/runtime_svc.h
+++ b/include/common/runtime_svc.h
@@ -122,8 +122,8 @@
void runtime_svc_init(void);
uintptr_t handle_runtime_svc(uint32_t smc_fid, void *cookie, void *handle,
unsigned int flags);
-extern uintptr_t __RT_SVC_DESCS_START__;
-extern uintptr_t __RT_SVC_DESCS_END__;
+IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_START__, RT_SVC_DESCS_START);
+IMPORT_SYM(uintptr_t, __RT_SVC_DESCS_END__, RT_SVC_DESCS_END);
void init_crash_reporting(void);
extern uint8_t rt_svc_descs_indices[MAX_RT_SVCS];
diff --git a/include/drivers/console.h b/include/drivers/console.h
index f8ec83d..c8a43a2 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -66,6 +66,8 @@
/* REMOVED on AArch64 -- use console_<driver>_register() instead! */
int console_init(uintptr_t base_addr,
unsigned int uart_clk, unsigned int baud_rate);
+int console_core_init(uintptr_t base_addr,
+ unsigned int uart_clk, unsigned int baud_rate);
void console_uninit(void);
#endif
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 4a5c3e0..8abc73c 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -99,4 +99,21 @@
((ARM_ARCH_MAJOR > _maj) || \
((ARM_ARCH_MAJOR == _maj) && (ARM_ARCH_MINOR >= _min)))
+/*
+ * Import an assembly or linker symbol as a C expression with the specified
+ * type
+ */
+#define IMPORT_SYM(type, sym, name) \
+ extern char sym[];\
+ static const __attribute__((unused)) type name = (type) sym;
+
+/*
+ * When the symbol is used to hold a pointer, its alignment can be asserted
+ * with this macro. For example, if there is a linker symbol that is going to
+ * be used as a 64-bit pointer, the value of the linker symbol must also be
+ * aligned to 64 bit. This macro makes sure this is the case.
+ */
+#define ASSERT_SYM_PTR_ALIGN(sym) assert(((size_t)(sym) % __alignof__(*(sym))) == 0)
+
+
#endif /* __UTILS_DEF_H__ */
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index a841c3d..84923b9 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -74,33 +74,13 @@
* page of it with the right memory attributes.
*/
#if SEPARATE_CODE_AND_RODATA
-#define BL_CODE_BASE (unsigned long)(&__TEXT_START__)
-#define BL_CODE_END (unsigned long)(&__TEXT_END__)
-#define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__)
-#define BL_RO_DATA_END (unsigned long)(&__RODATA_END__)
#define BL1_CODE_END BL_CODE_END
-#define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__)
+#define BL1_RO_DATA_BASE BL_RO_DATA_BASE
#define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE)
#else
-#define BL_CODE_BASE (unsigned long)(&__RO_START__)
-#define BL_CODE_END (unsigned long)(&__RO_END__)
#define BL_RO_DATA_BASE 0
#define BL_RO_DATA_END 0
-
#define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE)
-#define BL1_RO_DATA_BASE 0
-#define BL1_RO_DATA_END 0
#endif /* SEPARATE_CODE_AND_RODATA */
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL_COHERENT_RAM_END (unsigned long)(&__COHERENT_RAM_END__)
-
#endif /* __COMMON_DEF_H__ */
diff --git a/include/services/secure_partition.h b/include/services/secure_partition.h
index 93df2a1..f68f711 100644
--- a/include/services/secure_partition.h
+++ b/include/services/secure_partition.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,15 +11,11 @@
#include <types.h>
#include <utils_def.h>
-/* Linker symbols */
-extern uintptr_t __SP_IMAGE_XLAT_TABLES_START__;
-extern uintptr_t __SP_IMAGE_XLAT_TABLES_END__;
+/* Import linker symbols */
+IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_START__, SP_IMAGE_XLAT_TABLES_START);
+IMPORT_SYM(uintptr_t, __SP_IMAGE_XLAT_TABLES_END__, SP_IMAGE_XLAT_TABLES_END);
/* Definitions */
-#define SP_IMAGE_XLAT_TABLES_START \
- (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_START__)
-#define SP_IMAGE_XLAT_TABLES_END \
- (uintptr_t)(&__SP_IMAGE_XLAT_TABLES_END__)
#define SP_IMAGE_XLAT_TABLES_SIZE \
(SP_IMAGE_XLAT_TABLES_END - SP_IMAGE_XLAT_TABLES_START)
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 8f59215..37697f5 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <cpu_data.h>
#include <platform.h>
#include <string.h>
+#include <utils_def.h>
/*
* Functions in this file implement Bakery Algorithm for mutual exclusion with the
@@ -49,8 +50,7 @@
* Use the linker defined symbol which has evaluated the size reqiurement.
* This is not as efficient as using a platform defined constant
*/
-extern void *__PERCPU_BAKERY_LOCK_SIZE__;
-#define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__)
+IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE);
#endif
#define get_bakery_info(cpu_ix, lock) \
diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c
index 2cf260e..0208948 100644
--- a/lib/pmf/pmf_main.c
+++ b/lib/pmf/pmf_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <platform.h>
#include <pmf.h>
#include <string.h>
+#include <utils_def.h>
/*******************************************************************************
* The 'pmf_svc_descs' array holds the PMF service descriptors exported by
@@ -21,16 +22,12 @@
* index of the descriptor in the 'pmf_svc_descs' array which contains the
* service function pointers.
******************************************************************************/
-extern uintptr_t __PMF_SVC_DESCS_START__;
-extern uintptr_t __PMF_SVC_DESCS_END__;
-#define PMF_SVC_DESCS_START ((uintptr_t)(&__PMF_SVC_DESCS_START__))
-#define PMF_SVC_DESCS_END ((uintptr_t)(&__PMF_SVC_DESCS_END__))
-extern void *__PERCPU_TIMESTAMP_SIZE__;
-#define PMF_PERCPU_TIMESTAMP_SIZE ((uintptr_t)&__PERCPU_TIMESTAMP_SIZE__)
-extern uintptr_t __PMF_TIMESTAMP_START__;
-#define PMF_TIMESTAMP_ARRAY_START ((uintptr_t)&__PMF_TIMESTAMP_START__)
-extern uintptr_t __PMF_TIMESTAMP_END__;
-#define PMF_TIMESTAMP_ARRAY_END ((uintptr_t)&__PMF_TIMESTAMP_END__)
+
+IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_START__, PMF_SVC_DESCS_START);
+IMPORT_SYM(uintptr_t, __PMF_SVC_DESCS_END__, PMF_SVC_DESCS_END);
+IMPORT_SYM(uintptr_t, __PERCPU_TIMESTAMP_SIZE__, PMF_PERCPU_TIMESTAMP_SIZE);
+IMPORT_SYM(intptr_t, __PMF_TIMESTAMP_START__, PMF_TIMESTAMP_ARRAY_START);
+IMPORT_SYM(uintptr_t, __PMF_TIMESTAMP_END__, PMF_TIMESTAMP_ARRAY_END);
#define PMF_SVC_DESCS_MAX 10
diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c
index 3e79c5d..e925d34 100644
--- a/lib/psci/psci_stat.c
+++ b/lib/psci/psci_stat.c
@@ -24,7 +24,8 @@
* Following is used to keep track of the last cpu
* that goes to power down in non cpu power domains.
*/
-static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1};
+static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {
+ [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS-1] = -1};
/*
* Following are used to store PSCI STAT values for
@@ -129,6 +130,10 @@
* prior to this CPU powering on.
*/
parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
+ /* Return early if this is the first power up. */
+ if (last_cpu_in_non_cpu_pd[parent_idx] == -1)
+ return;
+
for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
local_state = state_info->pwr_domain_state[lvl];
if (is_local_state_run(local_state)) {
diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c
index f95af58..658760b 100644
--- a/plat/hisilicon/hikey/aarch64/hikey_common.c
+++ b/plat/hisilicon/hikey/aarch64/hikey_common.c
@@ -9,13 +9,12 @@
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
+#include <hikey_def.h>
+#include <hikey_layout.h>
#include <mmio.h>
#include <platform.h>
-#include <platform_def.h>
#include <xlat_tables.h>
-#include "../hikey_def.h"
-
#define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
DDR_SIZE - DDR_SEC_SIZE, \
MT_DEVICE | MT_RW | MT_NS)
diff --git a/plat/hisilicon/hikey/aarch64/hikey_helpers.S b/plat/hisilicon/hikey/aarch64/hikey_helpers.S
index 680c0a1..32ff8b4 100644
--- a/plat/hisilicon/hikey/aarch64/hikey_helpers.S
+++ b/plat/hisilicon/hikey/aarch64/hikey_helpers.S
@@ -1,12 +1,12 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
-#include "../hikey_def.h"
+#include <hikey_def.h>
.globl plat_my_core_pos
.globl platform_mem_init
diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c
index 69b194a..28ad9df 100644
--- a/plat/hisilicon/hikey/hikey_bl1_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl1_setup.c
@@ -13,33 +13,16 @@
#include <emmc.h>
#include <errno.h>
#include <hi6220.h>
+#include <hikey_def.h>
+#include <hikey_layout.h>
#include <mmio.h>
#include <platform.h>
-#include <platform_def.h>
#include <string.h>
#include <tbbr/tbbr_img_desc.h>
#include "../../bl1/bl1_private.h"
-#include "hikey_def.h"
#include "hikey_private.h"
-/*
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted RAM
- */
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
@@ -103,8 +86,8 @@
bl1_tzram_layout.total_size,
BL1_RO_BASE,
BL1_RO_LIMIT,
- BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
/*
diff --git a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
index 7c025c3..23c16ed 100644
--- a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
+++ b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
@@ -7,7 +7,7 @@
#include <bl_common.h>
#include <desc_image_load.h>
#include <platform.h>
-#include <platform_def.h>
+#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
/*******************************************************************************
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index 20bb752..8bb2824 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -21,10 +21,9 @@
#include <optee_utils.h>
#endif
#include <platform.h>
-#include <platform_def.h>
+#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
#include <string.h>
-#include "hikey_def.h"
#include "hikey_private.h"
/*
diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c
index e13ecf6..a193b5a 100644
--- a/plat/hisilicon/hikey/hikey_bl31_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl31_setup.c
@@ -14,12 +14,12 @@
#include <errno.h>
#include <gicv2.h>
#include <hi6220.h>
+#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <mmio.h>
#include <platform_def.h>
-#include "hikey_def.h"
#include "hikey_private.h"
/*
diff --git a/plat/hisilicon/hikey/hikey_pm.c b/plat/hisilicon/hikey/hikey_pm.c
index d4dd683..3128a3d 100644
--- a/plat/hisilicon/hikey/hikey_pm.c
+++ b/plat/hisilicon/hikey/hikey_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <debug.h>
#include <gicv2.h>
#include <hi6220.h>
+#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <hisi_sram_map.h>
@@ -17,8 +18,6 @@
#include <psci.h>
#include <sp804_delay_timer.h>
-#include "hikey_def.h"
-
#define CORE_PWR_STATE(state) \
((state)->pwr_domain_state[MPIDR_AFFLVL0])
#define CLUSTER_PWR_STATE(state) \
diff --git a/plat/hisilicon/hikey/hikey_def.h b/plat/hisilicon/hikey/include/hikey_def.h
similarity index 88%
rename from plat/hisilicon/hikey/hikey_def.h
rename to plat/hisilicon/hikey/include/hikey_def.h
index 668b459..deb375d 100644
--- a/plat/hisilicon/hikey/hikey_def.h
+++ b/plat/hisilicon/hikey/include/hikey_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,9 +7,6 @@
#ifndef __HIKEY_DEF_H__
#define __HIKEY_DEF_H__
-#include <common_def.h>
-#include <tbbr_img_def.h>
-
/* Always assume DDR is 1GB size. */
#define DDR_BASE 0x0
#define DDR_SIZE 0x40000000
@@ -17,9 +14,6 @@
#define DEVICE_BASE 0xF4000000
#define DEVICE_SIZE 0x05800000
-#define XG2RAM0_BASE 0xF9800000
-#define XG2RAM0_SIZE 0x00400000
-
/* Memory location options for TSP */
#define HIKEY_SRAM_ID 0
#define HIKEY_DRAM_ID 1
@@ -43,13 +37,6 @@
#define SRAM_SIZE 0x00012000
/*
- * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
- */
-#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
-#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
-#define BL1_XG2RAM0_OFFSET 0x1000
-
-/*
* PL011 related constants
*/
#define PL011_UART0_BASE 0xF8015000
diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h
new file mode 100644
index 0000000..637a1c9
--- /dev/null
+++ b/plat/hisilicon/hikey/include/hikey_layout.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HIKEY_LAYOUT_H
+#define __HIKEY_LAYOUT_H
+
+/*
+ * Platform memory map related constants
+ */
+#define XG2RAM0_BASE 0xF9800000
+#define XG2RAM0_SIZE 0x00400000
+
+/*
+ * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
+ */
+#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
+#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
+#define BL1_XG2RAM0_OFFSET 0x1000
+
+/*
+ * BL1 specific defines.
+ *
+ * Both loader and BL1_RO region stay in SRAM since they are used to simulate
+ * ROM.
+ * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
+ *
+ * ++++++++++ 0xF980_0000
+ * + loader +
+ * ++++++++++ 0xF980_1000
+ * + BL1_RO +
+ * ++++++++++ 0xF981_0000
+ * + BL1_RW +
+ * ++++++++++ 0xF989_8000
+ */
+#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
+#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
+#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
+#define BL1_RW_SIZE (0x00088000)
+#define BL1_RW_LIMIT (0xF9898000)
+
+/*
+ * Non-Secure BL1U specific defines.
+ */
+#define NS_BL1U_BASE (0xf9818000)
+#define NS_BL1U_SIZE (0x00010000)
+#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
+
+/*
+ * BL2 specific defines.
+ *
+ * Both loader and BL2 region stay in SRAM.
+ * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
+ *
+ * ++++++++++ 0xF980_0000
+ * + loader +
+ * ++++++++++ 0xF980_1000
+ * + BL2 +
+ * ++++++++++ 0xF981_8000
+ */
+#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
+#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
+
+/*
+ * SCP_BL2 specific defines.
+ * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
+ * at 0x0100_0000. Then BL2 will parse the sections and loaded them into
+ * predefined separated buffers.
+ */
+#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
+#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
+#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
+
+/*
+ * BL31 specific defines.
+ */
+#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
+#define BL31_LIMIT (0xF9898000)
+
+/*
+ * BL3-2 specific defines.
+ */
+
+/*
+ * The TSP currently executes from TZC secured area of DRAM or SRAM.
+ */
+#define BL32_SRAM_BASE BL31_LIMIT
+#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
+
+#define BL32_DRAM_BASE DDR_SEC_BASE
+#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
+
+#ifdef SPD_opteed
+/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
+#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
+#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
+#endif
+
+#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
+#define BL32_BASE BL32_DRAM_BASE
+#define BL32_LIMIT BL32_DRAM_LIMIT
+#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
+#define BL32_BASE BL32_SRAM_BASE
+#define BL32_LIMIT BL32_SRAM_LIMIT
+#else
+#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
+#endif
+
+/* BL32 is mandatory in AArch32 */
+#ifndef AARCH32
+#ifdef SPD_none
+#undef BL32_BASE
+#endif /* SPD_none */
+#endif
+
+#endif /* !__HIKEY_LAYOUT_H */
diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h
index 9b4f463..8c56004 100644
--- a/plat/hisilicon/hikey/include/platform_def.h
+++ b/plat/hisilicon/hikey/include/platform_def.h
@@ -8,7 +8,10 @@
#define __PLATFORM_DEF_H__
#include <arch.h>
-#include "../hikey_def.h"
+#include <common_def.h>
+#include <hikey_def.h>
+#include <hikey_layout.h> /* BL memory region sizes, etc */
+#include <tbbr_img_def.h>
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
@@ -27,7 +30,7 @@
#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
-#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1)
@@ -45,114 +48,6 @@
#define PLAT_ARM_GICH_BASE 0xF6804000
#define PLAT_ARM_GICV_BASE 0xF6806000
-
-/*
- * Platform memory map related constants
- */
-
-/*
- * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
- */
-#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
-#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
-#define BL1_XG2RAM0_OFFSET 0x1000
-
-/*
- * BL1 specific defines.
- *
- * Both loader and BL1_RO region stay in SRAM since they are used to simulate
- * ROM.
- * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
- *
- * ++++++++++ 0xF980_0000
- * + loader +
- * ++++++++++ 0xF980_1000
- * + BL1_RO +
- * ++++++++++ 0xF981_0000
- * + BL1_RW +
- * ++++++++++ 0xF989_8000
- */
-#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
-#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
-#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
-#define BL1_RW_SIZE (0x00088000)
-#define BL1_RW_LIMIT (0xF9898000)
-
-/*
- * BL2 specific defines.
- *
- * Both loader and BL2 region stay in SRAM.
- * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
- *
- * ++++++++++ 0xF980_0000
- * + loader +
- * ++++++++++ 0xF980_1000
- * + BL2 +
- * ++++++++++ 0xF981_8000
- */
-#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
-#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
-
-/*
- * SCP_BL2 specific defines.
- * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
- * at 0x0100_0000. Then BL2 will parse the sections and loaded them into
- * predefined separated buffers.
- */
-#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
-#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
-#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
-
-/*
- * BL31 specific defines.
- */
-#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
-#define BL31_LIMIT (0xF9898000)
-
-/*
- * BL3-2 specific defines.
- */
-
-/*
- * The TSP currently executes from TZC secured area of DRAM or SRAM.
- */
-#define BL32_SRAM_BASE BL31_LIMIT
-#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
-
-#define BL32_DRAM_BASE DDR_SEC_BASE
-#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
-
-#ifdef SPD_opteed
-/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
-#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
-#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
-#endif
-
-#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
-#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
-#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
-#define BL32_BASE BL32_DRAM_BASE
-#define BL32_LIMIT BL32_DRAM_LIMIT
-#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
-#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
-#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
-#define BL32_BASE BL32_SRAM_BASE
-#define BL32_LIMIT BL32_SRAM_LIMIT
-#else
-#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
-#endif
-
-/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
-#ifdef SPD_none
-#undef BL32_BASE
-#endif /* SPD_none */
-#endif
-
-#define NS_BL1U_BASE (0xf9818000)
-#define NS_BL1U_SIZE (0x00010000)
-#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
-
/*
* Platform specific page table and MMU setup constants
*/
@@ -172,8 +67,6 @@
#define MAX_MMAP_REGIONS 16
-#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
-
/*
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
index 9cadba0..6a07f09 100644
--- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
@@ -37,18 +37,6 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted RAM
*/
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
- * page-aligned addresses.
- */
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
@@ -131,8 +119,8 @@
bl1_tzram_layout.total_size,
BL1_RO_BASE,
BL1_RO_LIMIT,
- BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
static void hikey960_ufs_reset(void)
diff --git a/plat/hisilicon/hikey960/hikey960_pm.c b/plat/hisilicon/hikey960/hikey960_pm.c
index 22963c4..ffe7fcf 100644
--- a/plat/hisilicon/hikey960/hikey960_pm.c
+++ b/plat/hisilicon/hikey960/hikey960_pm.c
@@ -9,6 +9,7 @@
#include <cci.h>
#include <console.h>
#include <debug.h>
+#include <delay_timer.h>
#include <gicv2.h>
#include <hi3660.h>
#include <hi3660_crg.h>
@@ -114,6 +115,9 @@
static void __dead2 hikey960_system_reset(void)
{
+ dsb();
+ isb();
+ mdelay(2000);
mmio_write_32(SCTRL_SCPEREN1_REG,
SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS);
mmio_write_32(SCTRL_SCSYSSTAT_REG, 0xdeadbeef);
diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c
index 3955113..25eed59 100644
--- a/plat/hisilicon/poplar/bl1_plat_setup.c
+++ b/plat/hisilicon/poplar/bl1_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,13 +23,6 @@
#include "hi3798cv200.h"
#include "plat_private.h"
-/* Symbols from link script for conherent section */
-extern unsigned long __COHERENT_RAM_START__;
-extern unsigned long __COHERENT_RAM_END__;
-
-#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
@@ -92,8 +85,8 @@
bl1_tzram_layout.total_size,
BL1_RO_BASE, /* l-loader and BL1 ROM */
BL1_RO_LIMIT,
- BL1_COHERENT_RAM_BASE,
- BL1_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}
void bl1_platform_setup(void)
diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c
index 803f1ed..32f0157 100644
--- a/plat/mediatek/mt6795/bl31_plat_setup.c
+++ b/plat/mediatek/mt6795/bl31_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,22 +21,21 @@
#include <plat_private.h>
#include <platform.h>
#include <string.h>
+#include <utils_def.h>
#include <xlat_tables.h>
+
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
-unsigned long __RO_START__;
-unsigned long __RO_END__;
-
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
+IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE);
+IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT);
/*
* Placeholder variables for copying the arguments that have been passed to
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index 7b29307..e51bdbb 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,24 +17,6 @@
#include <platform.h>
#include <spm.h>
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-unsigned long __RO_START__;
-unsigned long __RO_END__;
-
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL31 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-#define BL31_END (unsigned long)(&__BL31_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
@@ -156,10 +138,10 @@
plat_cci_init();
plat_cci_enable();
- plat_configure_mmu_el3(BL31_RO_BASE,
- BL_COHERENT_RAM_END - BL31_RO_BASE,
- BL31_RO_BASE,
- BL31_RO_LIMIT,
+ plat_configure_mmu_el3(BL_CODE_BASE,
+ BL_COHERENT_RAM_END - BL_CODE_BASE,
+ BL_CODE_BASE,
+ BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index d89ad7b..2fe4e7d 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,6 +23,7 @@
#include <string.h>
#include <tegra_def.h>
#include <tegra_private.h>
+#include <utils_def.h>
/* length of Trusty's input parameters (in bytes) */
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
@@ -33,29 +34,17 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
-extern unsigned long __TEXT_START__;
-extern unsigned long __TEXT_END__;
-extern unsigned long __RW_START__;
-extern unsigned long __RW_END__;
-extern unsigned long __RODATA_START__;
-extern unsigned long __RODATA_END__;
-extern unsigned long __BL31_END__;
+
+IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
+IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
+IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE);
+IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END);
+IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START);
+IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END);
extern uint64_t tegra_bl31_phys_base;
extern uint64_t tegra_console_base;
-/*
- * The next 3 constants identify the extents of the code, RO data region and the
- * limit of the BL3-1 image. These addresses are used by the MMU setup code and
- * therefore they must be page-aligned. It is the responsibility of the linker
- * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_RW_START (unsigned long)(&__RW_START__)
-#define BL31_RW_END (unsigned long)(&__RW_END__)
-#define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__)
-#define BL31_RODATA_END (unsigned long)(&__RODATA_END__)
-#define BL31_END (unsigned long)(&__BL31_END__)
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
@@ -311,8 +300,8 @@
unsigned long rw_size = BL31_RW_END - BL31_RW_START;
unsigned long rodata_start = BL31_RODATA_BASE;
unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
- unsigned long code_base = (unsigned long)(&__TEXT_START__);
- unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base;
+ unsigned long code_base = TEXT_START;
+ unsigned long code_size = TEXT_END - TEXT_START;
const mmap_region_t *plat_mmio_map = NULL;
#if USE_COHERENT_MEM
unsigned long coh_start, coh_size;
diff --git a/plat/qemu/include/platform_def.h b/plat/qemu/include/platform_def.h
index f8764fb..2f2ca6f 100644
--- a/plat/qemu/include/platform_def.h
+++ b/plat/qemu/include/platform_def.h
@@ -75,7 +75,7 @@
#define NS_DRAM0_SIZE 0x3de00000
#define SEC_SRAM_BASE 0x0e000000
-#define SEC_SRAM_SIZE 0x00040000
+#define SEC_SRAM_SIZE 0x00060000
#define SEC_DRAM_BASE 0x0e100000
#define SEC_DRAM_SIZE 0x00f00000
@@ -123,7 +123,7 @@
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
-#define BL2_BASE (BL31_BASE - 0x1D000)
+#define BL2_BASE (BL31_BASE - 0x25000)
#define BL2_LIMIT BL31_BASE
/*
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index a9fbcd7..379ab3d 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -169,7 +169,16 @@
endif
SEPARATE_CODE_AND_RODATA := 1
-MULTI_CONSOLE_API := 1
+ENABLE_STACK_PROTECTOR := 0
+ifneq ($(ENABLE_STACK_PROTECTOR), 0)
+ PLAT_BL_COMMON_SOURCES += plat/qemu/qemu_stack_protector.c
+endif
+
+# Use MULTI_CONSOLE_API by default only on AArch64
+# as it is not yet supported on AArch32
+ifeq ($(ARCH),aarch64)
+MULTI_CONSOLE_API := 1
+endif
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
diff --git a/plat/qemu/qemu_console.c b/plat/qemu/qemu_console.c
index 9c02957..1cf84aa 100644
--- a/plat/qemu/qemu_console.c
+++ b/plat/qemu/qemu_console.c
@@ -7,8 +7,10 @@
#include <pl011.h>
#include <platform_def.h>
+#if MULTI_CONSOLE_API
static console_pl011_t console;
static console_pl011_t crash_console;
+#endif /* MULTI_CONSOLE_API */
void qemu_console_init(void)
{
diff --git a/plat/qemu/qemu_stack_protector.c b/plat/qemu/qemu_stack_protector.c
new file mode 100644
index 0000000..5b19828
--- /dev/null
+++ b/plat/qemu/qemu_stack_protector.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <platform.h>
+#include <stdint.h>
+
+#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+ /*
+ * Ideally, a random number should be returned instead of the
+ * combination of a timer's value and a compile-time constant.
+ * As the virt platform does not have any random number generator,
+ * this is better than nothing but not necessarily really secure.
+ */
+ return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
+}
+
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index 6199eda..e5ee68f 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,21 +17,14 @@
#include <platform_def.h>
#include <uart_16550.h>
-/*******************************************************************************
- * Declarations of linker defined symbols which will help us find the layout
- * of trusted SRAM
- ******************************************************************************/
-unsigned long __RO_START__;
-unsigned long __RO_END__;
-
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
-#define BL31_RO_BASE (unsigned long)(&__RO_START__)
-#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
+IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE);
+IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT);
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index f4893ef..caea7a7 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1319,10 +1319,14 @@
{
int i;
- for (i = 0; i < 2; i++) {
+ for (i = 1; i >= 0; i--) {
mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
}
+
+ /* write 0x76 to cnt_restart to keep watchdog alive */
+ mmio_write_32(WDT0_BASE + 0x0c, 0x76);
+ mmio_write_32(WDT1_BASE + 0x0c, 0x76);
}
int rockchip_soc_sys_pwr_dm_suspend(void)
@@ -1383,6 +1387,7 @@
}
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
+ wdt_register_save();
secure_watchdog_disable();
/*
@@ -1398,7 +1403,6 @@
suspend_uart();
grf_register_save();
cru_register_save();
- wdt_register_save();
sram_save();
plat_rockchip_save_gpio();
@@ -1411,7 +1415,6 @@
uint32_t status = 0;
plat_rockchip_restore_gpio();
- wdt_register_restore();
cru_register_restore();
grf_register_restore();
resume_uart();
@@ -1426,6 +1429,7 @@
secure_watchdog_enable();
secure_sgrf_init();
secure_sgrf_ddr_rgn_init();
+ wdt_register_restore();
/* restore clk_ddrc_bpll_src_en gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
diff --git a/plat/rpi3/aarch64/plat_helpers.S b/plat/rpi3/aarch64/plat_helpers.S
index 76a542f..65c1bf2 100644
--- a/plat/rpi3/aarch64/plat_helpers.S
+++ b/plat/rpi3/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -137,7 +137,7 @@
mov_imm x0, PLAT_RPI3_UART_BASE
mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ
mov_imm x2, PLAT_RPI3_UART_BAUDRATE
- b console_core_init
+ b console_16550_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
@@ -149,7 +149,7 @@
*/
func plat_crash_console_putc
mov_imm x1, PLAT_RPI3_UART_BASE
- b console_core_putc
+ b console_16550_core_putc
endfunc plat_crash_console_putc
/* ---------------------------------------------
@@ -161,8 +161,8 @@
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x1, PLAT_RPI3_UART_BASE
- b console_core_flush
+ mov_imm x0, PLAT_RPI3_UART_BASE
+ b console_16550_core_flush
endfunc plat_crash_console_flush
/* ---------------------------------------------
diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk
index e201cee..2cb7a15 100644
--- a/plat/rpi3/platform.mk
+++ b/plat/rpi3/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -81,6 +81,9 @@
# Enable new version of image loading
LOAD_IMAGE_V2 := 1
+# Use multi console API
+MULTI_CONSOLE_API := 1
+
# Platform build flags
# --------------------
@@ -110,6 +113,10 @@
$(error Error: rpi3 needs LOAD_IMAGE_V2=1)
endif
+ifneq (${MULTI_CONSOLE_API}, 1)
+ $(error Error: rpi3 needs MULTI_CONSOLE_API=1)
+endif
+
ifeq (${ARCH},aarch32)
$(error Error: AArch32 not supported on rpi3)
endif
diff --git a/plat/rpi3/rpi3_bl1_setup.c b/plat/rpi3/rpi3_bl1_setup.c
index 11c0f4a..c98715b 100644
--- a/plat/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi3/rpi3_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,6 @@
#include <arch.h>
#include <arch_helpers.h>
#include <bl_common.h>
-#include <console.h>
#include <platform_def.h>
#include <xlat_mmu_helpers.h>
#include <xlat_tables_defs.h>
@@ -29,8 +28,7 @@
void bl1_early_platform_setup(void)
{
/* Initialize the console to provide early debug support */
- console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ,
- PLAT_RPI3_UART_BAUDRATE);
+ rpi3_console_init();
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c
index 1fd822e..6d43dce 100644
--- a/plat/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi3/rpi3_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,6 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
-#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
#include <platform_def.h>
@@ -27,8 +26,7 @@
void bl2_early_platform_setup(meminfo_t *mem_layout)
{
/* Initialize the console to provide early debug support */
- console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ,
- PLAT_RPI3_UART_BAUDRATE);
+ rpi3_console_init();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
@@ -40,7 +38,7 @@
{
/*
* This is where a TrustZone address space controller and other
- * security related peripherals, would be configured.
+ * security related peripherals would be configured.
*/
}
diff --git a/plat/rpi3/rpi3_bl31_setup.c b/plat/rpi3/rpi3_bl31_setup.c
index 3913356..58344ae 100644
--- a/plat/rpi3/rpi3_bl31_setup.c
+++ b/plat/rpi3/rpi3_bl31_setup.c
@@ -1,12 +1,11 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <bl_common.h>
-#include <console.h>
#include <platform.h>
#include <platform_def.h>
#include <xlat_mmu_helpers.h>
@@ -58,8 +57,7 @@
void *plat_params_from_bl2)
{
/* Initialize the console to provide early debug support */
- console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ,
- PLAT_RPI3_UART_BAUDRATE);
+ rpi3_console_init();
#if RESET_TO_BL31
@@ -159,10 +157,3 @@
return;
}
-
-void bl31_plat_runtime_setup(void)
-{
- /* Initialize the runtime console */
- console_init(PLAT_RPI3_UART_BASE, PLAT_RPI3_UART_CLK_IN_HZ,
- PLAT_RPI3_UART_BAUDRATE);
-}
diff --git a/plat/rpi3/rpi3_common.c b/plat/rpi3/rpi3_common.c
index 97dce09..03914a6 100644
--- a/plat/rpi3/rpi3_common.c
+++ b/plat/rpi3/rpi3_common.c
@@ -1,14 +1,16 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <bl_common.h>
+#include <console.h>
#include <debug.h>
#include <interrupt_mgmt.h>
#include <platform_def.h>
+#include <uart_16550.h>
#include <xlat_tables_v2.h>
#include "rpi3_hw.h"
@@ -69,6 +71,30 @@
#endif
/*******************************************************************************
+ * Function that sets up the console
+ ******************************************************************************/
+static console_16550_t rpi3_console;
+
+void rpi3_console_init(void)
+{
+ int rc = console_16550_register(PLAT_RPI3_UART_BASE,
+ PLAT_RPI3_UART_CLK_IN_HZ,
+ PLAT_RPI3_UART_BAUDRATE,
+ &rpi3_console);
+ if (rc == 0) {
+ /*
+ * The crash console doesn't use the multi console API, it uses
+ * the core console functions directly. It is safe to call panic
+ * and let it print debug information.
+ */
+ panic();
+ }
+
+ console_set_scope(&rpi3_console.console,
+ CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
+}
+
+/*******************************************************************************
* Function that sets up the translation tables.
******************************************************************************/
void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
diff --git a/plat/rpi3/rpi3_private.h b/plat/rpi3/rpi3_private.h
index 01c4055..a9fbfe4 100644
--- a/plat/rpi3/rpi3_private.h
+++ b/plat/rpi3/rpi3_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
******************************************************************************/
/* Utility functions */
+void rpi3_console_init(void);
void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
uintptr_t code_start, uintptr_t code_limit,
uintptr_t rodata_start, uintptr_t rodata_limit
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index d6e5726..97f202c 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -451,7 +451,7 @@
uint32_t spsr;
ns_ep_info = bl31_plat_get_next_image_ep_info(NON_SECURE);
- if (!ep_info) {
+ if (ns_ep_info == NULL) {
NOTICE("Trusty: non-secure image missing.\n");
return -1;
}
diff --git a/services/std_svc/spm/spm_shim_private.h b/services/std_svc/spm/spm_shim_private.h
index ad953cd..8408d1e 100644
--- a/services/std_svc/spm/spm_shim_private.h
+++ b/services/std_svc/spm/spm_shim_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,21 +8,17 @@
#define __SPM_SHIM_PRIVATE__
#include <types.h>
+#include <utils_def.h>
/* Assembly source */
-extern uintptr_t spm_shim_exceptions_ptr;
+IMPORT_SYM(uintptr_t, spm_shim_exceptions_ptr, SPM_SHIM_EXCEPTIONS_PTR);
/* Linker symbols */
-extern uintptr_t __SPM_SHIM_EXCEPTIONS_START__;
-extern uintptr_t __SPM_SHIM_EXCEPTIONS_END__;
+IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_START__, SPM_SHIM_EXCEPTIONS_START);
+IMPORT_SYM(uintptr_t, __SPM_SHIM_EXCEPTIONS_END__, SPM_SHIM_EXCEPTIONS_END);
/* Definitions */
-#define SPM_SHIM_EXCEPTIONS_PTR (uintptr_t)(&spm_shim_exceptions_ptr)
-#define SPM_SHIM_EXCEPTIONS_START \
- (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_START__)
-#define SPM_SHIM_EXCEPTIONS_END \
- (uintptr_t)(&__SPM_SHIM_EXCEPTIONS_END__)
#define SPM_SHIM_EXCEPTIONS_SIZE \
(SPM_SHIM_EXCEPTIONS_END - SPM_SHIM_EXCEPTIONS_START)