Merge "feat(versal): deprecate build time arg VERSAL_PLATFORM" into integration
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 7b6a1f5..2d1afab 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2023, Arm Limited. All rights reserved
+# Copyright (c) 2023-2024, Arm Limited. All rights reserved
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -19,9 +19,8 @@
jobs:
post_create_environment:
- pip install poetry=="1.3.2"
- - poetry config virtualenvs.create false
post_install:
- - poetry install --with doc
+ - VIRTUAL_ENV=$READTHEDOCS_VIRTUALENV_PATH poetry install --with docs
sphinx:
configuration: docs/conf.py
diff --git a/Makefile b/Makefile
index 819d774..baf8431 100644
--- a/Makefile
+++ b/Makefile
@@ -24,6 +24,7 @@
MAKE_HELPERS_DIRECTORY := make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}build-rules.mk
include ${MAKE_HELPERS_DIRECTORY}common.mk
################################################################################
@@ -690,8 +691,6 @@
FFH_SUPPORT := 0
endif
-$(eval $(call MAKE_PREREQ_DIR,${BUILD_PLAT}))
-
ifeq (${ARM_ARCH_MAJOR},7)
include make_helpers/armv7-a-cpus.mk
endif
@@ -1480,7 +1479,6 @@
endif
endif #(!ERROR_DEPRECATED)
-$(eval $(call MAKE_LIB_DIRS))
$(eval $(call MAKE_LIB,c))
# Expand build macros for the different images
@@ -1564,7 +1562,7 @@
# Add Secure Partition packages
ifeq (${NEED_SP_PKG},yes)
-$(BUILD_PLAT)/sp_gen.mk: ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT}
+$(BUILD_PLAT)/sp_gen.mk: ${SP_MK_GEN} ${SP_LAYOUT_FILE} | $$(@D)/
$(q)${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT} ${SP_DTS_LIST_FRAGMENT}
sp: $(DTBS) $(BUILD_PLAT)/sp_gen.mk $(SP_PKGS)
$(s)echo
diff --git a/changelog.yaml b/changelog.yaml
index c085ede..2b760c7 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1444,6 +1444,9 @@
- title: R/ZG Layout Tool
scope: rzg-layout
+ - title: Transfer List Compiler
+ scope: tlc
+
- title: Dependencies
scope: deps
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index f59303e..4c070ed 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -23,8 +23,9 @@
is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
- zero at all but the highest implemented exception level. Reads from the
- memory mapped view are unaffected by this control.
+ zero at all but the highest implemented exception level. External
+ memory-mapped debug accesses are unaffected by this control.
+ The default value is 1 for all platforms.
- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
``aarch64`` or ``aarch32`` as values. By default, it is defined to
diff --git a/docs/plat/xilinx-versal-net.rst b/docs/plat/xilinx-versal-net.rst
index e9dd772..d22a46d 100644
--- a/docs/plat/xilinx-versal-net.rst
+++ b/docs/plat/xilinx-versal-net.rst
@@ -75,7 +75,7 @@
| 0xc2001000-0xc2001FFF | Fast SMC64 SiP Service call range used for AMD-Xilinx IPI |
+---------------------------+-----------------------------------------------------------+
-PM SMC call ranges
+PM SMC call ranges for SiP SVC version 0.1
--------------------------------------------------------
+---------------------------+---------------------------------------------------------------------------+
@@ -84,6 +84,19 @@
| 0xc2000000-0xc2000FFF | Fast SMC64 SiP Service call range used for AMD-Xilinx Platform Management |
+---------------------------+---------------------------------------------------------------------------+
+PM SMC call ranges for SiP SVC version 0.2
+--------------------------------------------------------
+
++---------------------------+---------------------------------------------------------------------------+
+| SMC Function Identifier | Service type |
++---------------------------+---------------------------------------------------------------------------+
+| 0xc2000FFF | Fast SMC64 SiP Service call used for pass-through of AMD-Xilinx Platform |
+| | Management APIs to firmware |
++---------------------------+---------------------------------------------------------------------------+
+| 0xc2000A00-0xc2000AFF | Fast SMC64 SiP Service call range used for AMD-Xilinx Platform Management |
+| | specific TF-A APIs |
++---------------------------+---------------------------------------------------------------------------+
+
SMC function IDs for SiP Service queries
----------------------------------------------
diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst
index 6e93115..7185d91 100644
--- a/docs/plat/xilinx-versal.rst
+++ b/docs/plat/xilinx-versal.rst
@@ -88,8 +88,8 @@
| 0xc2001000-0xc2001FFF | Fast SMC64 SiP Service call range used for AMD-Xilinx IPI |
+---------------------------+-----------------------------------------------------------+
-PM SMC call ranges
-------------------
+PM SMC call ranges for SiP SVC version 0.1
+--------------------------------------------------------
+---------------------------+---------------------------------------------------------------------------+
| SMC Function Identifier | Service type |
@@ -97,6 +97,19 @@
| 0xc2000000-0xc2000FFF | Fast SMC64 SiP Service call range used for AMD-Xilinx Platform Management |
+---------------------------+---------------------------------------------------------------------------+
+PM SMC call ranges for SiP SVC version 0.2
+--------------------------------------------------------
+
++---------------------------+---------------------------------------------------------------------------+
+| SMC Function Identifier | Service type |
++---------------------------+---------------------------------------------------------------------------+
+| 0xc2000FFF | Fast SMC64 SiP Service call used for pass-through of AMD-Xilinx Platform |
+| | Management APIs to firmware |
++---------------------------+---------------------------------------------------------------------------+
+| 0xc2000A00-0xc2000AFF | Fast SMC64 SiP Service call range used for AMD-Xilinx Platform Management |
+| | specific TF-A APIs |
++---------------------------+---------------------------------------------------------------------------+
+
SMC function IDs for SiP Service queries
----------------------------------------
diff --git a/docs/tools/index.rst b/docs/tools/index.rst
index 2dee2c0..91651bf 100644
--- a/docs/tools/index.rst
+++ b/docs/tools/index.rst
@@ -6,7 +6,8 @@
:caption: Contents
memory-layout-tool
+ transfer-list-compiler
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
diff --git a/docs/tools/transfer-list-compiler.rst b/docs/tools/transfer-list-compiler.rst
new file mode 100644
index 0000000..fa660dc
--- /dev/null
+++ b/docs/tools/transfer-list-compiler.rst
@@ -0,0 +1,311 @@
+Transfer List Compiler
+======================
+
+The Transfer List Compiler (tlc) is a host tool used by TF-A to generate transfer
+lists compliant with the v0.9 of the `Firmware Handoff specification`_. It enables
+developers to statically generate transfer list blobs containing any number of
+transfer entries.
+
+Getting Started
+~~~~~~~~~~~~~~~
+
+``tlc`` is installed by default with TF-A's poetry environment. All of it's
+dependencies are listed in `tools/tlc/pyproject.toml`_.
+
+To install ``tlc`` seperately, run the following command:
+
+.. code::
+
+ make -C tools/tlc install
+
+Creating a Transfer List
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+To create an empty TL, you can use the ``create`` command.
+
+.. code::
+
+ tlc create tl.bin
+
+This commands generates a binary blob representing an empty TL, shown in the
+hexdump below.
+
+.. code::
+
+ $ hexdump tl.bin | head
+ 0000000 b10b 4a0f 01a6 0318 0018 0000 1000 0000
+ 0000010 0001 0000 0000 0000
+
+A common use-case this tool supports is the addition of TE's via the option
+``--entry``. This takes as input the tag ID and path to a binary blob to be
+included in the transfer list. The snippet below shows how to include an FDT in
+the TL.
+
+.. code::
+
+ tlc create --entry 1 fdt.dtb tl.bin
+
+Alternatively, addition of a device tree is supported through the option
+``--fdt``. This has the same effect as passing the device tree and it's tag ID
+through the ``--entry`` option.
+
+.. code::
+
+ tlc create --fdt fdt.dtb tl.bin
+
+.. note::
+
+ ``tlc`` makes no effort to verify the contents of a binary blob against the
+ provided tag ID. It only checks that the tags provided as input are within
+ range and that there is sufficient memory to include their TE's.
+
+You can also create a TL from a YAML config file.
+
+.. code ::
+
+ tlc create --from-yaml config.yaml tl.bin
+
+Printing the contents of a TL
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Support is provided for dumping the contents of a TL via the ``info`` command.
+This prints the header of the TL and all included TE's.
+
+.. code::
+
+ $ tlc info tl.bin
+ signature 0x4a0fb10b
+ checksum 0xe1
+ version 0x1
+ hdr_size 0x18
+ alignment 0x3
+ size 0x2a6f
+ total_size 0x4e20
+ flags 0x1
+ ----
+ id 0x1
+ data_size 0x2a47
+ hdr_size 0x8
+ offset 0x18
+ ----
+ id 0x0
+ data_size 0x0
+ hdr_size 0x8
+ offset 0x2a68
+
+The example above shows the dump produced by ``tlc`` for a 20Kb TL containing a
+device tree (tag_id=1) and a NULL entry (tag_id=0).
+
+Modifying the contents of an existing TL
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+`tlc` supports removal of one or more entries from a TL through the ``remove``
+command. It takes as argument the filename, and one or more tag ID's, passed
+through the ``--tags`` option. It produces a valid TL blob without those
+entries.
+
+
+For example, using the same blob as in the section above, we can remove the FDT
+TE with the command.
+
+.. code::
+
+ $ tlc remove --tags 1 tl.bin
+
+Using the ``info`` command, shows the the TE has been remove:
+
+.. code::
+
+ $ tlc info tl.bin
+
+ signature 0x4a0fb10b
+ checksum 0x38
+ version 0x1
+ hdr_size 0x18
+ alignment 0x3
+ size 0x20
+ total_size 0x4e20
+ flags 0x1
+ ----
+ id 0x0
+ data_size 0x0
+ hdr_size 0x8
+ offset 0x18
+
+Note that more than one entry can be removed at a time. The ``--tags`` option
+accepts multiple tag ID's.
+
+Conversely, TE's can be added to an existing TL. This is achieved through the
+`add` command.
+
+.. code::
+
+ $ tlc add --entry 1 fdt.dtb tl.bin
+
+
+The result of this modification is shown below:
+
+.. code::
+
+ $ tlc info tl.bin
+
+ signature 0x4a0fb10b
+ checksum 0xe1
+ version 0x1
+ hdr_size 0x18
+ alignment 0x3
+ size 0x2a6f
+ total_size 0x4e20
+ flags 0x1
+ ----
+ id 0x0
+ data_size 0x0
+ hdr_size 0x8
+ offset 0x18
+ ----
+ id 0x1
+ data_size 0x2a47
+ hdr_size 0x8
+ offset 0x20
+
+Unpacking a Transfer List
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Given a transfer list, ``tlc`` also provides a mechanism for extracting TE data.
+Running the command ``unpack``, yields binary files containing data from all the TE's.
+
+.. code::
+
+ $ tlc create --size 20000 --fdt build/fvp/debug/fdts/fvp-base-gicv3-psci.dtb tl.bin
+ $ tlc unpack tl.bin
+ $ file te_1.bin
+ te_1.bin: Device Tree Blob version 17, size=10823, boot CPU=0, string block size=851, DT structure block size=9900
+
+Validate a Transfer List
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+``tlc validate`` provides a quick and simple mechanism for checking wether the TL
+is compliant with version of the specification supported by the tool. It
+performs the following checks:
+
+#. Validates the signature.
+#. Ensures that the specified version is greater than or equal to the tool’s current version.
+#. Verifies alignment criteria for all TE’s.
+
+YAML Config File Format
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Example YAML config file:
+
+.. code::
+
+ execution_state: aarch32
+ has_checksum: true
+ max_size: 4096
+ entries:
+ - tag_id: 258 # entry point info
+ ep_info:
+ args:
+ - 67112968
+ - 67112960
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ h:
+ attr: 8
+ type: 1
+ version: 2
+ pc: 67239936
+ spsr: 467
+ - tag_id: 3 # memory layout
+ addr: 8
+ size: 8
+ - tag_id: 1, # fdt
+ blob_file_path: "fdt.bin",
+
+`max_size` defaults to `0x1000`, `execution_state` defaults to `aarch64`, and `has_checksum`
+defaults to `true`.
+
+The fields of the YAML file should match the fields in the specification for the transfer list. You
+don't need to give the hdr_size or data_size fields. For example, a memory layout entry would have
+an entry like:
+
+.. code::
+
+ tag_id: 3
+ addr: 8
+ size: 8
+
+You can input blob files by giving paths to the current working directory. You can do this for any
+TE type. For example, an FDT layout would have an entry like:
+
+.. code::
+
+ tag_id: 1,
+ blob_file_path: "fdt.bin",
+
+You can input C-types by giving its fields. For example, an entry point
+info entry would have an entry like:
+
+.. code::
+
+ tag_id: 258
+ ep_info:
+ args:
+ - 67112968
+ - 67112960
+ - 0
+ - 0
+ h:
+ attr: 8
+ type: 1
+ version: 2
+ lr_svc: 0
+ pc: 67239936
+ spsr: 467
+
+You can give the name of the tag instead of the tag id number. The valid tag names are in the
+`transfer_entry_formats` dict in `tools/tlc/tlc/tl.py`_. Some examples are:
+
+* empty
+* fdt
+* hob_block
+* hob_list
+
+You can input the attr field of entry_point_info as a string of flag
+names separated by `|`. The names are taken from ep_info_exp.h in TF-A.
+For example:
+
+.. code::
+
+ has_checksum: true
+ max_size: 4096
+ entries:
+ - tag_id: 0x102
+ ep_info:
+ args:
+ - 67112976
+ - 67112960
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ h:
+ attr: EP_NON_SECURE | EP_ST_ENABLE
+ type: 1
+ version: 2
+ pc: 67239936
+ spsr: 965
+
+--------------
+
+*Copyright (c) 2024, Arm Limited. All rights reserved.*
+
+.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/
+.. _tools/tlc/pyproject.toml: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/heads/master/tools/tlc/pyproject.toml
+.. _tools/tlc/tlc/tl.py: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/heads/master/tools/tlc/tlc/tl.py
diff --git a/drivers/arm/gic/v3/arm_gicv3_common.c b/drivers/arm/gic/v3/arm_gicv3_common.c
index 4489892..cc82ddb 100644
--- a/drivers/arm/gic/v3/arm_gicv3_common.c
+++ b/drivers/arm/gic/v3/arm_gicv3_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,10 +28,13 @@
void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)
{
uintptr_t gicr_base = 0;
+ unsigned int typer_reg;
assert(gicv3_driver_data);
assert(gicv3_driver_data->rdistif_base_addrs);
+ assert(gicv3_driver_data->gicd_base != 0U);
+ typer_reg = gicd_read_typer(gicv3_driver_data->gicd_base);
/*
* The GICR_WAKER.Sleep bit should be set only when both
* GICR_WAKER.ChildrenAsleep and GICR_WAKER.ProcessorSleep are set on
@@ -60,9 +63,14 @@
*/
gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_SL_BIT);
- /* Wait until the GICR_WAKER.Quiescent bit is set */
- while (!(gicr_read_waker(gicr_base) & WAKER_QSC_BIT))
- ;
+ /*
+ * If LPIs are supported, wait until the GICR_WAKER.Quiescent bit is
+ * set.
+ */
+ if ((typer_reg & TYPER_LPIS) != 0U) {
+ while (!(gicr_read_waker(gicr_base) & WAKER_QSC_BIT))
+ ;
+ }
}
/*
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 2da97dc..53f8adf 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -104,242 +104,84 @@
#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
-static void construct_psa_key_alg_and_type(mbedtls_pk_type_t pk_alg,
- mbedtls_md_type_t md_alg,
- psa_ecc_family_t psa_ecc_family,
- psa_algorithm_t *psa_alg,
- psa_key_type_t *psa_key_type)
-{
- psa_algorithm_t psa_md_alg = mbedtls_md_psa_alg_from_type(md_alg);
-
- switch (pk_alg) {
- case MBEDTLS_PK_RSASSA_PSS:
- *psa_alg = PSA_ALG_RSA_PSS(psa_md_alg);
- *psa_key_type = PSA_KEY_TYPE_RSA_PUBLIC_KEY;
- break;
- case MBEDTLS_PK_ECDSA:
- *psa_alg = PSA_ALG_ECDSA(psa_md_alg);
- *psa_key_type = PSA_KEY_TYPE_ECC_PUBLIC_KEY(psa_ecc_family);
- break;
- default:
- *psa_alg = PSA_ALG_NONE;
- *psa_key_type = PSA_KEY_TYPE_NONE;
- break;
- }
-}
-
-
-#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
-TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
-
/*
- * This is a helper function to detect padding byte (if the MSB bit of the
- * first data byte is set to 1, for example 0x80) and on detection, ignore the
- * padded byte(0x00) and increase the buffer pointer beyond padded byte and
- * decrease the length of the buffer by 1.
- *
- * On Success returns 0, error otherwise.
- **/
-static inline int ignore_asn1_int_padding_byte(unsigned char **buf_start,
- size_t *buf_len)
-{
- unsigned char *local_buf = *buf_start;
-
- /* Check for negative number */
- if ((local_buf[0] & 0x80U) != 0U) {
- return -1;
- }
-
- if ((local_buf[0] == 0U) && (local_buf[1] > 0x7FU) &&
- (*buf_len > 1U)) {
- *buf_start = &local_buf[1];
- (*buf_len)--;
- }
-
- return 0;
-}
+ * NOTE: This has been made internal in mbedtls 3.6.0 and the mbedtls team has
+ * advised that it's better to copy out the declaration than it would be to
+ * update to 3.5.2, where this function is exposed.
+ */
+int mbedtls_x509_get_sig_alg(const mbedtls_x509_buf *sig_oid,
+ const mbedtls_x509_buf *sig_params,
+ mbedtls_md_type_t *md_alg,
+ mbedtls_pk_type_t *pk_alg,
+ void **sig_opts);
/*
- * This is a helper function that gets a pointer to the encoded ECDSA publicKey
- * and its length (as per RFC5280) and returns corresponding decoded publicKey
- * and its length. As well, it retrieves the family of ECC key in the PSA
- * format.
- *
- * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure,
- * otherwise success(0).
- **/
-static int get_ecdsa_pkinfo_from_asn1(unsigned char **pk_start,
- unsigned int *pk_len,
- psa_ecc_family_t *psa_ecc_family)
+ * This is a helper function which parses a SignatureAlgorithm OID.
+ * It extracts the pk algorithm and constructs a psa_algorithm_t object
+ * to be used by PSA calls.
+ */
+static int construct_psa_alg(void *sig_alg, unsigned int sig_alg_len,
+ mbedtls_pk_type_t *pk_alg, psa_algorithm_t *psa_alg)
{
- mbedtls_asn1_buf alg_oid, alg_params;
- mbedtls_ecp_group_id grp_id;
int rc;
- unsigned char *pk_end;
- size_t len;
- size_t curve_bits;
- unsigned char *pk_ptr = *pk_start;
+ mbedtls_md_type_t md_alg;
+ void *sig_opts = NULL;
+ mbedtls_asn1_buf sig_alg_oid, params;
+ unsigned char *p = (unsigned char *) sig_alg;
+ unsigned char *end = (unsigned char *) sig_alg + sig_alg_len;
- pk_end = pk_ptr + *pk_len;
- rc = mbedtls_asn1_get_tag(&pk_ptr, pk_end, &len,
- MBEDTLS_ASN1_CONSTRUCTED |
- MBEDTLS_ASN1_SEQUENCE);
+ rc = mbedtls_asn1_get_alg(&p, end, &sig_alg_oid, ¶ms);
if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end;
}
- pk_end = pk_ptr + len;
- rc = mbedtls_asn1_get_alg(&pk_ptr, pk_end, &alg_oid, &alg_params);
+ rc = mbedtls_x509_get_sig_alg(&sig_alg_oid, ¶ms, &md_alg, pk_alg, &sig_opts);
if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end;
}
- if (alg_params.tag == MBEDTLS_ASN1_OID) {
- if (mbedtls_oid_get_ec_grp(&alg_params, &grp_id) != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
- *psa_ecc_family = mbedtls_ecc_group_to_psa(grp_id,
- &curve_bits);
- } else {
- return CRYPTO_ERR_SIGNATURE;
- }
+ psa_algorithm_t psa_md_alg = mbedtls_md_psa_alg_from_type(md_alg);
- pk_end = pk_ptr + len - (alg_oid.len + alg_params.len +
- 2 * (SIZE_OF_ASN1_LEN + SIZE_OF_ASN1_TAG));
- rc = mbedtls_asn1_get_bitstring_null(&pk_ptr, pk_end, &len);
- if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
+ switch (*pk_alg) {
+ case MBEDTLS_PK_RSASSA_PSS:
+ *psa_alg = PSA_ALG_RSA_PSS(psa_md_alg);
+ rc = CRYPTO_SUCCESS;
+ break;
+ case MBEDTLS_PK_ECDSA:
+ *psa_alg = PSA_ALG_ECDSA(psa_md_alg);
+ rc = CRYPTO_SUCCESS;
+ break;
+ default:
+ *psa_alg = PSA_ALG_NONE;
+ rc = CRYPTO_ERR_SIGNATURE;
+ break;
}
- *pk_start = pk_ptr;
- *pk_len = len;
-
+end:
+ mbedtls_free(sig_opts);
return rc;
}
/*
- * Ecdsa-Sig-Value ::= SEQUENCE {
- * r INTEGER,
- * s INTEGER
- * }
- *
- * This helper function that gets a pointer to the encoded ECDSA signature and
- * its length (as per RFC5280) and returns corresponding decoded signature
- * (R_S pair) and its size.
- *
- * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure,
- * otherwise success(0).
- **/
-static int get_ecdsa_signature_from_asn1(unsigned char *sig_ptr,
- size_t *sig_len,
- unsigned char *r_s_pair)
+ * Helper functions for mbedtls PK contexts.
+ */
+static void initialize_pk_context(mbedtls_pk_context *pk, bool *pk_initialized)
{
- int rc;
- unsigned char *sig_end;
- size_t len, r_len, s_len;
-
- sig_end = sig_ptr + *sig_len;
- rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &len,
- MBEDTLS_ASN1_CONSTRUCTED |
- MBEDTLS_ASN1_SEQUENCE);
- if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
-
- sig_end = sig_ptr + len;
- rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &r_len,
- MBEDTLS_ASN1_INTEGER);
- if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
-
- if (ignore_asn1_int_padding_byte(&sig_ptr, &r_len) != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
-
- (void)memcpy((void *)&r_s_pair[0], (const void *)sig_ptr, r_len);
-
- sig_ptr = sig_ptr + r_len;
- sig_end = sig_ptr + len - (r_len + (SIZE_OF_ASN1_LEN +
- SIZE_OF_ASN1_TAG));
- rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &s_len,
- MBEDTLS_ASN1_INTEGER);
- if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
-
- if (ignore_asn1_int_padding_byte(&sig_ptr, &s_len) != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
-
- (void)memcpy((void *)&r_s_pair[r_len], (const void *)sig_ptr, s_len);
-
- *sig_len = s_len + r_len;
-
- return 0;
+ mbedtls_pk_init(pk);
+ *pk_initialized = true;
}
-#endif /*
- * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
- * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
- **/
-/*
- * This is a helper function that adjusts the start of the pk_start to point to
- * the subjectPublicKey bytes within the SubjectPublicKeyInfo block.
- *
- * SubjectPublicKeyInfo ::= SEQUENCE {
- * algorithm AlgorithmIdentifier,
- * subjectPublicKey BIT STRING }
- *
- * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure,
- * otherwise success(0).
- **/
-static int pk_bytes_from_subpubkey(unsigned char **pk_start,
- unsigned int *pk_len)
+static void cleanup_pk_context(mbedtls_pk_context *pk, bool *pk_initialized)
{
- mbedtls_asn1_buf alg_oid, alg_params;
- int rc;
- unsigned char *pk_end;
- size_t len;
- unsigned char *pk_ptr = *pk_start;
-
- pk_end = pk_ptr + *pk_len;
- rc = mbedtls_asn1_get_tag(&pk_ptr, pk_end, &len,
- MBEDTLS_ASN1_CONSTRUCTED |
- MBEDTLS_ASN1_SEQUENCE);
- if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
-
- pk_end = pk_ptr + len;
- rc = mbedtls_asn1_get_alg(&pk_ptr, pk_end, &alg_oid, &alg_params);
- if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
+ if (*pk_initialized) {
+ mbedtls_pk_free(pk);
+ *pk_initialized = false;
}
- pk_end = pk_ptr + len - (alg_oid.len + alg_params.len +
- 2 * (SIZE_OF_ASN1_LEN + SIZE_OF_ASN1_TAG));
- rc = mbedtls_asn1_get_bitstring_null(&pk_ptr, pk_end, &len);
- if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
- }
-
- *pk_start = pk_ptr;
- *pk_len = len;
-
- return rc;
}
/*
- * NOTE: This has been made internal in mbedtls 3.6.0 and the mbedtls team has
- * advised that it's better to copy out the declaration than it would be to
- * update to 3.5.2, where this function is exposed.
- */
-int mbedtls_x509_get_sig_alg(const mbedtls_x509_buf *sig_oid,
- const mbedtls_x509_buf *sig_params,
- mbedtls_md_type_t *md_alg,
- mbedtls_pk_type_t *pk_alg,
- void **sig_opts);
-/*
* Verify a signature.
*
* Parameters are passed using the DER encoding format following the ASN.1
@@ -350,141 +192,99 @@
void *sig_alg, unsigned int sig_alg_len,
void *pk_ptr, unsigned int pk_len)
{
- mbedtls_asn1_buf sig_oid, sig_params;
- mbedtls_asn1_buf signature;
- mbedtls_md_type_t md_alg;
- mbedtls_pk_type_t pk_alg;
- int rc;
- void *sig_opts = NULL;
unsigned char *p, *end;
+ mbedtls_pk_context pk;
+ bool pk_initialized = false;
+ int rc = CRYPTO_ERR_SIGNATURE;
+ psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED;
+ psa_key_attributes_t psa_key_attr = PSA_KEY_ATTRIBUTES_INIT;
+ psa_key_id_t psa_key_id;
+ mbedtls_pk_type_t pk_alg;
+ psa_algorithm_t psa_alg;
+ __unused unsigned char reformatted_sig[MAX_ECDSA_R_S_PAIR_LEN] = {0};
unsigned char *local_sig_ptr;
size_t local_sig_len;
- psa_ecc_family_t psa_ecc_family = 0U;
- __unused unsigned char reformatted_sig[MAX_ECDSA_R_S_PAIR_LEN] = {0};
- /* construct PSA key algo and type */
- psa_status_t status = PSA_SUCCESS;
- psa_key_attributes_t psa_key_attr = PSA_KEY_ATTRIBUTES_INIT;
- psa_key_id_t psa_key_id = PSA_KEY_ID_NULL;
- psa_key_type_t psa_key_type;
- psa_algorithm_t psa_alg;
+ /* Load the key into the PSA key store. */
+ initialize_pk_context(&pk, &pk_initialized);
- /* Get pointers to signature OID and parameters */
- p = (unsigned char *)sig_alg;
- end = (unsigned char *)(p + sig_alg_len);
- rc = mbedtls_asn1_get_alg(&p, end, &sig_oid, &sig_params);
+ p = (unsigned char *) pk_ptr;
+ end = p + pk_len;
+ rc = mbedtls_pk_parse_subpubkey(&p, end, &pk);
if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end2;
}
- /* Get the actual signature algorithm (MD + PK) */
- rc = mbedtls_x509_get_sig_alg(&sig_oid, &sig_params, &md_alg, &pk_alg, &sig_opts);
+ rc = mbedtls_pk_get_psa_attributes(&pk, PSA_KEY_USAGE_VERIFY_MESSAGE, &psa_key_attr);
if (rc != 0) {
- return CRYPTO_ERR_SIGNATURE;
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end2;
+ }
+
+ rc = construct_psa_alg(sig_alg, sig_alg_len, &pk_alg, &psa_alg);
+ if (rc != CRYPTO_SUCCESS) {
+ goto end2;
}
+ psa_set_key_algorithm(&psa_key_attr, psa_alg);
- /* Get the signature (bitstring) */
- p = (unsigned char *)sig_ptr;
- end = (unsigned char *)(p + sig_len);
- signature.tag = *p;
- rc = mbedtls_asn1_get_bitstring_null(&p, end, &signature.len);
- if ((rc != 0) || ((size_t)(end - p) != signature.len)) {
+ rc = mbedtls_pk_import_into_psa(&pk, &psa_key_attr, &psa_key_id);
+ if (rc != 0) {
rc = CRYPTO_ERR_SIGNATURE;
goto end2;
}
+ /* Optimize mbedtls heap usage by freeing the pk context now. */
+ cleanup_pk_context(&pk, &pk_initialized);
+
+ /* Extract the signature from sig_ptr. */
+ p = (unsigned char *) sig_ptr;
+ end = p + sig_len;
+ rc = mbedtls_asn1_get_bitstring_null(&p, end, &local_sig_len);
+ if (rc != 0) {
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end1;
+ }
local_sig_ptr = p;
- local_sig_len = signature.len;
#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
if (pk_alg == MBEDTLS_PK_ECDSA) {
- rc = get_ecdsa_signature_from_asn1(local_sig_ptr,
- &local_sig_len,
- reformatted_sig);
- if (rc != 0) {
- goto end2;
- }
-
- local_sig_ptr = reformatted_sig;
+ /* Convert the DER ASN.1 signature to raw format. */
+ size_t key_bits = psa_get_key_bits(&psa_key_attr);
- rc = get_ecdsa_pkinfo_from_asn1((unsigned char **)&pk_ptr,
- &pk_len,
- &psa_ecc_family);
+ rc = mbedtls_ecdsa_der_to_raw(key_bits, p, local_sig_len,
+ reformatted_sig, MAX_ECDSA_R_S_PAIR_LEN,
+ &local_sig_len);
if (rc != 0) {
- goto end2;
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end1;
}
+ local_sig_ptr = reformatted_sig;
}
#endif /*
* TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
* TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
**/
- /* Convert this pk_alg and md_alg to PSA key type and key algorithm */
- construct_psa_key_alg_and_type(pk_alg, md_alg, psa_ecc_family,
- &psa_alg, &psa_key_type);
-
-
- if ((psa_alg == PSA_ALG_NONE) || (psa_key_type == PSA_KEY_TYPE_NONE)) {
- rc = CRYPTO_ERR_SIGNATURE;
- goto end2;
- }
-
- /* filled-in key_attributes */
- psa_set_key_algorithm(&psa_key_attr, psa_alg);
- psa_set_key_type(&psa_key_attr, psa_key_type);
- psa_set_key_usage_flags(&psa_key_attr, PSA_KEY_USAGE_VERIFY_MESSAGE);
-
- /*
- * Note: In the implementation of the psa_import_key function in
- * version 3.6.0, the function expects the starting pointer of the
- * subject public key instead of the starting point of
- * SubjectPublicKeyInfo.
- * This is only needed while dealing with RSASSA_PSS (RSA Signature
- * scheme with Appendix based on Probabilistic Signature Scheme)
- * algorithm.
- */
- if (pk_alg == MBEDTLS_PK_RSASSA_PSS) {
- rc = pk_bytes_from_subpubkey((unsigned char **) &pk_ptr, &pk_len);
- if (rc != 0) {
- goto end2;
- }
- }
-
- /* Get the key_id using import API */
- status = psa_import_key(&psa_key_attr,
- pk_ptr,
- (size_t)pk_len,
- &psa_key_id);
-
- if (status != PSA_SUCCESS) {
- rc = CRYPTO_ERR_SIGNATURE;
- goto end2;
- }
-
- /*
- * Hash calculation and Signature verification of the given data payload
- * is wrapped under the psa_verify_message function.
- */
- status = psa_verify_message(psa_key_id, psa_alg,
+ /* Verify the signature. */
+ psa_status = psa_verify_message(psa_key_id, psa_alg,
data_ptr, data_len,
local_sig_ptr, local_sig_len);
-
- if (status != PSA_SUCCESS) {
+ if (psa_status == PSA_SUCCESS) {
+ /* The signature has been successfully verified. */
+ rc = CRYPTO_SUCCESS;
+ } else {
rc = CRYPTO_ERR_SIGNATURE;
- goto end1;
}
- /* Signature verification success */
- rc = CRYPTO_SUCCESS;
-
end1:
- /*
- * Destroy the key if it is created successfully
- */
+ /* Destroy the key from the PSA subsystem. */
psa_destroy_key(psa_key_id);
end2:
- mbedtls_free(sig_opts);
+ /* Free the pk context, if it is initialized. */
+ cleanup_pk_context(&pk, &pk_initialized);
+
return rc;
}
diff --git a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
index 7ae9624..d62eed7 100644
--- a/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
+++ b/drivers/nxp/clk/s32cc/include/s32cc-clk-regs.h
@@ -8,6 +8,10 @@
#include <lib/utils_def.h>
#define FXOSC_BASE_ADDR (0x40050000UL)
+#define ARMPLL_BASE_ADDR (0x40038000UL)
+#define ARM_DFS_BASE_ADDR (0x40054000UL)
+#define CGM0_BASE_ADDR (0x40030000UL)
+#define CGM1_BASE_ADDR (0x40034000UL)
/* FXOSC */
#define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL)
@@ -26,4 +30,80 @@
#define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL)
#define FXOSC_STAT_OSC_STAT BIT_32(31U)
+/* PLL */
+#define PLLDIG_PLLCR(PLL) ((PLL) + 0x0UL)
+#define PLLDIG_PLLCR_PLLPD BIT_32(31U)
+
+#define PLLDIG_PLLSR(PLL) ((PLL) + 0x4UL)
+#define PLLDIG_PLLSR_LOCK BIT_32(2U)
+
+#define PLLDIG_PLLDV(PLL) ((PLL) + 0x8UL)
+#define PLLDIG_PLLDV_RDIV_OFFSET 12U
+#define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET)
+#define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \
+ ((VAL) << PLLDIG_PLLDV_RDIV_OFFSET))
+#define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U)
+#define PLLDIG_PLLDV_MFI(DIV) (PLLDIG_PLLDV_MFI_MASK & (DIV))
+
+#define PLLDIG_PLLFD(PLL) ((PLL) + 0x10UL)
+#define PLLDIG_PLLFD_SMDEN BIT_32(30U)
+#define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U)
+#define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL))
+
+#define PLLDIG_PLLCLKMUX(PLL) ((PLL) + 0x20UL)
+
+#define PLLDIG_PLLODIV(PLL, N) ((PLL) + 0x80UL + ((N) * 0x4UL))
+#define PLLDIG_PLLODIV_DE BIT_32(31U)
+#define PLLDIG_PLLODIV_DIV_OFFSET 16U
+#define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET)
+#define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \
+ PLLDIG_PLLODIV_DIV_OFFSET)
+#define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \
+ PLLDIG_PLLODIV_DIV_OFFSET))
+
+/* MMC_CGM */
+#define CGM_MUXn_CSC(CGM_ADDR, MUX) ((CGM_ADDR) + 0x300UL + ((MUX) * 0x40UL))
+#define MC_CGM_MUXn_CSC_SELCTL_OFFSET 24U
+#define MC_CGM_MUXn_CSC_SELCTL_MASK GENMASK_32(29U, MC_CGM_MUXn_CSC_SELCTL_OFFSET)
+#define MC_CGM_MUXn_CSC_SELCTL(val) (MC_CGM_MUXn_CSC_SELCTL_MASK & ((val) \
+ << MC_CGM_MUXn_CSC_SELCTL_OFFSET))
+#define MC_CGM_MUXn_CSC_CLK_SW BIT_32(2U)
+#define MC_CGM_MUXn_CSC_SAFE_SW BIT_32(3U)
+
+#define CGM_MUXn_CSS(CGM_ADDR, MUX) ((CGM_ADDR) + 0x304UL + ((MUX) * 0x40UL))
+#define MC_CGM_MUXn_CSS_SELSTAT_OFFSET 24U
+#define MC_CGM_MUXn_CSS_SELSTAT_MASK GENMASK_32(29U, MC_CGM_MUXn_CSS_SELSTAT_OFFSET)
+#define MC_CGM_MUXn_CSS_SELSTAT(css) ((MC_CGM_MUXn_CSS_SELSTAT_MASK & (css))\
+ >> MC_CGM_MUXn_CSS_SELSTAT_OFFSET)
+#define MC_CGM_MUXn_CSS_SWTRG(css) ((MC_CGM_MUXn_CSS_SWTRG_MASK & (css)) \
+ >> MC_CGM_MUXn_CSS_SWTRG_OFFSET)
+#define MC_CGM_MUXn_CSS_SWTRG_OFFSET 17U
+#define MC_CGM_MUXn_CSS_SWTRG_MASK GENMASK_32(19U, MC_CGM_MUXn_CSS_SWTRG_OFFSET)
+#define MC_CGM_MUXn_CSS_SWTRG_SUCCESS 0x1U
+#define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK 0x4U
+#define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE 0x5U
+#define MC_CGM_MUXn_CSS_SWIP BIT_32(16U)
+#define MC_CGM_MUXn_CSS_SAFE_SW BIT_32(3U)
+
+/* DFS */
+#define DFS_PORTSR(DFS_ADDR) ((DFS_ADDR) + 0xCUL)
+#define DFS_PORTOLSR(DFS_ADDR) ((DFS_ADDR) + 0x10UL)
+#define DFS_PORTOLSR_LOL(N) (BIT_32(N) & GENMASK_32(5U, 0U))
+#define DFS_PORTRESET(DFS_ADDR) ((DFS_ADDR) + 0x14UL)
+#define DFS_PORTRESET_MASK GENMASK_32(5U, 0U)
+#define DFS_PORTRESET_SET(VAL) (((VAL) & DFS_PORTRESET_MASK))
+
+#define DFS_CTL(DFS_ADDR) ((DFS_ADDR) + 0x18UL)
+#define DFS_CTL_RESET BIT_32(1U)
+
+#define DFS_DVPORTn(DFS_ADDR, PORT) ((DFS_ADDR) + 0x1CUL + ((PORT) * 0x4UL))
+#define DFS_DVPORTn_MFI_MASK GENMASK_32(15U, 8U)
+#define DFS_DVPORTn_MFI_SHIFT 8U
+#define DFS_DVPORTn_MFN_MASK GENMASK_32(7U, 0U)
+#define DFS_DVPORTn_MFN_SHIFT 0U
+#define DFS_DVPORTn_MFI(MFI) (((MFI) & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_SHIFT)
+#define DFS_DVPORTn_MFN(MFN) (((MFN) & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_SHIFT)
+#define DFS_DVPORTn_MFI_SET(VAL) (((VAL) << DFS_DVPORTn_MFI_SHIFT) & DFS_DVPORTn_MFI_MASK)
+#define DFS_DVPORTn_MFN_SET(VAL) (((VAL) << DFS_DVPORTn_MFN_SHIFT) & DFS_DVPORTn_MFN_MASK)
+
#endif /* S32CC_CLK_REGS_H */
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
index f35a469..e23d928 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -10,13 +10,21 @@
#include <common/debug.h>
#include <drivers/clk.h>
#include <lib/mmio.h>
+#include <s32cc-clk-ids.h>
#include <s32cc-clk-modules.h>
#include <s32cc-clk-utils.h>
#define MAX_STACK_DEPTH (15U)
+/* This is used for floating-point precision calculations. */
+#define FP_PRECISION (100000000UL)
+
struct s32cc_clk_drv {
uintptr_t fxosc_base;
+ uintptr_t armpll_base;
+ uintptr_t armdfs_base;
+ uintptr_t cgm0_base;
+ uintptr_t cgm1_base;
};
static int update_stack_depth(unsigned int *depth)
@@ -33,6 +41,10 @@
{
static struct s32cc_clk_drv driver = {
.fxosc_base = FXOSC_BASE_ADDR,
+ .armpll_base = ARMPLL_BASE_ADDR,
+ .armdfs_base = ARM_DFS_BASE_ADDR,
+ .cgm0_base = CGM0_BASE_ADDR,
+ .cgm1_base = CGM1_BASE_ADDR,
};
return &driver;
@@ -67,6 +79,43 @@
return -EINVAL;
}
+static int get_base_addr(enum s32cc_clk_source id, const struct s32cc_clk_drv *drv,
+ uintptr_t *base)
+{
+ int ret = 0;
+
+ switch (id) {
+ case S32CC_FXOSC:
+ *base = drv->fxosc_base;
+ break;
+ case S32CC_ARM_PLL:
+ *base = drv->armpll_base;
+ break;
+ case S32CC_ARM_DFS:
+ *base = drv->armdfs_base;
+ break;
+ case S32CC_CGM0:
+ *base = drv->cgm0_base;
+ break;
+ case S32CC_CGM1:
+ *base = drv->cgm1_base;
+ break;
+ case S32CC_FIRC:
+ break;
+ case S32CC_SIRC:
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret != 0) {
+ ERROR("Unknown clock source id: %u\n", id);
+ }
+
+ return ret;
+}
+
static void enable_fxosc(const struct s32cc_clk_drv *drv)
{
uintptr_t fxosc_base = drv->fxosc_base;
@@ -121,6 +170,593 @@
return ret;
}
+static int get_pll_mfi_mfn(unsigned long pll_vco, unsigned long ref_freq,
+ uint32_t *mfi, uint32_t *mfn)
+
+{
+ unsigned long vco;
+ unsigned long mfn64;
+
+ /* FRAC-N mode */
+ *mfi = (uint32_t)(pll_vco / ref_freq);
+
+ /* MFN formula : (double)(pll_vco % ref_freq) / ref_freq * 18432.0 */
+ mfn64 = pll_vco % ref_freq;
+ mfn64 *= FP_PRECISION;
+ mfn64 /= ref_freq;
+ mfn64 *= 18432UL;
+ mfn64 /= FP_PRECISION;
+
+ if (mfn64 > UINT32_MAX) {
+ return -EINVAL;
+ }
+
+ *mfn = (uint32_t)mfn64;
+
+ vco = ((unsigned long)*mfn * FP_PRECISION) / 18432UL;
+ vco += (unsigned long)*mfi * FP_PRECISION;
+ vco *= ref_freq;
+ vco /= FP_PRECISION;
+
+ if (vco != pll_vco) {
+ ERROR("Failed to find MFI and MFN settings for PLL freq %lu. Nearest freq = %lu\n",
+ pll_vco, vco);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct s32cc_clkmux *get_pll_mux(const struct s32cc_pll *pll)
+{
+ const struct s32cc_clk_obj *source = pll->source;
+ const struct s32cc_clk *clk;
+
+ if (source == NULL) {
+ ERROR("Failed to identify PLL's parent\n");
+ return NULL;
+ }
+
+ if (source->type != s32cc_clk_t) {
+ ERROR("The parent of the PLL isn't a clock\n");
+ return NULL;
+ }
+
+ clk = s32cc_obj2clk(source);
+
+ if (clk->module == NULL) {
+ ERROR("The clock isn't connected to a module\n");
+ return NULL;
+ }
+
+ source = clk->module;
+
+ if ((source->type != s32cc_clkmux_t) &&
+ (source->type != s32cc_shared_clkmux_t)) {
+ ERROR("The parent of the PLL isn't a MUX\n");
+ return NULL;
+ }
+
+ return s32cc_obj2clkmux(source);
+}
+
+static void disable_odiv(uintptr_t pll_addr, uint32_t div_index)
+{
+ mmio_clrbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE);
+}
+
+static void enable_odiv(uintptr_t pll_addr, uint32_t div_index)
+{
+ mmio_setbits_32(PLLDIG_PLLODIV(pll_addr, div_index), PLLDIG_PLLODIV_DE);
+}
+
+static void disable_odivs(uintptr_t pll_addr, uint32_t ndivs)
+{
+ uint32_t i;
+
+ for (i = 0; i < ndivs; i++) {
+ disable_odiv(pll_addr, i);
+ }
+}
+
+static void enable_pll_hw(uintptr_t pll_addr)
+{
+ /* Enable the PLL. */
+ mmio_write_32(PLLDIG_PLLCR(pll_addr), 0x0);
+
+ /* Poll until PLL acquires lock. */
+ while ((mmio_read_32(PLLDIG_PLLSR(pll_addr)) & PLLDIG_PLLSR_LOCK) == 0U) {
+ }
+}
+
+static void disable_pll_hw(uintptr_t pll_addr)
+{
+ mmio_write_32(PLLDIG_PLLCR(pll_addr), PLLDIG_PLLCR_PLLPD);
+}
+
+static int program_pll(const struct s32cc_pll *pll, uintptr_t pll_addr,
+ const struct s32cc_clk_drv *drv, uint32_t sclk_id,
+ unsigned long sclk_freq)
+{
+ uint32_t rdiv = 1, mfi, mfn;
+ int ret;
+
+ ret = get_pll_mfi_mfn(pll->vco_freq, sclk_freq, &mfi, &mfn);
+ if (ret != 0) {
+ return -EINVAL;
+ }
+
+ /* Disable ODIVs*/
+ disable_odivs(pll_addr, pll->ndividers);
+
+ /* Disable PLL */
+ disable_pll_hw(pll_addr);
+
+ /* Program PLLCLKMUX */
+ mmio_write_32(PLLDIG_PLLCLKMUX(pll_addr), sclk_id);
+
+ /* Program VCO */
+ mmio_clrsetbits_32(PLLDIG_PLLDV(pll_addr),
+ PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK,
+ PLLDIG_PLLDV_RDIV_SET(rdiv) | PLLDIG_PLLDV_MFI(mfi));
+
+ mmio_write_32(PLLDIG_PLLFD(pll_addr),
+ PLLDIG_PLLFD_MFN_SET(mfn) | PLLDIG_PLLFD_SMDEN);
+
+ enable_pll_hw(pll_addr);
+
+ return ret;
+}
+
+static int enable_pll(const struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int *depth)
+{
+ const struct s32cc_pll *pll = s32cc_obj2pll(module);
+ const struct s32cc_clkmux *mux;
+ uintptr_t pll_addr = UL(0x0);
+ unsigned long sclk_freq;
+ uint32_t sclk_id;
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ mux = get_pll_mux(pll);
+ if (mux == NULL) {
+ return -EINVAL;
+ }
+
+ if (pll->instance != mux->module) {
+ ERROR("MUX type is not in sync with PLL ID\n");
+ return -EINVAL;
+ }
+
+ ret = get_base_addr(pll->instance, drv, &pll_addr);
+ if (ret != 0) {
+ ERROR("Failed to detect PLL instance\n");
+ return ret;
+ }
+
+ switch (mux->source_id) {
+ case S32CC_CLK_FIRC:
+ sclk_freq = 48U * MHZ;
+ sclk_id = 0;
+ break;
+ case S32CC_CLK_FXOSC:
+ sclk_freq = 40U * MHZ;
+ sclk_id = 1;
+ break;
+ default:
+ ERROR("Invalid source selection for PLL 0x%lx\n",
+ pll_addr);
+ return -EINVAL;
+ };
+
+ return program_pll(pll, pll_addr, drv, sclk_id, sclk_freq);
+}
+
+static inline struct s32cc_pll *get_div_pll(const struct s32cc_pll_out_div *pdiv)
+{
+ const struct s32cc_clk_obj *parent;
+
+ parent = pdiv->parent;
+ if (parent == NULL) {
+ ERROR("Failed to identify PLL divider's parent\n");
+ return NULL;
+ }
+
+ if (parent->type != s32cc_pll_t) {
+ ERROR("The parent of the divider is not a PLL instance\n");
+ return NULL;
+ }
+
+ return s32cc_obj2pll(parent);
+}
+
+static void config_pll_out_div(uintptr_t pll_addr, uint32_t div_index, uint32_t dc)
+{
+ uint32_t pllodiv;
+ uint32_t pdiv;
+
+ pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, div_index));
+ pdiv = PLLDIG_PLLODIV_DIV(pllodiv);
+
+ if (((pdiv + 1U) == dc) && ((pllodiv & PLLDIG_PLLODIV_DE) != 0U)) {
+ return;
+ }
+
+ if ((pllodiv & PLLDIG_PLLODIV_DE) != 0U) {
+ disable_odiv(pll_addr, div_index);
+ }
+
+ pllodiv = PLLDIG_PLLODIV_DIV_SET(dc - 1U);
+ mmio_write_32(PLLDIG_PLLODIV(pll_addr, div_index), pllodiv);
+
+ enable_odiv(pll_addr, div_index);
+}
+
+static int enable_pll_div(const struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int *depth)
+{
+ const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
+ uintptr_t pll_addr = 0x0ULL;
+ const struct s32cc_pll *pll;
+ uint32_t dc;
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ pll = get_div_pll(pdiv);
+ if (pll == NULL) {
+ ERROR("The parent of the PLL DIV is invalid\n");
+ return 0;
+ }
+
+ ret = get_base_addr(pll->instance, drv, &pll_addr);
+ if (ret != 0) {
+ ERROR("Failed to detect PLL instance\n");
+ return -EINVAL;
+ }
+
+ dc = (uint32_t)(pll->vco_freq / pdiv->freq);
+
+ config_pll_out_div(pll_addr, pdiv->index, dc);
+
+ return 0;
+}
+
+static int cgm_mux_clk_config(uintptr_t cgm_addr, uint32_t mux, uint32_t source,
+ bool safe_clk)
+{
+ uint32_t css, csc;
+
+ css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux));
+
+ /* Already configured */
+ if ((MC_CGM_MUXn_CSS_SELSTAT(css) == source) &&
+ (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) &&
+ ((css & MC_CGM_MUXn_CSS_SWIP) == 0U) && !safe_clk) {
+ return 0;
+ }
+
+ /* Ongoing clock switch? */
+ while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) &
+ MC_CGM_MUXn_CSS_SWIP) != 0U) {
+ }
+
+ csc = mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux));
+
+ /* Clear previous source. */
+ csc &= ~(MC_CGM_MUXn_CSC_SELCTL_MASK);
+
+ if (!safe_clk) {
+ /* Select the clock source and trigger the clock switch. */
+ csc |= MC_CGM_MUXn_CSC_SELCTL(source) | MC_CGM_MUXn_CSC_CLK_SW;
+ } else {
+ /* Switch to safe clock */
+ csc |= MC_CGM_MUXn_CSC_SAFE_SW;
+ }
+
+ mmio_write_32(CGM_MUXn_CSC(cgm_addr, mux), csc);
+
+ /* Wait for configuration bit to auto-clear. */
+ while ((mmio_read_32(CGM_MUXn_CSC(cgm_addr, mux)) &
+ MC_CGM_MUXn_CSC_CLK_SW) != 0U) {
+ }
+
+ /* Is the clock switch completed? */
+ while ((mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux)) &
+ MC_CGM_MUXn_CSS_SWIP) != 0U) {
+ }
+
+ /*
+ * Check if the switch succeeded.
+ * Check switch trigger cause and the source.
+ */
+ css = mmio_read_32(CGM_MUXn_CSS(cgm_addr, mux));
+ if (!safe_clk) {
+ if ((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SUCCESS) &&
+ (MC_CGM_MUXn_CSS_SELSTAT(css) == source)) {
+ return 0;
+ }
+
+ ERROR("Failed to change the source of mux %" PRIu32 " to %" PRIu32 " (CGM=%lu)\n",
+ mux, source, cgm_addr);
+ } else {
+ if (((MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK) ||
+ (MC_CGM_MUXn_CSS_SWTRG(css) == MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE)) &&
+ ((MC_CGM_MUXn_CSS_SAFE_SW & css) != 0U)) {
+ return 0;
+ }
+
+ ERROR("The switch of mux %" PRIu32 " (CGM=%lu) to safe clock failed\n",
+ mux, cgm_addr);
+ }
+
+ return -EINVAL;
+}
+
+static int enable_cgm_mux(const struct s32cc_clkmux *mux,
+ const struct s32cc_clk_drv *drv)
+{
+ uintptr_t cgm_addr = UL(0x0);
+ uint32_t mux_hw_clk;
+ int ret;
+
+ ret = get_base_addr(mux->module, drv, &cgm_addr);
+ if (ret != 0) {
+ return ret;
+ }
+
+ mux_hw_clk = (uint32_t)S32CC_CLK_ID(mux->source_id);
+
+ return cgm_mux_clk_config(cgm_addr, mux->index,
+ mux_hw_clk, false);
+}
+
+static int enable_mux(const struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int *depth)
+{
+ const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+ const struct s32cc_clk *clk;
+ int ret = 0;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (mux == NULL) {
+ return -EINVAL;
+ }
+
+ clk = s32cc_get_arch_clk(mux->source_id);
+ if (clk == NULL) {
+ ERROR("Invalid parent (%lu) for mux %" PRIu8 "\n",
+ mux->source_id, mux->index);
+ return -EINVAL;
+ }
+
+ switch (mux->module) {
+ /* PLL mux will be enabled by PLL setup */
+ case S32CC_ARM_PLL:
+ break;
+ case S32CC_CGM1:
+ ret = enable_cgm_mux(mux, drv);
+ break;
+ case S32CC_CGM0:
+ ret = enable_cgm_mux(mux, drv);
+ break;
+ default:
+ ERROR("Unknown mux parent type: %d\n", mux->module);
+ ret = -EINVAL;
+ break;
+ };
+
+ return ret;
+}
+
+static int enable_dfs(const struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int *depth)
+{
+ int ret = 0;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct s32cc_dfs *get_div_dfs(const struct s32cc_dfs_div *dfs_div)
+{
+ const struct s32cc_clk_obj *parent = dfs_div->parent;
+
+ if (parent->type != s32cc_dfs_t) {
+ ERROR("DFS DIV doesn't have a DFS as parent\n");
+ return NULL;
+ }
+
+ return s32cc_obj2dfs(parent);
+}
+
+static struct s32cc_pll *dfsdiv2pll(const struct s32cc_dfs_div *dfs_div)
+{
+ const struct s32cc_clk_obj *parent;
+ const struct s32cc_dfs *dfs;
+
+ dfs = get_div_dfs(dfs_div);
+ if (dfs == NULL) {
+ return NULL;
+ }
+
+ parent = dfs->parent;
+ if (parent->type != s32cc_pll_t) {
+ return NULL;
+ }
+
+ return s32cc_obj2pll(parent);
+}
+
+static int get_dfs_mfi_mfn(unsigned long dfs_freq, const struct s32cc_dfs_div *dfs_div,
+ uint32_t *mfi, uint32_t *mfn)
+{
+ uint64_t factor64, tmp64, ofreq;
+ uint32_t factor32;
+
+ unsigned long in = dfs_freq;
+ unsigned long out = dfs_div->freq;
+
+ /**
+ * factor = (IN / OUT) / 2
+ * MFI = integer(factor)
+ * MFN = (factor - MFI) * 36
+ */
+ factor64 = ((((uint64_t)in) * FP_PRECISION) / ((uint64_t)out)) / 2ULL;
+ tmp64 = factor64 / FP_PRECISION;
+ if (tmp64 > UINT32_MAX) {
+ return -EINVAL;
+ }
+
+ factor32 = (uint32_t)tmp64;
+ *mfi = factor32;
+
+ tmp64 = ((factor64 - ((uint64_t)*mfi * FP_PRECISION)) * 36UL) / FP_PRECISION;
+ if (tmp64 > UINT32_MAX) {
+ return -EINVAL;
+ }
+
+ *mfn = (uint32_t)tmp64;
+
+ /* div_freq = in / (2 * (*mfi + *mfn / 36.0)) */
+ factor64 = (((uint64_t)*mfn) * FP_PRECISION) / 36ULL;
+ factor64 += ((uint64_t)*mfi) * FP_PRECISION;
+ factor64 *= 2ULL;
+ ofreq = (((uint64_t)in) * FP_PRECISION) / factor64;
+
+ if (ofreq != dfs_div->freq) {
+ ERROR("Failed to find MFI and MFN settings for DFS DIV freq %lu\n",
+ dfs_div->freq);
+ ERROR("Nearest freq = %" PRIx64 "\n", ofreq);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int init_dfs_port(uintptr_t dfs_addr, uint32_t port,
+ uint32_t mfi, uint32_t mfn)
+{
+ uint32_t portsr, portolsr;
+ uint32_t mask, old_mfi, old_mfn;
+ uint32_t dvport;
+ bool init_dfs;
+
+ dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, port));
+
+ old_mfi = DFS_DVPORTn_MFI(dvport);
+ old_mfn = DFS_DVPORTn_MFN(dvport);
+
+ portsr = mmio_read_32(DFS_PORTSR(dfs_addr));
+ portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr));
+
+ /* Skip configuration if it's not needed */
+ if (((portsr & BIT_32(port)) != 0U) &&
+ ((portolsr & BIT_32(port)) == 0U) &&
+ (mfi == old_mfi) && (mfn == old_mfn)) {
+ return 0;
+ }
+
+ init_dfs = (portsr == 0U);
+
+ if (init_dfs) {
+ mask = DFS_PORTRESET_MASK;
+ } else {
+ mask = DFS_PORTRESET_SET(BIT_32(port));
+ }
+
+ mmio_write_32(DFS_PORTOLSR(dfs_addr), mask);
+ mmio_write_32(DFS_PORTRESET(dfs_addr), mask);
+
+ while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & mask) != 0U) {
+ }
+
+ if (init_dfs) {
+ mmio_write_32(DFS_CTL(dfs_addr), DFS_CTL_RESET);
+ }
+
+ mmio_write_32(DFS_DVPORTn(dfs_addr, port),
+ DFS_DVPORTn_MFI_SET(mfi) | DFS_DVPORTn_MFN_SET(mfn));
+
+ if (init_dfs) {
+ /* DFS clk enable programming */
+ mmio_clrbits_32(DFS_CTL(dfs_addr), DFS_CTL_RESET);
+ }
+
+ mmio_clrbits_32(DFS_PORTRESET(dfs_addr), BIT_32(port));
+
+ while ((mmio_read_32(DFS_PORTSR(dfs_addr)) & BIT_32(port)) != BIT_32(port)) {
+ }
+
+ portolsr = mmio_read_32(DFS_PORTOLSR(dfs_addr));
+ if ((portolsr & DFS_PORTOLSR_LOL(port)) != 0U) {
+ ERROR("Failed to lock DFS divider\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int enable_dfs_div(const struct s32cc_clk_obj *module,
+ const struct s32cc_clk_drv *drv,
+ unsigned int *depth)
+{
+ const struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+ const struct s32cc_pll *pll;
+ const struct s32cc_dfs *dfs;
+ uintptr_t dfs_addr = 0UL;
+ uint32_t mfi, mfn;
+ int ret = 0;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ dfs = get_div_dfs(dfs_div);
+ if (dfs == NULL) {
+ return -EINVAL;
+ }
+
+ pll = dfsdiv2pll(dfs_div);
+ if (pll == NULL) {
+ ERROR("Failed to identify DFS divider's parent\n");
+ return -EINVAL;
+ }
+
+ ret = get_base_addr(dfs->instance, drv, &dfs_addr);
+ if ((ret != 0) || (dfs_addr == 0UL)) {
+ return -EINVAL;
+ }
+
+ ret = get_dfs_mfi_mfn(pll->vco_freq, dfs_div, &mfi, &mfn);
+ if (ret != 0) {
+ return -EINVAL;
+ }
+
+ return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);
+}
+
static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth)
{
const struct s32cc_clk_drv *drv = get_drv();
@@ -142,19 +778,27 @@
case s32cc_clk_t:
ret = enable_clk_module(module, drv, depth);
break;
+ case s32cc_pll_t:
+ ret = enable_pll(module, drv, depth);
+ break;
+ case s32cc_pll_out_div_t:
+ ret = enable_pll_div(module, drv, depth);
+ break;
case s32cc_clkmux_t:
- ret = -ENOTSUP;
+ ret = enable_mux(module, drv, depth);
break;
case s32cc_shared_clkmux_t:
- ret = -ENOTSUP;
+ ret = enable_mux(module, drv, depth);
break;
- case s32cc_pll_t:
- ret = -ENOTSUP;
- break;
- case s32cc_pll_out_div_t:
case s32cc_fixed_div_t:
ret = -ENOTSUP;
break;
+ case s32cc_dfs_t:
+ ret = enable_dfs(module, drv, depth);
+ break;
+ case s32cc_dfs_div_t:
+ ret = enable_dfs_div(module, drv, depth);
+ break;
default:
ret = -EINVAL;
break;
@@ -340,6 +984,63 @@
return ret;
}
+static int set_mux_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ const struct s32cc_clkmux *mux = s32cc_obj2clkmux(module);
+ const struct s32cc_clk *clk = s32cc_get_arch_clk(mux->source_id);
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (clk == NULL) {
+ ERROR("Mux (id:%" PRIu8 ") without a valid source (%lu)\n",
+ mux->index, mux->source_id);
+ return -EINVAL;
+ }
+
+ return set_module_rate(&clk->desc, rate, orate, depth);
+}
+
+static int set_dfs_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
+ unsigned long *orate, unsigned int *depth)
+{
+ struct s32cc_dfs_div *dfs_div = s32cc_obj2dfsdiv(module);
+ const struct s32cc_dfs *dfs;
+ int ret;
+
+ ret = update_stack_depth(depth);
+ if (ret != 0) {
+ return ret;
+ }
+
+ if (dfs_div->parent == NULL) {
+ ERROR("Failed to identify DFS divider's parent\n");
+ return -EINVAL;
+ }
+
+ /* Sanity check */
+ dfs = s32cc_obj2dfs(dfs_div->parent);
+ if (dfs->parent == NULL) {
+ ERROR("Failed to identify DFS's parent\n");
+ return -EINVAL;
+ }
+
+ if ((dfs_div->freq != 0U) && (dfs_div->freq != rate)) {
+ ERROR("DFS DIV frequency was already set to %lu\n",
+ dfs_div->freq);
+ return -EINVAL;
+ }
+
+ dfs_div->freq = rate;
+ *orate = rate;
+
+ return ret;
+}
+
static int set_module_rate(const struct s32cc_clk_obj *module,
unsigned long rate, unsigned long *orate,
unsigned int *depth)
@@ -351,6 +1052,8 @@
return ret;
}
+ ret = -EINVAL;
+
switch (module->type) {
case s32cc_clk_t:
ret = set_clk_freq(module, rate, orate, depth);
@@ -368,11 +1071,18 @@
ret = set_fixed_div_freq(module, rate, orate, depth);
break;
case s32cc_clkmux_t:
+ ret = set_mux_freq(module, rate, orate, depth);
+ break;
case s32cc_shared_clkmux_t:
- ret = -ENOTSUP;
+ ret = set_mux_freq(module, rate, orate, depth);
+ break;
+ case s32cc_dfs_t:
+ ERROR("Setting the frequency of a DFS is not allowed!");
+ break;
+ case s32cc_dfs_div_t:
+ ret = set_dfs_div_freq(module, rate, orate, depth);
break;
default:
- ret = -EINVAL;
break;
}
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
index 039db2a..c4c73c7 100644
--- a/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_modules.c
@@ -43,6 +43,45 @@
static struct s32cc_clk arm_pll_phi0_clk =
S32CC_FREQ_MODULE_CLK(arm_pll_phi0_div, 0, GHZ);
+/* ARM DFS */
+static struct s32cc_dfs armdfs =
+ S32CC_DFS_INIT(armpll, S32CC_ARM_DFS);
+static struct s32cc_dfs_div arm_dfs1_div =
+ S32CC_DFS_DIV_INIT(armdfs, 0);
+static struct s32cc_clk arm_dfs1_clk =
+ S32CC_FREQ_MODULE_CLK(arm_dfs1_div, 0, 800 * MHZ);
+
+/* MC_CGM0 */
+static struct s32cc_clkmux cgm0_mux0 =
+ S32CC_SHARED_CLKMUX_INIT(S32CC_CGM0, 0, 2,
+ S32CC_CLK_FIRC,
+ S32CC_CLK_ARM_PLL_DFS1, 0, 0, 0);
+static struct s32cc_clk cgm0_mux0_clk = S32CC_MODULE_CLK(cgm0_mux0);
+
+/* XBAR */
+static struct s32cc_clk xbar_2x_clk =
+ S32CC_CHILD_CLK(cgm0_mux0_clk, 48 * MHZ, 800 * MHZ);
+static struct s32cc_fixed_div xbar_div2 =
+ S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 2);
+static struct s32cc_clk xbar_clk =
+ S32CC_FREQ_MODULE_CLK(xbar_div2, 24 * MHZ, 400 * MHZ);
+static struct s32cc_fixed_div xbar_div4 =
+ S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 4);
+static struct s32cc_clk xbar_div2_clk =
+ S32CC_FREQ_MODULE_CLK(xbar_div4, 12 * MHZ, 200 * MHZ);
+static struct s32cc_fixed_div xbar_div6 =
+ S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 6);
+static struct s32cc_clk xbar_div3_clk =
+ S32CC_FREQ_MODULE_CLK(xbar_div6, 8 * MHZ, 133333333);
+static struct s32cc_fixed_div xbar_div8 =
+ S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 8);
+static struct s32cc_clk xbar_div4_clk =
+ S32CC_FREQ_MODULE_CLK(xbar_div8, 6 * MHZ, 100 * MHZ);
+static struct s32cc_fixed_div xbar_div12 =
+ S32CC_FIXED_DIV_INIT(cgm0_mux0_clk, 12);
+static struct s32cc_clk xbar_div6_clk =
+ S32CC_FREQ_MODULE_CLK(xbar_div12, 4 * MHZ, 66666666);
+
/* MC_CGM1 */
static struct s32cc_clkmux cgm1_mux0 =
S32CC_SHARED_CLKMUX_INIT(S32CC_CGM1, 0, 3,
@@ -68,13 +107,15 @@
S32CC_FREQ_MODULE_CLK(a53_core_div10, S32CC_A53_MIN_FREQ / 10,
S32CC_A53_MAX_FREQ / 10);
-static struct s32cc_clk *s32cc_hw_clk_list[5] = {
+static struct s32cc_clk *s32cc_hw_clk_list[13] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
[S32CC_CLK_ID(S32CC_CLK_SIRC)] = &sirc_clk,
[S32CC_CLK_ID(S32CC_CLK_FXOSC)] = &fxosc_clk,
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_PHI0)] = &arm_pll_phi0_clk,
+ /* ARM DFS */
+ [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_DFS1)] = &arm_dfs1_clk,
};
static struct s32cc_clk_array s32cc_hw_clocks = {
@@ -83,10 +124,19 @@
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
-static struct s32cc_clk *s32cc_arch_clk_list[6] = {
+static struct s32cc_clk *s32cc_arch_clk_list[13] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
+ /* MC_CGM0 */
+ [S32CC_CLK_ID(S32CC_CLK_MC_CGM0_MUX0)] = &cgm0_mux0_clk,
+ /* XBAR */
+ [S32CC_CLK_ID(S32CC_CLK_XBAR_2X)] = &xbar_2x_clk,
+ [S32CC_CLK_ID(S32CC_CLK_XBAR)] = &xbar_clk,
+ [S32CC_CLK_ID(S32CC_CLK_XBAR_DIV2)] = &xbar_div2_clk,
+ [S32CC_CLK_ID(S32CC_CLK_XBAR_DIV3)] = &xbar_div3_clk,
+ [S32CC_CLK_ID(S32CC_CLK_XBAR_DIV4)] = &xbar_div4_clk,
+ [S32CC_CLK_ID(S32CC_CLK_XBAR_DIV6)] = &xbar_div6_clk,
/* MC_CGM1 */
[S32CC_CLK_ID(S32CC_CLK_MC_CGM1_MUX0)] = &cgm1_mux0_clk,
/* A53 */
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index ac1f7d0..2c256a5 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -11,39 +11,129 @@
#define S32CC_FXOSC_FREQ (40U * MHZ)
#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
+#define S32CC_A53_FREQ (1U * GHZ)
+#define S32CC_XBAR_2X_FREQ (800U * MHZ)
-int s32cc_init_early_clks(void)
+static int enable_fxosc_clk(void)
{
int ret;
- s32cc_clk_register_drv();
+ ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_FXOSC);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+static int enable_arm_pll(void)
+{
+ int ret;
ret = clk_set_parent(S32CC_CLK_ARM_PLL_MUX, S32CC_CLK_FXOSC);
if (ret != 0) {
return ret;
}
+ ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_ARM_PLL_VCO);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+static int enable_a53_clk(void)
+{
+ int ret;
+
ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0);
if (ret != 0) {
return ret;
}
- ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL);
+ ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL);
if (ret != 0) {
return ret;
}
- ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL);
+ ret = clk_enable(S32CC_CLK_A53_CORE);
if (ret != 0) {
return ret;
}
- ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL);
+ return ret;
+}
+
+static int enable_xbar_clk(void)
+{
+ int ret;
+
+ ret = clk_set_parent(S32CC_CLK_MC_CGM0_MUX0, S32CC_CLK_ARM_PLL_DFS1);
if (ret != 0) {
return ret;
}
- ret = clk_enable(S32CC_CLK_FXOSC);
+ ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_ARM_PLL_DFS1);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_XBAR_2X);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
+int s32cc_init_early_clks(void)
+{
+ int ret;
+
+ s32cc_clk_register_drv();
+
+ ret = enable_fxosc_clk();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = enable_arm_pll();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = enable_a53_clk();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = enable_xbar_clk();
if (ret != 0) {
return ret;
}
diff --git a/drivers/nxp/gpio/nxp_gpio.c b/drivers/nxp/gpio/nxp_gpio.c
index 28c9db9..b477b79 100644
--- a/drivers/nxp/gpio/nxp_gpio.c
+++ b/drivers/nxp/gpio/nxp_gpio.c
@@ -28,8 +28,8 @@
ERROR("GPIO is not initialized.\n");
return GPIO_FAILURE;
}
-
- gpdir = gpio_base_addr + GPDIR_REG_OFFSET;
+ /* Divide by 4 since we're operating on 32-bit pointer addresses. */
+ gpdir = gpio_base_addr + (GPDIR_REG_OFFSET >> 2);
gpdat = gpio_base_addr + (GPDAT_REG_OFFSET >> 2);
/*
@@ -67,8 +67,9 @@
return GPIO_FAILURE;
}
- gpdir = gpio_base_addr + GPDIR_REG_OFFSET;
- gpdat = gpio_base_addr + GPDAT_REG_OFFSET;
+ /* Divide by 4 since we're operating on 32-bit pointer addresses. */
+ gpdir = gpio_base_addr + (GPDIR_REG_OFFSET >> 2);
+ gpdat = gpio_base_addr + (GPDAT_REG_OFFSET >> 2);
/*
* Reset the corresponding bit in direction and data register
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 2e03be2..fc6fe78 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -265,9 +265,22 @@
method = "smc";
};
- cpu-pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ cpu-pmu-little {
+ compatible = LIT_CPU_PMU_COMPATIBLE;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_little>;
+ status = "okay";
+ };
+
+ cpu-pmu-mid {
+ compatible = MID_CPU_PMU_COMPATIBLE;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>;
+ status = "okay";
+ };
+
+ cpu-pmu-big {
+ compatible = BIG_CPU_PMU_COMPATIBLE;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>;
+ status = "okay";
};
sram: sram@6000000 {
@@ -290,7 +303,7 @@
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <MHU_MBOX_CELLS>;
- interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI MHU_RX_INT_NUM IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = MHU_RX_INT_NAME;
};
@@ -332,23 +345,35 @@
gic: interrupt-controller@GIC_CTRL_ADDR {
compatible = "arm,gic-v3";
#address-cells = <2>;
- #interrupt-cells = <3>;
+ #interrupt-cells = <4>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x30000000 0 0x10000>, /* GICD */
<0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
- interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW 0>;
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
+ spe-pmu-mid {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_mid>;
+ status = "disabled";
+ };
+
+ spe-pmu-big {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_HIGH &ppi_partition_big>;
+ status = "disabled";
+ };
+
soc_refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -374,7 +399,7 @@
os_uart: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&soc_uartclk>, <&soc_refclk>;
clock-names = "uartclk", "apb_pclk";
status = "okay";
@@ -414,7 +439,7 @@
ethernet: ethernet@18000000 {
reg = <0x0 0x18000000 0x0 0x10000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
reg-io-width = <2>;
smsc,irq-push-pull;
@@ -446,8 +471,8 @@
mmci: mmci@1c050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
wp-gpios = <&sysreg 1 0>;
bus-width = <4>;
max-frequency = <25000000>;
@@ -471,9 +496,9 @@
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&gpu_core_clk>;
clock-names = "shadercores";
@@ -507,10 +532,10 @@
smmu_600: smmu@2ce00000 {
compatible = "arm,smmu-v3";
reg = <0 0x2ce00000 0 0x20000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING 0>;
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
#iommu-cells = <1>;
status = "disabled";
@@ -520,9 +545,9 @@
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <0x0 0x3f000000 0x0 0x5000000>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING 0>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
status = "disabled";
@@ -532,9 +557,9 @@
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>;
- interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 482 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 483 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 482 IRQ_TYPE_EDGE_RISING 0>,
+ <GIC_SPI 483 IRQ_TYPE_EDGE_RISING 0>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
status = "disabled";
@@ -545,7 +570,7 @@
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>;
- interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "DPU";
DPU_CLK_ATTR1;
@@ -630,7 +655,7 @@
trbe {
compatible = "arm,trace-buffer-extension";
- interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>;
};
trusty {
diff --git a/fdts/tc-fvp.dtsi b/fdts/tc-fvp.dtsi
index 9f3a9ac..1e14f0b 100644
--- a/fdts/tc-fvp.dtsi
+++ b/fdts/tc-fvp.dtsi
@@ -54,7 +54,7 @@
rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
};
@@ -62,7 +62,7 @@
kmi@1c060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
- interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
@@ -70,7 +70,7 @@
kmi@1c070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c070000 0x0 0x1000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
@@ -79,6 +79,6 @@
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
/* spec lists this wrong */
- interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
};
};
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index 4946aca..ae37ce3 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -31,6 +31,10 @@
#define MHU_RX_INT_NUM 317
#define MHU_RX_INT_NAME "mhu_rx"
+#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
+#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
+#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
+
#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
#define UARTCLK_FREQ 5000000
@@ -193,22 +197,10 @@
};
#endif /* TARGET_FLAVOUR_FPGA */
- cpu-pmu {
-#if TARGET_FLAVOUR_FPGA
- interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
- <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>,
- <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
- <&CPU12>, <&CPU13>;
-#else
- interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
- <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
-#endif
- };
-
cmn-pmu {
compatible = "arm,ci-700";
reg = <0x0 0x50000000 0x0 0x10000000>;
- interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>;
};
mbox_db_rx: mhu@MHU_RX_ADDR {
@@ -237,6 +229,36 @@
};
};
+ gic: interrupt-controller@GIC_CTRL_ADDR {
+ ppi-partitions {
+ ppi_partition_little: interrupt-partition-0 {
+ affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
+ };
+
+#if TARGET_FLAVOUR_FVP
+ ppi_partition_mid: interrupt-partition-1 {
+ affinity = <&CPU4>, <&CPU5>, <&CPU6>;
+ };
+
+ ppi_partition_big: interrupt-partition-2 {
+ affinity = <&CPU7>;
+ };
+#elif TARGET_FLAVOUR_FPGA
+ ppi_partition_mid: interrupt-partition-1 {
+ affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, <&CPU8>;
+ };
+
+ ppi_partition_big: interrupt-partition-2 {
+ affinity = <&CPU9>, <&CPU10>, <&CPU11>, <&CPU12>, <&CPU13>;
+ };
+#endif
+ };
+ };
+
+ spe-pmu-big {
+ status = "okay";
+ };
+
smmu_700: iommu@3f000000 {
status = "okay";
};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index 71b3cb1..58c8edc 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -25,6 +25,10 @@
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"
+#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
+#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
+#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
+
#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
@@ -67,11 +71,6 @@
};
};
- cpu-pmu {
- interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
- <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
- };
-
cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
@@ -92,11 +91,24 @@
reg = <0x0 MCN_PMU_ADDR(3) 0x0 0xffc>;
};
+ spe-pmu-mid {
+ status = "okay";
+ };
+
+ spe-pmu-big {
+ status = "okay";
+ };
+
dsu-pmu {
compatible = "arm,dsu-pmu";
cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
+ ni-pmu {
+ compatible = "arm,ni-tower";
+ reg = <0x0 0x4f000000 0x0 0x4000000>;
+ };
+
sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
@@ -111,6 +123,22 @@
};
};
+ gic: interrupt-controller@GIC_CTRL_ADDR {
+ ppi-partitions {
+ ppi_partition_little: interrupt-partition-0 {
+ affinity = <&CPU0>, <&CPU1>;
+ };
+
+ ppi_partition_mid: interrupt-partition-1 {
+ affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
+ };
+
+ ppi_partition_big: interrupt-partition-2 {
+ affinity = <&CPU6>, <&CPU7>;
+ };
+ };
+ };
+
#if TARGET_FLAVOUR_FVP
smmu_700: iommu@3f000000 {
status = "okay";
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index 8e39529..abe34a4 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -16,6 +16,7 @@
((unsigned int)(((reg) >> (feat)) & mask))
#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
+__attribute__((always_inline)) \
static inline bool is_ ## name ## _supported(void) \
{ \
if ((guard) == FEAT_STATE_DISABLED) { \
@@ -28,6 +29,7 @@
}
#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+__attribute__((always_inline)) \
static inline bool is_ ## name ## _present(void) \
{ \
return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
@@ -68,6 +70,7 @@
*/
/* GENTIMER */
+__attribute__((always_inline))
static inline bool is_armv7_gentimer_present(void)
{
return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER_SHIFT,
@@ -111,6 +114,7 @@
ID_DFR0_PERFMON_MASK, 3U)
/* FEAT_MTPMU */
+__attribute__((always_inline))
static inline bool is_feat_mtpmu_present(void)
{
unsigned int mtpmu = ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU_SHIFT,
@@ -124,39 +128,71 @@
* code. In fact, EL2 context switching is only needed for AArch64 (since
* there is no secure AArch32 EL2), so just disable these features here.
*/
+__attribute__((always_inline))
static inline bool is_feat_twed_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_ecv_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_ecv_v2_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_csv2_2_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_csv2_3_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_ras_supported(void) { return false; }
/* The following features are supported in AArch64 only. */
+__attribute__((always_inline))
static inline bool is_feat_vhe_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_sel2_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_fgt_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_tcr2_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_spe_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_rng_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_gcs_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_mte2_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_mpam_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_hcx_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_sve_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_brbe_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_trbe_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_nv2_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_sme_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_sme2_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_s2poe_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_s1poe_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_sxpoe_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_s2pie_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_s1pie_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_sxpie_supported(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_uao_present(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_nmi_present(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_ebep_present(void) { return false; }
+__attribute__((always_inline))
static inline bool is_feat_sebep_present(void) { return false; }
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index c63eec8..f03c9d5 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -16,6 +16,7 @@
((unsigned int)(((reg) >> (feat)) & mask))
#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
+__attribute__((always_inline)) \
static inline bool is_ ## name ## _supported(void) \
{ \
if ((guard) == FEAT_STATE_DISABLED) { \
@@ -28,6 +29,7 @@
}
#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+__attribute__((always_inline)) \
static inline bool is_ ## name ## _present(void) \
{ \
return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
@@ -134,6 +136,7 @@
* +----------------------------+
*/
+__attribute__((always_inline))
static inline bool is_armv7_gentimer_present(void)
{
/* The Generic Timer is always present in an ARMv8-A implementation */
@@ -162,6 +165,7 @@
(ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U)
/* PAUTH */
+__attribute__((always_inline))
static inline bool is_armv8_3_pauth_present(void)
{
uint64_t mask_id_aa64isar1 =
@@ -244,6 +248,7 @@
CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE)
+__attribute__((always_inline))
static inline bool is_feat_sxpoe_supported(void)
{
return is_feat_s1poe_supported() || is_feat_s2poe_supported();
@@ -257,6 +262,7 @@
CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE)
+__attribute__((always_inline))
static inline bool is_feat_sxpie_supported(void)
{
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
@@ -283,6 +289,7 @@
* 0x11: v1.1 Armv8.4 or later
*
*/
+__attribute__((always_inline))
static inline bool is_feat_mpam_present(void)
{
unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >>
@@ -398,6 +405,7 @@
* Function to get hardware granularity support
******************************************************************************/
+__attribute__((always_inline))
static inline bool is_feat_tgran4K_present(void)
{
unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
@@ -408,6 +416,7 @@
CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED)
+__attribute__((always_inline))
static inline bool is_feat_tgran64K_present(void)
{
unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
@@ -420,6 +429,7 @@
ID_AA64DFR0_PMUVER_MASK, 1U)
/* FEAT_MTPMU */
+__attribute__((always_inline))
static inline bool is_feat_mtpmu_present(void)
{
unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S
index 9f82399..b9b0e3d 100644
--- a/include/arch/aarch64/el2_common_macros.S
+++ b/include/arch/aarch64/el2_common_macros.S
@@ -408,7 +408,7 @@
* -----------------------------------------------------------
*/
isb
- ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1]
+ ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1]
msr sctlr_el1, x28
isb
msr tcr_el1, x29
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index b4c5c1b..60c5a0c 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -437,7 +437,7 @@
* -----------------------------------------------------------
*/
isb
- ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1]
+ ldp x28, x29, [sp, #CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1]
msr sctlr_el1, x28
isb
msr tcr_el1, x29
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index bfda31b..ca46eb1 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -150,6 +150,7 @@
/* GICD_TYPER shifts and masks */
#define TYPER_ESPI U(1 << 8)
#define TYPER_DVIS U(1 << 18)
+#define TYPER_LPIS U(1 << 17)
#define TYPER_ESPI_RANGE_MASK U(0x1f)
#define TYPER_ESPI_RANGE_SHIFT U(27)
#define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
index 633f173..b95cd32 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-ids.h
@@ -78,4 +78,13 @@
#define S32CC_CLK_A53_CORE_DIV2 S32CC_ARCH_CLK(4)
#define S32CC_CLK_A53_CORE_DIV10 S32CC_ARCH_CLK(5)
+/* XBAR clock*/
+#define S32CC_CLK_MC_CGM0_MUX0 S32CC_ARCH_CLK(6)
+#define S32CC_CLK_XBAR_2X S32CC_ARCH_CLK(7)
+#define S32CC_CLK_XBAR S32CC_ARCH_CLK(8)
+#define S32CC_CLK_XBAR_DIV2 S32CC_ARCH_CLK(9)
+#define S32CC_CLK_XBAR_DIV3 S32CC_ARCH_CLK(10)
+#define S32CC_CLK_XBAR_DIV4 S32CC_ARCH_CLK(11)
+#define S32CC_CLK_XBAR_DIV6 S32CC_ARCH_CLK(12)
+
#endif /* S32CC_CLK_IDS_H */
diff --git a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
index 41fc6f4..703713b 100644
--- a/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
+++ b/include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
@@ -17,6 +17,8 @@
s32cc_clk_t,
s32cc_pll_t,
s32cc_pll_out_div_t,
+ s32cc_dfs_t,
+ s32cc_dfs_div_t,
s32cc_clkmux_t,
s32cc_shared_clkmux_t,
s32cc_fixed_div_t,
@@ -27,6 +29,8 @@
S32CC_FXOSC,
S32CC_SIRC,
S32CC_ARM_PLL,
+ S32CC_ARM_DFS,
+ S32CC_CGM0,
S32CC_CGM1,
};
@@ -122,6 +126,38 @@
.index = (INDEX), \
}
+struct s32cc_dfs {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *parent;
+ enum s32cc_clk_source instance;
+ uintptr_t base;
+};
+
+#define S32CC_DFS_INIT(PARENT, INSTANCE) \
+{ \
+ .desc = { \
+ .type = s32cc_dfs_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .instance = (INSTANCE), \
+}
+
+struct s32cc_dfs_div {
+ struct s32cc_clk_obj desc;
+ struct s32cc_clk_obj *parent;
+ uint32_t index;
+ unsigned long freq;
+};
+
+#define S32CC_DFS_DIV_INIT(PARENT, INDEX) \
+{ \
+ .desc = { \
+ .type = s32cc_dfs_div_t, \
+ }, \
+ .parent = &(PARENT).desc, \
+ .index = (INDEX), \
+}
+
struct s32cc_fixed_div {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *parent;
@@ -151,22 +187,26 @@
size_t n_clks;
};
-#define S32CC_FREQ_MODULE(PARENT_MODULE, MIN_F, MAX_F) \
-{ \
- .desc = { \
- .type = s32cc_clk_t, \
- }, \
- .module = &(PARENT_MODULE).desc, \
- .min_freq = (MIN_F), \
- .max_freq = (MAX_F), \
+#define S32CC_FREQ_CLK(PARENT_MODULE, PARENT, MIN_F, MAX_F) \
+{ \
+ .desc = { \
+ .type = s32cc_clk_t, \
+ }, \
+ .pclock = (PARENT), \
+ .module = (PARENT_MODULE), \
+ .min_freq = (MIN_F), \
+ .max_freq = (MAX_F), \
}
#define S32CC_FREQ_MODULE_CLK(PARENT_MODULE, MIN_F, MAX_F) \
- S32CC_FREQ_MODULE(PARENT_MODULE, MIN_F, MAX_F)
+ S32CC_FREQ_CLK(&(PARENT_MODULE).desc, NULL, MIN_F, MAX_F)
#define S32CC_MODULE_CLK(PARENT_MODULE) \
S32CC_FREQ_MODULE_CLK(PARENT_MODULE, 0, 0)
+#define S32CC_CHILD_CLK(PARENT, MIN_F, MAX_F) \
+ S32CC_FREQ_CLK(NULL, &(PARENT), MIN_F, MAX_F)
+
static inline struct s32cc_osc *s32cc_obj2osc(const struct s32cc_clk_obj *mod)
{
uintptr_t osc_addr;
@@ -237,4 +277,20 @@
return (struct s32cc_fixed_div *)fdiv_addr;
}
+static inline struct s32cc_dfs *s32cc_obj2dfs(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t dfs_addr;
+
+ dfs_addr = ((uintptr_t)mod) - offsetof(struct s32cc_dfs, desc);
+ return (struct s32cc_dfs *)dfs_addr;
+}
+
+static inline struct s32cc_dfs_div *s32cc_obj2dfsdiv(const struct s32cc_clk_obj *mod)
+{
+ uintptr_t dfs_div_addr;
+
+ dfs_div_addr = ((uintptr_t)mod) - offsetof(struct s32cc_dfs_div, desc);
+ return (struct s32cc_dfs_div *)dfs_div_addr;
+}
+
#endif /* S32CC_CLK_MODULES_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index acf111b..7c10506 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -7,6 +7,7 @@
#ifndef CONTEXT_H
#define CONTEXT_H
+#include <lib/el3_runtime/context_el1.h>
#include <lib/el3_runtime/context_el2.h>
#include <lib/el3_runtime/cpu_data.h>
#include <lib/utils_def.h>
@@ -82,151 +83,10 @@
#endif /* FFH_SUPPORT */
/*******************************************************************************
- * Constants that allow assembler code to access members of and the
- * 'el1_sys_regs' structure at their correct offsets. Note that some of the
- * registers are only 32-bits wide but are stored as 64-bit values for
- * convenience
- ******************************************************************************/
-#define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
-#define CTX_SPSR_EL1 U(0x0)
-#define CTX_ELR_EL1 U(0x8)
-#define CTX_SCTLR_EL1 U(0x10)
-#define CTX_TCR_EL1 U(0x18)
-#define CTX_CPACR_EL1 U(0x20)
-#define CTX_CSSELR_EL1 U(0x28)
-#define CTX_SP_EL1 U(0x30)
-#define CTX_ESR_EL1 U(0x38)
-#define CTX_TTBR0_EL1 U(0x40)
-#define CTX_TTBR1_EL1 U(0x48)
-#define CTX_MAIR_EL1 U(0x50)
-#define CTX_AMAIR_EL1 U(0x58)
-#define CTX_ACTLR_EL1 U(0x60)
-#define CTX_TPIDR_EL1 U(0x68)
-#define CTX_TPIDR_EL0 U(0x70)
-#define CTX_TPIDRRO_EL0 U(0x78)
-#define CTX_PAR_EL1 U(0x80)
-#define CTX_FAR_EL1 U(0x88)
-#define CTX_AFSR0_EL1 U(0x90)
-#define CTX_AFSR1_EL1 U(0x98)
-#define CTX_CONTEXTIDR_EL1 U(0xa0)
-#define CTX_VBAR_EL1 U(0xa8)
-#define CTX_MDCCINT_EL1 U(0xb0)
-#define CTX_MDSCR_EL1 U(0xb8)
-
-#define CTX_AARCH64_END U(0xc0) /* Align to the next 16 byte boundary */
-
-/*
- * If the platform is AArch64-only, there is no need to save and restore these
- * AArch32 registers.
- */
-#if CTX_INCLUDE_AARCH32_REGS
-#define CTX_SPSR_ABT (CTX_AARCH64_END + U(0x0))
-#define CTX_SPSR_UND (CTX_AARCH64_END + U(0x8))
-#define CTX_SPSR_IRQ (CTX_AARCH64_END + U(0x10))
-#define CTX_SPSR_FIQ (CTX_AARCH64_END + U(0x18))
-#define CTX_DACR32_EL2 (CTX_AARCH64_END + U(0x20))
-#define CTX_IFSR32_EL2 (CTX_AARCH64_END + U(0x28))
-#define CTX_AARCH32_END (CTX_AARCH64_END + U(0x30)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_AARCH32_END CTX_AARCH64_END
-#endif /* CTX_INCLUDE_AARCH32_REGS */
-
-/*
- * If the timer registers aren't saved and restored, we don't have to reserve
- * space for them in the context
- */
-#if NS_TIMER_SWITCH
-#define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0))
-#define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8))
-#define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10))
-#define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18))
-#define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20))
-#define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_TIMER_SYSREGS_END CTX_AARCH32_END
-#endif /* NS_TIMER_SWITCH */
-
-#if ENABLE_FEAT_MTE2
-#define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0))
-#define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8))
-#define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10))
-#define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18))
-#define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END
-#endif /* ENABLE_FEAT_MTE2 */
-
-#if ENABLE_FEAT_RAS
-#define CTX_DISR_EL1 (CTX_MTE_REGS_END + U(0x0))
-#define CTX_RAS_REGS_END (CTX_MTE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_RAS_REGS_END CTX_MTE_REGS_END
-#endif /* ENABLE_FEAT_RAS */
-
-#if ENABLE_FEAT_S1PIE
-#define CTX_PIRE0_EL1 (CTX_RAS_REGS_END + U(0x0))
-#define CTX_PIR_EL1 (CTX_RAS_REGS_END + U(0x8))
-#define CTX_S1PIE_REGS_END (CTX_RAS_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_S1PIE_REGS_END CTX_RAS_REGS_END
-#endif /* ENABLE_FEAT_S1PIE */
-
-#if ENABLE_FEAT_S1POE
-#define CTX_POR_EL1 (CTX_S1PIE_REGS_END + U(0x0))
-#define CTX_S1POE_REGS_END (CTX_S1PIE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_S1POE_REGS_END CTX_S1PIE_REGS_END
-#endif /* ENABLE_FEAT_S1POE */
-
-#if ENABLE_FEAT_S2POE
-#define CTX_S2POR_EL1 (CTX_S1POE_REGS_END + U(0x0))
-#define CTX_S2POE_REGS_END (CTX_S1POE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_S2POE_REGS_END CTX_S1POE_REGS_END
-#endif /* ENABLE_FEAT_S2POE */
-
-#if ENABLE_FEAT_TCR2
-#define CTX_TCR2_EL1 (CTX_S2POE_REGS_END + U(0x0))
-#define CTX_TCR2_REGS_END (CTX_S2POE_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_TCR2_REGS_END CTX_S2POE_REGS_END
-#endif /* ENABLE_FEAT_TCR2 */
-
-#if ENABLE_TRF_FOR_NS
-#define CTX_TRFCR_EL1 (CTX_TCR2_REGS_END + U(0x0))
-#define CTX_TRF_REGS_END (CTX_TCR2_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_TRF_REGS_END CTX_TCR2_REGS_END
-#endif /* ENABLE_TRF_FOR_NS */
-
-#if ENABLE_FEAT_CSV2_2
-#define CTX_SCXTNUM_EL0 (CTX_TRF_REGS_END + U(0x0))
-#define CTX_SCXTNUM_EL1 (CTX_TRF_REGS_END + U(0x8))
-#define CTX_CSV2_2_REGS_END (CTX_TRF_REGS_END + U(0x10)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_CSV2_2_REGS_END CTX_TRF_REGS_END
-#endif /* ENABLE_FEAT_CSV2_2 */
-
-#if ENABLE_FEAT_GCS
-#define CTX_GCSCR_EL1 (CTX_CSV2_2_REGS_END + U(0x0))
-#define CTX_GCSCRE0_EL1 (CTX_CSV2_2_REGS_END + U(0x8))
-#define CTX_GCSPR_EL1 (CTX_CSV2_2_REGS_END + U(0x10))
-#define CTX_GCSPR_EL0 (CTX_CSV2_2_REGS_END + U(0x18))
-#define CTX_GCS_REGS_END (CTX_CSV2_2_REGS_END + U(0x20)) /* Align to the next 16 byte boundary */
-#else
-#define CTX_GCS_REGS_END CTX_CSV2_2_REGS_END
-#endif /* ENABLE_FEAT_GCS */
-
-/*
- * End of EL1 system registers.
- */
-#define CTX_EL1_SYSREGS_END CTX_GCS_REGS_END
-
-/*******************************************************************************
* Constants that allow assembler code to access members of and the 'fp_regs'
* structure at their correct offsets.
******************************************************************************/
-# define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END)
+# define CTX_FPREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
#if CTX_INCLUDE_FPREGS
#define CTX_FP_Q0 U(0x0)
#define CTX_FP_Q1 U(0x10)
@@ -280,9 +140,53 @@
#define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */
/*******************************************************************************
+ * Registers related to ERRATA_SPECULATIVE_AT
+ *
+ * This is essential as with EL1 and EL2 context registers being decoupled,
+ * both will not be present for a given build configuration.
+ * As ERRATA_SPECULATIVE_AT errata requires SCTLR_EL1 and TCR_EL1 registers
+ * independent of the above logic, we need explicit context entries to be
+ * reserved for these registers.
+ *
+ * NOTE: Based on this we end up with following different configurations depending
+ * on the presence of errata and inclusion of EL1 or EL2 context.
+ *
+ * ============================================================================
+ * | ERRATA_SPECULATIVE_AT | EL1 context| Memory allocation(Sctlr_el1,Tcr_el1)|
+ * ============================================================================
+ * | 0 | 0 | None |
+ * | 0 | 1 | EL1 C-Context structure |
+ * | 1 | 0 | Errata Context Offset Entries |
+ * | 1 | 1 | Errata Context Offset Entries |
+ * ============================================================================
+ *
+ * In the above table, when ERRATA_SPECULATIVE_AT=1, EL1_Context=0, it implies
+ * there is only EL2 context and memory for SCTLR_EL1 and TCR_EL1 registers is
+ * reserved explicitly under ERRATA_SPECULATIVE_AT build flag here.
+ *
+ * In situations when EL1_Context=1 and ERRATA_SPECULATIVE_AT=1, since SCTLR_EL1
+ * and TCR_EL1 registers will be modified under errata and it happens at the
+ * early in the codeflow prior to el1 context (save and restore operations),
+ * context memory still will be reserved under the errata logic here explicitly.
+ * These registers will not be part of EL1 context save & restore routines.
+ *
+ * Only when ERRATA_SPECULATIVE_AT=0, EL1_Context=1, for this combination,
+ * SCTLR_EL1 and TCR_EL1 will be part of EL1 context structure (context_el1.h)
+ * -----------------------------------------------------------------------------
+ ******************************************************************************/
+#define CTX_ERRATA_SPEC_AT_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END)
+#if ERRATA_SPECULATIVE_AT
+#define CTX_ERRATA_SPEC_AT_SCTLR_EL1 U(0x0)
+#define CTX_ERRATA_SPEC_AT_TCR_EL1 U(0x8)
+#define CTX_ERRATA_SPEC_AT_END U(0x10) /* Align to the next 16 byte boundary */
+#else
+#define CTX_ERRATA_SPEC_AT_END U(0x0)
+#endif /* ERRATA_SPECULATIVE_AT */
+
+/*******************************************************************************
* Registers related to ARMv8.3-PAuth.
******************************************************************************/
-#define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END)
+#define CTX_PAUTH_REGS_OFFSET (CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_END)
#if CTX_INCLUDE_PAUTH_REGS
#define CTX_PACIAKEY_LO U(0x0)
#define CTX_PACIAKEY_HI U(0x8)
@@ -325,13 +229,16 @@
/* Constants to determine the size of individual context structures */
#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
-#define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT)
#if CTX_INCLUDE_FPREGS
# define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
#endif
#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
#define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT)
+
+#if ERRATA_SPECULATIVE_AT
+#define CTX_ERRATA_SPEC_AT_ALL (CTX_ERRATA_SPEC_AT_END >> DWORD_SHIFT)
+#endif
#if CTX_INCLUDE_PAUTH_REGS
# define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT)
#endif
@@ -346,12 +253,6 @@
DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
/*
- * AArch64 EL1 system register context structure for preserving the
- * architectural state during world switches.
- */
-DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL);
-
-/*
* AArch64 floating point register context structure for preserving
* the floating point state during switches from one security state to
* another.
@@ -369,6 +270,11 @@
/* Function pointer used by CVE-2018-3639 dynamic mitigation */
DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL);
+/* Registers associated to Errata_Speculative */
+#if ERRATA_SPECULATIVE_AT
+DEFINE_REG_STRUCT(errata_speculative_at, CTX_ERRATA_SPEC_AT_ALL);
+#endif
+
/* Registers associated to ARMv8.3-PAuth */
#if CTX_INCLUDE_PAUTH_REGS
DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL);
@@ -393,17 +299,22 @@
typedef struct cpu_context {
gp_regs_t gpregs_ctx;
el3_state_t el3state_ctx;
- el1_sysregs_t el1_sysregs_ctx;
#if CTX_INCLUDE_FPREGS
fp_regs_t fpregs_ctx;
#endif
cve_2018_3639_t cve_2018_3639_ctx;
+#if ERRATA_SPECULATIVE_AT
+ errata_speculative_at_t errata_speculative_at_ctx;
+#endif
+
#if CTX_INCLUDE_PAUTH_REGS
pauth_t pauth_ctx;
#endif
+ el1_sysregs_t el1_sysregs_ctx;
+
#if CTX_INCLUDE_EL2_REGS
el2_sysregs_t el2_sysregs_ctx;
#endif
@@ -433,6 +344,11 @@
#endif
#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
#define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx)
+
+#if ERRATA_SPECULATIVE_AT
+#define get_errata_speculative_at_ctx(h) (&((cpu_context_t *) h)->errata_speculative_at_ctx)
+#endif
+
#if CTX_INCLUDE_PAUTH_REGS
# define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx)
#endif
@@ -448,9 +364,6 @@
CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx),
assert_core_context_el3state_offset_mismatch);
-CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx),
- assert_core_context_el1_sys_offset_mismatch);
-
#if CTX_INCLUDE_FPREGS
CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx),
assert_core_context_fp_offset_mismatch);
@@ -459,6 +372,11 @@
CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx),
assert_core_context_cve_2018_3639_offset_mismatch);
+#if ERRATA_SPECULATIVE_AT
+CASSERT(CTX_ERRATA_SPEC_AT_OFFSET == __builtin_offsetof(cpu_context_t, errata_speculative_at_ctx),
+ assert_core_context_errata_speculative_at_offset_mismatch);
+#endif
+
#if CTX_INCLUDE_PAUTH_REGS
CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx),
assert_core_context_pauth_offset_mismatch);
diff --git a/include/lib/el3_runtime/context_el1.h b/include/lib/el3_runtime/context_el1.h
new file mode 100644
index 0000000..038de25
--- /dev/null
+++ b/include/lib/el3_runtime/context_el1.h
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CONTEXT_EL1_H
+#define CONTEXT_EL1_H
+
+#ifndef __ASSEMBLER__
+
+/*******************************************************************************
+ * EL1 Registers:
+ * AArch64 EL1 system register context structure for preserving the
+ * architectural state during world switches.
+ ******************************************************************************/
+
+typedef struct el1_common_regs {
+ uint64_t spsr_el1;
+ uint64_t elr_el1;
+
+#if (!ERRATA_SPECULATIVE_AT)
+ uint64_t sctlr_el1;
+ uint64_t tcr_el1;
+#endif /* ERRATA_SPECULATIVE_AT=0 */
+
+ uint64_t cpacr_el1;
+ uint64_t csselr_el1;
+ uint64_t sp_el1;
+ uint64_t esr_el1;
+ uint64_t ttbr0_el1;
+ uint64_t ttbr1_el1;
+ uint64_t mair_el1;
+ uint64_t amair_el1;
+ uint64_t actlr_el1;
+ uint64_t tpidr_el1;
+ uint64_t tpidr_el0;
+ uint64_t tpidrro_el0;
+ uint64_t par_el1;
+ uint64_t far_el1;
+ uint64_t afsr0_el1;
+ uint64_t afsr1_el1;
+ uint64_t contextidr_el1;
+ uint64_t vbar_el1;
+ uint64_t mdccint_el1;
+ uint64_t mdscr_el1;
+} el1_common_regs_t;
+
+typedef struct el1_aarch32_regs {
+ uint64_t spsr_abt;
+ uint64_t spsr_und;
+ uint64_t spsr_irq;
+ uint64_t spsr_fiq;
+ uint64_t dacr32_el2;
+ uint64_t ifsr32_el2;
+} el1_aarch32_regs_t;
+
+typedef struct el1_arch_timer_regs {
+ uint64_t cntp_ctl_el0;
+ uint64_t cntp_cval_el0;
+ uint64_t cntv_ctl_el0;
+ uint64_t cntv_cval_el0;
+ uint64_t cntkctl_el1;
+} el1_arch_timer_regs_t;
+
+typedef struct el1_mte2_regs {
+ uint64_t tfsre0_el1;
+ uint64_t tfsr_el1;
+ uint64_t rgsr_el1;
+ uint64_t gcr_el1;
+} el1_mte2_regs_t;
+
+typedef struct el1_ras_regs {
+ uint64_t disr_el1;
+} el1_ras_regs_t;
+
+typedef struct el1_s1pie_regs {
+ uint64_t pire0_el1;
+ uint64_t pir_el1;
+} el1_s1pie_regs_t;
+
+typedef struct el1_s1poe_regs {
+ uint64_t por_el1;
+} el1_s1poe_regs_t;
+
+typedef struct el1_s2poe_regs {
+ uint64_t s2por_el1;
+} el1_s2poe_regs_t;
+
+typedef struct el1_tcr2_regs {
+ uint64_t tcr2_el1;
+} el1_tcr2_regs_t;
+
+typedef struct el1_trf_regs {
+ uint64_t trfcr_el1;
+} el1_trf_regs_t;
+
+typedef struct el1_csv2_2_regs {
+ uint64_t scxtnum_el0;
+ uint64_t scxtnum_el1;
+} el1_csv2_2_regs_t;
+
+typedef struct el1_gcs_regs {
+ uint64_t gcscr_el1;
+ uint64_t gcscre0_el1;
+ uint64_t gcspr_el1;
+ uint64_t gcspr_el0;
+} el1_gcs_regs_t;
+
+typedef struct el1_sysregs {
+
+ el1_common_regs_t common;
+
+#if CTX_INCLUDE_AARCH32_REGS
+ el1_aarch32_regs_t el1_aarch32;
+#endif
+
+#if NS_TIMER_SWITCH
+ el1_arch_timer_regs_t arch_timer;
+#endif
+
+#if ENABLE_FEAT_MTE2
+ el1_mte2_regs_t mte2;
+#endif
+
+#if ENABLE_FEAT_RAS
+ el1_ras_regs_t ras;
+#endif
+
+#if ENABLE_FEAT_S1PIE
+ el1_s1pie_regs_t s1pie;
+#endif
+
+#if ENABLE_FEAT_S1POE
+ el1_s1poe_regs_t s1poe;
+#endif
+
+#if ENABLE_FEAT_S2POE
+ el1_s2poe_regs_t s2poe;
+#endif
+
+#if ENABLE_FEAT_TCR2
+ el1_tcr2_regs_t tcr2;
+#endif
+
+#if ENABLE_TRF_FOR_NS
+ el1_trf_regs_t trf;
+#endif
+
+#if ENABLE_FEAT_CSV2_2
+ el1_csv2_2_regs_t csv2_2;
+#endif
+
+#if ENABLE_FEAT_GCS
+ el1_gcs_regs_t gcs;
+#endif
+
+} el1_sysregs_t;
+
+
+/*
+ * Macros to access members related to individual features of the el1_sysregs_t
+ * structures.
+ */
+
+#define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg)
+
+#define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \
+ = (uint64_t) (val))
+
+#if NS_TIMER_SWITCH
+#define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg)
+#define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_arch_timer(ctx, reg) ULL(0)
+#define write_el1_ctx_arch_timer(ctx, reg, val)
+#endif /* NS_TIMER_SWITCH */
+
+#if CTX_INCLUDE_AARCH32_REGS
+#define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg)
+#define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_aarch32(ctx, reg) ULL(0)
+#define write_el1_ctx_aarch32(ctx, reg, val)
+#endif /* CTX_INCLUDE_AARCH32_REGS */
+
+#if ENABLE_FEAT_MTE2
+#define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg)
+#define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_mte2(ctx, reg) ULL(0)
+#define write_el1_ctx_mte2(ctx, reg, val)
+#endif /* ENABLE_FEAT_MTE2 */
+
+#if ENABLE_FEAT_RAS
+#define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg)
+#define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_ras(ctx, reg) ULL(0)
+#define write_el1_ctx_ras(ctx, reg, val)
+#endif /* ENABLE_FEAT_RAS */
+
+#if ENABLE_FEAT_S1PIE
+#define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg)
+#define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_s1pie(ctx, reg) ULL(0)
+#define write_el1_ctx_s1pie(ctx, reg, val)
+#endif /* ENABLE_FEAT_S1PIE */
+
+#if ENABLE_FEAT_S1POE
+#define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg)
+#define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_s1poe(ctx, reg) ULL(0)
+#define write_el1_ctx_s1poe(ctx, reg, val)
+#endif /* ENABLE_FEAT_S1POE */
+
+#if ENABLE_FEAT_S2POE
+#define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg)
+#define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_s2poe(ctx, reg) ULL(0)
+#define write_el1_ctx_s2poe(ctx, reg, val)
+#endif /* ENABLE_FEAT_S2POE */
+
+#if ENABLE_FEAT_TCR2
+#define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg)
+#define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_tcr2(ctx, reg) ULL(0)
+#define write_el1_ctx_tcr2(ctx, reg, val)
+#endif /* ENABLE_FEAT_TCR2 */
+
+#if ENABLE_TRF_FOR_NS
+#define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg)
+#define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_trf(ctx, reg) ULL(0)
+#define write_el1_ctx_trf(ctx, reg, val)
+#endif /* ENABLE_TRF_FOR_NS */
+
+#if ENABLE_FEAT_CSV2_2
+#define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg)
+#define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_csv2_2(ctx, reg) ULL(0)
+#define write_el1_ctx_csv2_2(ctx, reg, val)
+#endif /* ENABLE_FEAT_CSV2_2 */
+
+#if ENABLE_FEAT_GCS
+#define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg)
+#define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_gcs(ctx, reg) ULL(0)
+#define write_el1_ctx_gcs(ctx, reg, val)
+#endif /* ENABLE_FEAT_GCS */
+/******************************************************************************/
+#endif /* __ASSEMBLER__ */
+
+#endif /* CONTEXT_EL1_H */
diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h
index c6e44f9..4801a22 100644
--- a/include/lib/extensions/spe.h
+++ b/include/lib/extensions/spe.h
@@ -12,16 +12,20 @@
#if ENABLE_SPE_FOR_NS
void spe_enable(cpu_context_t *ctx);
+void spe_disable(cpu_context_t *ctx);
void spe_init_el2_unused(void);
-void spe_disable(void);
+void spe_stop(void);
#else
static inline void spe_enable(cpu_context_t *ctx)
{
}
+static inline void spe_disable(cpu_context_t *ctx)
+{
+}
static inline void spe_init_el2_unused(void)
{
}
-static inline void spe_disable(void)
+static inline void spe_stop(void)
{
}
#endif /* ENABLE_SPE_FOR_NS */
diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h
index 5db3316..2c488e0 100644
--- a/include/lib/extensions/trbe.h
+++ b/include/lib/extensions/trbe.h
@@ -10,9 +10,13 @@
#include <context.h>
#if ENABLE_TRBE_FOR_NS
+void trbe_disable(cpu_context_t *ctx);
void trbe_enable(cpu_context_t *ctx);
void trbe_init_el2_unused(void);
#else
+static inline void trbe_disable(cpu_context_t *ctx)
+{
+}
static inline void trbe_enable(cpu_context_t *ctx)
{
}
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
index cb11dac..43a77e3 100644
--- a/include/plat/arm/board/common/v2m_def.h
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -17,6 +17,7 @@
/* V2M motherboard system registers & offsets */
#define V2M_SYSREGS_BASE UL(0x1c010000)
+#define V2M_SYSREGS_SIZE UL(0x00010000)
#define V2M_SYS_ID UL(0x0)
#define V2M_SYS_SWITCH UL(0x4)
#define V2M_SYS_LED UL(0x8)
@@ -78,6 +79,8 @@
/* NOR Flash */
#define V2M_FLASH0_BASE (V2M_OFFSET + UL(0x08000000))
#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH1_BASE (V2M_OFFSET + UL(0x0c000000))
+#define V2M_FLASH1_SIZE UL(0x04000000)
#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
#define V2M_IOFPGA_BASE (V2M_OFFSET + UL(0x1c000000))
@@ -126,6 +129,14 @@
V2M_FLASH0_SIZE, \
MT_RO_DATA | MT_SECURE)
+#define V2M_MAP_FLASH1_RW MAP_REGION_FLAT(V2M_FLASH1_BASE,\
+ V2M_FLASH1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define V2M_MAP_FLASH1_RO MAP_REGION_FLAT(V2M_FLASH1_BASE,\
+ V2M_FLASH1_SIZE, \
+ MT_RO_DATA | MT_SECURE)
+
#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
V2M_IOFPGA_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
@@ -136,5 +147,19 @@
V2M_IOFPGA_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#define V2M_MAP_SECURE_SYSTEMREG_EL0 MAP_REGION_FLAT( \
+ V2M_SYSREGS_BASE, \
+ V2M_SYSREGS_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define V2M_MAP_FLASH0_RW_EL0 MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define V2M_MAP_FLASH1_RW_EL0 MAP_REGION_FLAT( \
+ V2M_FLASH1_BASE, \
+ V2M_FLASH1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
#endif /* V2M_DEF_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index ba8df2a..83a5cd2 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -284,10 +284,7 @@
/* Firmware Handoff utility functions */
void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl);
void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node,
- struct transfer_list_header *secure_tl,
- struct transfer_list_header *ns_tl);
-void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl,
- struct transfer_list_header *ns_tl);
+ struct transfer_list_header *secure_tl);
/* TSP utility functions */
void arm_tsp_early_platform_setup(void);
@@ -365,6 +362,7 @@
void plat_arm_interconnect_exit_coherency(void);
void plat_arm_program_trusted_mailbox(uintptr_t address);
bool plat_arm_bl1_fwu_needed(void);
+int plat_arm_ni_setup(uintptr_t global_cfg);
__dead2 void plat_arm_error_handler(int err);
__dead2 void plat_arm_system_reset(void);
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 1fce1bf..62895ff 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -14,9 +14,13 @@
.global fpregs_context_save
.global fpregs_context_restore
#endif /* CTX_INCLUDE_FPREGS */
+
+#if ERRATA_SPECULATIVE_AT
+ .global save_and_update_ptw_el1_sys_regs
+#endif /* ERRATA_SPECULATIVE_AT */
+
.global prepare_el3_entry
.global restore_gp_pmcr_pauth_regs
- .global save_and_update_ptw_el1_sys_regs
.global el3_exit
/* ------------------------------------------------------------------
@@ -329,10 +333,12 @@
ret
endfunc restore_gp_pmcr_pauth_regs
-/*
+#if ERRATA_SPECULATIVE_AT
+/* --------------------------------------------------------------------
* In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1
* registers and update EL1 registers to disable stage1 and stage2
- * page table walk
+ * page table walk.
+ * --------------------------------------------------------------------
*/
func save_and_update_ptw_el1_sys_regs
/* ----------------------------------------------------------
@@ -340,9 +346,9 @@
* ----------------------------------------------------------
*/
mrs x29, sctlr_el1
- str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1)]
+ str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_SCTLR_EL1)]
mrs x29, tcr_el1
- str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_TCR_EL1)]
+ str x29, [sp, #(CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_TCR_EL1)]
/* ------------------------------------------------------------
* Must follow below order in order to disable page table
@@ -367,10 +373,11 @@
orr x29, x29, #SCTLR_M_BIT
msr sctlr_el1, x29
isb
-
ret
endfunc save_and_update_ptw_el1_sys_regs
+#endif /* ERRATA_SPECULATIVE_AT */
+
/* -----------------------------------------------------------------
* The below macro returns the address of the per_world context for
* the security state, retrieved through "get_security_state" macro.
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index c525247..15db9e5 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -92,8 +92,13 @@
*/
sctlr_elx |= SCTLR_IESB_BIT;
#endif
+
/* Store the initialised SCTLR_EL1 value in the cpu_context */
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
+#if (ERRATA_SPECULATIVE_AT)
+ write_ctx_reg(get_errata_speculative_at_ctx(ctx), CTX_ERRATA_SPEC_AT_SCTLR_EL1, sctlr_elx);
+#else
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1, sctlr_elx);
+#endif /* ERRATA_SPECULATIVE_AT */
/*
* Base the context ACTLR_EL1 on the current value, as it is
@@ -103,7 +108,7 @@
* be zero.
*/
actlr_elx = read_actlr_el1();
- write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx);
}
/******************************************************************************
@@ -1548,220 +1553,192 @@
static void el1_sysregs_context_save(el1_sysregs_t *ctx)
{
- write_ctx_reg(ctx, CTX_SPSR_EL1, read_spsr_el1());
- write_ctx_reg(ctx, CTX_ELR_EL1, read_elr_el1());
+ write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1());
+ write_el1_ctx_common(ctx, elr_el1, read_elr_el1());
-#if !ERRATA_SPECULATIVE_AT
- write_ctx_reg(ctx, CTX_SCTLR_EL1, read_sctlr_el1());
- write_ctx_reg(ctx, CTX_TCR_EL1, read_tcr_el1());
+#if (!ERRATA_SPECULATIVE_AT)
+ write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1());
+ write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1());
#endif /* (!ERRATA_SPECULATIVE_AT) */
- write_ctx_reg(ctx, CTX_CPACR_EL1, read_cpacr_el1());
- write_ctx_reg(ctx, CTX_CSSELR_EL1, read_csselr_el1());
- write_ctx_reg(ctx, CTX_SP_EL1, read_sp_el1());
- write_ctx_reg(ctx, CTX_ESR_EL1, read_esr_el1());
- write_ctx_reg(ctx, CTX_TTBR0_EL1, read_ttbr0_el1());
- write_ctx_reg(ctx, CTX_TTBR1_EL1, read_ttbr1_el1());
- write_ctx_reg(ctx, CTX_MAIR_EL1, read_mair_el1());
- write_ctx_reg(ctx, CTX_AMAIR_EL1, read_amair_el1());
- write_ctx_reg(ctx, CTX_ACTLR_EL1, read_actlr_el1());
- write_ctx_reg(ctx, CTX_TPIDR_EL1, read_tpidr_el1());
- write_ctx_reg(ctx, CTX_TPIDR_EL0, read_tpidr_el0());
- write_ctx_reg(ctx, CTX_TPIDRRO_EL0, read_tpidrro_el0());
- write_ctx_reg(ctx, CTX_PAR_EL1, read_par_el1());
- write_ctx_reg(ctx, CTX_FAR_EL1, read_far_el1());
- write_ctx_reg(ctx, CTX_AFSR0_EL1, read_afsr0_el1());
- write_ctx_reg(ctx, CTX_AFSR1_EL1, read_afsr1_el1());
- write_ctx_reg(ctx, CTX_CONTEXTIDR_EL1, read_contextidr_el1());
- write_ctx_reg(ctx, CTX_VBAR_EL1, read_vbar_el1());
- write_ctx_reg(ctx, CTX_MDCCINT_EL1, read_mdccint_el1());
- write_ctx_reg(ctx, CTX_MDSCR_EL1, read_mdscr_el1());
+ write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1());
+ write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1());
+ write_el1_ctx_common(ctx, sp_el1, read_sp_el1());
+ write_el1_ctx_common(ctx, esr_el1, read_esr_el1());
+ write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1());
+ write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1());
+ write_el1_ctx_common(ctx, mair_el1, read_mair_el1());
+ write_el1_ctx_common(ctx, amair_el1, read_amair_el1());
+ write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1());
+ write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1());
+ write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0());
+ write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0());
+ write_el1_ctx_common(ctx, par_el1, read_par_el1());
+ write_el1_ctx_common(ctx, far_el1, read_far_el1());
+ write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1());
+ write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1());
+ write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1());
+ write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1());
+ write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1());
+ write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1());
-#if CTX_INCLUDE_AARCH32_REGS
- write_ctx_reg(ctx, CTX_SPSR_ABT, read_spsr_abt());
- write_ctx_reg(ctx, CTX_SPSR_UND, read_spsr_und());
- write_ctx_reg(ctx, CTX_SPSR_IRQ, read_spsr_irq());
- write_ctx_reg(ctx, CTX_SPSR_FIQ, read_spsr_fiq());
- write_ctx_reg(ctx, CTX_DACR32_EL2, read_dacr32_el2());
- write_ctx_reg(ctx, CTX_IFSR32_EL2, read_ifsr32_el2());
-#endif /* CTX_INCLUDE_AARCH32_REGS */
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ /* Save Aarch32 registers */
+ write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt());
+ write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und());
+ write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq());
+ write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq());
+ write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2());
+ write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2());
+ }
-#if NS_TIMER_SWITCH
- write_ctx_reg(ctx, CTX_CNTP_CTL_EL0, read_cntp_ctl_el0());
- write_ctx_reg(ctx, CTX_CNTP_CVAL_EL0, read_cntp_cval_el0());
- write_ctx_reg(ctx, CTX_CNTV_CTL_EL0, read_cntv_ctl_el0());
- write_ctx_reg(ctx, CTX_CNTV_CVAL_EL0, read_cntv_cval_el0());
- write_ctx_reg(ctx, CTX_CNTKCTL_EL1, read_cntkctl_el1());
-#endif /* NS_TIMER_SWITCH */
+ if (NS_TIMER_SWITCH) {
+ /* Save NS Timer registers */
+ write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0());
+ write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0());
+ write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0());
+ write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0());
+ write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1());
+ }
-#if ENABLE_FEAT_MTE2
- write_ctx_reg(ctx, CTX_TFSRE0_EL1, read_tfsre0_el1());
- write_ctx_reg(ctx, CTX_TFSR_EL1, read_tfsr_el1());
- write_ctx_reg(ctx, CTX_RGSR_EL1, read_rgsr_el1());
- write_ctx_reg(ctx, CTX_GCR_EL1, read_gcr_el1());
-#endif /* ENABLE_FEAT_MTE2 */
+ if (is_feat_mte2_supported()) {
+ write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1());
+ write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1());
+ write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1());
+ write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1());
+ }
-#if ENABLE_FEAT_RAS
if (is_feat_ras_supported()) {
- write_ctx_reg(ctx, CTX_DISR_EL1, read_disr_el1());
+ write_el1_ctx_ras(ctx, disr_el1, read_disr_el1());
}
-#endif
-#if ENABLE_FEAT_S1PIE
if (is_feat_s1pie_supported()) {
- write_ctx_reg(ctx, CTX_PIRE0_EL1, read_pire0_el1());
- write_ctx_reg(ctx, CTX_PIR_EL1, read_pir_el1());
+ write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1());
+ write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1());
}
-#endif
-#if ENABLE_FEAT_S1POE
if (is_feat_s1poe_supported()) {
- write_ctx_reg(ctx, CTX_POR_EL1, read_por_el1());
+ write_el1_ctx_s1poe(ctx, por_el1, read_por_el1());
}
-#endif
-#if ENABLE_FEAT_S2POE
if (is_feat_s2poe_supported()) {
- write_ctx_reg(ctx, CTX_S2POR_EL1, read_s2por_el1());
+ write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1());
}
-#endif
-#if ENABLE_FEAT_TCR2
if (is_feat_tcr2_supported()) {
- write_ctx_reg(ctx, CTX_TCR2_EL1, read_tcr2_el1());
+ write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1());
}
-#endif
-#if ENABLE_TRF_FOR_NS
if (is_feat_trf_supported()) {
- write_ctx_reg(ctx, CTX_TRFCR_EL1, read_trfcr_el1());
+ write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1());
}
-#endif
-#if ENABLE_FEAT_CSV2_2
if (is_feat_csv2_2_supported()) {
- write_ctx_reg(ctx, CTX_SCXTNUM_EL0, read_scxtnum_el0());
- write_ctx_reg(ctx, CTX_SCXTNUM_EL1, read_scxtnum_el1());
+ write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0());
+ write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1());
}
-#endif
-#if ENABLE_FEAT_GCS
if (is_feat_gcs_supported()) {
- write_ctx_reg(ctx, CTX_GCSCR_EL1, read_gcscr_el1());
- write_ctx_reg(ctx, CTX_GCSCRE0_EL1, read_gcscre0_el1());
- write_ctx_reg(ctx, CTX_GCSPR_EL1, read_gcspr_el1());
- write_ctx_reg(ctx, CTX_GCSPR_EL0, read_gcspr_el0());
+ write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1());
+ write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1());
+ write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1());
+ write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0());
}
-#endif
}
static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
{
- write_spsr_el1(read_ctx_reg(ctx, CTX_SPSR_EL1));
- write_elr_el1(read_ctx_reg(ctx, CTX_ELR_EL1));
+ write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1));
+ write_elr_el1(read_el1_ctx_common(ctx, elr_el1));
-#if !ERRATA_SPECULATIVE_AT
- write_sctlr_el1(read_ctx_reg(ctx, CTX_SCTLR_EL1));
- write_tcr_el1(read_ctx_reg(ctx, CTX_TCR_EL1));
+#if (!ERRATA_SPECULATIVE_AT)
+ write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1));
+ write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1));
#endif /* (!ERRATA_SPECULATIVE_AT) */
- write_cpacr_el1(read_ctx_reg(ctx, CTX_CPACR_EL1));
- write_csselr_el1(read_ctx_reg(ctx, CTX_CSSELR_EL1));
- write_sp_el1(read_ctx_reg(ctx, CTX_SP_EL1));
- write_esr_el1(read_ctx_reg(ctx, CTX_ESR_EL1));
- write_ttbr0_el1(read_ctx_reg(ctx, CTX_TTBR0_EL1));
- write_ttbr1_el1(read_ctx_reg(ctx, CTX_TTBR1_EL1));
- write_mair_el1(read_ctx_reg(ctx, CTX_MAIR_EL1));
- write_amair_el1(read_ctx_reg(ctx, CTX_AMAIR_EL1));
- write_actlr_el1(read_ctx_reg(ctx, CTX_ACTLR_EL1));
- write_tpidr_el1(read_ctx_reg(ctx, CTX_TPIDR_EL1));
- write_tpidr_el0(read_ctx_reg(ctx, CTX_TPIDR_EL0));
- write_tpidrro_el0(read_ctx_reg(ctx, CTX_TPIDRRO_EL0));
- write_par_el1(read_ctx_reg(ctx, CTX_PAR_EL1));
- write_far_el1(read_ctx_reg(ctx, CTX_FAR_EL1));
- write_afsr0_el1(read_ctx_reg(ctx, CTX_AFSR0_EL1));
- write_afsr1_el1(read_ctx_reg(ctx, CTX_AFSR1_EL1));
- write_contextidr_el1(read_ctx_reg(ctx, CTX_CONTEXTIDR_EL1));
- write_vbar_el1(read_ctx_reg(ctx, CTX_VBAR_EL1));
- write_mdccint_el1(read_ctx_reg(ctx, CTX_MDCCINT_EL1));
- write_mdscr_el1(read_ctx_reg(ctx, CTX_MDSCR_EL1));
+ write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1));
+ write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1));
+ write_sp_el1(read_el1_ctx_common(ctx, sp_el1));
+ write_esr_el1(read_el1_ctx_common(ctx, esr_el1));
+ write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1));
+ write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1));
+ write_mair_el1(read_el1_ctx_common(ctx, mair_el1));
+ write_amair_el1(read_el1_ctx_common(ctx, amair_el1));
+ write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1));
+ write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1));
+ write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0));
+ write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0));
+ write_par_el1(read_el1_ctx_common(ctx, par_el1));
+ write_far_el1(read_el1_ctx_common(ctx, far_el1));
+ write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1));
+ write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1));
+ write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1));
+ write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1));
+ write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1));
+ write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1));
-#if CTX_INCLUDE_AARCH32_REGS
- write_spsr_abt(read_ctx_reg(ctx, CTX_SPSR_ABT));
- write_spsr_und(read_ctx_reg(ctx, CTX_SPSR_UND));
- write_spsr_irq(read_ctx_reg(ctx, CTX_SPSR_IRQ));
- write_spsr_fiq(read_ctx_reg(ctx, CTX_SPSR_FIQ));
- write_dacr32_el2(read_ctx_reg(ctx, CTX_DACR32_EL2));
- write_ifsr32_el2(read_ctx_reg(ctx, CTX_IFSR32_EL2));
-#endif /* CTX_INCLUDE_AARCH32_REGS */
+ if (CTX_INCLUDE_AARCH32_REGS) {
+ /* Restore Aarch32 registers */
+ write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt));
+ write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und));
+ write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq));
+ write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq));
+ write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2));
+ write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2));
+ }
-#if NS_TIMER_SWITCH
- write_cntp_ctl_el0(read_ctx_reg(ctx, CTX_CNTP_CTL_EL0));
- write_cntp_cval_el0(read_ctx_reg(ctx, CTX_CNTP_CVAL_EL0));
- write_cntv_ctl_el0(read_ctx_reg(ctx, CTX_CNTV_CTL_EL0));
- write_cntv_cval_el0(read_ctx_reg(ctx, CTX_CNTV_CVAL_EL0));
- write_cntkctl_el1(read_ctx_reg(ctx, CTX_CNTKCTL_EL1));
-#endif /* NS_TIMER_SWITCH */
+ if (NS_TIMER_SWITCH) {
+ /* Restore NS Timer registers */
+ write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0));
+ write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0));
+ write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0));
+ write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0));
+ write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1));
+ }
-#if ENABLE_FEAT_MTE2
- write_tfsre0_el1(read_ctx_reg(ctx, CTX_TFSRE0_EL1));
- write_tfsr_el1(read_ctx_reg(ctx, CTX_TFSR_EL1));
- write_rgsr_el1(read_ctx_reg(ctx, CTX_RGSR_EL1));
- write_gcr_el1(read_ctx_reg(ctx, CTX_GCR_EL1));
-#endif /* ENABLE_FEAT_MTE2 */
+ if (is_feat_mte2_supported()) {
+ write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1));
+ write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1));
+ write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1));
+ write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1));
+ }
-#if ENABLE_FEAT_RAS
if (is_feat_ras_supported()) {
- write_disr_el1(read_ctx_reg(ctx, CTX_DISR_EL1));
+ write_disr_el1(read_el1_ctx_ras(ctx, disr_el1));
}
-#endif
-#if ENABLE_FEAT_S1PIE
if (is_feat_s1pie_supported()) {
- write_pire0_el1(read_ctx_reg(ctx, CTX_PIRE0_EL1));
- write_pir_el1(read_ctx_reg(ctx, CTX_PIR_EL1));
+ write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1));
+ write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1));
}
-#endif
-#if ENABLE_FEAT_S1POE
if (is_feat_s1poe_supported()) {
- write_por_el1(read_ctx_reg(ctx, CTX_POR_EL1));
+ write_por_el1(read_el1_ctx_s1poe(ctx, por_el1));
}
-#endif
-#if ENABLE_FEAT_S2POE
if (is_feat_s2poe_supported()) {
- write_s2por_el1(read_ctx_reg(ctx, CTX_S2POR_EL1));
+ write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1));
}
-#endif
-#if ENABLE_FEAT_TCR2
if (is_feat_tcr2_supported()) {
- write_tcr2_el1(read_ctx_reg(ctx, CTX_TCR2_EL1));
+ write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1));
}
-#endif
-#if ENABLE_TRF_FOR_NS
if (is_feat_trf_supported()) {
- write_trfcr_el1(read_ctx_reg(ctx, CTX_TRFCR_EL1));
+ write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1));
}
-#endif
-#if ENABLE_FEAT_CSV2_2
if (is_feat_csv2_2_supported()) {
- write_scxtnum_el0(read_ctx_reg(ctx, CTX_SCXTNUM_EL0));
- write_scxtnum_el1(read_ctx_reg(ctx, CTX_SCXTNUM_EL1));
+ write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0));
+ write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1));
}
-#endif
-#if ENABLE_FEAT_GCS
if (is_feat_gcs_supported()) {
- write_gcscr_el1(read_ctx_reg(ctx, CTX_GCSCR_EL1));
- write_gcscre0_el1(read_ctx_reg(ctx, CTX_GCSCRE0_EL1));
- write_gcspr_el1(read_ctx_reg(ctx, CTX_GCSPR_EL1));
- write_gcspr_el0(read_ctx_reg(ctx, CTX_GCSPR_EL0));
+ write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1));
+ write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1));
+ write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1));
+ write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0));
}
-#endif
}
/*******************************************************************************
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index c6076fe..d653222 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -52,6 +52,27 @@
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
+void spe_disable(cpu_context_t *ctx)
+{
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
+
+ /*
+ * MDCR_EL3.NSPB: Clear these bits to disable SPE feature, as it was enabled
+ * for Non-secure state only. After clearing these bits Secure state owns
+ * the Profiling Buffer and accesses to Statistical Profiling and Profiling
+ * Buffer control registers at EL2 and EL1 generate Trap exceptions to EL3
+ *
+ * MDCR_EL3.NSPBE: Don't care as it was cleared during spe_enable and setting
+ * this to 1 does not make sense as NSPBE{1} and NSPB{0b0x} is RESERVED.
+ *
+ * MDCR_EL3.EnPMSN (ARM v8.7): Clear the bit to trap access of PMSNEVFR_EL1
+ * from EL2/EL1 to EL3.
+ */
+ mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
+}
+
void spe_init_el2_unused(void)
{
uint64_t v;
@@ -70,7 +91,7 @@
write_mdcr_el2(v);
}
-void spe_disable(void)
+void spe_stop(void)
{
uint64_t v;
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c
index 9157734..8c1c421 100644
--- a/lib/extensions/trbe/trbe.c
+++ b/lib/extensions/trbe/trbe.c
@@ -39,6 +39,25 @@
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
+void trbe_disable(cpu_context_t *ctx)
+{
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
+
+ /*
+ * MDCR_EL3.NSTBE = 0b0
+ * Trace Buffer owning Security state is secure state. If FEAT_RME
+ * is not implemented, this field is RES0.
+ *
+ * MDCR_EL3.NSTB = 0b00
+ * Clear these bits to disable access of trace buffer control registers
+ * from lower ELs in any security state.
+ */
+ mdcr_el3_val &= ~(MDCR_NSTB(MDCR_NSTB_EL1));
+ mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
+}
+
void trbe_init_el2_unused(void)
{
/*
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 60449f6..375cdba 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -182,9 +182,9 @@
}
my_idx = plat_my_core_pos();
-
- for (lvl = PSCI_CPU_PWR_LVL; lvl <= end_pwrlvl; lvl++) {
- parent_idx = psci_cpu_pd_nodes[my_idx].parent_node;
+ parent_idx = psci_cpu_pd_nodes[my_idx].parent_node;
+ for (lvl = PSCI_CPU_PWR_LVL + U(1); lvl < end_pwrlvl; lvl++) {
+ parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
}
cpu_start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx;
@@ -1303,7 +1303,7 @@
* before exiting coherency.
*/
if (is_feat_spe_supported()) {
- spe_disable();
+ spe_stop();
}
}
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 9ade331..9859ce1 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -10,6 +10,7 @@
toolchains := aarch64
endif
+include ../../make_helpers/build-rules.mk
include ../../make_helpers/common.mk
include ../../make_helpers/toolchain.mk
@@ -46,45 +47,45 @@
all: $(BUILD_DIR)/romlib.bin $(LIB_DIR)/libwrappers.a
-%.o: %.s
+%.o: %.s | $$(@D)/
$(s)echo " AS $@"
$(q)$(aarch64-as) -c $(ASFLAGS) -o $@ $<
-$(BUILD_DIR)/%.o: %.s
+$(BUILD_DIR)/%.o: %.s | $$(@D)/
$(s)echo " AS $@"
$(q)$(aarch64-as) -c $(ASFLAGS) -o $@ $<
-$(BUILD_DIR)/romlib.ld: romlib.ld.S
+$(BUILD_DIR)/romlib.ld: romlib.ld.S | $$(@D)/
$(s)echo " PP $@"
$(q)$(aarch64-cpp) -E $(PPFLAGS) -o $@ romlib.ld.S
-$(BUILD_DIR)/romlib.elf: $(OBJS) $(BUILD_DIR)/romlib.ld
+$(BUILD_DIR)/romlib.elf: $(OBJS) $(BUILD_DIR)/romlib.ld | $$(@D)/
$(s)echo " LD $@"
$(q)$(aarch64-ld) -T $(BUILD_DIR)/romlib.ld -L$(LIB_DIR) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)
-$(BUILD_DIR)/romlib.bin: $(BUILD_DIR)/romlib.elf
+$(BUILD_DIR)/romlib.bin: $(BUILD_DIR)/romlib.elf | $$(@D)/
$(s)echo " BIN $@"
$(q)$(aarch64-oc) -O binary $(BUILD_DIR)/romlib.elf $@
-$(WRAPPER_DIR)/jmpvar.s: $(BUILD_DIR)/romlib.elf
+$(WRAPPER_DIR)/jmpvar.s: $(BUILD_DIR)/romlib.elf | $$(@D)/
$(s)echo " VAR $@"
$(q)$(ROMLIB_GEN) genvar --output $@ $<
-$(LIB_DIR)/libwrappers.a: $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
+$(LIB_DIR)/libwrappers.a: $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS) | $$(@D)/
$(s)echo " AR $@"
$(q)$(aarch64-ar) -rc $@ $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
-$(BUILD_DIR)/jmptbl.i: ../../$(PLAT_DIR)/jmptbl.i
+$(BUILD_DIR)/jmptbl.i: ../../$(PLAT_DIR)/jmptbl.i | $$(@D)/
$(s)echo " PRE $@"
$(q)$(ROMLIB_GEN) pre --output $@ --deps $(BUILD_DIR)/jmptbl.d $<
-$(WRAPPER_SOURCES) &: $(BUILD_DIR)/jmptbl.i
+$(WRAPPER_SOURCES) &: $(BUILD_DIR)/jmptbl.i | $$(@D)/
$(s)echo " WRP $<"
$(q)$(ROMLIB_GEN) genwrappers --bti=$(ENABLE_BTI) -b $(WRAPPER_DIR) $<
-$(WRAPPER_OBJS): $(WRAPPER_DIR)/%.o: $(WRAPPER_DIR)/%.s
+$(WRAPPER_OBJS): $(WRAPPER_DIR)/%.o: $(WRAPPER_DIR)/%.s | $$(@D)/
-$(BUILD_DIR)/jmptbl.s: $(BUILD_DIR)/jmptbl.i
+$(BUILD_DIR)/jmptbl.s: $(BUILD_DIR)/jmptbl.i | $$(@D)/
$(s)echo " TBL $@"
$(q)$(ROMLIB_GEN) gentbl --output $@ --bti=$(ENABLE_BTI) $<
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 3097181..ceff4ba 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -280,7 +280,7 @@
ENABLE_FEAT_AMU ?= 0
ENABLE_AMU_AUXILIARY_COUNTERS ?= 0
ENABLE_AMU_FCONF ?= 0
-AMU_RESTRICT_COUNTERS ?= 0
+AMU_RESTRICT_COUNTERS ?= 1
# Build option to enable MPAM for lower ELs.
# Enabling it by default
diff --git a/make_helpers/build-rules.mk b/make_helpers/build-rules.mk
new file mode 100644
index 0000000..d325b3a
--- /dev/null
+++ b/make_helpers/build-rules.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifndef build-rules-mk
+ build-rules-mk := $(lastword $(MAKEFILE_LIST))
+
+ include $(dir $(build-rules-mk))common.mk
+ include $(dir $(build-rules-mk))utilities.mk
+
+ .SECONDEXPANSION:
+
+ %/:
+ $(s)echo ' MD '$(call escape-shell,$(abspath $@))
+ $(q)mkdir -p $(call escape-shell,$@)
+endif
diff --git a/make_helpers/build_env.mk b/make_helpers/build_env.mk
index a545cd0..13acaae 100644
--- a/make_helpers/build_env.mk
+++ b/make_helpers/build_env.mk
@@ -15,8 +15,6 @@
COPY := $$(error "Replace COPY with call to SHELL_COPY or SHELL_COPY_TREE.")
CP := $$(error "Replace CP with call to SHELL_COPY or SHELL_COPY_TREE.")
DEL := $$(error "Replace DEL with call to SHELL_DELETE.")
- MD := $$(error "Replace MD with call to MAKE_PREREQ_DIR.")
- MKDIR := $$(error "Replace MKDIR with call to MAKE_PREREQ_DIR.")
RD := $$(error "Replace RD with call to SHELL_REMOVE_DIR.")
RM := $$(error "Replace RM with call to SHELL_DELETE.")
RMDIR := $$(error "Replace RMDIR with call to SHELL_REMOVE_DIR.")
@@ -62,9 +60,6 @@
ifndef SHELL_DELETE
$(error "SHELL_DELETE not defined for build environment.")
endif
- ifndef MAKE_PREREQ_DIR
- $(error "MAKE_PREREQ_DIR not defined for build environment.")
- endif
ifndef SHELL_REMOVE_DIR
$(error "SHELL_REMOVE_DIR not defined for build environment.")
endif
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index d27408c..7050916 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -289,7 +289,7 @@
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
$(eval LIB := $(call uppercase, $(notdir $(1))))
-$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | lib$(3)_dirs
+$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " CC $$<"
$$(q)$($(ARCH)-cc) $$($(LIB)_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(MAKE_DEP) -c $$< -o $$@
@@ -305,7 +305,7 @@
$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | lib$(3)_dirs
+$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " AS $$<"
$$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(MAKE_DEP) -c $$< -o $$@
@@ -328,7 +328,7 @@
$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
$(eval BL_CFLAGS := $($(call uppercase,$(3))_CFLAGS) $(PLAT_BL_COMMON_CFLAGS))
-$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
+$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " CC $$<"
$$(q)$($(ARCH)-cc) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CPPFLAGS) $(BL_CFLAGS) $(MAKE_DEP) -c $$< -o $$@
@@ -351,7 +351,7 @@
$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
$(eval BL_ASFLAGS := $($(call uppercase,$(3))_ASFLAGS) $(PLAT_BL_COMMON_ASFLAGS))
-$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
+$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " AS $$<"
$$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(BL_CPPFLAGS) $(BL_ASFLAGS) $(MAKE_DEP) -c $$< -o $$@
@@ -372,7 +372,7 @@
$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS))
$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
-$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
+$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " PP $$<"
$$(q)$($(ARCH)-cpp) -E $$(CPPFLAGS) $(BL_CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -o $$@ $$<
@@ -424,17 +424,6 @@
.PHONY: libraries
-# MAKE_LIB_DIRS macro defines the target for the directory where
-# libraries are created
-define MAKE_LIB_DIRS
- $(eval LIB_DIR := ${BUILD_PLAT}/lib)
- $(eval ROMLIB_DIR := ${BUILD_PLAT}/romlib)
- $(eval LIBWRAPPER_DIR := ${BUILD_PLAT}/libwrapper)
- $(eval $(call MAKE_PREREQ_DIR,${LIB_DIR},${BUILD_PLAT}))
- $(eval $(call MAKE_PREREQ_DIR,${ROMLIB_DIR},${BUILD_PLAT}))
- $(eval $(call MAKE_PREREQ_DIR,${LIBWRAPPER_DIR},${BUILD_PLAT}))
-endef
-
# MAKE_LIB macro defines the targets and options to build each BL image.
# Arguments:
# $(1) = Library name
@@ -445,11 +434,8 @@
$(eval SOURCES := $(LIB$(call uppercase,$(1))_SRCS))
$(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
-$(eval $(call MAKE_PREREQ_DIR,${BUILD_DIR},${BUILD_PLAT}))
$(eval $(call MAKE_LIB_OBJS,$(BUILD_DIR),$(SOURCES),$(1)))
-.PHONY : lib${1}_dirs
-lib${1}_dirs: | ${BUILD_DIR} ${LIB_DIR} ${ROMLIB_DIR} ${LIBWRAPPER_DIR}
libraries: ${LIB_DIR}/lib$(1).a
ifeq ($($(ARCH)-ld-id),arm-link)
LDPATHS = --userlibpath=${LIB_DIR}
@@ -465,7 +451,7 @@
all: ${LIB_DIR}/lib$(1).a
-${LIB_DIR}/lib$(1).a: $(OBJS)
+${LIB_DIR}/lib$(1).a: $(OBJS) | $$$$(@D)/
$$(s)echo " AR $$@"
$$(q)$($(ARCH)-ar) cr $$@ $$?
endef
@@ -503,26 +489,6 @@
$(eval LINKER_SCRIPT_SOURCES := $($(call uppercase,$(1))_LINKER_SCRIPT_SOURCES))
$(eval LINKER_SCRIPTS := $(call linker_script_path,$(LINKER_SCRIPT_SOURCES)))
- # We use sort only to get a list of unique object directory names.
- # ordering is not relevant but sort removes duplicates.
- $(eval TEMP_OBJ_DIRS := $(sort $(dir ${OBJS} ${DEFAULT_LINKER_SCRIPT} ${LINKER_SCRIPTS})))
- # The $(dir ) function leaves a trailing / on the directory names
- # Rip off the / to match directory names with make rule targets.
- $(eval OBJ_DIRS := $(patsubst %/,%,$(TEMP_OBJ_DIRS)))
-
-# Create generators for object directory structure
-
-$(eval $(call MAKE_PREREQ_DIR,${BUILD_DIR},${BUILD_PLAT}))
-
-$(eval $(foreach objd,${OBJ_DIRS},
- $(call MAKE_PREREQ_DIR,${objd},${BUILD_DIR})))
-
-.PHONY : ${1}_dirs
-
-# We use order-only prerequisites to ensure that directories are created,
-# but do not cause re-builds every time a file is written.
-${1}_dirs: | ${OBJ_DIRS}
-
$(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1)))
# Generate targets to preprocess each required linker script
@@ -532,14 +498,14 @@
$(eval BL_LDFLAGS := $($(call uppercase,$(1))_LDFLAGS))
ifeq ($(USE_ROMLIB),1)
-$(ELF): romlib.bin
+$(ELF): romlib.bin | $$$$(@D)/
endif
# MODULE_OBJS can be assigned by vendors with different compiled
# object file path, and prebuilt object file path.
$(eval OBJS += $(MODULE_OBJS))
-$(ELF): $(OBJS) $(DEFAULT_LINKER_SCRIPT) $(LINKER_SCRIPTS) | $(1)_dirs libraries $(BL_LIBS)
+$(ELF): $(OBJS) $(DEFAULT_LINKER_SCRIPT) $(LINKER_SCRIPTS) | $$$$(@D)/ libraries $(BL_LIBS)
$$(s)echo " LD $$@"
ifeq ($($(ARCH)-ld-id),arm-link)
$$(q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) --entry=${1}_entrypoint \
@@ -562,11 +528,11 @@
$(s)echo
endif
-$(DUMP): $(ELF)
+$(DUMP): $(ELF) | $$$$(@D)/
$$(s)echo " OD $$@"
$$(q)$($(ARCH)-od) -dx $$< > $$@
-$(BIN): $(ELF)
+$(BIN): $(ELF) | $$$$(@D)/
$$(s)echo " BIN $$@"
$$(q)$($(ARCH)-oc) -O binary $$< $$@
$(s)echo
@@ -598,22 +564,6 @@
$(notdir $(patsubst %.dts,%.dtb,$(filter %.dts,$(1))))
endef
-# MAKE_FDT_DIRS macro creates the prerequisite directories that host the
-# FDT binaries
-# $(1) = output directory
-# $(2) = input dts
-define MAKE_FDT_DIRS
- $(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2))))
- $(eval TEMP_DTB_DIRS := $(sort $(dir ${DTBS})))
- # The $(dir ) function leaves a trailing / on the directory names
- # Rip off the / to match directory names with make rule targets.
- $(eval DTB_DIRS := $(patsubst %/,%,$(TEMP_DTB_DIRS)))
-
-$(eval $(foreach objd,${DTB_DIRS},$(call MAKE_PREREQ_DIR,${objd},${BUILD_DIR})))
-
-fdt_dirs: ${DTB_DIRS}
-endef
-
# MAKE_DTB generate the Flattened device tree binary
# $(1) = output directory
# $(2) = input dts
@@ -628,12 +578,12 @@
# Dependencies of the DT compilation on its pre-compiled DTS
$(eval DTBDEP := $(patsubst %.dtb,%.d,$(DOBJ)))
-$(DPRE): $(2) | fdt_dirs
+$(DPRE): $(2) | $$$$(@D)/
$$(s)echo " CPP $$<"
$(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2))))
$$(q)$($(ARCH)-cpp) -E $$(TF_CFLAGS_$(ARCH)) $$(DTC_CPPFLAGS) -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$<
-$(DOBJ): $(DPRE) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs
+$(DOBJ): $(DPRE) $(filter-out %.d,$(MAKEFILE_LIST)) | $$$$(@D)/
$$(s)echo " DTC $$<"
$$(q)$($(ARCH)-dtc) $$(DTC_FLAGS) -d $(DTBDEP) -o $$@ $$<
@@ -651,8 +601,6 @@
$(and $(REMAIN),$(error FDT_SOURCES contain non-DTS files: $(REMAIN)))
$(eval $(foreach obj,$(DOBJS),$(call MAKE_DTB,$(1),$(obj))))
- $(eval $(call MAKE_FDT_DIRS,$(1),$(2)))
-
-dtbs: $(DTBS)
+dtbs: $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2)))
all: dtbs
endef
diff --git a/make_helpers/unix.mk b/make_helpers/unix.mk
index 4fd819a..fa7722a 100644
--- a/make_helpers/unix.mk
+++ b/make_helpers/unix.mk
@@ -38,18 +38,6 @@
-$(q)rm -rf ${1}
endef
- # ${1} is the directory to be generated.
- # ${2} is optional, and allows a prerequisite to be specified.
- # Do nothing if $1 == $2, to ignore self dependencies.
- define MAKE_PREREQ_DIR
- ifneq (${1},${2})
-
-${1} : ${2}
- $(q)mkdir -p "${1}"
-
- endif
- endef
-
define SHELL_REMOVE_DIR
-$(q)rm -rf "${1}"
endef
diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk
index 2f5d51b..c24aa08 100644
--- a/make_helpers/windows.mk
+++ b/make_helpers/windows.mk
@@ -47,19 +47,6 @@
$(eval $(foreach filename,$(wildcard ${1}),$(call DELETE_IF_THERE,${filename})))
endef
- # ${1} is the directory to be generated.
- # ${2} is optional, and allows prerequisites to be specified.
- # Do nothing if $1 == $2, to ignore self dependencies.
- define MAKE_PREREQ_DIR
- ifneq (${1},${2})
-
-${1} : ${2}
- $(eval tmp_dir:=$(subst /,\,${1}))
- -@if not exist "$(tmp_dir)" mkdir "${tmp_dir}"
-
- endif
- endef
-
# ${1} is the directory to be removed.
define SHELL_REMOVE_DIR
$(eval tmp_dir:=$(subst /,\,${1}))
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h
index 6a38657..b9ca3f6 100644
--- a/plat/allwinner/common/include/sunxi_private.h
+++ b/plat/allwinner/common/include/sunxi_private.h
@@ -58,4 +58,12 @@
}
#endif
+#ifdef PLAT_sun50i_h616
+void sunxi_soc_fdt_fixup(void *dtb);
+#else
+static inline void sunxi_soc_fdt_fixup(void *dtb)
+{
+}
+#endif
+
#endif /* SUNXI_PRIVATE_H */
diff --git a/plat/allwinner/common/sunxi_prepare_dtb.c b/plat/allwinner/common/sunxi_prepare_dtb.c
index 66af35a..0f68974 100644
--- a/plat/allwinner/common/sunxi_prepare_dtb.c
+++ b/plat/allwinner/common/sunxi_prepare_dtb.c
@@ -34,6 +34,8 @@
}
#endif
+ sunxi_soc_fdt_fixup(fdt);
+
if (sunxi_psci_is_scpi()) {
ret = fdt_add_cpu_idle_states(fdt, sunxi_idle_states);
if (ret < 0) {
diff --git a/plat/allwinner/sun50i_h616/platform.mk b/plat/allwinner/sun50i_h616/platform.mk
index de494a2..6f44e8c 100644
--- a/plat/allwinner/sun50i_h616/platform.mk
+++ b/plat/allwinner/sun50i_h616/platform.mk
@@ -18,5 +18,8 @@
$(error "H616 does not support SCPI PSCI ops")
endif
-BL31_SOURCES += drivers/allwinner/axp/axp805.c \
+BL31_SOURCES += common/fdt_wrappers.c \
+ drivers/allwinner/axp/axp805.c \
drivers/allwinner/sunxi_rsb.c \
+ drivers/mentor/i2c/mi2cv.c \
+ ${AW_PLAT}/${PLAT}/sunxi_h616_dtb.c
diff --git a/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c b/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
new file mode 100644
index 0000000..58bad53
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Amend the device tree to adjust the L2 cache size, which is different
+ * between the revisions of the H616 chips: earlier versions have 256 KB of L2,
+ * later versions 1 MB.
+ * Read the cache ID registers and adjust the size and number of sets entries
+ * in the L2 cache DT node.
+ */
+
+#include <common/fdt_wrappers.h>
+#include <lib/utils_def.h>
+#include <libfdt.h>
+
+#define CACHE_L1D 0x0
+#define CACHE_L1I 0x1
+#define CACHE_L2U 0x2
+
+#define CCSIDR_SETS_SHIFT 13
+#define CCSIDR_SETS_MASK GENMASK(14, 0)
+#define CCSIDR_ASSOC_SHIFT 3
+#define CCSIDR_ASSOC_MASK GENMASK(9, 0)
+#define CCSIDR_LSIZE_SHIFT 0
+#define CCSIDR_LSIZE_MASK GENMASK(2, 0)
+
+static uint32_t armv8_get_ccsidr(unsigned int sel)
+{
+ uint32_t reg;
+
+ __asm__ volatile ("msr CSSELR_EL1, %0\n" :: "r" (sel));
+ __asm__ volatile ("mrs %0, CCSIDR_EL1\n" : "=r" (reg));
+
+ return reg;
+}
+
+void sunxi_soc_fdt_fixup(void *dtb)
+{
+ int node = fdt_path_offset(dtb, "/cpus/cpu@0");
+ uint32_t phandle, ccsidr, cell;
+ int sets, line_size, assoc;
+ int ret;
+
+ if (node < 0) {
+ return;
+ }
+
+ ret = fdt_read_uint32(dtb, node, "next-level-cache", &phandle);
+ if (ret != 0) {
+ return;
+ }
+
+ node = fdt_node_offset_by_phandle(dtb, phandle);
+ if (node < 0) {
+ return;
+ }
+
+ ccsidr = armv8_get_ccsidr(CACHE_L2U);
+ sets = ((ccsidr >> CCSIDR_SETS_SHIFT) & CCSIDR_SETS_MASK) + 1;
+ line_size = 16U << ((ccsidr >> CCSIDR_LSIZE_SHIFT) & CCSIDR_LSIZE_MASK);
+ assoc = ((ccsidr >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1;
+
+ cell = cpu_to_fdt32(sets);
+ fdt_setprop(dtb, node, "cache-sets", &cell, sizeof(cell));
+
+ cell = cpu_to_fdt32(line_size);
+ fdt_setprop(dtb, node, "cache-line-size", &cell, sizeof(cell));
+
+ cell = cpu_to_fdt32(sets * assoc * line_size);
+ fdt_setprop(dtb, node, "cache-size", &cell, sizeof(cell));
+}
diff --git a/plat/allwinner/sun50i_h616/sunxi_power.c b/plat/allwinner/sun50i_h616/sunxi_power.c
index dd6ebba..cab7e46 100644
--- a/plat/allwinner/sun50i_h616/sunxi_power.c
+++ b/plat/allwinner/sun50i_h616/sunxi_power.c
@@ -10,97 +10,254 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <common/fdt_wrappers.h>
#include <drivers/allwinner/axp.h>
#include <drivers/allwinner/sunxi_rsb.h>
+#include <drivers/mentor/mi2cv.h>
#include <lib/mmio.h>
+#include <libfdt.h>
#include <sunxi_cpucfg.h>
#include <sunxi_def.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
-#define AXP305_I2C_ADDR 0x36
-#define AXP305_HW_ADDR 0x745
-#define AXP305_RT_ADDR 0x3a
+static uint16_t pmic_bus_addr;
+static uint8_t rsb_rt_addr;
+
+static bool is_using_rsb(void)
+{
+ return rsb_rt_addr != 0;
+}
static enum pmic_type {
UNKNOWN,
AXP305,
+ AXP313,
+ AXP717,
} pmic;
+static uint8_t get_rsb_rt_address(uint16_t hw_addr)
+{
+ switch (hw_addr) {
+ case 0x3a3: return 0x2d;
+ case 0x745: return 0x3a;
+ }
+
+ return 0;
+}
+
int axp_read(uint8_t reg)
{
- return rsb_read(AXP305_RT_ADDR, reg);
+ uint8_t val;
+ int ret;
+
+ if (is_using_rsb()) {
+ return rsb_read(rsb_rt_addr, reg);
+ }
+
+ ret = i2c_write(pmic_bus_addr, 0, 0, ®, 1);
+ if (ret == 0) {
+ ret = i2c_read(pmic_bus_addr, 0, 0, &val, 1);
+ }
+ if (ret) {
+ ERROR("PMIC: Cannot read PMIC register %02x\n", reg);
+ return ret;
+ }
+
+ return val;
}
int axp_write(uint8_t reg, uint8_t val)
{
- return rsb_write(AXP305_RT_ADDR, reg, val);
+ int ret;
+
+ if (is_using_rsb()) {
+ return rsb_write(rsb_rt_addr, reg, val);
+ }
+
+ ret = i2c_write(pmic_bus_addr, reg, 1, &val, 1);
+ if (ret) {
+ ERROR("PMIC: Cannot write PMIC register %02x\n", reg);
+ }
+
+ return ret;
}
-static int rsb_init(void)
+static int rsb_init(int rsb_hw_addr)
{
int ret;
ret = rsb_init_controller();
- if (ret)
+ if (ret) {
return ret;
+ }
/* Switch to the recommended 3 MHz bus clock. */
ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
- if (ret)
+ if (ret) {
return ret;
+ }
/* Initiate an I2C transaction to switch the PMIC to RSB mode. */
ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
- if (ret)
+ if (ret) {
return ret;
+ }
/* Associate the 8-bit runtime address with the 12-bit bus address. */
- ret = rsb_assign_runtime_address(AXP305_HW_ADDR, AXP305_RT_ADDR);
- if (ret)
+ ret = rsb_assign_runtime_address(rsb_hw_addr, rsb_rt_addr);
+ if (ret) {
return ret;
+ }
- return axp_check_id();
+ return 0;
}
-int sunxi_pmic_setup(uint16_t socid, const void *fdt)
+static int pmic_bus_init(uint16_t socid, uint16_t rsb_hw_addr)
{
int ret;
- INFO("PMIC: Probing AXP305 on RSB\n");
-
- ret = sunxi_init_platform_r_twi(socid, true);
+ ret = sunxi_init_platform_r_twi(socid, is_using_rsb());
if (ret) {
INFO("Could not init platform bus: %d\n", ret);
+ pmic = UNKNOWN;
return ret;
}
+ if (is_using_rsb()) {
+ ret = rsb_init(rsb_hw_addr);
+ if (ret) {
+ pmic = UNKNOWN;
+ return ret;
+ }
+ } else {
+ /* initialise mi2cv driver */
+ i2c_init((void *)SUNXI_R_I2C_BASE);
+ }
+
+ return 0;
+}
+
+int sunxi_pmic_setup(uint16_t socid, const void *fdt)
+{
+ int node, parent, ret;
+ uint32_t reg;
+
+ node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp806");
+ if (node >= 0) {
+ pmic = AXP305;
+ }
+
+ if (pmic == UNKNOWN) {
+ node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp313a");
+ if (node >= 0) {
+ pmic = AXP313;
+ }
+ }
+
+ if (pmic == UNKNOWN) {
+ node = fdt_node_offset_by_compatible(fdt, 0, "x-powers,axp717");
+ if (node >= 0) {
+ pmic = AXP717;
+ }
+ }
+
+ if (pmic == UNKNOWN) {
+ INFO("PMIC: No known PMIC in DT, skipping setup.\n");
+ return -ENODEV;
+ }
+
- ret = rsb_init();
+ if (fdt_read_uint32(fdt, node, "reg", ®)) {
+ ERROR("PMIC: PMIC DT node does not contain reg property.\n");
+ return -EINVAL;
+ }
+
+ pmic_bus_addr = reg;
+ parent = fdt_parent_offset(fdt, node);
+ ret = fdt_node_check_compatible(fdt, parent, "allwinner,sun8i-a23-rsb");
+ if (ret == 0) {
+ rsb_rt_addr = get_rsb_rt_address(pmic_bus_addr);
+ if (rsb_rt_addr == 0) {
+ ERROR("PMIC: no mapping for RSB address 0x%x\n",
+ pmic_bus_addr);
+ return -EINVAL;
+ }
+ }
+
+ INFO("Probing for PMIC on %s:\n", is_using_rsb() ? "RSB" : "I2C");
+
+ ret = pmic_bus_init(socid, pmic_bus_addr);
if (ret) {
- INFO("Could not init RSB: %d\n", ret);
return ret;
}
- pmic = AXP305;
- axp_setup_regulators(fdt);
+ ret = axp_read(0x03);
+ switch (ret & 0xcf) {
+ case 0x40: /* AXP305 */
+ if (pmic == AXP305) {
+ INFO("PMIC: found AXP305, setting up regulators\n");
+ axp_setup_regulators(fdt);
+ } else {
+ pmic = UNKNOWN;
+ }
+ break;
+ case 0x48: /* AXP1530 */
+ case 0x4b: /* AXP313A */
+ case 0x4c: /* AXP313B */
+ if (pmic == AXP313) {
+ INFO("PMIC: found AXP313\n");
+ /* no regulators to set up */
+ } else {
+ pmic = UNKNOWN;
+ }
+ break;
+ case 0xcf: /* version reg not implemented on AXP717 */
+ if (pmic == AXP717) {
+ INFO("PMIC: found AXP717\n");
+ /* no regulators to set up, U-Boot takes care of this */
+ } else {
+ pmic = UNKNOWN;
+ }
+ break;
+ }
- /* Switch the PMIC back to I2C mode. */
- ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
- if (ret)
- return ret;
+ if (is_using_rsb()) {
+ /* Switch the PMIC back to I2C mode. */
+ return rsb_write(rsb_rt_addr, AXP20X_MODE_REG, AXP20X_MODE_I2C);
+ }
+
+ if (pmic == UNKNOWN) {
+ INFO("Incompatible or unknown PMIC found.\n");
+ return -ENODEV;
+ }
return 0;
}
void sunxi_power_down(void)
{
+ int ret;
+
+ if (pmic == UNKNOWN) {
+ return;
+ }
+
+ /* Re-initialise after rich OS might have used it. */
+ ret = pmic_bus_init(SUNXI_SOC_H616, pmic_bus_addr);
+ if (ret) {
+ return;
+ }
+
switch (pmic) {
case AXP305:
- /* Re-initialise after rich OS might have used it. */
- sunxi_init_platform_r_twi(SUNXI_SOC_H616, true);
- rsb_init();
- axp_power_off();
+ axp_setbits(0x32, BIT(7));
+ break;
+ case AXP313:
+ axp_setbits(0x1a, BIT(7));
+ break;
+ case AXP717:
+ axp_setbits(0x27, BIT(0));
break;
default:
break;
diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
index 457d181..de6a15a 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, 2024 ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -77,7 +77,8 @@
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
.ep_info.pc = BL33_BASE,
-
+ .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = BL33_BASE,
diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
index ed3801c..e388c82 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,7 +23,6 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
- ARM_MAP_NS_SHARED_RAM,
ARM_MAP_NS_DRAM1,
CORSTONE1000_MAP_DEVICE,
CORSTONE1000_EXTERNAL_FLASH,
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
index 51d696c..bd3faec 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
@@ -8,6 +8,7 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
#include <plat/common/platform.h>
+#include <drivers/arm/gicv2.h>
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform layer will take care of registering the handlers with PSCI.
@@ -19,6 +20,15 @@
uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG;
uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG;
+ /*
+ * Disable GIC CPU interface to prevent pending interrupt
+ * from waking up the AP from WFI.
+ */
+ gicv2_cpuif_disable();
+
+ /* Flush and invalidate data cache */
+ dcsw_op_all(DCCISW);
+
*(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
*watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
while (1) {
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index e3f3268..caf3d46 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -55,42 +55,42 @@
/* Memory related constants */
-/* SRAM (CVM) memory layout
+/* Memory mappings of where the BLs in the FIP are copied to
*
- * <ARM_TRUSTED_SRAM_BASE>
+ * <ARM_TRUSTED_SRAM_BASE> = 0x02000000
* partition size: sizeof(meminfo_t) = 16 bytes
* content: memory info area used by the next BL
*
- * <ARM_FW_CONFIG_BASE>
+ * <ARM_FW_CONFIG_BASE> = 0x02000010
* partition size: 4080 bytes
*
- * <ARM_BL2_MEM_DESC_BASE>
+ * <ARM_BL2_MEM_DESC_BASE> = 0x02001000
* partition size: 4 KB
* content: Area where BL2 copies the images descriptors
*
- * <ARM_BL_RAM_BASE> = <BL32_BASE>
- * partition size: 688 KB
+ * <ARM_BL_RAM_BASE> = <BL32_BASE> = 0x02002000
+ * partition size: 3752 KB
* content: BL32 (optee-os)
*
- * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
+ * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x023AC000
* partition size: 8 KB
* content: BL32 config (TOS_FW_CONFIG)
*
- * <BL31_BASE>
+ * <BL31_BASE> = 0x023AE000
* partition size: 140 KB
* content: BL31
*
- * <BL2_SIGNATURE_BASE>
+ * <BL2_SIGNATURE_BASE> = 0x023D1000
* partition size: 4 KB
* content: MCUBOOT data needed to verify TF-A BL2
*
- * <BL2_BASE>
+ * <BL2_BASE> = 0x023D2000
* partition size: 176 KB
* content: BL2
*
- * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
- * partition size: 512 KB
- * content: BL33 (u-boot)
+ * <BL33_BASE> = 0x80000000
+ * partition size: 12 MB
+ * content: BL33 (U-Boot)
*/
/* DDR memory */
@@ -115,11 +115,8 @@
/* The remaining Trusted SRAM is used to load the BL images */
#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */
-/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
-#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K)
#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \
- ARM_NS_SHARED_RAM_SIZE - \
ARM_SHARED_RAM_SIZE)
#define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */
@@ -158,11 +155,6 @@
/* NS memory */
-/* The last 512KB of the SRAM is allocated as shared memory */
-#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
- (PLAT_ARM_MAX_BL31_SIZE + \
- PLAT_ARM_MAX_BL32_SIZE))
-
#define BL33_BASE ARM_DRAM1_BASE
#define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/
#define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
@@ -277,7 +269,7 @@
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
-#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
+#define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
@@ -306,11 +298,6 @@
ARM_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
-#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \
- ARM_NS_SHARED_RAM_BASE, \
- ARM_NS_SHARED_RAM_SIZE, \
- MT_MEMORY | MT_RW | MT_NS)
-
#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
ARM_NS_DRAM1_BASE, \
ARM_NS_DRAM1_SIZE, \
diff --git a/plat/arm/board/fvp/fdts/optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
index a6b4886..4611f80 100644
--- a/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
@@ -46,6 +46,7 @@
base-address = <0x00000000 0x1c0a0000>;
pages-count = <1>;
attributes = <0x3>; /* read-write */
+ interrupts = <38 0x900>;
};
};
};
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 5557d59..0c5a76c 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -210,7 +210,7 @@
#ifdef MAP_FW_NS_HANDOFF
MAP_FW_NS_HANDOFF,
#endif
-#ifdef MAP_EL3_FW_HANDOFF
+#if defined(MAP_EL3_FW_HANDOFF) && !RESET_TO_BL31
MAP_EL3_FW_HANDOFF,
#endif
{ 0 }
@@ -219,6 +219,11 @@
#if defined(IMAGE_BL31) && SPM_MM
const mmap_region_t plat_arm_secure_partition_mmap[] = {
V2M_MAP_IOFPGA_EL0, /* for the UART */
+ V2M_MAP_SECURE_SYSTEMREG_EL0, /* for initializing flash */
+#if PSA_FWU_SUPPORT
+ V2M_MAP_FLASH0_RW_EL0, /* for firmware update service in standalone mm */
+#endif
+ V2M_MAP_FLASH1_RW_EL0, /* for secure variable service in standalone mm */
MAP_REGION_FLAT(DEVICE0_BASE,
DEVICE0_SIZE,
MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 6d63646..cef7bdf 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -323,10 +323,6 @@
BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c
endif
-ifeq (${TRANSFER_LIST}, 1)
-include lib/transfer_list/transfer_list.mk
-endif
-
# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
ifdef UNIX_MK
FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
@@ -386,6 +382,17 @@
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
endif
+ifeq (${TRANSFER_LIST}, 1)
+include lib/transfer_list/transfer_list.mk
+
+ifeq ($(RESET_TO_BL31), 1)
+HW_CONFIG := ${FVP_HW_CONFIG}
+FW_HANDOFF_SIZE := 20000
+
+$(eval $(call add_define,ARM_PRELOADED_DTB_OFFSET))
+endif
+endif
+
# Enable dynamic mitigation support by default
DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
diff --git a/plat/arm/board/fvp_ve/fvp_ve_def.h b/plat/arm/board/fvp_ve/fvp_ve_def.h
index 98de5f6..cb4b74c 100644
--- a/plat/arm/board/fvp_ve/fvp_ve_def.h
+++ b/plat/arm/board/fvp_ve/fvp_ve_def.h
@@ -70,15 +70,4 @@
#define FVP_VE_IRQ_TZ_WDOG 56
#define FVP_VE_IRQ_SEC_SYS_TIMER 57
-#define V2M_FLASH1_BASE UL(0x0C000000)
-#define V2M_FLASH1_SIZE UL(0x04000000)
-
-#define V2M_MAP_FLASH1_RW MAP_REGION_FLAT(V2M_FLASH1_BASE,\
- V2M_FLASH1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define V2M_MAP_FLASH1_RO MAP_REGION_FLAT(V2M_FLASH1_BASE,\
- V2M_FLASH1_SIZE, \
- MT_RO_DATA | MT_SECURE)
-
#endif /* FVP_VE_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c b/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c
index 371bde6..cf1eb6f 100644
--- a/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c
+++ b/plat/arm/board/neoverse_rd/common/ras/nrd_ras_cpu.c
@@ -62,37 +62,50 @@
cpu_info->SecurityState = security_state;
/* populate CPU EL1 context information. */
- cpu_info->ErrCtxEl1Reg[0] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_ELR_EL1);
- cpu_info->ErrCtxEl1Reg[1] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_ESR_EL1);
- cpu_info->ErrCtxEl1Reg[2] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_FAR_EL1);
+ cpu_info->ErrCtxEl1Reg[0] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ elr_el1);
+ cpu_info->ErrCtxEl1Reg[1] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ esr_el1);
+ cpu_info->ErrCtxEl1Reg[2] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ far_el1);
cpu_info->ErrCtxEl1Reg[3] = read_isr_el1();
- cpu_info->ErrCtxEl1Reg[4] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_MAIR_EL1);
+ cpu_info->ErrCtxEl1Reg[4] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ mair_el1);
cpu_info->ErrCtxEl1Reg[5] = read_midr_el1();
cpu_info->ErrCtxEl1Reg[6] = read_mpidr_el1();
- cpu_info->ErrCtxEl1Reg[7] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_SCTLR_EL1);
+
+#if (ERRATA_SPECULATIVE_AT)
+ cpu_info->ErrCtxEl1Reg[7] = read_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_SCTLR_EL1);
+#else
+ cpu_info->ErrCtxEl1Reg[7] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ sctlr_el1);
+#endif /* ERRATA_SPECULATIVE_AT */
+
cpu_info->ErrCtxEl1Reg[8] = read_ctx_reg(get_gpregs_ctx(ctx),
CTX_GPREG_SP_EL0);
- cpu_info->ErrCtxEl1Reg[9] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_SP_EL1);
- cpu_info->ErrCtxEl1Reg[10] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_SPSR_EL1);
- cpu_info->ErrCtxEl1Reg[11] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_TCR_EL1);
- cpu_info->ErrCtxEl1Reg[12] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_TPIDR_EL0);
- cpu_info->ErrCtxEl1Reg[13] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_TPIDR_EL1);
- cpu_info->ErrCtxEl1Reg[14] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_TPIDRRO_EL0);
- cpu_info->ErrCtxEl1Reg[15] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_TTBR0_EL1);
- cpu_info->ErrCtxEl1Reg[16] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_TTBR1_EL1);
+ cpu_info->ErrCtxEl1Reg[9] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ sp_el1);
+ cpu_info->ErrCtxEl1Reg[10] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ spsr_el1);
+#if (ERRATA_SPECULATIVE_AT)
+ cpu_info->ErrCtxEl1Reg[11] = read_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_TCR_EL1);
+#else
+ cpu_info->ErrCtxEl1Reg[11] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ tcr_el1);
+#endif /* ERRATA_SPECULATIVE_AT */
+
+ cpu_info->ErrCtxEl1Reg[12] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ tpidr_el0);
+ cpu_info->ErrCtxEl1Reg[13] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ tpidr_el1);
+ cpu_info->ErrCtxEl1Reg[14] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ tpidrro_el0);
+ cpu_info->ErrCtxEl1Reg[15] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ ttbr0_el1);
+ cpu_info->ErrCtxEl1Reg[16] = read_el1_ctx_common(get_el1_sysregs_ctx(ctx),
+ ttbr1_el1);
#if CTX_INCLUDE_EL2_REGS
cpu_info->ErrCtxEl2Reg[0] = read_el2_ctx_common(get_el2_sysregs_ctx(ctx),
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 78b6945..fb70500 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -121,7 +121,8 @@
lib/cpus/aarch64/cortex_x925.S
endif
-INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c
+INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c \
+ plat/arm/common/arm_ni.c
PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \
${TC_BASE}/include/tc_helpers.S
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 7d1bc9c..53404df 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -110,6 +110,7 @@
#if TARGET_PLATFORM == 3
enable_ns_mcn_pmu();
set_mcn_slc_alloc_mode();
+ plat_arm_ni_setup(NCI_BASE_ADDR);
#endif
}
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 99243dc..b5a7db1 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -162,16 +162,6 @@
#if defined(PLAT_ARM_MEM_PROT_ADDR)
arm_nor_psci_do_static_mem_protect();
#endif
-
-#if TRANSFER_LIST
- ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE,
- PLAT_ARM_FW_HANDOFF_SIZE);
-
- if (ns_tl == NULL) {
- ERROR("Non-secure transfer list initialisation failed!");
- panic();
- }
-#endif
}
void bl2_platform_setup(void)
@@ -326,7 +316,8 @@
#if TRANSFER_LIST
if (image_id == HW_CONFIG_ID) {
- arm_transfer_list_copy_hw_config(secure_tl, ns_tl);
+ /* Refresh the now stale checksum following loading of HW_CONFIG into the TL. */
+ transfer_list_update_checksum(secure_tl);
}
#endif /* TRANSFER_LIST */
@@ -340,5 +331,5 @@
&next_param_node->ep_info);
assert(ep != NULL);
- arm_transfer_list_populate_ep_info(next_param_node, secure_tl, ns_tl);
+ arm_transfer_list_populate_ep_info(next_param_node, secure_tl);
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index b7941ec..e91746b 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -25,6 +25,8 @@
#include <platform_def.h>
static struct transfer_list_header *secure_tl __unused;
+static struct transfer_list_header *ns_tl __unused;
+
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@@ -95,7 +97,12 @@
assert(sec_state_is_valid(type));
if (type == NON_SECURE) {
+#if TRANSFER_LIST && !RESET_TO_BL31
+ next_image_info = transfer_list_set_handoff_args(
+ ns_tl, &bl33_image_ep_info);
+#else
next_image_info = &bl33_image_ep_info;
+#endif
}
#if ENABLE_RME
else if (type == REALM) {
@@ -128,6 +135,24 @@
void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+#if RESET_TO_BL31
+ /* Populate entry point information for BL33 */
+ SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
+ /*
+ * Tell BL31 where the non-trusted software image
+ * is located and the entry state information
+ */
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+
+ bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+
+ bl33_image_ep_info.args.arg0 =
+ FW_NS_HANDOFF_BASE + ARM_PRELOADED_DTB_OFFSET;
+ bl33_image_ep_info.args.arg1 =
+ TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION);
+ bl33_image_ep_info.args.arg3 = FW_NS_HANDOFF_BASE;
+#else
struct transfer_list_entry *te = NULL;
struct entry_point_info *ep;
@@ -160,6 +185,7 @@
}
}
}
+#endif /* RESET_TO_BL31 */
}
#else
void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
@@ -338,6 +364,28 @@
******************************************************************************/
void arm_bl31_platform_setup(void)
{
+ struct transfer_list_entry *te __unused;
+
+#if TRANSFER_LIST && !RESET_TO_BL31
+ /* Initialise the non-secure world tl, BL31 may modify the HW_CONFIG so defer
+ * copying it until later.
+ */
+ ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE,
+ PLAT_ARM_FW_HANDOFF_SIZE);
+
+ if (ns_tl == NULL) {
+ ERROR("Non-secure transfer list initialisation failed!");
+ panic();
+ }
+
+#if !RESET_TO_BL2
+ te = transfer_list_find(secure_tl, TL_TAG_FDT);
+ assert(te != NULL);
+
+ fconf_populate("HW_CONFIG", (uintptr_t)transfer_list_entry_data(te));
+#endif /* !(RESET_TO_BL2 && RESET_TO_BL31) */
+#endif /* TRANSFER_LIST */
+
/* Initialize the GIC driver, cpu and distributor interfaces */
plat_arm_gic_driver_init();
plat_arm_gic_init();
@@ -380,9 +428,26 @@
******************************************************************************/
void arm_bl31_plat_runtime_setup(void)
{
+ struct transfer_list_entry *te __unused;
/* Initialize the runtime console */
arm_console_runtime_init();
+#if TRANSFER_LIST && !RESET_TO_BL31
+ te = transfer_list_find(secure_tl, TL_TAG_FDT);
+ assert(te != NULL);
+
+ te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
+ transfer_list_entry_data(te));
+ assert(te != NULL);
+
+ /*
+ * We assume BL31 has added all TE's required by BL33 at this stage, ensure
+ * that data is visible to all observers by performing a flush operation, so
+ * they can access the updated data even if caching is not enabled.
+ */
+ flush_dcache_range((uintptr_t)ns_tl, ns_tl->size);
+#endif /* TRANSFER_LIST && !(RESET_TO_BL2 || RESET_TO_BL31) */
+
#if RECLAIM_INIT_CODE
arm_free_init_memory();
#endif
@@ -497,15 +562,5 @@
void __init bl31_plat_arch_setup(void)
{
- struct transfer_list_entry *te __unused;
-
arm_bl31_plat_arch_setup();
-
-#if TRANSFER_LIST && !RESET_TO_BL2
- te = transfer_list_find(secure_tl, TL_TAG_FDT);
- assert(te != NULL);
-
- /* Populate HW_CONFIG device tree with the mapped address */
- fconf_populate("HW_CONFIG", (uintptr_t)transfer_list_entry_data(te));
-#endif
}
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index f5919ab..2c1888d 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -458,3 +458,17 @@
$(error To reclaim init code xlat tables v2 must be used)
endif
endif
+
+TRANSFER_LIST_BIN := ${BUILD_PLAT}/tl.bin
+
+.PHONY: tl
+tl: ${HW_CONFIG}
+ @echo " TLC ${TRANSFER_LIST_BIN}"
+ $(Q)${PYTHON} -m tools.tlc.tlc create --fdt ${HW_CONFIG} -s ${FW_HANDOFF_SIZE} ${TRANSFER_LIST_BIN}
+ $(Q)$(eval ARM_PRELOADED_DTB_OFFSET := `tlc info --fdt-offset ${TRANSFER_LIST_BIN}`)
+
+ifeq (${TRANSFER_LIST}, 1)
+ ifeq (${RESET_TO_BL31}, 1)
+ bl31: tl
+ endif
+endif
diff --git a/plat/arm/common/arm_ni.c b/plat/arm/common/arm_ni.c
new file mode 100644
index 0000000..b3ad8b3
--- /dev/null
+++ b/plat/arm/common/arm_ni.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+#define NI_CHILD_NODE_COUNT 4
+#define NI_CHILD_POINTERS_START 8
+
+#define NI_PMU_SECURE_CTRL 0x100
+#define NI_PMU_SECURE_EVENT_OBSERVATION 0x108
+#define NI_PMU_DEBUG_ENABLE 0x110
+#define NI_COMP_NUM_SUBFEATURES 0x100
+#define NI_COMP_SUBFEATURE_TYPE_START 0x108
+#define NI_COMP_SUBFEATURE_SECURE_CTRL_START 0x308
+
+#define SECURE_OVERRIDE_DEFAULT BIT(0)
+#define SECURE_EVENT_ENABLE BIT(2)
+#define NA_EVENT_ENABLE BIT(3)
+#define PMU_ENABLE BIT(0)
+
+#define NI_NODE_MASK 0x0000ffff
+#define NI_NODE_TYPE(node_info) (node_info & NI_NODE_MASK)
+#define NI_CHILD_POINTER(i) (NI_CHILD_POINTERS_START + (i * 4))
+#define NI_COMP_SUBFEATURE_TYPE(i) (NI_COMP_SUBFEATURE_TYPE_START + (i * 8))
+#define NI_COMP_SUBFEATURE_SECURE_CTRL(i) (NI_COMP_SUBFEATURE_SECURE_CTRL_START + (i * 8))
+
+#define NI_PERIPHERAL_ID0 0xfe0
+#define NI_PIDR0_PART_MASK 0xff
+#define NI_PERIPHERAL_ID1 0xfe4
+#define NI_PIDR1_PART_MASK 0xf
+#define NI_PIDR1_PART_SHIFT 8
+
+enum ni_part {
+ NI_700 = 0x43b,
+ NI_710AE = 0x43d,
+ NI_TOWER = 0x43f,
+};
+
+enum ni_node_type {
+ NI_INVALID_NODE = 0,
+ NI_VOLTAGE_DOMAIN = 1,
+ NI_POWER_DOMAIN = 2,
+ NI_CLOCK_DOMAIN = 3,
+ NI_ASNI = 4,
+ NI_AMNI = 5,
+ NI_PMU = 6,
+ NI_HSNI = 7,
+ NI_HMNI = 8,
+ NI_PMNI = 9,
+ NI_CMNI = 14,
+ NI_CFGNI = 15
+};
+
+enum ni_subfeature_type {
+ NI_SUBFEATURE_APU = 0,
+ NI_SUBFEATURE_ADDR_MAP = 1,
+ NI_SUBFEATURE_FCU = 2,
+ NI_SUBFEATURE_IDM = 3
+};
+
+static void ni_enable_pmu(uintptr_t pmu_addr)
+{
+ mmio_setbits_32(pmu_addr + NI_PMU_DEBUG_ENABLE, PMU_ENABLE);
+}
+
+static void ni_enable_fcu_ns_access(uintptr_t comp_addr)
+{
+ uint32_t subfeature_type;
+ uint32_t subfeature_count;
+ uint32_t subfeature_secure_ctrl;
+
+ subfeature_count = mmio_read_32(comp_addr + NI_COMP_NUM_SUBFEATURES);
+ for (uint32_t i = 0U; i < subfeature_count; i++) {
+ subfeature_type =
+ NI_NODE_TYPE(mmio_read_32(comp_addr + NI_COMP_SUBFEATURE_TYPE(i)));
+ if (subfeature_type == NI_SUBFEATURE_FCU) {
+ subfeature_secure_ctrl = comp_addr + NI_COMP_SUBFEATURE_SECURE_CTRL(i);
+ mmio_setbits_32(subfeature_secure_ctrl, SECURE_OVERRIDE_DEFAULT);
+ }
+ }
+}
+
+static void ni_enable_pmu_ns_access(uintptr_t comp_addr)
+{
+ mmio_setbits_32(comp_addr + NI_PMU_SECURE_CTRL, SECURE_OVERRIDE_DEFAULT);
+ mmio_setbits_32(comp_addr + NI_PMU_SECURE_EVENT_OBSERVATION,
+ SECURE_EVENT_ENABLE | NA_EVENT_ENABLE);
+}
+
+static void ni_setup_component(uintptr_t comp_addr)
+{
+ uint32_t node_info;
+
+ node_info = mmio_read_32(comp_addr);
+
+ switch (NI_NODE_TYPE(node_info)) {
+ case NI_ASNI:
+ case NI_AMNI:
+ case NI_HSNI:
+ case NI_HMNI:
+ case NI_PMNI:
+ ni_enable_fcu_ns_access(comp_addr);
+ break;
+ case NI_PMU:
+ ni_enable_pmu_ns_access(comp_addr);
+ ni_enable_pmu(comp_addr);
+ break;
+ default:
+ return;
+ }
+}
+
+int plat_arm_ni_setup(uintptr_t global_cfg)
+{
+ uintptr_t vd_addr;
+ uintptr_t pd_addr;
+ uintptr_t cd_addr;
+ uintptr_t comp_addr;
+ uint32_t vd_count;
+ uint32_t pd_count;
+ uint32_t cd_count;
+ uint32_t comp_count;
+ uint32_t part;
+ uint32_t reg;
+
+ reg = mmio_read_32(global_cfg + NI_PERIPHERAL_ID0);
+ part = reg & NI_PIDR0_PART_MASK;
+ reg = mmio_read_32(global_cfg + NI_PERIPHERAL_ID1);
+ part |= ((reg & NI_PIDR1_PART_MASK) << NI_PIDR1_PART_SHIFT);
+
+ if (part != NI_TOWER) {
+ ERROR("0x%x is not supported\n", part);
+ return -EINVAL;
+ }
+
+ vd_count = mmio_read_32(global_cfg + NI_CHILD_NODE_COUNT);
+
+ for (uint32_t i = 0U; i < vd_count; i++) {
+ vd_addr = global_cfg + mmio_read_32(global_cfg + NI_CHILD_POINTER(i));
+ pd_count = mmio_read_32(vd_addr + NI_CHILD_NODE_COUNT);
+
+ for (uint32_t j = 0U; j < pd_count; j++) {
+ pd_addr = global_cfg + mmio_read_32(vd_addr + NI_CHILD_POINTER(j));
+ cd_count = mmio_read_32(pd_addr + NI_CHILD_NODE_COUNT);
+
+ for (uint32_t k = 0U; k < cd_count; k++) {
+ cd_addr = global_cfg + mmio_read_32(pd_addr + NI_CHILD_POINTER(k));
+ comp_count = mmio_read_32(cd_addr + NI_CHILD_NODE_COUNT);
+
+ for (uint32_t l = 0U; l < comp_count; l++) {
+ comp_addr = global_cfg +
+ mmio_read_32(cd_addr + NI_CHILD_POINTER(l));
+ ni_setup_component(comp_addr);
+ }
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/arm/common/arm_transfer_list.c b/plat/arm/common/arm_transfer_list.c
index d144bbb..59fb039 100644
--- a/plat/arm/common/arm_transfer_list.c
+++ b/plat/arm/common/arm_transfer_list.c
@@ -30,8 +30,7 @@
}
void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node,
- struct transfer_list_header *secure_tl,
- struct transfer_list_header *ns_tl)
+ struct transfer_list_header *secure_tl)
{
uint32_t next_exe_img_id;
entry_point_info_t *ep;
@@ -53,10 +52,7 @@
ep = transfer_list_entry_data(te);
- if (next_exe_img_id == BL33_IMAGE_ID) {
- ep = transfer_list_set_handoff_args(ns_tl, ep);
- assert(ep != NULL);
- } else if ((next_exe_img_id == BL32_IMAGE_ID) && SPMC_AT_EL3) {
+ if ((next_exe_img_id == BL32_IMAGE_ID) && SPMC_AT_EL3) {
/*
* Populate the BL32 image base, size and max limit in
* the entry point information, since there is no
@@ -78,19 +74,3 @@
flush_dcache_range((uintptr_t)secure_tl, secure_tl->size);
}
-
-void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl,
- struct transfer_list_header *ns_tl)
-{
- struct transfer_list_entry *te =
- transfer_list_find(secure_tl, TL_TAG_FDT);
- assert(te != NULL);
-
- /* Refresh the now stale checksum following loading of HW_CONFIG into the TL. */
- transfer_list_update_checksum(secure_tl);
-
- /* Copy the hardware configuration to the non-secure TL. */
- te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
- transfer_list_entry_data(te));
- assert(te != NULL);
-}
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c
index 9fec3e8..087b479 100644
--- a/plat/aspeed/ast2700/plat_bl31_setup.c
+++ b/plat/aspeed/ast2700/plat_bl31_setup.c
@@ -174,7 +174,7 @@
break;
}
} else {
- if (pll_reg.b.bypass != 0U) {
+ if (pll_reg.b.bypass == 0U) {
if (pll_idx == PLAT_CLK_MPLL) {
/* F = 25Mhz * [M / (n + 1)] / (p + 1) */
mul = (pll_reg.b.m) / ((pll_reg.b.n + 1));
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index 950d8fd..2bda3a5 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk
@@ -71,7 +71,6 @@
ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
-$(eval $(call MAKE_LIB_DIRS))
$(BUILD_PLAT)/bl2/imx7_rotpk.o: $(ROTPK_HASH)
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 40554c3..f0cdb3e 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -127,7 +127,6 @@
ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
-$(eval $(call MAKE_LIB_DIRS))
$(BUILD_PLAT)/bl2/imx8mm_rotpk.o: $(ROTPK_HASH)
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 5f4ddee..5df598c 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -124,7 +124,6 @@
ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
-$(eval $(call MAKE_LIB_DIRS))
$(BUILD_PLAT)/bl2/imx8mp_rotpk.o: $(ROTPK_HASH)
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index 18f5430..e8f892d 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -167,10 +167,9 @@
$(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
$(q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
-$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL)
+$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL) | $(BUILD_PLAT)/$(BUILD_UART)/ $$(@D)/
$(s)echo
$(s)echo "Building uart images"
- $(q)mkdir -p $(BUILD_PLAT)/$(BUILD_UART)
$(q)cp -a $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/$(BUILD_UART)/wtmi.bin
$(q)cp -a $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/$(BUILD_UART)/$(BOOT_IMAGE)
$(q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TIMBUILD) $(TIMBLDUARTARGS)
diff --git a/plat/mediatek/build_helpers/mtk_build_helpers.mk b/plat/mediatek/build_helpers/mtk_build_helpers.mk
index a497049..0cb2014 100644
--- a/plat/mediatek/build_helpers/mtk_build_helpers.mk
+++ b/plat/mediatek/build_helpers/mtk_build_helpers.mk
@@ -71,15 +71,6 @@
$(eval SOURCES := $(2))
$(eval OBJS_TEMP := $(addprefix $(BUILD_DIR)/$(MODULE)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
$(eval MODULE_OBJS += $(OBJS_TEMP))
- # We use sort only to get a list of unique object directory names.
- # ordering is not relevant but sort removes duplicates.
- $(eval TEMP_OBJ_DIRS := $(sort $(dir ${OBJS_TEMP} ${LINKERFILE})))
- # The $(dir ) function leaves a trailing / on the directory names
- # Rip off the / to match directory names with make rule targets.
- $(eval OBJ_DIRS := $(patsubst %/,%,$(TEMP_OBJ_DIRS)))
-
-$(eval $(foreach objd,${OBJ_DIRS},$(call MAKE_PREREQ_DIR,${objd},${BUILD_DIR})))
-${3}_dirs: | ${OBJ_DIRS}
$(eval $(call MAKE_OBJS,$(BUILD_DIR)/$(MODULE),$(SOURCES),${3}))
diff --git a/plat/nvidia/tegra/common/tegra_fiq_glue.c b/plat/nvidia/tegra/common/tegra_fiq_glue.c
index 5309d98..4ff9888 100644
--- a/plat/nvidia/tegra/common/tegra_fiq_glue.c
+++ b/plat/nvidia/tegra/common/tegra_fiq_glue.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -142,7 +142,7 @@
val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0));
write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val));
- val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1));
+ val = read_el1_ctx_common(el1state_ctx, sp_el1);
write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val));
return 0;
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 83d815a..8232883 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -356,10 +356,10 @@
* will re-init this info from non-secure software when the
* core come online.
*/
- actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1));
+ actlr_elx = read_el1_ctx_common((get_el1_sysregs_ctx(ctx)), actlr_el1);
actlr_elx &= ~DENVER_CPU_PMSTATE_MASK;
actlr_elx |= DENVER_CPU_PMSTATE_C1;
- write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
+ write_el1_ctx_common((get_el1_sysregs_ctx(ctx)), actlr_el1, actlr_elx);
/*
* Check if we are exiting from deep sleep and restore SE
diff --git a/plat/nxp/soc-lx2160a/ddr_fip.mk b/plat/nxp/soc-lx2160a/ddr_fip.mk
index e717cbc..c303ced 100644
--- a/plat/nxp/soc-lx2160a/ddr_fip.mk
+++ b/plat/nxp/soc-lx2160a/ddr_fip.mk
@@ -38,8 +38,6 @@
DDR_DMEM_RDIMM_2D := ${DDR_PHY_BIN_PATH}/ddr4_rdimm2d_pmu_train_dmem.bin
endif
-$(shell mkdir -p '${BUILD_PLAT}')
-
ifeq (${DDR_FIP_NAME},)
ifeq (${TRUSTED_BOARD_BOOT},1)
DDR_FIP_NAME := ddr_fip_sec.bin
diff --git a/plat/nxp/soc-lx2160a/ddr_tbbr.mk b/plat/nxp/soc-lx2160a/ddr_tbbr.mk
index deb475b..836a431 100644
--- a/plat/nxp/soc-lx2160a/ddr_tbbr.mk
+++ b/plat/nxp/soc-lx2160a/ddr_tbbr.mk
@@ -39,8 +39,6 @@
# Pass the non-volatile counters to the cert_create tool
$(eval $(call CERT_ADD_CMD_OPT,${TFW_NVCTR_VAL},--tfw-nvctr,DDR_))
-$(shell mkdir -p '${BUILD_PLAT}')
-
ifeq (${DDR_KEY},)
DDR_KEY=${BUILD_PLAT}/ddr.pem
endif
diff --git a/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c b/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c
index c4cd259..804ad42 100644
--- a/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c
+++ b/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c
@@ -142,10 +142,10 @@
qti_ns_ctx->elr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_ELR_EL3);
qti_ns_ctx->spsr_el1 =
- read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SPSR_EL1);
+ read_el1_ctx_common(get_el1_sysregs_ctx(ctx), spsr_el1);
qti_ns_ctx->elr_el1 =
- read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_ELR_EL1);
- qti_ns_ctx->sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SP_EL1);
+ read_el1_ctx_common(get_el1_sysregs_ctx(ctx), elr_el1);
+ qti_ns_ctx->sp_el1 = read_el1_ctx_common(get_el1_sysregs_ctx(ctx), sp_el1);
qti_ns_ctx->x0 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0);
qti_ns_ctx->x1 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1);
diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h
index f1c2553..8676444 100644
--- a/plat/renesas/common/include/rcar_def.h
+++ b/plat/renesas/common/include/rcar_def.h
@@ -310,4 +310,31 @@
#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
#define LOSSY_ENA_DIS2 LOSSY_DISABLE
+#define RCAR_CC63_BASE 0xE6600000U
+#define CC63_TRNG_ISR_REG_ADDR 0x104U
+#define CC63_TRNG_ISR_REG_EHR_VALID BIT_32(0)
+#define CC63_TRNG_ISR_REG_AUTOCORR_ERR BIT_32(1)
+#define CC63_TRNG_ICR_REG_ADDR 0x108U
+#define CC63_TRNG_CONFIG_REG_ADDR 0x10CU
+#define CC63_TRNG_CONFIG_REG_ROSC_MAX_LENGTH 3
+#define CC63_TRNG_VALID_REG_ADDR 0x110U
+#define CC63_TRNG_VALID_REG_EHR_NOT_READY 0x0
+#define CC63_TRNG_EHR_DATA_ADDR_0_REG_ADDR 0x114U
+#define CC63_TRNG_SOURCE_ENABLE_REG_ADDR 0x12CU
+#define CC63_TRNG_SOURCE_ENABLE_REG_SET 0x1
+#define CC63_TRNG_SOURCE_ENABLE_REG_CLR 0x0
+#define CC63_TRNG_SAMPLE_CNT1_REG_ADDR 0x130U
+#define CC63_TRNG_SAMPLE_CNT1_REG_SAMPLE_COUNT 100
+#define CC63_TRNG_DEBUG_CONTROL_REG_ADDR 0x138U
+#define CC63_TRNG_DEBUG_CONTROL_REG_VNC_BYPASS BIT_32(1)
+#define CC63_TRNG_DEBUG_CONTROL_REG_AUTOCORR_BYPASS BIT_32(3)
+#define CC63_TRNG_DEBUG_CONTROL_REG_80090B \
+ (CC63_TRNG_DEBUG_CONTROL_REG_VNC_BYPASS | \
+ CC63_TRNG_DEBUG_CONTROL_REG_AUTOCORR_BYPASS)
+#define CC63_TRNG_SW_RESET_REG_ADDR 0x140U
+#define CC63_TRNG_SW_RESET_REG_SET 0x1
+#define CC63_TRNG_VERSION_REG_ADDR 0x1C0U
+#define CC63_TRNG_CLK_ENABLE_REG_ADDR 0x1C4U
+#define CC63_TRNG_CLK_ENABLE_REG_SET 0x1
+
#endif /* RCAR_DEF_H */
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 41031d6..c548240 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -756,6 +756,69 @@
#endif
}
+static void bl2_add_kaslr_seed(void)
+{
+ uint32_t cnt, isr, prr;
+ uint64_t seed;
+ int ret, node;
+
+ /* SCEG is only available on H3/M3-W/M3-N */
+ prr = mmio_read_32(RCAR_PRR);
+ switch (prr & PRR_PRODUCT_MASK) {
+ case PRR_PRODUCT_H3:
+ case PRR_PRODUCT_M3:
+ case PRR_PRODUCT_M3N:
+ break;
+ default:
+ return;
+ }
+
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SW_RESET_REG_ADDR,
+ CC63_TRNG_SW_RESET_REG_SET);
+
+ do {
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_CLK_ENABLE_REG_ADDR,
+ CC63_TRNG_CLK_ENABLE_REG_SET);
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SAMPLE_CNT1_REG_ADDR,
+ CC63_TRNG_SAMPLE_CNT1_REG_SAMPLE_COUNT);
+ cnt = mmio_read_32(RCAR_CC63_BASE + CC63_TRNG_SAMPLE_CNT1_REG_ADDR);
+ } while (cnt != CC63_TRNG_SAMPLE_CNT1_REG_SAMPLE_COUNT);
+
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_CONFIG_REG_ADDR,
+ CC63_TRNG_CONFIG_REG_ROSC_MAX_LENGTH);
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_DEBUG_CONTROL_REG_ADDR,
+ CC63_TRNG_DEBUG_CONTROL_REG_80090B);
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SOURCE_ENABLE_REG_ADDR,
+ CC63_TRNG_SOURCE_ENABLE_REG_SET);
+
+ do {
+ isr = mmio_read_32(RCAR_CC63_BASE + CC63_TRNG_ISR_REG_ADDR);
+ if ((isr & CC63_TRNG_ISR_REG_AUTOCORR_ERR) != 0U) {
+ panic();
+ }
+ } while ((isr & CC63_TRNG_ISR_REG_EHR_VALID) == 0U);
+
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_ICR_REG_ADDR, UINT32_MAX);
+ seed = mmio_read_64(RCAR_CC63_BASE + CC63_TRNG_EHR_DATA_ADDR_0_REG_ADDR);
+ mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SOURCE_ENABLE_REG_ADDR,
+ CC63_TRNG_SOURCE_ENABLE_REG_CLR);
+
+ node = ret = fdt_add_subnode(fdt, 0, "chosen");
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_setprop_u64(fdt, node, "kaslr-seed", seed);
+ if (ret < 0) {
+ goto err;
+ }
+
+ return;
+err:
+ NOTICE("BL2: Cannot add KASLR seed to FDT (ret=%i)\n", ret);
+ panic();
+}
+
static void bl2_add_dram_entry(uint64_t start, uint64_t size)
{
char nodename[32] = { 0 };
@@ -1215,6 +1278,9 @@
/* Print DRAM layout */
bl2_advertise_dram_size(product);
+ /* Add KASLR seed */
+ bl2_add_kaslr_seed();
+
if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
if (rcar_emmc_init() != EMMC_SUCCESS) {
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index 2394dce..9d0e215 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -104,9 +104,8 @@
${BUILD_PLAT}/bl31/pmu_fw.o: CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW)
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.S: $(RK3399M0FW)
-$(eval $(call MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT}))
.PHONY: $(RK3399M0FW)
-$(RK3399M0FW): | ${BUILD_M0}
+$(RK3399M0FW): | $$(@D)/
$(MAKE) -C ${RK_PLAT_SOC}/drivers/m0 BUILD=$(abspath ${BUILD_PLAT}/m0)
# Do not enable SVE
diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index 8b81c7f..fba7783 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk
@@ -41,7 +41,7 @@
fi
# Create DTB file for BL2
-${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | ${BUILD_PLAT} fdt_dirs
+${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | $$(@D)/
$(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@
$(q)echo '#include "${BL2_DTSI}"' >> $@
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index a1f44e8..138f16c 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -255,11 +255,11 @@
ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32
-${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | ${BUILD_PLAT} fdt_dirs
+${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | $$(@D)/
$(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@
$(q)echo '#include "${BL32_DTSI}"' >> $@
-${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts
+${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts | $$(@D)/
endif
include plat/st/common/common_rules.mk
diff --git a/plat/xilinx/common/include/pm_api_sys.h b/plat/xilinx/common/include/pm_api_sys.h
index ffee805..029bb43 100644
--- a/plat/xilinx/common/include/pm_api_sys.h
+++ b/plat/xilinx/common/include/pm_api_sys.h
@@ -64,6 +64,7 @@
uint32_t wake, uint32_t enable,
uint32_t flag);
enum pm_ret_status pm_get_chipid(uint32_t *value);
+enum pm_ret_status eemi_feature_check(uint32_t api_id, uint32_t *ret_payload);
/*
* Assigning of argument values into array elements.
@@ -97,4 +98,9 @@
PM_PACK_PAYLOAD5(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
}
+#define PM_PACK_PAYLOAD7(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5, arg6) { \
+ pl[6] = (uint32_t)(arg6); \
+ PM_PACK_PAYLOAD6(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4), (arg5)); \
+}
+
#endif /* PM_API_SYS_H */
diff --git a/plat/xilinx/common/include/pm_common.h b/plat/xilinx/common/include/pm_common.h
index c0308ab..c38cdef 100644
--- a/plat/xilinx/common/include/pm_common.h
+++ b/plat/xilinx/common/include/pm_common.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,13 +18,15 @@
#if IPI_CRC_CHECK
#define PAYLOAD_ARG_CNT 8U
+#define RET_PAYLOAD_ARG_CNT 7U
#define IPI_W0_TO_W6_SIZE 28U
#define PAYLOAD_CRC_POS 7U
#define CRC_INIT_VALUE 0x4F4EU
#define CRC_ORDER 16U
#define CRC_POLYNOM 0x8005U
#else
-#define PAYLOAD_ARG_CNT 6U
+#define PAYLOAD_ARG_CNT 7U
+#define RET_PAYLOAD_ARG_CNT 6U
#endif
#define PAYLOAD_ARG_SIZE 4U /* size in bytes */
diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index 055fa3d..30b75bc 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h
@@ -35,6 +35,7 @@
(uint32_t)XPM_NODESUBCL_DEV_PERIPH, \
(uint32_t)XPM_NODETYPE_DEV_PERIPH, (IDX))
+#define TF_A_FEATURE_CHECK 0xa00U
#define PM_GET_CALLBACK_DATA 0xa01U
#define PM_GET_TRUSTZONE_VERSION 0xa03U
#define TF_A_PM_REGISTER_SGI 0xa04U
diff --git a/plat/xilinx/common/include/pm_svc_main.h b/plat/xilinx/common/include/pm_svc_main.h
index 67fbeae..000f198 100644
--- a/plat/xilinx/common/include/pm_svc_main.h
+++ b/plat/xilinx/common/include/pm_svc_main.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,8 @@
extern bool pwrdwn_req_received;
+#define PASS_THROUGH_FW_CMD_ID U(0xfff)
+
/******************************************************************************/
/**
* SECURE_REDUNDANT_CALL() - Adds redundancy to the function call. This is to
diff --git a/plat/xilinx/common/pm_service/pm_api_sys.c b/plat/xilinx/common/pm_service/pm_api_sys.c
index 0a6e810..e9c5f13 100644
--- a/plat/xilinx/common/pm_service/pm_api_sys.c
+++ b/plat/xilinx/common/pm_service/pm_api_sys.c
@@ -122,7 +122,7 @@
}
PM_PACK_PAYLOAD6(payload, module_id, flag, x0, x1, x2, x3, x4, x5);
- return pm_ipi_send_sync(primary_proc, payload, (uint32_t *)result, PAYLOAD_ARG_CNT);
+ return pm_ipi_send_sync(primary_proc, payload, (uint32_t *)result, RET_PAYLOAD_ARG_CNT);
}
/**
@@ -364,6 +364,37 @@
}
/**
+ * eemi_feature_check() - Returns the supported API version if supported.
+ * @api_id: API ID to check.
+ * @ret_payload: pointer to array of PAYLOAD_ARG_CNT number of
+ * words Returned supported API version
+ *
+ * Return: Returns status, either success or error+reason.
+ */
+enum pm_ret_status eemi_feature_check(uint32_t api_id, uint32_t *ret_payload)
+{
+ enum pm_ret_status ret;
+
+ /* Return version of API which are implemented in TF-A only */
+ switch (api_id) {
+ case PM_GET_CALLBACK_DATA:
+ case PM_GET_TRUSTZONE_VERSION:
+ ret_payload[0] = PM_API_VERSION_2;
+ ret = PM_RET_SUCCESS;
+ break;
+ case TF_A_PM_REGISTER_SGI:
+ case TF_A_FEATURE_CHECK:
+ ret_payload[0] = PM_API_BASE_VERSION;
+ ret = PM_RET_SUCCESS;
+ break;
+ default:
+ ret = PM_RET_ERROR_NO_FEATURE;
+ }
+
+ return ret;
+}
+
+/**
* pm_feature_check() - Returns the supported API version if supported.
* @api_id: API ID to check.
* @flag: 0 - Call from secure source.
@@ -406,7 +437,7 @@
PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
PM_FEATURE_CHECK, api_id);
- return pm_ipi_send_sync(primary_proc, payload, ret_payload, PAYLOAD_ARG_CNT);
+ return pm_ipi_send_sync(primary_proc, payload, ret_payload, RET_PAYLOAD_ARG_CNT);
}
/**
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index 56567dd..205877c 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -164,15 +164,10 @@
*
*/
static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc,
- uint32_t *value, size_t count)
+ uint32_t value[PAYLOAD_ARG_CNT])
{
size_t i;
enum pm_ret_status ret;
-#if IPI_CRC_CHECK
- uint32_t *payload_ptr = value;
- size_t j;
- uint32_t response_payload[PAYLOAD_ARG_CNT];
-#endif
uintptr_t buffer_base = proc->ipi->buffer_base +
IPI_BUFFER_TARGET_REMOTE_OFFSET +
IPI_BUFFER_RESP_OFFSET;
@@ -184,27 +179,21 @@
* buf-2: unused
* buf-3: unused
*/
- for (i = 1; i <= count; i++) {
- *value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
- value++;
+ for (i = 0; i < PAYLOAD_ARG_CNT; i++) {
+ value[i] = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
}
- ret = mmio_read_32(buffer_base);
+ ret = value[0];
#if IPI_CRC_CHECK
- for (j = 0; j < PAYLOAD_ARG_CNT; j++) {
- response_payload[j] = mmio_read_32(buffer_base +
- (j * PAYLOAD_ARG_SIZE));
- }
-
- if (response_payload[PAYLOAD_CRC_POS] !=
- calculate_crc(response_payload, IPI_W0_TO_W6_SIZE)) {
+ if (value[PAYLOAD_CRC_POS] !=
+ calculate_crc(value, IPI_W0_TO_W6_SIZE)) {
NOTICE("ERROR in CRC response payload value:0x%x\n",
- response_payload[PAYLOAD_CRC_POS]);
+ value[PAYLOAD_CRC_POS]);
ret = PM_RET_ERROR_INVALID_CRC;
/* Payload data is invalid as CRC validation failed
* Clear the payload to avoid leakage of data to upper layers
*/
- memset(payload_ptr, 0, count);
+ memset(value, 0, PAYLOAD_ARG_CNT);
}
#endif
@@ -240,7 +229,7 @@
count = IPI_BUFFER_MAX_WORDS;
}
- for (i = 0; i <= count; i++) {
+ for (i = 0; i < count; i++) {
*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
value++;
}
@@ -282,6 +271,7 @@
uint32_t *value, size_t count)
{
enum pm_ret_status ret;
+ uint32_t i, ret_payload[PAYLOAD_ARG_CNT] = {0U};
pm_ipi_lock_get();
@@ -290,7 +280,12 @@
goto unlock;
}
+ ret = ERROR_CODE_MASK & (pm_ipi_buff_read(proc, ret_payload));
+
- ret = ERROR_CODE_MASK & (pm_ipi_buff_read(proc, value, count));
+ for (i = 1U; i <= count; i++) {
+ *value = ret_payload[i];
+ value++;
+ }
unlock:
pm_ipi_lock_release();
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index 7ac0ac1..b431a6c 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -36,6 +36,32 @@
#define EVENT_CPU_PWRDWN (4U)
#define MBOX_SGI_SHARED_IPI (7U)
+/**
+ * upper_32_bits - return bits 32-63 of a number
+ * @n: the number we're accessing
+ */
+#define upper_32_bits(n) ((uint32_t)((n) >> 32U))
+
+/**
+ * lower_32_bits - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define lower_32_bits(n) ((uint32_t)((n) & 0xffffffffU))
+
+/**
+ * EXTRACT_SMC_ARGS - extracts 32-bit payloads from 64-bit SMC arguments
+ * @pm_arg: array of 32-bit payloads
+ * @x: array of 64-bit SMC arguments
+ */
+#define EXTRACT_ARGS(pm_arg, x) \
+ for (uint32_t i = 0U; i < (PAYLOAD_ARG_CNT - 1U); i++) { \
+ if ((i % 2U) != 0U) { \
+ pm_arg[i] = lower_32_bits(x[(i / 2U) + 1U]); \
+ } else { \
+ pm_arg[i] = upper_32_bits(x[i / 2U]); \
+ } \
+ }
+
/* 1 sec of wait timeout for secondary core down */
#define PWRDWN_WAIT_TIMEOUT (1000U)
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6)
@@ -278,7 +304,7 @@
case (uint32_t)PM_FEATURE_CHECK:
{
- uint32_t result[PAYLOAD_ARG_CNT] = {0U};
+ uint32_t result[RET_PAYLOAD_ARG_CNT] = {0U};
ret = pm_feature_check(pm_arg[0], result, security_flag);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
@@ -367,6 +393,15 @@
{
switch (api_id) {
+ case TF_A_FEATURE_CHECK:
+ {
+ enum pm_ret_status ret;
+ uint32_t result[PAYLOAD_ARG_CNT] = {0U};
+
+ ret = eemi_feature_check(pm_arg[0], result);
+ SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U));
+ }
+
case TF_A_PM_REGISTER_SGI:
{
int32_t ret;
@@ -424,7 +459,7 @@
void *handle, uint32_t security_flag)
{
enum pm_ret_status ret;
- uint32_t buf[PAYLOAD_ARG_CNT] = {0};
+ uint32_t buf[RET_PAYLOAD_ARG_CNT] = {0};
ret = pm_handle_eemi_call(security_flag, api_id, pm_arg[0], pm_arg[1],
pm_arg[2], pm_arg[3], pm_arg[4],
@@ -449,6 +484,45 @@
}
/**
+ * eemi_api_handler() - Prepare EEMI payload and perform IPI transaction.
+ * @api_id: identifier for the API being called.
+ * @pm_arg: pointer to the argument data for the API call.
+ * @handle: Pointer to caller's context structure.
+ * @security_flag: SECURE_FLAG or NON_SECURE_FLAG.
+ *
+ * EEMI - Embedded Energy Management Interface is AMD-Xilinx proprietary
+ * protocol to allow communication between power management controller and
+ * different processing clusters.
+ *
+ * This handler prepares EEMI protocol payload received from kernel and performs
+ * IPI transaction.
+ *
+ * Return: If EEMI API found then, uintptr_t type address, else 0
+ */
+static uintptr_t eemi_api_handler(uint32_t api_id, const uint32_t *pm_arg,
+ void *handle, uint32_t security_flag)
+{
+ enum pm_ret_status ret;
+ uint32_t buf[PAYLOAD_ARG_CNT] = {0};
+ uint32_t payload[PAYLOAD_ARG_CNT] = {0};
+ uint32_t module_id;
+
+ module_id = (api_id & MODULE_ID_MASK) >> 8U;
+
+ PM_PACK_PAYLOAD7(payload, module_id, security_flag, api_id,
+ pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
+ pm_arg[4], pm_arg[5]);
+
+ ret = pm_ipi_send_sync(primary_proc, payload, (uint32_t *)buf,
+ PAYLOAD_ARG_CNT);
+
+ SMC_RET4(handle, (uint64_t)ret | ((uint64_t)buf[0] << 32U),
+ (uint64_t)buf[1] | ((uint64_t)buf[2] << 32U),
+ (uint64_t)buf[3] | ((uint64_t)buf[4] << 32U),
+ (uint64_t)buf[5]);
+}
+
+/**
* pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2.
* @smc_fid: Function Identifier.
* @x1: SMC64 Arguments from kernel.
@@ -477,6 +551,7 @@
uint32_t security_flag = NON_SECURE_FLAG;
uint32_t api_id;
bool status = false, status_tmp = false;
+ uint64_t x[4] = {x1, x2, x3, x4};
/* Handle case where PM wasn't initialized properly */
if (pm_up == false) {
@@ -494,6 +569,14 @@
security_flag = SECURE_FLAG;
}
+ if ((smc_fid & FUNCID_NUM_MASK) == PASS_THROUGH_FW_CMD_ID) {
+ api_id = lower_32_bits(x[0]);
+
+ EXTRACT_ARGS(pm_arg, x);
+
+ return eemi_api_handler(api_id, pm_arg, handle, security_flag);
+ }
+
pm_arg[0] = (uint32_t)x1;
pm_arg[1] = (uint32_t)(x1 >> 32U);
pm_arg[2] = (uint32_t)x2;
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 4cf1ed1..74c5bf3 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -197,7 +197,7 @@
*/
static void versal_pwr_domain_off(const psci_power_state_t *target_state)
{
- uint32_t ret, fw_api_version, version[PAYLOAD_ARG_CNT] = {0U};
+ uint32_t ret, fw_api_version, version[RET_PAYLOAD_ARG_CNT] = {0U};
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index 4441d3e..3c0bd63 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,7 +22,7 @@
/* SiP Service Calls version numbers */
#define SIP_SVC_VERSION_MAJOR U(0)
-#define SIP_SVC_VERSION_MINOR U(1)
+#define SIP_SVC_VERSION_MINOR U(2)
/* These macros are used to identify PM calls from the SMC function ID */
#define SIP_FID_MASK GENMASK(23, 16)
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index e5a5235..fb2005d 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -59,7 +59,7 @@
*/
static void versal_net_pwr_domain_off(const psci_power_state_t *target_state)
{
- uint32_t ret, fw_api_version, version[PAYLOAD_ARG_CNT] = {0U};
+ uint32_t ret, fw_api_version, version[RET_PAYLOAD_ARG_CNT] = {0U};
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
diff --git a/plat/xilinx/versal_net/sip_svc_setup.c b/plat/xilinx/versal_net/sip_svc_setup.c
index 80d5a53..c974810 100644
--- a/plat/xilinx/versal_net/sip_svc_setup.c
+++ b/plat/xilinx/versal_net/sip_svc_setup.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,7 +25,7 @@
/* SiP Service Calls version numbers */
#define SIP_SVC_VERSION_MAJOR (0U)
-#define SIP_SVC_VERSION_MINOR (1U)
+#define SIP_SVC_VERSION_MINOR (2U)
/* These macros are used to identify PM calls from the SMC function ID */
#define SIP_FID_MASK GENMASK(23, 16)
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 3d546b3..66f011a 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -919,7 +919,7 @@
enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *version,
uint32_t *bit_mask, uint8_t len)
{
- uint32_t ret_payload[PAYLOAD_ARG_CNT] = {0U};
+ uint32_t ret_payload[RET_PAYLOAD_ARG_CNT] = {0U};
uint32_t status;
/* Get API version implemented in TF-A */
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index 5a6a9f8..bf17ea4 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -285,7 +285,7 @@
uint32_t payload[PAYLOAD_ARG_CNT];
uint32_t pm_arg[5];
- uint32_t result[PAYLOAD_ARG_CNT] = {0};
+ uint32_t result[RET_PAYLOAD_ARG_CNT] = {0};
uint32_t api_id;
/* Handle case where PM wasn't initialized properly */
@@ -566,7 +566,7 @@
PM_PACK_PAYLOAD6(payload, api_id, pm_arg[0], pm_arg[1],
pm_arg[2], pm_arg[3], pm_arg[4]);
ret = pm_ipi_send_sync(primary_proc, payload, result,
- PAYLOAD_ARG_CNT);
+ RET_PAYLOAD_ARG_CNT);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32U),
(uint64_t)result[1] | ((uint64_t)result[2] << 32U));
}
diff --git a/poetry.lock b/poetry.lock
index 6bfbd50..b465f48 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -1,4 +1,4 @@
-# This file is automatically @generated by Poetry 1.8.3 and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.8.2 and should not be changed by hand.
[[package]]
name = "alabaster"
@@ -13,57 +13,58 @@
[[package]]
name = "anytree"
-version = "2.8.0"
-description = "Powerful and Lightweight Python Tree Data Structure.."
+version = "2.12.1"
+description = "Powerful and Lightweight Python Tree Data Structure with various plugins"
optional = false
-python-versions = "*"
+python-versions = ">=3.7.2,<4"
files = [
- {file = "anytree-2.8.0-py2.py3-none-any.whl", hash = "sha256:14c55ac77492b11532395049a03b773d14c7e30b22aa012e337b1e983de31521"},
- {file = "anytree-2.8.0.tar.gz", hash = "sha256:3f0f93f355a91bc3e6245319bf4c1d50e3416cc7a35cc1133c1ff38306bbccab"},
+ {file = "anytree-2.12.1-py3-none-any.whl", hash = "sha256:5ea9e61caf96db1e5b3d0a914378d2cd83c269dfce1fb8242ce96589fa3382f0"},
+ {file = "anytree-2.12.1.tar.gz", hash = "sha256:244def434ccf31b668ed282954e5d315b4e066c4940b94aff4a7962d85947830"},
]
[package.dependencies]
-six = ">=1.9.0"
-
-[package.extras]
-dev = ["check-manifest"]
-test = ["coverage"]
+six = "*"
[[package]]
name = "babel"
-version = "2.12.1"
+version = "2.15.0"
description = "Internationalization utilities"
optional = false
-python-versions = ">=3.7"
+python-versions = ">=3.8"
files = [
- {file = "Babel-2.12.1-py3-none-any.whl", hash = "sha256:b4246fb7677d3b98f501a39d43396d3cafdc8eadb045f4a31be01863f655c610"},
- {file = "Babel-2.12.1.tar.gz", hash = "sha256:cc2d99999cd01d44420ae725a21c9e3711b3aadc7976d6147f622d8581963455"},
+ {file = "Babel-2.15.0-py3-none-any.whl", hash = "sha256:08706bdad8d0a3413266ab61bd6c34d0c28d6e1e7badf40a2cebe67644e2e1fb"},
+ {file = "babel-2.15.0.tar.gz", hash = "sha256:8daf0e265d05768bc6c7a314cf1321e9a123afc328cc635c18622a2f30a04413"},
]
[package.dependencies]
pytz = {version = ">=2015.7", markers = "python_version < \"3.9\""}
+[package.extras]
+dev = ["freezegun (>=1.0,<2.0)", "pytest (>=6.0)", "pytest-cov"]
+
[[package]]
name = "build"
-version = "0.10.0"
+version = "1.2.1"
description = "A simple, correct Python build frontend"
optional = false
-python-versions = ">= 3.7"
+python-versions = ">=3.8"
files = [
- {file = "build-0.10.0-py3-none-any.whl", hash = "sha256:af266720050a66c893a6096a2f410989eeac74ff9a68ba194b3f6473e8e26171"},
- {file = "build-0.10.0.tar.gz", hash = "sha256:d5b71264afdb5951d6704482aac78de887c80691c52b88a9ad195983ca2c9269"},
+ {file = "build-1.2.1-py3-none-any.whl", hash = "sha256:75e10f767a433d9a86e50d83f418e83efc18ede923ee5ff7df93b6cb0306c5d4"},
+ {file = "build-1.2.1.tar.gz", hash = "sha256:526263f4870c26f26c433545579475377b2b7588b6f1eac76a001e873ae3e19d"},
]
[package.dependencies]
colorama = {version = "*", markers = "os_name == \"nt\""}
-packaging = ">=19.0"
+importlib-metadata = {version = ">=4.6", markers = "python_full_version < \"3.10.2\""}
+packaging = ">=19.1"
pyproject_hooks = "*"
tomli = {version = ">=1.1.0", markers = "python_version < \"3.11\""}
[package.extras]
-docs = ["furo (>=2021.08.31)", "sphinx (>=4.0,<5.0)", "sphinx-argparse-cli (>=1.5)", "sphinx-autodoc-typehints (>=1.10)"]
-test = ["filelock (>=3)", "pytest (>=6.2.4)", "pytest-cov (>=2.12)", "pytest-mock (>=2)", "pytest-rerunfailures (>=9.1)", "pytest-xdist (>=1.34)", "setuptools (>=42.0.0)", "setuptools (>=56.0.0)", "toml (>=0.10.0)", "wheel (>=0.36.0)"]
-typing = ["importlib-metadata (>=5.1)", "mypy (==0.991)", "tomli", "typing-extensions (>=3.7.4.3)"]
+docs = ["furo (>=2023.08.17)", "sphinx (>=7.0,<8.0)", "sphinx-argparse-cli (>=1.5)", "sphinx-autodoc-typehints (>=1.10)", "sphinx-issues (>=3.0.0)"]
+test = ["build[uv,virtualenv]", "filelock (>=3)", "pytest (>=6.2.4)", "pytest-cov (>=2.12)", "pytest-mock (>=2)", "pytest-rerunfailures (>=9.1)", "pytest-xdist (>=1.34)", "setuptools (>=42.0.0)", "setuptools (>=56.0.0)", "setuptools (>=56.0.0)", "setuptools (>=67.8.0)", "wheel (>=0.36.0)"]
+typing = ["build[uv]", "importlib-metadata (>=5.1)", "mypy (>=1.9.0,<1.10.0)", "tomli", "typing-extensions (>=3.7.4.3)"]
+uv = ["uv (>=0.1.18)"]
virtualenv = ["virtualenv (>=20.0.35)"]
[[package]]
@@ -79,97 +80,112 @@
[[package]]
name = "charset-normalizer"
-version = "3.1.0"
+version = "3.3.2"
description = "The Real First Universal Charset Detector. Open, modern and actively maintained alternative to Chardet."
optional = false
python-versions = ">=3.7.0"
files = [
- {file = "charset-normalizer-3.1.0.tar.gz", hash = "sha256:34e0a2f9c370eb95597aae63bf85eb5e96826d81e3dcf88b8886012906f509b5"},
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lock-version = "2.0"
python-versions = "^3.8"
-content-hash = "62d9ce9ca1c9f4669c7b40724acfc93968cde31c0460d1d7515d289739dc9464"
+content-hash = "8798a2d1efd456c3b68ae464a216f015afaa1bbb653a905148bef17ab8ce278e"
diff --git a/pyproject.toml b/pyproject.toml
index 7814497..03d898e 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -14,8 +14,12 @@
[tool.poetry.dependencies]
python = "^3.8"
+tlc = {path = "tools/tlc"}
+
+[tool.poetry.group.docs]
+optional = true
-[tool.poetry.group.doc.dependencies]
+[tool.poetry.group.docs.dependencies]
sphinx = "^5.3.0"
myst-parser = "^0.18.1"
sphinxcontrib-plantuml = "^0.24.1"
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index 7daebcd..f2048a3 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -160,9 +160,9 @@
(void)memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs));
ctx->fiq_pc = SMC_GET_EL3(handle, CTX_ELR_EL3);
ctx->fiq_cpsr = SMC_GET_EL3(handle, CTX_SPSR_EL3);
- ctx->fiq_sp_el1 = read_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1);
+ ctx->fiq_sp_el1 = read_el1_ctx_common(get_el1_sysregs_ctx(handle), sp_el1);
- write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_handler_sp);
+ write_el1_ctx_common(get_el1_sysregs_ctx(handle), sp_el1, ctx->fiq_handler_sp);
cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, (uint32_t)ctx->fiq_handler_cpsr);
SMC_RET0(handle);
@@ -221,7 +221,7 @@
*/
(void)memcpy(get_gpregs_ctx(handle), &ctx->fiq_gpregs, sizeof(ctx->fiq_gpregs));
ctx->fiq_handler_active = 0;
- write_ctx_reg(get_el1_sysregs_ctx(handle), CTX_SP_EL1, ctx->fiq_sp_el1);
+ write_el1_ctx_common(get_el1_sysregs_ctx(handle), sp_el1, ctx->fiq_sp_el1);
cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, (uint32_t)ctx->fiq_cpsr);
SMC_RET0(handle);
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 6ccb003..15b3724 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -202,19 +202,23 @@
int rc;
/* Make sure RME is supported. */
- assert(is_feat_rme_present());
+ if (is_feat_rme_present() == 0U) {
+ /* Mark the RMM boot as failed for all the CPUs */
+ rmm_boot_failed = true;
+ return -ENOTSUP;
+ }
rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM);
- if (rmm_ep_info == NULL) {
+ if ((rmm_ep_info == NULL) || (rmm_ep_info->pc == 0)) {
WARN("No RMM image provided by BL2 boot loader, Booting "
"device without RMM initialization. SMCs destined for "
"RMM will return SMC_UNK\n");
+
+ /* Mark the boot as failed for all the CPUs */
+ rmm_boot_failed = true;
return -ENOENT;
}
- /* Under no circumstances will this parameter be 0 */
- assert(rmm_ep_info->pc == RMM_BASE);
-
/* Initialise an entrypoint to set up the CPU context */
ep_attr = EP_REALM;
if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0U) {
@@ -239,6 +243,8 @@
rc = plat_rmmd_load_manifest(manifest);
if (rc != 0) {
ERROR("Error loading RMM Boot Manifest (%i)\n", rc);
+ /* Mark the boot as failed for all the CPUs */
+ rmm_boot_failed = true;
return rc;
}
flush_dcache_range((uintptr_t)shared_buf_base, shared_buf_size);
diff --git a/services/std_svc/spm/el3_spmc/spmc_setup.c b/services/std_svc/spm/el3_spmc/spmc_setup.c
index 609d968..e8beae1 100644
--- a/services/std_svc/spm/el3_spmc/spmc_setup.c
+++ b/services/std_svc/spm/el3_spmc/spmc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -319,24 +319,35 @@
xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
EL1_EL0_REGIME);
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), mair_el1,
mmu_cfg_params[MMU_CFG_MAIR]);
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1,
+ /* Store the initialised SCTLR_EL1 value in the cpu_context */
+#if (ERRATA_SPECULATIVE_AT)
+ write_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_TCR_EL1, mmu_cfg_params[MMU_CFG_TCR]);
+#else
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), tcr_el1,
mmu_cfg_params[MMU_CFG_TCR]);
+#endif /* ERRATA_SPECULATIVE_AT */
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), ttbr0_el1,
mmu_cfg_params[MMU_CFG_TTBR0]);
}
static void spmc_el0_sp_setup_sctlr_el1(cpu_context_t *ctx)
{
- u_register_t sctlr_el1;
+ u_register_t sctlr_el1_val;
/* Setup SCTLR_EL1 */
- sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1);
+#if (ERRATA_SPECULATIVE_AT)
+ sctlr_el1_val = read_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_SCTLR_EL1);
+#else
+ sctlr_el1_val = read_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1);
+#endif /* ERRATA_SPECULATIVE_AT */
- sctlr_el1 |=
+ sctlr_el1_val |=
/*SCTLR_EL1_RES1 |*/
/* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
SCTLR_UCI_BIT |
@@ -357,7 +368,7 @@
/* Enable MMU. */
SCTLR_M_BIT;
- sctlr_el1 &= ~(
+ sctlr_el1_val &= ~(
/* Explicit data accesses at EL0 are little-endian. */
SCTLR_E0E_BIT |
/*
@@ -369,7 +380,13 @@
SCTLR_UMA_BIT
);
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
+ /* Store the initialised SCTLR_EL1 value in the cpu_context */
+#if (ERRATA_SPECULATIVE_AT)
+ write_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_SCTLR_EL1, sctlr_el1_val);
+#else
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1, sctlr_el1_val);
+#endif /* ERRATA_SPECULATIVE_AT */
}
static void spmc_el0_sp_setup_system_registers(struct secure_partition_desc *sp,
@@ -383,10 +400,10 @@
/* Setup other system registers. */
/* Shim Exception Vector Base Address */
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), vbar_el1,
SPM_SHIM_EXCEPTIONS_PTR);
#if NS_TIMER_SWITCH
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), cntkctl_el1,
EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
#endif
@@ -397,7 +414,7 @@
* TTA: Enable access to trace registers.
* ZEN (v8.2): Trap SVE instructions and access to SVE registers.
*/
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CPACR_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), cpacr_el1,
CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
}
diff --git a/services/std_svc/spm/spm_mm/spm_mm_setup.c b/services/std_svc/spm/spm_mm/spm_mm_setup.c
index 4e65c9c..bb9c7a9 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_setup.c
+++ b/services/std_svc/spm/spm_mm/spm_mm_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -27,7 +27,7 @@
void spm_sp_setup(sp_context_t *sp_ctx)
{
cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
-
+ u_register_t sctlr_el1_val;
/* Pointer to the MP information from the platform port. */
const spm_mm_boot_info_t *sp_boot_info =
plat_get_secure_partition_boot_info(NULL);
@@ -122,19 +122,30 @@
xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
EL1_EL0_REGIME);
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), mair_el1,
mmu_cfg_params[MMU_CFG_MAIR]);
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1,
+ /* Store the initialised SCTLR_EL1 value in the cpu_context */
+#if (ERRATA_SPECULATIVE_AT)
+ write_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_TCR_EL1, mmu_cfg_params[MMU_CFG_TCR]);
+#else
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), tcr_el1,
mmu_cfg_params[MMU_CFG_TCR]);
+#endif /* ERRATA_SPECULATIVE_AT */
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), ttbr0_el1,
mmu_cfg_params[MMU_CFG_TTBR0]);
/* Setup SCTLR_EL1 */
- u_register_t sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1);
+#if (ERRATA_SPECULATIVE_AT)
+ sctlr_el1_val = read_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_SCTLR_EL1);
+#else
+ sctlr_el1_val = read_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1);
+#endif /* ERRATA_SPECULATIVE_AT */
- sctlr_el1 |=
+ sctlr_el1_val |=
/*SCTLR_EL1_RES1 |*/
/* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
SCTLR_UCI_BIT |
@@ -156,7 +167,7 @@
SCTLR_M_BIT
;
- sctlr_el1 &= ~(
+ sctlr_el1_val &= ~(
/* Explicit data accesses at EL0 are little-endian. */
SCTLR_E0E_BIT |
/*
@@ -168,7 +179,13 @@
SCTLR_UMA_BIT
);
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
+ /* Store the initialised SCTLR_EL1 value in the cpu_context */
+#if (ERRATA_SPECULATIVE_AT)
+ write_ctx_reg(get_errata_speculative_at_ctx(ctx),
+ CTX_ERRATA_SPEC_AT_SCTLR_EL1, sctlr_el1_val);
+#else
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1, sctlr_el1_val);
+#endif /* ERRATA_SPECULATIVE_AT */
/*
* Setup other system registers
@@ -176,10 +193,10 @@
*/
/* Shim Exception Vector Base Address */
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), vbar_el1,
SPM_SHIM_EXCEPTIONS_PTR);
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1,
+ write_el1_ctx_arch_timer(get_el1_sysregs_ctx(ctx), cntkctl_el1,
EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
/*
@@ -189,7 +206,7 @@
* TTA: Enable access to trace registers.
* ZEN (v8.2): Trap SVE instructions and access to SVE registers.
*/
- write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CPACR_EL1,
+ write_el1_ctx_common(get_el1_sysregs_ctx(ctx), cpacr_el1,
CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
/*
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index e782d09..5cfe5f9 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -66,7 +66,7 @@
#if ENABLE_RME
if (rmmd_setup() != 0) {
- ret = 1;
+ WARN("RMMD setup failed. Continuing boot.\n");
}
#endif
diff --git a/tools/renesas/rcar_layout_create/makefile b/tools/renesas/rcar_layout_create/makefile
index 115ca5c..7a64b19 100644
--- a/tools/renesas/rcar_layout_create/makefile
+++ b/tools/renesas/rcar_layout_create/makefile
@@ -7,6 +7,7 @@
toolchains := aarch64
+include ../../../make_helpers/build-rules.mk
include ../../../make_helpers/common.mk
include ../../../make_helpers/toolchain.mk
@@ -94,29 +95,29 @@
# Linker
###################################################
-$(FILE_NAME_SA0).srec: $(OUTPUT_FILE_SA0)
+$(FILE_NAME_SA0).srec: $(OUTPUT_FILE_SA0) | $$(@D)/
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
-$(FILE_NAME_SA0).bin: $(OUTPUT_FILE_SA0)
+$(FILE_NAME_SA0).bin: $(OUTPUT_FILE_SA0) | $$(@D)/
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
-$(OUTPUT_FILE_SA0): $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
+$(OUTPUT_FILE_SA0): $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) | $$(@D)/
$(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib -T $(MEMORY_DEF_SA0) -o $(OUTPUT_FILE_SA0) -Wl,-Map $(FILE_NAME_SA0).map
-$(FILE_NAME_SA6).srec: $(OUTPUT_FILE_SA6)
+$(FILE_NAME_SA6).srec: $(OUTPUT_FILE_SA6) | $$(@D)/
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
-$(FILE_NAME_SA6).bin: $(OUTPUT_FILE_SA6)
+$(FILE_NAME_SA6).bin: $(OUTPUT_FILE_SA6) | $$(@D)/
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
-$(OUTPUT_FILE_SA6): $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
+$(OUTPUT_FILE_SA6): $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) | $$(@D)/
$(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib -T $(MEMORY_DEF_SA6) -o $(OUTPUT_FILE_SA6) -Wl,-Map $(FILE_NAME_SA6).map
###################################################
# Compile
###################################################
-%.o: %.c
+%.o: %.c | $$(@D)/
$(aarch64-cc) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<
.PHONY: clean
diff --git a/tools/renesas/rzg_layout_create/makefile b/tools/renesas/rzg_layout_create/makefile
index 1e8f7ff..936420d 100644
--- a/tools/renesas/rzg_layout_create/makefile
+++ b/tools/renesas/rzg_layout_create/makefile
@@ -7,6 +7,7 @@
toolchains := aarch64
+include ../../../make_helpers/build-rules.mk
include ../../../make_helpers/common.mk
include ../../../make_helpers/toolchain.mk
@@ -91,29 +92,29 @@
# Linker
###################################################
-$(FILE_NAME_SA0).srec: $(OUTPUT_FILE_SA0)
+$(FILE_NAME_SA0).srec: $(OUTPUT_FILE_SA0) | $$(@D)/
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
-$(FILE_NAME_SA0).bin: $(OUTPUT_FILE_SA0)
+$(FILE_NAME_SA0).bin: $(OUTPUT_FILE_SA0) | $$(@D)/
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
-$(OUTPUT_FILE_SA0): $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
+$(OUTPUT_FILE_SA0): $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) | $$(@D)/
$(aarch64-ld) $(OBJ_FILE_SA0) -nostdlib -T $(MEMORY_DEF_SA0) -o $(OUTPUT_FILE_SA0) -Wl,-Map $(FILE_NAME_SA0).map
-$(FILE_NAME_SA6).srec: $(OUTPUT_FILE_SA6)
+$(FILE_NAME_SA6).srec: $(OUTPUT_FILE_SA6) | $$(@D)/
$(aarch64-oc) -O srec --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
-$(FILE_NAME_SA6).bin: $(OUTPUT_FILE_SA6)
+$(FILE_NAME_SA6).bin: $(OUTPUT_FILE_SA6) | $$(@D)/
$(aarch64-oc) -O binary --adjust-vma=$(RCAR_VMA_ADJUST_ADDR) --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
-$(OUTPUT_FILE_SA6): $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
+$(OUTPUT_FILE_SA6): $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) | $$(@D)/
$(aarch64-ld) $(OBJ_FILE_SA6) -nostdlib -T $(MEMORY_DEF_SA6) -o $(OUTPUT_FILE_SA6) -Wl,-Map $(FILE_NAME_SA6).map
###################################################
# Compile
###################################################
-%.o: %.c
+%.o: %.c | $$(@D)/
$(aarch64-cc) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<
.PHONY: clean
diff --git a/tools/tlc/Makefile b/tools/tlc/Makefile
new file mode 100644
index 0000000..e50b9dd
--- /dev/null
+++ b/tools/tlc/Makefile
@@ -0,0 +1,109 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+##* Variables
+SHELL := /usr/bin/env bash
+PYTHON := python
+PYTHONPATH := `pwd`
+
+#* Docker variables
+IMAGE := tlc
+VERSION := latest
+
+#* Installation
+.PHONY: dist
+dist: clean
+ poetry build
+
+.PHONY: dev-install
+dev-install:
+ poetry lock -n --no-update && poetry export --without-hashes > requirements.txt
+ poetry install -n
+ -poetry run mypy --install-types --non-interactive ./
+
+.PHONY: install
+install: dist
+ pip install dist/*.whl
+
+.PHONY: pre-commit-install
+pre-commit-install:
+ poetry run pre-commit install
+
+#* Formatters
+.PHONY: codestyle
+codestyle:
+ poetry run pyupgrade --exit-zero-even-if-changed --py38-plus **/*.py
+ poetry run isort --settings-path pyproject.toml ./
+ poetry run black --config pyproject.toml ./
+
+.PHONY: formatting
+formatting: codestyle
+
+#* Linting
+.PHONY: test
+test:
+ PYTHONPATH=$(PYTHONPATH) poetry run pytest -c pyproject.toml --cov-report=html --cov=tlc tests/
+ poetry run coverage-badge -o assets/images/coverage.svg -f
+
+.PHONY: check-codestyle
+check-codestyle:
+ poetry run isort --diff --check-only --settings-path pyproject.toml ./
+ poetry run black --diff --check --config pyproject.toml ./
+ poetry run darglint --verbosity 2 tlc tests
+
+.PHONY: mypy
+mypy:
+ poetry run mypy --config-file pyproject.toml ./
+
+.PHONY: check-safety
+check-safety:
+ poetry check
+ poetry run safety check --full-report
+ poetry run bandit -ll --recursive tlc tests
+
+.PHONY: lint
+lint: test check-codestyle mypy check-safety
+
+.PHONY: update-dev-deps
+update-dev-deps:
+ poetry add -D bandit@latest darglint@latest "isort[colors]@latest" mypy@latest pre-commit@latest pydocstyle@latest pylint@latest pytest@latest pyupgrade@latest safety@latest coverage@latest coverage-badge@latest pytest-html@latest pytest-cov@latest
+ poetry add -D --allow-prereleases black@latest
+
+#* Docker
+.PHONY: docker-build docker-remove
+docker-build:
+ @echo Building docker $(IMAGE):$(VERSION) ...
+ docker build \
+ -t $(IMAGE):$(VERSION) . \
+ -f ./docker/Dockerfile --no-cache
+
+docker-remove:
+ @echo Removing docker $(IMAGE):$(VERSION) ...
+ docker rmi -f $(IMAGE):$(VERSION)
+
+
+#* Cleaning
+.PHONY: clean .clean-build clean-pyc clean-test
+clean: clean-build clean-pyc clean-test ## remove all build, test, coverage and Python artifacts
+
+clean-build: ## remove build artifacts
+ rm -fr build/
+ rm -fr dist/
+ rm -fr .eggs/
+ find . -name '*.egg-info' -exec rm -fr {} +
+ find . -name '*.egg' -exec rm -f {} +
+
+clean-pyc: ## remove Python file artifacts
+ find . -name '*.pyc' -exec rm -f {} +
+ find . -name '*.pyo' -exec rm -f {} +
+ find . -name '*~' -exec rm -f {} +
+ find . -name '__pycache__' -exec rm -fr {} +
+ find . | grep -E ".pytest_cache" | xargs rm -rf
+ find . | grep -E ".mypy_cache" | xargs rm -rf
+
+clean-test: ## remove test and coverage artifacts
+ rm -fr .tox/
+ rm -f .coverage
+ rm -fr htmlcov/
diff --git a/tools/tlc/assets/images/coverage.svg b/tools/tlc/assets/images/coverage.svg
new file mode 100644
index 0000000..b6c4e36
--- /dev/null
+++ b/tools/tlc/assets/images/coverage.svg
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<svg xmlns="http://www.w3.org/2000/svg" width="99" height="20">
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diff --git a/tools/tlc/pyproject.toml b/tools/tlc/pyproject.toml
new file mode 100644
index 0000000..5661abf
--- /dev/null
+++ b/tools/tlc/pyproject.toml
@@ -0,0 +1,147 @@
+# Poetry pyproject.toml: https://python-poetry.org/docs/pyproject/
+[build-system]
+requires = ["poetry_core>=1.0.0"]
+build-backend = "poetry.core.masonry.api"
+
+[tool.poetry]
+name = "tlc"
+version = "0.9.0"
+description = "Transfer List Compiler (TLC) is a Python-based CLI for efficiently handling transfer lists."
+authors = ["Arm Ltd <tf-a@lists.trustedfirmware.org>"]
+license = "BSD-3"
+repository = "https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/"
+homepage = "https://trustedfirmware-a.readthedocs.io/en/latest/index.html"
+
+# Keywords description https://python-poetry.org/docs/pyproject/#keywords
+keywords = [] #! Update me
+
+# Pypi classifiers: https://pypi.org/classifiers/
+classifiers = [
+ "Development Status :: 3 - Alpha",
+ "Intended Audience :: Developers",
+ "Operating System :: OS Independent",
+ "Topic :: Software Development :: Libraries :: Python Modules",
+ "License :: OSI Approved :: BSD License",
+ "Programming Language :: Python :: 3",
+ "Programming Language :: Python :: 3.8",
+ "Programming Language :: Python :: 3.9",
+]
+
+[tool.poetry.scripts]
+# Entry points for the package https://python-poetry.org/docs/pyproject/#scripts
+"tlc" = "tlc.__main__:cli"
+
+[tool.poetry.dependencies]
+python = "^3.8"
+
+typer = {extras = ["all"], version = "^0.4.0"}
+rich = "^10.14.0"
+click = "^8.1.7"
+pyyaml = "^6.0.1"
+
+[tool.poetry.dev-dependencies]
+bandit = "^1.7.1"
+darglint = "^1.8.1"
+black = "^24.4.2"
+isort = {extras = ["colors"], version = "^5.10.1"}
+mypy = "^0.910"
+mypy-extensions = "^0.4.3"
+pre-commit = "^2.15.0"
+pydocstyle = "^6.1.1"
+pylint = "^2.11.1"
+pytest = "^7.0.0"
+pyupgrade = "^2.29.1"
+safety = "^2.2.0"
+coverage = "^6.1.2"
+coverage-badge = "^1.1.0"
+pytest-html = "^4.1.1"
+pytest-cov = "^3.0.0"
+
+[tool.black]
+# https://github.com/psf/black
+target-version = ["py38"]
+line-length = 88
+color = true
+
+exclude = '''
+/(
+ \.git
+ | \.hg
+ | \.mypy_cache
+ | \.tox
+ | \.venv
+ | _build
+ | buck-out
+ | build
+ | dist
+ | env
+ | venv
+)/
+'''
+
+[tool.isort]
+# https://github.com/timothycrosley/isort/
+py_version = 38
+line_length = 88
+
+known_typing = ["typing", "types", "typing_extensions", "mypy", "mypy_extensions"]
+sections = ["FUTURE", "TYPING", "STDLIB", "THIRDPARTY", "FIRSTPARTY", "LOCALFOLDER"]
+include_trailing_comma = true
+profile = "black"
+multi_line_output = 3
+indent = 4
+color_output = true
+
+[tool.mypy]
+# https://mypy.readthedocs.io/en/latest/config_file.html#using-a-pyproject-toml-file
+python_version = 3.8
+pretty = true
+show_traceback = true
+color_output = true
+
+allow_redefinition = false
+check_untyped_defs = true
+disallow_any_generics = true
+disallow_incomplete_defs = true
+ignore_missing_imports = true
+implicit_reexport = false
+no_implicit_optional = true
+show_column_numbers = true
+show_error_codes = true
+show_error_context = true
+strict_equality = true
+strict_optional = true
+warn_no_return = true
+warn_redundant_casts = true
+warn_return_any = true
+warn_unreachable = true
+warn_unused_configs = true
+warn_unused_ignores = true
+
+
+[tool.pytest.ini_options]
+# https://docs.pytest.org/en/6.2.x/customize.html#pyproject-toml
+# Directories that are not visited by pytest collector:
+norecursedirs =["hooks", "*.egg", ".eggs", "dist", "build", "docs", ".tox", ".git", "__pycache__"]
+doctest_optionflags = ["NUMBER", "NORMALIZE_WHITESPACE", "IGNORE_EXCEPTION_DETAIL"]
+
+# Extra options:
+addopts = [
+ "--strict-markers",
+ "--tb=short",
+ "--doctest-modules",
+ "--doctest-continue-on-failure",
+]
+
+[tool.coverage.run]
+source = ["tests"]
+
+[coverage.paths]
+source = "tlc"
+
+[coverage.run]
+branch = true
+
+[coverage.report]
+fail_under = 50
+show_missing = true
diff --git a/tools/tlc/setup.cfg b/tools/tlc/setup.cfg
new file mode 100644
index 0000000..3c46a08
--- /dev/null
+++ b/tools/tlc/setup.cfg
@@ -0,0 +1,4 @@
+[darglint]
+# https://github.com/terrencepreilly/darglint
+strictness = long
+docstring_style = google
diff --git a/tools/tlc/tests/conftest.py b/tools/tlc/tests/conftest.py
new file mode 100644
index 0000000..b8f88b5
--- /dev/null
+++ b/tools/tlc/tests/conftest.py
@@ -0,0 +1,72 @@
+#!/usr/bin/env python3
+# type: ignore[attr-defined]
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+""" Common configurations and fixtures for test environment."""
+
+import pytest
+import yaml
+from click.testing import CliRunner
+
+from tlc.cli import cli
+
+
+@pytest.fixture
+def tmptlstr(tmpdir):
+ return tmpdir.join("tl.bin").strpath
+
+
+@pytest.fixture
+def tmpyamlconfig(tmpdir):
+ return tmpdir.join("config.yaml").strpath
+
+
+@pytest.fixture
+def tmpfdt(tmpdir):
+ fdt = tmpdir.join("fdt.dtb")
+ fdt.write_binary(b"\x00" * 100)
+ return fdt
+
+
+@pytest.fixture(params=[1, 2, 3, 4, 5, 0x100, 0x101, 0x102, 0x104])
+def non_empty_tag_id(request):
+ return request.param
+
+
+@pytest.fixture
+def tmpyamlconfig_blob_file(tmpdir, tmpfdt, non_empty_tag_id):
+ config_path = tmpdir.join("config.yaml")
+
+ config = {
+ "has_checksum": True,
+ "max_size": 0x1000,
+ "entries": [
+ {
+ "tag_id": non_empty_tag_id,
+ "blob_file_path": tmpfdt.strpath,
+ },
+ ],
+ }
+
+ with open(config_path, "w") as f:
+ yaml.safe_dump(config, f)
+
+ return config_path
+
+
+@pytest.fixture
+def tlcrunner(tmptlstr):
+ runner = CliRunner()
+ with runner.isolated_filesystem():
+ runner.invoke(cli, ["create", tmptlstr])
+ return runner
+
+
+@pytest.fixture
+def tlc_entries(tmpfdt):
+ return [(0, "/dev/null"), (1, tmpfdt.strpath), (0x102, tmpfdt.strpath)]
diff --git a/tools/tlc/tests/test_cli.py b/tools/tlc/tests/test_cli.py
new file mode 100644
index 0000000..99b5816
--- /dev/null
+++ b/tools/tlc/tests/test_cli.py
@@ -0,0 +1,413 @@
+#!/usr/bin/env python3
+# type: ignore[attr-defined]
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+"""Contains unit tests for the CLI functionality."""
+
+from pathlib import Path
+from unittest import mock
+from math import log2, ceil
+
+import pytest
+import pytest
+import yaml
+from click.testing import CliRunner
+
+from tlc.cli import cli
+from tlc.te import TransferEntry
+from tlc.tl import TransferList
+
+
+def test_create_empty_tl(tmpdir):
+ runner = CliRunner()
+ test_file = tmpdir.join("tl.bin")
+
+ result = runner.invoke(cli, ["create", test_file.strpath])
+ assert result.exit_code == 0
+ assert TransferList.fromfile(test_file) is not None
+
+
+def test_create_with_fdt(tmpdir):
+ runner = CliRunner()
+ fdt = tmpdir.join("fdt.dtb")
+ fdt.write_binary(b"\x00" * 100)
+
+ result = runner.invoke(
+ cli,
+ [
+ "create",
+ "--fdt",
+ fdt.strpath,
+ "--size",
+ "1000",
+ tmpdir.join("tl.bin").strpath,
+ ],
+ )
+ assert result.exit_code == 0
+
+
+def test_add_single_entry(tlcrunner, tmptlstr):
+ tlcrunner.invoke(cli, ["add", "--entry", "0", "/dev/null", tmptlstr])
+
+ tl = TransferList.fromfile(tmptlstr)
+ assert tl is not None
+ assert len(tl.entries) == 1
+ assert tl.entries[0].id == 0
+
+
+def test_add_multiple_entries(tlcrunner, tlc_entries, tmptlstr):
+ for id, path in tlc_entries:
+ tlcrunner.invoke(cli, ["add", "--entry", id, path, tmptlstr])
+
+ tl = TransferList.fromfile(tmptlstr)
+ assert tl is not None
+ assert len(tl.entries) == len(tlc_entries)
+
+
+def test_info(tlcrunner, tmptlstr, tmpfdt):
+ tlcrunner.invoke(cli, ["add", "--entry", "0", "/dev/null", tmptlstr])
+ tlcrunner.invoke(cli, ["add", "--fdt", tmpfdt.strpath, tmptlstr])
+
+ result = tlcrunner.invoke(cli, ["info", tmptlstr])
+ assert result.exit_code == 0
+ assert "signature" in result.stdout
+ assert "id" in result.stdout
+
+ result = tlcrunner.invoke(cli, ["info", "--header", tmptlstr])
+ assert result.exit_code == 0
+ assert "signature" in result.stdout
+ assert "id" not in result.stdout
+
+ result = tlcrunner.invoke(cli, ["info", "--entries", tmptlstr])
+ assert result.exit_code == 0
+ assert "signature" not in result.stdout
+ assert "id" in result.stdout
+
+
+def test_raises_max_size_error(tmptlstr, tmpfdt):
+ tmpfdt.write_binary(bytes(6000))
+
+ runner = CliRunner()
+ result = runner.invoke(cli, ["create", "--fdt", tmpfdt, tmptlstr])
+
+ assert result.exception
+ assert isinstance(result.exception, MemoryError)
+ assert "TL max size exceeded, consider increasing with the option -s" in str(
+ result.exception
+ )
+ assert "TL size has exceeded the maximum allocation" in str(
+ result.exception.__cause__
+ )
+
+
+def test_info_get_fdt_offset(tmptlstr, tmpfdt):
+ runner = CliRunner()
+ with runner.isolated_filesystem():
+ runner.invoke(cli, ["create", "--size", "1000", tmptlstr])
+ runner.invoke(cli, ["add", "--entry", "1", tmpfdt.strpath, tmptlstr])
+ result = runner.invoke(cli, ["info", "--fdt-offset", tmptlstr])
+
+ assert result.exit_code == 0
+ assert result.output.strip("\n").isdigit()
+
+
+def test_remove_tag(tlcrunner, tmptlstr):
+ tlcrunner.invoke(cli, ["add", "--entry", "0", "/dev/null", tmptlstr])
+ result = tlcrunner.invoke(cli, ["info", tmptlstr])
+
+ assert result.exit_code == 0
+ assert "signature" in result.stdout
+
+ tlcrunner.invoke(cli, ["remove", "--tags", "0", tmptlstr])
+ tl = TransferList.fromfile(tmptlstr)
+
+ assert result.exit_code == 0
+ assert len(tl.entries) == 0
+
+
+def test_unpack_tl(tlcrunner, tmptlstr, tmpfdt, tmpdir):
+ with tlcrunner.isolated_filesystem(temp_dir=tmpdir):
+ tlcrunner.invoke(cli, ["add", "--entry", 1, tmpfdt.strpath, tmptlstr])
+ tlcrunner.invoke(cli, ["unpack", tmptlstr])
+ assert Path("te_0_1.bin").exists()
+
+
+def test_unpack_multiple_tes(tlcrunner, tlc_entries, tmptlstr, tmpdir):
+ with tlcrunner.isolated_filesystem(temp_dir=tmpdir):
+ for id, path in tlc_entries:
+ tlcrunner.invoke(cli, ["add", "--entry", id, path, tmptlstr])
+
+ assert all(
+ filter(
+ lambda te: (Path(tmpdir.strpath) / f"te_{te[0]}.bin").exists(), tlc_entries
+ )
+ )
+
+
+def test_unpack_into_dir(tlcrunner, tmpdir, tmptlstr, tmpfdt):
+ tlcrunner.invoke(cli, ["add", "--entry", 1, tmpfdt.strpath, tmptlstr])
+ tlcrunner.invoke(cli, ["unpack", "-C", tmpdir.strpath, tmptlstr])
+
+ assert (Path(tmpdir.strpath) / "te_0_1.bin").exists()
+
+
+def test_unpack_into_dir_with_conflicting_tags(tlcrunner, tmpdir, tmptlstr, tmpfdt):
+ tlcrunner.invoke(cli, ["add", "--entry", 1, tmpfdt.strpath, tmptlstr])
+ tlcrunner.invoke(cli, ["add", "--entry", 1, tmpfdt.strpath, tmptlstr])
+ tlcrunner.invoke(cli, ["unpack", "-C", tmpdir.strpath, tmptlstr])
+
+ assert (Path(tmpdir.strpath) / "te_0_1.bin").exists()
+ assert (Path(tmpdir.strpath) / "te_1_1.bin").exists()
+
+
+def test_validate_invalid_signature(tmptlstr, tlcrunner, monkeypatch):
+ tl = TransferList()
+ tl.signature = 0xDEADBEEF
+
+ mock_open = lambda tmptlstr, mode: mock.mock_open(read_data=tl.header_to_bytes())()
+ monkeypatch.setattr("builtins.open", mock_open)
+
+ result = tlcrunner.invoke(cli, ["validate", tmptlstr])
+ assert result.exit_code != 0
+
+
+def test_validate_misaligned_entries(tmptlstr, tlcrunner, monkeypatch):
+ """Base address of a TE must be 8-byte aligned."""
+ mock_open = lambda tmptlstr, mode: mock.mock_open(
+ read_data=TransferList().header_to_bytes()
+ + bytes(5)
+ + TransferEntry(0, 0, bytes(0)).header_to_bytes
+ )()
+ monkeypatch.setattr("builtins.open", mock_open)
+
+ result = tlcrunner.invoke(cli, ["validate", tmptlstr])
+
+ assert result.exit_code == 1
+
+
+@pytest.mark.parametrize(
+ "version", [0, TransferList.version, TransferList.version + 1, 1 << 8]
+)
+def test_validate_unsupported_version(version, tmptlstr, tlcrunner, monkeypatch):
+ tl = TransferList()
+ tl.version = version
+
+ mock_open = lambda tmptlstr, mode: mock.mock_open(read_data=tl.header_to_bytes())()
+ monkeypatch.setattr("builtins.open", mock_open)
+
+ result = tlcrunner.invoke(cli, ["validate", tmptlstr])
+
+ if version >= TransferList.version and version <= 0xFF:
+ assert result.exit_code == 0
+ else:
+ assert result.exit_code == 1
+
+
+def test_create_entry_from_yaml_and_blob_file(
+ tlcrunner, tmpyamlconfig_blob_file, tmptlstr, non_empty_tag_id
+):
+ tlcrunner.invoke(
+ cli,
+ [
+ "create",
+ "--from-yaml",
+ tmpyamlconfig_blob_file.strpath,
+ tmptlstr,
+ ],
+ )
+
+ tl = TransferList.fromfile(tmptlstr)
+ assert tl is not None
+ assert len(tl.entries) == 1
+ assert tl.entries[0].id == non_empty_tag_id
+
+
+@pytest.mark.parametrize(
+ "entry",
+ [
+ {"tag_id": 0},
+ {
+ "tag_id": 0x104,
+ "addr": 0x0400100000000010,
+ "size": 0x0003300000000000,
+ },
+ {
+ "tag_id": 0x100,
+ "pp_addr": 100,
+ },
+ {
+ "tag_id": "optee_pageable_part",
+ "pp_addr": 100,
+ },
+ ],
+)
+def test_create_from_yaml_check_sum_bytes(tlcrunner, tmpyamlconfig, tmptlstr, entry):
+ """Test creating a TL from a yaml file, but only check that the sum of the
+ data in the yaml file matches the sum of the data in the TL. This means
+ you don't have to type the exact sequence of expected bytes. All the data
+ in the yaml file must be integers (except for the tag IDs, which can be
+ strings).
+ """
+ # create yaml config file
+ config = {
+ "has_checksum": True,
+ "max_size": 0x1000,
+ "entries": [entry],
+ }
+ with open(tmpyamlconfig, "w") as f:
+ yaml.safe_dump(config, f)
+
+ # invoke TLC
+ tlcrunner.invoke(
+ cli,
+ [
+ "create",
+ "--from-yaml",
+ tmpyamlconfig,
+ tmptlstr,
+ ],
+ )
+
+ # open created TL, and check
+ tl = TransferList.fromfile(tmptlstr)
+ assert tl is not None
+ assert len(tl.entries) == 1
+
+ # Check that the sum of all the data in the transfer entry in the yaml file
+ # is the same as the sum of all the data in the transfer list. Don't count
+ # the tag id or the TE headers.
+
+ # every item in the entry dict must be an integer
+ yaml_total = 0
+ for key, data in iter_nested_dict(entry):
+ if key != "tag_id":
+ num_bytes = ceil(log2(data + 1) / 8)
+ yaml_total += sum(data.to_bytes(num_bytes, "little"))
+
+ tl_total = sum(tl.entries[0].data)
+
+ assert tl_total == yaml_total
+
+
+@pytest.mark.parametrize(
+ "entry,expected",
+ [
+ (
+ {
+ "tag_id": 0x102,
+ "ep_info": {
+ "h": {
+ "type": 0x01,
+ "version": 0x02,
+ "attr": 8,
+ },
+ "pc": 67239936,
+ "spsr": 965,
+ "args": [67112976, 67112960, 0, 0, 0, 0, 0, 0],
+ },
+ },
+ (
+ "0x00580201 0x00000008 0x04020000 0x00000000 "
+ "0x000003C5 0x00000000 0x04001010 0x00000000 "
+ "0x04001000 0x00000000 0x00000000 0x00000000 "
+ "0x00000000 0x00000000 0x00000000 0x00000000 "
+ "0x00000000 0x00000000 0x00000000 0x00000000 "
+ "0x00000000 0x00000000"
+ ),
+ ),
+ (
+ {
+ "tag_id": 0x102,
+ "ep_info": {
+ "h": {
+ "type": 0x01,
+ "version": 0x02,
+ "attr": "EP_NON_SECURE | EP_ST_ENABLE",
+ },
+ "pc": 67239936,
+ "spsr": 965,
+ "args": [67112976, 67112960, 0, 0, 0, 0, 0, 0],
+ },
+ },
+ (
+ "0x00580201 0x00000005 0x04020000 0x00000000 "
+ "0x000003C5 0x00000000 0x04001010 0x00000000 "
+ "0x04001000 0x00000000 0x00000000 0x00000000 "
+ "0x00000000 0x00000000 0x00000000 0x00000000 "
+ "0x00000000 0x00000000 0x00000000 0x00000000 "
+ "0x00000000 0x00000000"
+ ),
+ ),
+ ],
+)
+def test_create_from_yaml_check_exact_data(
+ tlcrunner, tmpyamlconfig, tmptlstr, entry, expected
+):
+ """Test creating a TL from a yaml file, checking the exact sequence of
+ bytes. This is useful for checking that the alignment is correct. You can
+ get the expected sequence of bytes by copying it from the ArmDS debugger.
+ """
+ # create yaml config file
+ config = {
+ "has_checksum": True,
+ "max_size": 0x1000,
+ "entries": [entry],
+ }
+ with open(tmpyamlconfig, "w") as f:
+ yaml.safe_dump(config, f)
+
+ # invoke TLC
+ tlcrunner.invoke(
+ cli,
+ [
+ "create",
+ "--from-yaml",
+ tmpyamlconfig,
+ tmptlstr,
+ ],
+ )
+
+ # open TL and check
+ tl = TransferList.fromfile(tmptlstr)
+ assert tl is not None
+ assert len(tl.entries) == 1
+
+ # check expected and actual data
+ actual = tl.entries[0].data
+ actual = bytes_to_hex(actual)
+
+ assert actual == expected
+
+
+def bytes_to_hex(data: bytes) -> str:
+ """Convert bytes to a hex string in the same format as the debugger in
+ ArmDS
+
+ You can copy data from the debugger in Arm Development Studio and put it
+ into a unit test. You can then run this function on the output from tlc,
+ and compare it to the data you copied.
+
+ The format is groups of 4 bytes with 0x prefixes separated by spaces.
+ Little endian is used.
+ """
+ words_hex = []
+ for i in range(0, len(data), 4):
+ word = data[i : i + 4]
+ word_int = int.from_bytes(word, "little")
+ word_hex = "0x" + f"{word_int:0>8x}".upper()
+ words_hex.append(word_hex)
+
+ return " ".join(words_hex)
+
+
+def iter_nested_dict(dictionary: dict):
+ for key, value in dictionary.items():
+ if isinstance(value, dict):
+ yield from iter_nested_dict(value)
+ else:
+ yield key, value
diff --git a/tools/tlc/tests/test_transfer_list.py b/tools/tlc/tests/test_transfer_list.py
new file mode 100644
index 0000000..e8c430e
--- /dev/null
+++ b/tools/tlc/tests/test_transfer_list.py
@@ -0,0 +1,234 @@
+#!/usr/bin/env python3
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+"""Contains unit tests for the types TransferEntry and TransferList."""
+
+import math
+
+import pytest
+
+from tlc.te import TransferEntry
+from tlc.tl import TransferList
+
+large_data = 0xDEADBEEF.to_bytes(4, "big")
+small_data = 0x1234.to_bytes(3, "big")
+test_entries = [
+ (0, b""),
+ (1, small_data),
+ (1, large_data),
+ (0xFFFFFF, small_data),
+ (0xFFFFFF, large_data),
+]
+
+
+@pytest.mark.parametrize(
+ "size,csum",
+ [
+ (-1, None),
+ (0x18, 0x9E),
+ (0x1000, 0xA6),
+ (0x2000, 0x96),
+ (0x4000, 0x76),
+ ],
+)
+def test_make_transfer_list(size, csum):
+ if size < 8:
+ with pytest.raises(AssertionError):
+ tl = TransferList(size)
+ else:
+ tl = TransferList(size)
+
+ assert tl.signature == 0x4A0FB10B
+ assert not tl.entries
+ assert tl.sum_of_bytes() == 0
+ assert tl.checksum == csum
+
+
+@pytest.mark.parametrize(("tag_id", "data"), test_entries)
+def test_add_transfer_entry(tag_id, data):
+ tl = TransferList(0x1000)
+ te = TransferEntry(tag_id, len(data), data)
+
+ tl.add_transfer_entry(tag_id, data)
+
+ assert te in tl.entries
+ assert tl.size == TransferList.hdr_size + te.size
+
+
+@pytest.mark.parametrize(
+ ("tag_id", "data"),
+ [
+ (-1, None), # tag out of range
+ (1, None), # no data provided
+ (1, bytes(8000)), # very large data > total size
+ (0x100000, b"0dd0edfe"), # tag out of range
+ ],
+)
+def test_add_out_of_range_transfer_entry(tag_id, data):
+ tl = TransferList()
+
+ with pytest.raises(Exception):
+ tl.add_transfer_entry(tag_id, data)
+
+
+@pytest.mark.parametrize(("tag_id", "data"), test_entries)
+def test_calculate_te_sum_of_bytes(tag_id, data):
+ te = TransferEntry(tag_id, len(data), data)
+ csum = (
+ sum(data)
+ + sum(len(data).to_bytes(4, "big"))
+ + te.hdr_size
+ + sum(tag_id.to_bytes(4, "big"))
+ ) % 256
+ assert te.sum_of_bytes == csum
+
+
+@pytest.mark.parametrize(("tag_id", "data"), test_entries)
+def test_calculate_tl_checksum(tag_id, data):
+ tl = TransferList(0x1000)
+
+ tl.add_transfer_entry(tag_id, data)
+ assert tl.sum_of_bytes() == 0
+
+
+def test_empty_transfer_list_blob(tmpdir):
+ """Check that we can correctly create a transfer list header."""
+ test_file = tmpdir.join("test_tl_blob.bin")
+ tl = TransferList()
+ tl.write_to_file(test_file)
+
+ with open(test_file, "rb") as f:
+ assert f.read(tl.hdr_size) == tl.header_to_bytes()
+
+
+@pytest.mark.parametrize(("tag_id", "data"), test_entries)
+def test_single_te_transfer_list(tag_id, data, tmpdir):
+ """Check that we can create a complete TL with a single TE."""
+ test_file = tmpdir.join("test_tl_blob.bin")
+ tl = TransferList(0x1000)
+
+ tl.add_transfer_entry(tag_id, data)
+ tl.write_to_file(test_file)
+
+ te = tl.entries[0]
+
+ with open(test_file, "rb") as f:
+ assert f.read(tl.hdr_size) == tl.header_to_bytes()
+ assert int.from_bytes(f.read(3), "little") == te.id
+ assert int.from_bytes(f.read(1), "little") == te.hdr_size
+ assert int.from_bytes(f.read(4), "little") == te.data_size
+ assert f.read(te.data_size) == te.data
+
+
+def test_multiple_te_transfer_list(tmpdir):
+ """Check that we can create a TL with multiple TE's."""
+ test_file = tmpdir.join("test_tl_blob.bin")
+ tl = TransferList(0x1000)
+
+ for tag_id, data in test_entries:
+ tl.add_transfer_entry(tag_id, data)
+
+ tl.write_to_file(test_file)
+
+ with open(test_file, "rb") as f:
+ assert f.read(tl.hdr_size) == tl.header_to_bytes()
+ # Ensure that TE's have the correct alignment
+ for tag_id, data in test_entries:
+ f.seek(int(math.ceil(f.tell() / 2**tl.alignment) * 2**tl.alignment))
+ print(f.tell())
+ assert int.from_bytes(f.read(3), "little") == tag_id
+ assert int.from_bytes(f.read(1), "little") == TransferEntry.hdr_size
+ # Make sure the data in the TE matches the data in the original case
+ data_size = int.from_bytes(f.read(4), "little")
+ assert f.read(data_size) == data
+
+
+def test_read_empty_transfer_list_from_file(tmpdir):
+ test_file = tmpdir.join("test_tl_blob.bin")
+ original_tl = TransferList(0x1000)
+ original_tl.write_to_file(test_file)
+
+ # Read the contents of the file we just wrote
+ tl = TransferList.fromfile(test_file)
+ assert tl.header_to_bytes() == original_tl.header_to_bytes()
+ assert tl.sum_of_bytes() == 0
+
+
+def test_read_single_transfer_list_from_file(tmpdir):
+ test_file = tmpdir.join("test_tl_blob.bin")
+ original_tl = TransferList(0x1000)
+
+ original_tl.add_transfer_entry(test_entries[0][0], test_entries[0][1])
+ original_tl.write_to_file(test_file)
+
+ # Read the contents of the file we just wrote
+ tl = TransferList.fromfile(test_file)
+ assert tl.entries
+
+ te = tl.entries[0]
+ assert te.id == test_entries[0][0]
+ assert te.data == test_entries[0][1]
+ assert tl.sum_of_bytes() == 0
+
+
+def test_read_multiple_transfer_list_from_file(tmpdir):
+ test_file = tmpdir.join("test_tl_blob.bin")
+ original_tl = TransferList(0x1000)
+
+ for tag_id, data in test_entries:
+ original_tl.add_transfer_entry(tag_id, data)
+
+ original_tl.write_to_file(test_file)
+
+ # Read the contents of the file we just wrote
+ tl = TransferList.fromfile(test_file)
+
+ # The TE we derive from the file might have a an associated offset, compare
+ # the TE's based on the header in bytes, which doesn't account for this.
+ for te0, te1 in zip(tl.entries, original_tl.entries):
+ assert te0.header_to_bytes() == te1.header_to_bytes()
+
+ assert tl.sum_of_bytes() == 0
+
+
+@pytest.mark.parametrize("tag", [tag for tag, _ in test_entries])
+def test_remove_tag_from_file(tag):
+ tl = TransferList(0x1000)
+
+ for tag_id, data in test_entries:
+ tl.add_transfer_entry(tag_id, data)
+
+ removed_entries = list(filter(lambda te: te.id == tag, tl.entries))
+ original_size = tl.size
+ tl.remove_tag(tag)
+
+ assert not any(tag == te.id for te in tl.entries)
+ assert tl.size == original_size - sum(map(lambda te: te.size, removed_entries))
+
+
+def test_get_fdt_offset(tmpdir):
+ tl = TransferList(0x1000)
+ tl.add_transfer_entry(1, 0xEDFE0DD0.to_bytes(4, "big"))
+ f = tmpdir.join("blob.bin")
+
+ tl.write_to_file(f)
+
+ blob_tl = TransferList.fromfile(f)
+
+ assert blob_tl.hdr_size + TransferEntry.hdr_size == blob_tl.get_entry_data_offset(1)
+
+
+def test_get_missing_fdt_offset(tmpdir):
+ tl = TransferList(0x1000)
+ f = tmpdir.join("blob.bin")
+
+ tl.write_to_file(f)
+ blob_tl = TransferList.fromfile(f)
+
+ with pytest.raises(ValueError):
+ blob_tl.get_entry_data_offset(1)
diff --git a/tools/tlc/tlc/__init__.py b/tools/tlc/tlc/__init__.py
new file mode 100644
index 0000000..82f5f5b
--- /dev/null
+++ b/tools/tlc/tlc/__init__.py
@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+# type: ignore[attr-defined]
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+"""Transfer List Compiler (TLC) is a Python-based CLI for efficiently handling transfer lists."""
+
+import sys
+
+if sys.version_info >= (3, 8):
+ from importlib import metadata as importlib_metadata
+else:
+ import importlib_metadata
+
+
+def get_version() -> str:
+ try:
+ return importlib_metadata.version(__name__)
+ except importlib_metadata.PackageNotFoundError: # pragma: no cover
+ return "unknown"
+
+
+version: str = get_version()
diff --git a/tools/tlc/tlc/__main__.py b/tools/tlc/tlc/__main__.py
new file mode 100644
index 0000000..03ffa0e
--- /dev/null
+++ b/tools/tlc/tlc/__main__.py
@@ -0,0 +1,13 @@
+#!/usr/bin/env python3
+# type: ignore[attr-defined]
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+from tlc.cli import cli
+
+if __name__ == "__main__":
+ cli()
diff --git a/tools/tlc/tlc/cli.py b/tools/tlc/tlc/cli.py
new file mode 100644
index 0000000..1d4949d
--- /dev/null
+++ b/tools/tlc/tlc/cli.py
@@ -0,0 +1,172 @@
+#!/usr/bin/env python3
+# type: ignore[attr-defined]
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+"""Module defining the Transfer List Compiler (TLC) command line interface."""
+
+from pathlib import Path
+
+import click
+import yaml
+
+from tlc.tl import *
+
+
+@click.group()
+@click.version_option()
+def cli():
+ pass
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(dir_okay=False))
+@click.option(
+ "-s", "--size", default=0x1000, type=int, help="Maximum size of the Transfer List"
+)
+@click.option(
+ "--fdt",
+ type=click.Path(exists=True),
+ help="Path to flattened device tree (FDT).",
+)
+@click.option(
+ "--entry",
+ type=(int, click.Path(exists=True)),
+ multiple=True,
+ help="A tag ID and the corresponding path to a binary blob in the form <id> <path-to-blob>.",
+)
+@click.option(
+ "--flags",
+ default=TRANSFER_LIST_ENABLE_CHECKSUM,
+ show_default=True,
+ help="Settings for the TL's properties.",
+)
+@click.option(
+ "--from-yaml",
+ type=click.Path(exists=True),
+ help="Create the transfer list from a YAML config file.",
+)
+def create(filename, size, fdt, entry, flags, from_yaml):
+ """Create a new Transfer List."""
+ try:
+ if from_yaml:
+ with open(from_yaml, "r") as f:
+ config = yaml.safe_load(f)
+
+ tl = TransferList.from_dict(config)
+ else:
+ tl = TransferList(size)
+
+ entry = (*entry, (1, fdt)) if fdt else entry
+
+ for id, path in entry:
+ tl.add_transfer_entry_from_file(id, path)
+ except MemoryError as mem_excp:
+ raise MemoryError(
+ "TL max size exceeded, consider increasing with the option -s"
+ ) from mem_excp
+
+ tl.write_to_file(filename)
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+@click.option(
+ "--fdt-offset",
+ is_flag=True,
+ help="Returns the offset of FDT in the TL if it is present.",
+)
+@click.option(
+ "--header",
+ is_flag=True,
+ help="Print the Transfer List header.",
+)
+@click.option(
+ "--entries",
+ is_flag=True,
+ help="Print the Transfer List entries.",
+)
+def info(filename, fdt_offset, header, entries):
+ """Print the contents of an existing Transfer List.
+
+ This command allows you to extract the data stored in a binary blob
+ representing a transfer list (TL). The transfer list must comply with the
+ version of the firmware handoff specification supported by this tool.
+ """
+ tl = TransferList.fromfile(filename)
+
+ if fdt_offset:
+ return print(tl.get_entry_data_offset(1))
+
+ if header and entries or not (header or entries):
+ print(tl, sep="")
+ if tl.entries:
+ print("----", tl.get_transfer_entries_str(), sep="\n")
+ elif entries:
+ print(tl.get_transfer_entries_str())
+ elif header:
+ print(tl)
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+@click.option(
+ "--tags",
+ type=int,
+ multiple=True,
+ help="Tags to be removed from TL.",
+)
+def remove(filename, tags):
+ """Remove Transfer Entries with given tags.
+
+ Remove Transfer Entries with given tags from a Transfer List."""
+ tl = TransferList.fromfile(filename)
+
+ for tag in tags:
+ tl.remove_tag(tag)
+ tl.write_to_file(filename)
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+@click.option(
+ "--entry",
+ type=(int, click.Path(exists=True)),
+ multiple=True,
+ help="A tag ID and the corresponding path to a binary blob in the form <id> <path-to-blob>.",
+)
+def add(filename, entry):
+ """Update an existing Transfer List with given images."""
+ tl = TransferList.fromfile(filename)
+
+ for id, path in entry:
+ tl.add_transfer_entry_from_file(id, path)
+
+ tl.write_to_file(filename)
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+@click.option(
+ "-C", type=click.Path(exists=True), help="Output directory for extracted images."
+)
+def unpack(filename, c):
+ """Unpack images from a Transfer List."""
+ tl = TransferList.fromfile(filename)
+ pwd = Path(".") if not c else Path(c)
+
+ for i, te in enumerate(tl.entries):
+ with open(pwd / f"te_{i}_{te.id}.bin", "wb") as f:
+ f.write(te.data)
+
+
+@cli.command()
+@click.argument("filename", type=click.Path(exists=True, dir_okay=False))
+def validate(filename):
+ """Validate the contents of an existing Transfer List."""
+ TransferList.fromfile(filename)
+ print("Valid TL!")
diff --git a/tools/tlc/tlc/te.py b/tools/tlc/tlc/te.py
new file mode 100644
index 0000000..cf7aa67
--- /dev/null
+++ b/tools/tlc/tlc/te.py
@@ -0,0 +1,56 @@
+#!/usr/bin/env python3
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+"""Module containing definitions pertaining to the 'Transfer Entry' (TE) type."""
+
+from typing import ClassVar
+
+import struct
+from dataclasses import dataclass
+
+
+@dataclass
+class TransferEntry:
+ """Class representing a Transfer Entry."""
+
+ id: int
+ data_size: int
+ data: bytes
+ hdr_size: int = 8
+ offset: int = 0
+ # Header encoding, with little-endian byte order.
+ encoding: ClassVar[str] = "<BI"
+
+ def __post_init__(self):
+ if self.id < 0 or self.id > 0xFFFFFF:
+ raise ValueError(
+ f"Out of bounds tag ID: {self.id:x}.\n"
+ f"Valid range is from 0 to 0xFFFFFF. Please ensure the tag ID is within this range."
+ )
+
+ def __str__(self) -> str:
+ return "\n".join(
+ [
+ f"{k:<10} {hex(v)}"
+ for k, v in vars(self).items()
+ if not isinstance(v, bytes)
+ ]
+ )
+
+ @property
+ def size(self) -> int:
+ return self.hdr_size + len(self.data)
+
+ @property
+ def sum_of_bytes(self) -> int:
+ return (sum(self.header_to_bytes()) + sum(self.data)) % 256
+
+ def header_to_bytes(self) -> bytes:
+ return self.id.to_bytes(3, "little") + struct.pack(
+ self.encoding, self.hdr_size, self.data_size
+ )
diff --git a/tools/tlc/tlc/tl.py b/tools/tlc/tlc/tl.py
new file mode 100644
index 0000000..3f0065d
--- /dev/null
+++ b/tools/tlc/tlc/tl.py
@@ -0,0 +1,353 @@
+#!/usr/bin/env python3
+
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+"""Module containing definitions pertaining to the 'Transfer List' (TL) type."""
+
+import typing
+
+import math
+import struct
+from dataclasses import dataclass
+from functools import reduce
+from pathlib import Path
+
+from tlc.te import TransferEntry
+
+TRANSFER_LIST_ENABLE_CHECKSUM = 0b1
+
+# Description of each TE type. For each TE, there is a tag ID, a format (to be
+# used in struct.pack to encode the TE), and a list of field names that can
+# appear in the yaml file for that TE. Some fields are missing, if that TE has
+# to be processed differently, or if it can only be added with a blob file.
+transfer_entry_formats = {
+ 0: {
+ "tag_name": "empty",
+ "format": "4x",
+ "fields": [],
+ },
+ 1: {
+ "tag_name": "fdt",
+ },
+ 2: {
+ "tag_name": "hob_block",
+ },
+ 3: {
+ "tag_name": "hob_list",
+ },
+ 4: {
+ "tag_name": "acpi_table_aggregate",
+ },
+ 5: {
+ "tag_name": "tpm_event_log_table",
+ "fields": ["event_log", "flags"],
+ },
+ 6: {
+ "tag_name": "tpm_crb_base_address_table",
+ "format": "QI",
+ "fields": ["crb_base_address", "crb_size"],
+ },
+ 0x100: {
+ "tag_name": "optee_pageable_part",
+ "format": "Q",
+ "fields": ["pp_addr"],
+ },
+ 0x101: {
+ "tag_name": "dt_spmc_manifest",
+ },
+ 0x102: {
+ "tag_name": "exec_ep_info",
+ "format": "2BHIQI4x8Q",
+ "fields": ["ep_info"],
+ },
+ 0x104: {
+ "tag_name": "sram_layout",
+ "format": "2Q",
+ "fields": ["addr", "size"],
+ },
+}
+tag_name_to_tag_id = {
+ te["tag_name"]: tag_id for tag_id, te in transfer_entry_formats.items()
+}
+
+
+class TransferList:
+ """Class representing a Transfer List based on version 1.0 of the Firmware Handoff specification."""
+
+ # Header encoding, with little-endian byte order.
+ encoding = "<I4B4I"
+ hdr_size = 0x18
+ signature = 0x4A0FB10B
+ version = 1
+
+ def __init__(
+ self, max_size: int = hdr_size, flags: int = TRANSFER_LIST_ENABLE_CHECKSUM
+ ) -> None:
+ assert max_size >= self.hdr_size
+ self.checksum: int = 0
+ self.alignment: int = 3
+ self.size = self.hdr_size
+ self.total_size = max_size
+ self.flags = flags
+ self.entries: typing.List["TransferEntry"] = []
+ self.update_checksum()
+
+ def __str__(self) -> str:
+ return "\n".join(
+ [
+ f"{k:<10} {hex(v)}"
+ for k, v in vars(self).items()
+ if not isinstance(v, list)
+ ]
+ )
+
+ def get_transfer_entries_str(self):
+ return "\n----\n".join([str(te) for _, te in enumerate(self.entries)])
+
+ @classmethod
+ def fromfile(cls, filepath: Path) -> "TransferList":
+ tl = cls()
+
+ with open(filepath, "rb") as f:
+ (
+ tl.signature,
+ tl.checksum,
+ tl.version,
+ tl.hdr_size,
+ tl.alignment,
+ used_size,
+ tl.total_size,
+ tl.flags,
+ _,
+ ) = struct.unpack(
+ cls.encoding,
+ f.read(tl.hdr_size),
+ )
+
+ if tl.signature != TransferList.signature:
+ raise ValueError(f"Invalid TL signature 0x{tl.signature:x}!")
+ elif tl.version == 0 or tl.version > 0xFF:
+ raise ValueError(f"Invalid TL version 0x{tl.version:x}!")
+ else:
+ while tl.size < used_size:
+ # We add an extra padding byte into the header so we can extract
+ # the 3-byte wide ID as a 4-byte uint, shift out this padding
+ # once we have the id.
+ te_base = f.tell()
+ (id, hdr_size, data_size) = struct.unpack(
+ TransferEntry.encoding[0] + "I" + TransferEntry.encoding[1:],
+ b"\x00" + f.read(TransferEntry.hdr_size),
+ )
+
+ id >>= 8
+
+ te = tl.add_transfer_entry(id, f.read(data_size))
+ te.offset = te_base
+ f.seek(align(te_base + hdr_size + data_size, 2**tl.alignment))
+
+ return tl
+
+ @classmethod
+ def from_dict(cls, config: dict):
+ """Create a TL from data in a dictionary
+
+ The dictionary should have the same format as the yaml config files.
+ See the readme for more detail.
+
+ :param config: Dictionary containing the data described above.
+ """
+ # get settings from config and set defaults
+ max_size = config.get("max_size", 0x1000)
+ has_checksum = config.get("has_checksum", True)
+
+ flags = TRANSFER_LIST_ENABLE_CHECKSUM if has_checksum else 0
+
+ tl = cls(max_size, flags)
+
+ for entry in config["entries"]:
+ tl.add_transfer_entry_from_dict(entry)
+
+ return tl
+
+ def header_to_bytes(self) -> bytes:
+ return struct.pack(
+ self.encoding,
+ self.signature,
+ self.checksum,
+ self.version,
+ self.hdr_size,
+ self.alignment,
+ self.size,
+ self.total_size,
+ self.flags,
+ 0,
+ )
+
+ def update_checksum(self) -> None:
+ """Calculates the checksum based on the sum of bytes."""
+ self.checksum = 256 - ((self.sum_of_bytes() - self.checksum) % 256)
+
+ def sum_of_bytes(self) -> int:
+ """Sum of all bytes between the base address and the end of that last TE (modulo 0xff)."""
+ return (
+ sum(self.header_to_bytes()) + sum(te.sum_of_bytes for te in self.entries)
+ ) % 256
+
+ def get_entry_data_offset(self, tag_id: int) -> int:
+ """Returns offset of data of a TE from the base of the TL."""
+ for te in self.entries:
+ if te.id == tag_id:
+ return te.offset + te.hdr_size
+
+ raise ValueError(f"Tag {tag_id} not found in TL!")
+
+ def add_transfer_entry(self, tag_id: int, data: bytes) -> "TransferEntry":
+ """Appends a TransferEntry into the internal list of TE's."""
+ if not (self.total_size >= self.size + TransferEntry.hdr_size + len(data)):
+ raise MemoryError(
+ f"TL size has exceeded the maximum allocation {self.total_size}."
+ )
+ else:
+ te = TransferEntry(tag_id, len(data), data)
+ self.entries.append(te)
+ self.size += te.size
+ self.update_checksum()
+ return te
+
+ def add_transfer_entry_from_struct_format(
+ self, tag_id: int, struct_format: str, *args
+ ):
+ struct_format = "<" + struct_format
+ data = struct.pack(struct_format, *args)
+ return self.add_transfer_entry(tag_id, data)
+
+ def add_entry_point_info_transfer_entry(self, entry: dict) -> "TransferEntry":
+ """Add entry_point_info transfer entry
+
+ :param entry: Dictionary of the transfer entry, in the same format as
+ the YAML file.
+ """
+ ep_info = entry["ep_info"]
+ header = ep_info["h"]
+
+ # size of the entry_point_info struct
+ entry_point_size = 88
+
+ attr = header["attr"]
+ if type(attr) is str:
+ # convert string of flags names to an integer
+
+ # bit number | 0 | 1 |
+ # ------------|-----------------------|----------------------|
+ # 0 | secure | non-secure |
+ # 1 | little endian | big-endian |
+ # 2 | disable secure timer | enable secure timer |
+ # 3 | executable | non-executable |
+ # 4 | first exe | not first exe |
+ #
+ # Bit 5 and bit 0 are used to determine the security state.
+
+ flag_names = {
+ "EP_SECURE": 0x0,
+ "EP_NON_SECURE": 0x1,
+ "EP_REALM": 0x21,
+ "EP_EE_LITTLE": 0x0,
+ "EP_EE_BIG": 0x2,
+ "EP_ST_DISABLE": 0x0,
+ "EP_ST_ENABLE": 0x4,
+ "EP_NON_EXECUTABLE": 0x0,
+ "EP_EXECUTABLE": 0x8,
+ "EP_FIRST_EXE": 0x10,
+ }
+
+ # create list of integer flags, then bitwise-or them together
+ flags = [flag_names[f.strip()] for f in attr.split("|")]
+ attr = reduce(lambda x, y: x | y, flags)
+
+ return self.add_transfer_entry_from_struct_format(
+ 0x102,
+ transfer_entry_formats[0x102]["format"],
+ header["type"],
+ header["version"],
+ entry_point_size,
+ attr,
+ ep_info["pc"],
+ ep_info["spsr"],
+ *ep_info["args"],
+ )
+
+ def add_transfer_entry_from_dict(
+ self,
+ entry: dict,
+ ) -> "TransferEntry":
+ """Add a transfer entry from data in a dictionary
+
+ The dictionary should have the same format as the entries in the yaml
+ config files. See the readme for more detail.
+
+ :param entry: Dictionary containing the data described above.
+ """
+ # Tag_id is either a tag name or a tag id. Use it to get the TE format.
+ tag_id = entry["tag_id"]
+ if tag_id in tag_name_to_tag_id:
+ tag_id = tag_name_to_tag_id[tag_id]
+ te_format = transfer_entry_formats[tag_id]
+ tag_name = te_format["tag_name"]
+
+ if "blob_file_path" in entry:
+ return self.add_transfer_entry_from_file(tag_id, entry["blob_file_path"])
+ elif tag_name == "tpm_event_log_table":
+ with open(entry["event_log"], "rb") as f:
+ event_log_data = f.read()
+
+ flags_bytes = entry["flags"].to_bytes(4, "little")
+ data = flags_bytes + event_log_data
+
+ return self.add_transfer_entry(tag_id, data)
+ elif tag_name == "exec_ep_info":
+ return self.add_entry_point_info_transfer_entry(entry)
+ elif "format" in te_format and "fields" in te_format:
+ fields = [entry[field] for field in te_format["fields"]]
+ return self.add_transfer_entry_from_struct_format(
+ tag_id, te_format["format"], *fields
+ )
+ else:
+ raise ValueError(f"Invalid transfer entry {entry}.")
+
+ def add_transfer_entry_from_file(self, tag_id: int, path: Path) -> "TransferEntry":
+ with open(path, "rb") as f:
+ return self.add_transfer_entry(tag_id, f.read())
+
+ def write_to_file(self, file: Path) -> None:
+ """Write the contents of the TL to a file."""
+ with open(file, "wb") as f:
+ f.write(self.header_to_bytes())
+ for te in self.entries:
+ assert f.tell() + te.hdr_size + te.data_size < self.total_size
+ te_base = f.tell()
+ f.write(te.header_to_bytes())
+ f.write(te.data)
+ # Ensure the next TE has the correct alignment
+ f.write(
+ bytes(
+ (
+ align(
+ te_base + te.hdr_size + te.data_size, 2**self.alignment
+ )
+ - f.tell()
+ )
+ )
+ )
+
+ def remove_tag(self, tag: int) -> None:
+ self.entries = list(filter(lambda te: te.id != tag, self.entries))
+ self.size = self.hdr_size + sum(map(lambda te: te.size, self.entries))
+ self.update_checksum()
+
+
+def align(n, alignment):
+ return int(math.ceil(n / alignment) * alignment)
