mediatek: mt8195: add rtc power off sequence
mt8195 also uses mt6359p RTC. Revice mt8192 RTC and share the
driver with mt8195.
Change-Id: I20c73f6e0af67ef9d4c3d4e0ff373f93950e07db
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.c b/plat/mediatek/mt8192/drivers/rtc/rtc.c
deleted file mode 100644
index 124bc8f..0000000
--- a/plat/mediatek/mt8192/drivers/rtc/rtc.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <rtc.h>
-
-
-static void RTC_Config_Interface(uint32_t addr, uint16_t data,
- uint16_t mask, uint16_t shift)
-{
- uint16_t pmic_reg;
-
- pmic_reg = RTC_Read(addr);
-
- pmic_reg &= ~(mask << shift);
- pmic_reg |= (data << shift);
-
- RTC_Write(addr, pmic_reg);
-}
-
-static int32_t rtc_disable_2sec_reboot(void)
-{
- uint16_t reboot;
-
- reboot = (RTC_Read(RTC_AL_SEC) & ~RTC_BBPU_2SEC_EN) &
- ~RTC_BBPU_AUTO_PDN_SEL;
- RTC_Write(RTC_AL_SEC, reboot);
-
- return RTC_Write_Trigger();
-}
-
-static int32_t rtc_enable_k_eosc(void)
-{
- uint16_t alm_dow, alm_sec;
- int16_t ret;
-
- /* Turning on eosc cali mode clock */
- RTC_Config_Interface(PMIC_RG_SCK_TOP_CKPDN_CON0_CLR, 1,
- PMIC_RG_RTC_EOSC32_CK_PDN_MASK,
- PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT);
-
- alm_sec = RTC_Read(RTC_AL_SEC) & (~RTC_LPD_OPT_MASK);
- RTC_Write(RTC_AL_SEC, alm_sec);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- RTC_Write(RTC_CON, RTC_LPD_EN);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- RTC_Write(RTC_CON, RTC_LPD_RST);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- RTC_Write(RTC_CON, RTC_LPD_EN);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- RTC_Write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
- RTC_Write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- /* set RTC EOSC calibration period = 8sec */
- alm_dow = (RTC_Read(RTC_AL_DOW) & (~RTC_RG_EOSC_CALI_TD_MASK)) |
- RTC_RG_EOSC_CALI_TD_8SEC;
- RTC_Write(RTC_AL_DOW, alm_dow);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- RTC_Write(RTC_BBPU,
- RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- /* Enable K EOSC mode :use solution1 of eosc cali to fix mt6359p 32K*/
- RTC_Write(RTC_AL_YEA, (((RTC_Read(RTC_AL_YEA) | RTC_K_EOSC_RSV_0)
- & (~RTC_K_EOSC_RSV_1)) | (RTC_K_EOSC_RSV_2)));
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return 0;
- }
-
- INFO("[RTC] RTC_enable_k_eosc\n");
-
- return 1;
-}
-
-void rtc_power_off_sequence(void)
-{
- uint16_t bbpu;
- int16_t ret;
-
- ret = rtc_disable_2sec_reboot();
- if (ret == 0) {
- return;
- }
-
- ret = rtc_enable_k_eosc();
- if (ret == 0) {
- return;
- }
-
- bbpu = RTC_BBPU_KEY | RTC_BBPU_PWREN;
-
- if (Writeif_unlock() != 0) {
- RTC_Write(RTC_BBPU,
- bbpu | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR);
- RTC_Write(RTC_AL_MASK, RTC_AL_MASK_DOW);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return;
- }
- mdelay(1);
-
- bbpu = RTC_Read(RTC_BBPU);
-
- if (((bbpu & RTC_BBPU_RESET_ALARM) > 0) ||
- ((bbpu & RTC_BBPU_RESET_SPAR) > 0)) {
- INFO("[RTC] timeout\n");
- }
-
- bbpu = RTC_Read(RTC_BBPU) | RTC_BBPU_KEY | RTC_BBPU_RELOAD;
- RTC_Write(RTC_BBPU, bbpu);
- ret = RTC_Write_Trigger();
- if (ret == 0) {
- return;
- }
- }
-}
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.h b/plat/mediatek/mt8192/drivers/rtc/rtc.h
deleted file mode 100644
index 419bfe4..0000000
--- a/plat/mediatek/mt8192/drivers/rtc/rtc.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RTC_H
-#define RTC_H
-
-/* RTC registers */
-enum {
- RTC_BBPU = 0x0588,
- RTC_IRQ_STA = 0x058A,
- RTC_IRQ_EN = 0x058C,
- RTC_CII_EN = 0x058E
-};
-
-enum {
- RTC_AL_SEC = 0x05A0,
- RTC_AL_MIN = 0x05A2,
- RTC_AL_HOU = 0x05A4,
- RTC_AL_DOM = 0x05A6,
- RTC_AL_DOW = 0x05A8,
- RTC_AL_MTH = 0x05AA,
- RTC_AL_YEA = 0x05AC,
- RTC_AL_MASK = 0x0590
-};
-
-enum {
- RTC_OSC32CON = 0x05AE,
- RTC_CON = 0x05C4,
- RTC_WRTGR = 0x05C2
-};
-
-enum {
- RTC_POWERKEY1 = 0x05B0,
- RTC_POWERKEY2 = 0x05B2
-};
-
-enum {
- RTC_POWERKEY1_KEY = 0xA357,
- RTC_POWERKEY2_KEY = 0x67D2
-};
-
-enum {
- RTC_PDN1 = 0x05B4,
- RTC_PDN2 = 0x05B6,
- RTC_SPAR0 = 0x05B8,
- RTC_SPAR1 = 0x05BA,
- RTC_PROT = 0x05BC,
- RTC_DIFF = 0x05BE,
- RTC_CALI = 0x05C0
-};
-
-enum {
- RTC_OSC32CON_UNLOCK1 = 0x1A57,
- RTC_OSC32CON_UNLOCK2 = 0x2B68
-};
-
-enum {
- RTC_LPD_EN = 0x0406,
- RTC_LPD_RST = 0x040E
-};
-
-enum {
- RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
- RTC_LPD_OPT_EOSC_LPD = 1U << 13,
- RTC_LPD_OPT_XOSC_LPD = 2U << 13,
- RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
-};
-
-#define RTC_LPD_OPT_MASK (3U << 13)
-
-enum {
- RTC_PROT_UNLOCK1 = 0x586A,
- RTC_PROT_UNLOCK2 = 0x9136
-};
-
-enum {
- RTC_BBPU_PWREN = 1U << 0,
- RTC_BBPU_SPAR_SW = 1U << 1,
- RTC_BBPU_RESET_SPAR = 1U << 2,
- RTC_BBPU_RESET_ALARM = 1U << 3,
- RTC_BBPU_CLRPKY = 1U << 4,
- RTC_BBPU_RELOAD = 1U << 5,
- RTC_BBPU_CBUSY = 1U << 6
-};
-
-enum {
- RTC_AL_MASK_SEC = 1U << 0,
- RTC_AL_MASK_MIN = 1U << 1,
- RTC_AL_MASK_HOU = 1U << 2,
- RTC_AL_MASK_DOM = 1U << 3,
- RTC_AL_MASK_DOW = 1U << 4,
- RTC_AL_MASK_MTH = 1U << 5,
- RTC_AL_MASK_YEA = 1U << 6
-};
-
-enum {
- RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
- RTC_BBPU_2SEC_CK_SEL = 1U << 7,
- RTC_BBPU_2SEC_EN = 1U << 8,
- RTC_BBPU_2SEC_MODE = 0x3 << 9,
- RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
- RTC_BBPU_2SEC_STAT_STA = 1U << 12
-};
-
-enum {
- RTC_BBPU_KEY = 0x43 << 8
-};
-
-enum {
- RTC_EMBCK_SRC_SEL = 1 << 8,
- RTC_EMBCK_SEL_MODE = 3 << 6,
- RTC_XOSC32_ENB = 1 << 5,
- RTC_REG_XOSC32_ENB = 1 << 15
-};
-
-enum {
- RTC_K_EOSC_RSV_0 = 1 << 8,
- RTC_K_EOSC_RSV_1 = 1 << 9,
- RTC_K_EOSC_RSV_2 = 1 << 10
-};
-
-enum {
- RTC_RG_EOSC_CALI_TD_1SEC = 3 << 5,
- RTC_RG_EOSC_CALI_TD_2SEC = 4 << 5,
- RTC_RG_EOSC_CALI_TD_4SEC = 5 << 5,
- RTC_RG_EOSC_CALI_TD_8SEC = 6 << 5,
- RTC_RG_EOSC_CALI_TD_16SEC = 7 << 5,
- RTC_RG_EOSC_CALI_TD_MASK = 7 << 5
-};
-
-/* PMIC TOP Register Definition */
-enum {
- PMIC_RG_TOP_CON = 0x0020,
- PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
- PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
- PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
- PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
- PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
- PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
-};
-
-/* PMIC SCK Register Definition */
-enum {
- PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x0514,
- PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x0516,
- PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x0518,
- PMIC_RG_EOSC_CALI_CON0 = 0x53A
-};
-
-enum {
- PMIC_EOSC_CALI_START_ADDR = 0x53A
-};
-
-enum {
- PMIC_EOSC_CALI_START_MASK = 0x1,
- PMIC_EOSC_CALI_START_SHIFT = 0
-};
-
-/* PMIC DCXO Register Definition */
-enum {
- PMIC_RG_DCXO_CW00 = 0x0788,
- PMIC_RG_DCXO_CW02 = 0x0790,
- PMIC_RG_DCXO_CW08 = 0x079C,
- PMIC_RG_DCXO_CW09 = 0x079E,
- PMIC_RG_DCXO_CW09_CLR = 0x07A2,
- PMIC_RG_DCXO_CW10 = 0x07A4,
- PMIC_RG_DCXO_CW12 = 0x07A8,
- PMIC_RG_DCXO_CW13 = 0x07AA,
- PMIC_RG_DCXO_CW15 = 0x07AE,
- PMIC_RG_DCXO_CW19 = 0x07B6,
-};
-
-enum {
- PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
- PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
- PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
- PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
- PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
- PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
- PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
- PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
- PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
- PMIC_RG_XO_EN32K_MAN_SHIFT = 0
-};
-
-/* external API */
-uint16_t RTC_Read(uint32_t addr);
-void RTC_Write(uint32_t addr, uint16_t data);
-int32_t rtc_busy_wait(void);
-int32_t RTC_Write_Trigger(void);
-int32_t Writeif_unlock(void);
-void rtc_power_off_sequence(void);
-
-#endif /* RTC_H */
diff --git a/plat/mediatek/mt8192/include/rtc.h b/plat/mediatek/mt8192/include/rtc.h
new file mode 100644
index 0000000..a9c7bc8
--- /dev/null
+++ b/plat/mediatek/mt8192/include/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif /* RTC_H */
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index 49d1059..86e353f 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -10,6 +10,7 @@
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/gic600/ \
-I${MTK_PLAT}/common/drivers/gpio/ \
+ -I${MTK_PLAT}/common/drivers/rtc/ \
-I${MTK_PLAT}/common/drivers/timer/ \
-I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT}/common/lpm/ \
@@ -21,7 +22,6 @@
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/ptp3/ \
- -I${MTK_PLAT_SOC}/drivers/rtc/ \
-I${MTK_PLAT_SOC}/drivers/spmc/
GICV3_SUPPORT_GIC600 := 1
@@ -46,6 +46,7 @@
${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \
${MTK_PLAT}/common/drivers/timer/mt_timer.c \
${MTK_PLAT}/common/drivers/uart/uart.c \
${MTK_PLAT}/common/lpm/mt_lp_rm.c \
@@ -57,7 +58,6 @@
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
- ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \