Merge pull request #1335 from JoelHutton/jh/cleanup_void_pointers
Clean usage of void pointers to access symbols
diff --git a/Makefile b/Makefile
index 94ae63e..ca91e69 100644
--- a/Makefile
+++ b/Makefile
@@ -275,13 +275,6 @@
endif
################################################################################
-# Include libraries' Makefile that are used in all BL
-################################################################################
-
-include lib/stack_protector/stack_protector.mk
-
-
-################################################################################
# Include the platform specific Makefile after the SPD Makefile (the platform
# makefile may use all previous definitions in this file)
################################################################################
@@ -441,6 +434,12 @@
endif
################################################################################
+# Include libraries' Makefile that are used in all BL
+################################################################################
+
+include lib/stack_protector/stack_protector.mk
+
+################################################################################
# Auxiliary tools (fiptool, cert_create, etc)
################################################################################
diff --git a/include/drivers/console.h b/include/drivers/console.h
index f8ec83d..c8a43a2 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -66,6 +66,8 @@
/* REMOVED on AArch64 -- use console_<driver>_register() instead! */
int console_init(uintptr_t base_addr,
unsigned int uart_clk, unsigned int baud_rate);
+int console_core_init(uintptr_t base_addr,
+ unsigned int uart_clk, unsigned int baud_rate);
void console_uninit(void);
#endif
diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c
index 3e79c5d..e925d34 100644
--- a/lib/psci/psci_stat.c
+++ b/lib/psci/psci_stat.c
@@ -24,7 +24,8 @@
* Following is used to keep track of the last cpu
* that goes to power down in non cpu power domains.
*/
-static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1};
+static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {
+ [0 ... PSCI_NUM_NON_CPU_PWR_DOMAINS-1] = -1};
/*
* Following are used to store PSCI STAT values for
@@ -129,6 +130,10 @@
* prior to this CPU powering on.
*/
parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
+ /* Return early if this is the first power up. */
+ if (last_cpu_in_non_cpu_pd[parent_idx] == -1)
+ return;
+
for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
local_state = state_info->pwr_domain_state[lvl];
if (is_local_state_run(local_state)) {
diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c
index f95af58..658760b 100644
--- a/plat/hisilicon/hikey/aarch64/hikey_common.c
+++ b/plat/hisilicon/hikey/aarch64/hikey_common.c
@@ -9,13 +9,12 @@
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
+#include <hikey_def.h>
+#include <hikey_layout.h>
#include <mmio.h>
#include <platform.h>
-#include <platform_def.h>
#include <xlat_tables.h>
-#include "../hikey_def.h"
-
#define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \
DDR_SIZE - DDR_SEC_SIZE, \
MT_DEVICE | MT_RW | MT_NS)
diff --git a/plat/hisilicon/hikey/aarch64/hikey_helpers.S b/plat/hisilicon/hikey/aarch64/hikey_helpers.S
index 680c0a1..32ff8b4 100644
--- a/plat/hisilicon/hikey/aarch64/hikey_helpers.S
+++ b/plat/hisilicon/hikey/aarch64/hikey_helpers.S
@@ -1,12 +1,12 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
-#include "../hikey_def.h"
+#include <hikey_def.h>
.globl plat_my_core_pos
.globl platform_mem_init
diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c
index 9ede1db..28ad9df 100644
--- a/plat/hisilicon/hikey/hikey_bl1_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl1_setup.c
@@ -13,14 +13,14 @@
#include <emmc.h>
#include <errno.h>
#include <hi6220.h>
+#include <hikey_def.h>
+#include <hikey_layout.h>
#include <mmio.h>
#include <platform.h>
-#include <platform_def.h>
#include <string.h>
#include <tbbr/tbbr_img_desc.h>
#include "../../bl1/bl1_private.h"
-#include "hikey_def.h"
#include "hikey_private.h"
/* Data structure which holds the extents of the trusted RAM for BL1 */
diff --git a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
index 7c025c3..23c16ed 100644
--- a/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
+++ b/plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c
@@ -7,7 +7,7 @@
#include <bl_common.h>
#include <desc_image_load.h>
#include <platform.h>
-#include <platform_def.h>
+#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
/*******************************************************************************
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index 20bb752..8bb2824 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -21,10 +21,9 @@
#include <optee_utils.h>
#endif
#include <platform.h>
-#include <platform_def.h>
+#include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
#include <string.h>
-#include "hikey_def.h"
#include "hikey_private.h"
/*
diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c
index e13ecf6..a193b5a 100644
--- a/plat/hisilicon/hikey/hikey_bl31_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl31_setup.c
@@ -14,12 +14,12 @@
#include <errno.h>
#include <gicv2.h>
#include <hi6220.h>
+#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <mmio.h>
#include <platform_def.h>
-#include "hikey_def.h"
#include "hikey_private.h"
/*
diff --git a/plat/hisilicon/hikey/hikey_pm.c b/plat/hisilicon/hikey/hikey_pm.c
index d4dd683..3128a3d 100644
--- a/plat/hisilicon/hikey/hikey_pm.c
+++ b/plat/hisilicon/hikey/hikey_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <debug.h>
#include <gicv2.h>
#include <hi6220.h>
+#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
#include <hisi_sram_map.h>
@@ -17,8 +18,6 @@
#include <psci.h>
#include <sp804_delay_timer.h>
-#include "hikey_def.h"
-
#define CORE_PWR_STATE(state) \
((state)->pwr_domain_state[MPIDR_AFFLVL0])
#define CLUSTER_PWR_STATE(state) \
diff --git a/plat/hisilicon/hikey/hikey_def.h b/plat/hisilicon/hikey/include/hikey_def.h
similarity index 88%
rename from plat/hisilicon/hikey/hikey_def.h
rename to plat/hisilicon/hikey/include/hikey_def.h
index 668b459..deb375d 100644
--- a/plat/hisilicon/hikey/hikey_def.h
+++ b/plat/hisilicon/hikey/include/hikey_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,9 +7,6 @@
#ifndef __HIKEY_DEF_H__
#define __HIKEY_DEF_H__
-#include <common_def.h>
-#include <tbbr_img_def.h>
-
/* Always assume DDR is 1GB size. */
#define DDR_BASE 0x0
#define DDR_SIZE 0x40000000
@@ -17,9 +14,6 @@
#define DEVICE_BASE 0xF4000000
#define DEVICE_SIZE 0x05800000
-#define XG2RAM0_BASE 0xF9800000
-#define XG2RAM0_SIZE 0x00400000
-
/* Memory location options for TSP */
#define HIKEY_SRAM_ID 0
#define HIKEY_DRAM_ID 1
@@ -43,13 +37,6 @@
#define SRAM_SIZE 0x00012000
/*
- * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
- */
-#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
-#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
-#define BL1_XG2RAM0_OFFSET 0x1000
-
-/*
* PL011 related constants
*/
#define PL011_UART0_BASE 0xF8015000
diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h
new file mode 100644
index 0000000..637a1c9
--- /dev/null
+++ b/plat/hisilicon/hikey/include/hikey_layout.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HIKEY_LAYOUT_H
+#define __HIKEY_LAYOUT_H
+
+/*
+ * Platform memory map related constants
+ */
+#define XG2RAM0_BASE 0xF9800000
+#define XG2RAM0_SIZE 0x00400000
+
+/*
+ * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
+ */
+#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
+#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
+#define BL1_XG2RAM0_OFFSET 0x1000
+
+/*
+ * BL1 specific defines.
+ *
+ * Both loader and BL1_RO region stay in SRAM since they are used to simulate
+ * ROM.
+ * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
+ *
+ * ++++++++++ 0xF980_0000
+ * + loader +
+ * ++++++++++ 0xF980_1000
+ * + BL1_RO +
+ * ++++++++++ 0xF981_0000
+ * + BL1_RW +
+ * ++++++++++ 0xF989_8000
+ */
+#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
+#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
+#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
+#define BL1_RW_SIZE (0x00088000)
+#define BL1_RW_LIMIT (0xF9898000)
+
+/*
+ * Non-Secure BL1U specific defines.
+ */
+#define NS_BL1U_BASE (0xf9818000)
+#define NS_BL1U_SIZE (0x00010000)
+#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
+
+/*
+ * BL2 specific defines.
+ *
+ * Both loader and BL2 region stay in SRAM.
+ * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
+ *
+ * ++++++++++ 0xF980_0000
+ * + loader +
+ * ++++++++++ 0xF980_1000
+ * + BL2 +
+ * ++++++++++ 0xF981_8000
+ */
+#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
+#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
+
+/*
+ * SCP_BL2 specific defines.
+ * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
+ * at 0x0100_0000. Then BL2 will parse the sections and loaded them into
+ * predefined separated buffers.
+ */
+#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
+#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
+#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
+
+/*
+ * BL31 specific defines.
+ */
+#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
+#define BL31_LIMIT (0xF9898000)
+
+/*
+ * BL3-2 specific defines.
+ */
+
+/*
+ * The TSP currently executes from TZC secured area of DRAM or SRAM.
+ */
+#define BL32_SRAM_BASE BL31_LIMIT
+#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
+
+#define BL32_DRAM_BASE DDR_SEC_BASE
+#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
+
+#ifdef SPD_opteed
+/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
+#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
+#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
+#endif
+
+#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
+#define BL32_BASE BL32_DRAM_BASE
+#define BL32_LIMIT BL32_DRAM_LIMIT
+#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
+#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
+#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
+#define BL32_BASE BL32_SRAM_BASE
+#define BL32_LIMIT BL32_SRAM_LIMIT
+#else
+#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
+#endif
+
+/* BL32 is mandatory in AArch32 */
+#ifndef AARCH32
+#ifdef SPD_none
+#undef BL32_BASE
+#endif /* SPD_none */
+#endif
+
+#endif /* !__HIKEY_LAYOUT_H */
diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h
index 9b4f463..8c56004 100644
--- a/plat/hisilicon/hikey/include/platform_def.h
+++ b/plat/hisilicon/hikey/include/platform_def.h
@@ -8,7 +8,10 @@
#define __PLATFORM_DEF_H__
#include <arch.h>
-#include "../hikey_def.h"
+#include <common_def.h>
+#include <hikey_def.h>
+#include <hikey_layout.h> /* BL memory region sizes, etc */
+#include <tbbr_img_def.h>
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
@@ -27,7 +30,7 @@
#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
-#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1)
@@ -45,114 +48,6 @@
#define PLAT_ARM_GICH_BASE 0xF6804000
#define PLAT_ARM_GICV_BASE 0xF6806000
-
-/*
- * Platform memory map related constants
- */
-
-/*
- * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
- */
-#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
-#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
-#define BL1_XG2RAM0_OFFSET 0x1000
-
-/*
- * BL1 specific defines.
- *
- * Both loader and BL1_RO region stay in SRAM since they are used to simulate
- * ROM.
- * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
- *
- * ++++++++++ 0xF980_0000
- * + loader +
- * ++++++++++ 0xF980_1000
- * + BL1_RO +
- * ++++++++++ 0xF981_0000
- * + BL1_RW +
- * ++++++++++ 0xF989_8000
- */
-#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
-#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
-#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
-#define BL1_RW_SIZE (0x00088000)
-#define BL1_RW_LIMIT (0xF9898000)
-
-/*
- * BL2 specific defines.
- *
- * Both loader and BL2 region stay in SRAM.
- * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
- *
- * ++++++++++ 0xF980_0000
- * + loader +
- * ++++++++++ 0xF980_1000
- * + BL2 +
- * ++++++++++ 0xF981_8000
- */
-#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
-#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
-
-/*
- * SCP_BL2 specific defines.
- * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
- * at 0x0100_0000. Then BL2 will parse the sections and loaded them into
- * predefined separated buffers.
- */
-#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
-#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
-#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
-
-/*
- * BL31 specific defines.
- */
-#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
-#define BL31_LIMIT (0xF9898000)
-
-/*
- * BL3-2 specific defines.
- */
-
-/*
- * The TSP currently executes from TZC secured area of DRAM or SRAM.
- */
-#define BL32_SRAM_BASE BL31_LIMIT
-#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
-
-#define BL32_DRAM_BASE DDR_SEC_BASE
-#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
-
-#ifdef SPD_opteed
-/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
-#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
-#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
-#endif
-
-#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
-#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
-#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
-#define BL32_BASE BL32_DRAM_BASE
-#define BL32_LIMIT BL32_DRAM_LIMIT
-#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
-#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
-#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
-#define BL32_BASE BL32_SRAM_BASE
-#define BL32_LIMIT BL32_SRAM_LIMIT
-#else
-#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
-#endif
-
-/* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
-#ifdef SPD_none
-#undef BL32_BASE
-#endif /* SPD_none */
-#endif
-
-#define NS_BL1U_BASE (0xf9818000)
-#define NS_BL1U_SIZE (0x00010000)
-#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
-
/*
* Platform specific page table and MMU setup constants
*/
@@ -172,8 +67,6 @@
#define MAX_MMAP_REGIONS 16
-#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
-
/*
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index a9fbcd7..017807b 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -169,7 +169,12 @@
endif
SEPARATE_CODE_AND_RODATA := 1
-MULTI_CONSOLE_API := 1
+
+# Use MULTI_CONSOLE_API by default only on AArch64
+# as it is not yet supported on AArch32
+ifeq ($(ARCH),aarch64)
+MULTI_CONSOLE_API := 1
+endif
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
diff --git a/plat/qemu/qemu_console.c b/plat/qemu/qemu_console.c
index 9c02957..1cf84aa 100644
--- a/plat/qemu/qemu_console.c
+++ b/plat/qemu/qemu_console.c
@@ -7,8 +7,10 @@
#include <pl011.h>
#include <platform_def.h>
+#if MULTI_CONSOLE_API
static console_pl011_t console;
static console_pl011_t crash_console;
+#endif /* MULTI_CONSOLE_API */
void qemu_console_init(void)
{
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index f4893ef..caea7a7 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1319,10 +1319,14 @@
{
int i;
- for (i = 0; i < 2; i++) {
+ for (i = 1; i >= 0; i--) {
mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
}
+
+ /* write 0x76 to cnt_restart to keep watchdog alive */
+ mmio_write_32(WDT0_BASE + 0x0c, 0x76);
+ mmio_write_32(WDT1_BASE + 0x0c, 0x76);
}
int rockchip_soc_sys_pwr_dm_suspend(void)
@@ -1383,6 +1387,7 @@
}
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
+ wdt_register_save();
secure_watchdog_disable();
/*
@@ -1398,7 +1403,6 @@
suspend_uart();
grf_register_save();
cru_register_save();
- wdt_register_save();
sram_save();
plat_rockchip_save_gpio();
@@ -1411,7 +1415,6 @@
uint32_t status = 0;
plat_rockchip_restore_gpio();
- wdt_register_restore();
cru_register_restore();
grf_register_restore();
resume_uart();
@@ -1426,6 +1429,7 @@
secure_watchdog_enable();
secure_sgrf_init();
secure_sgrf_ddr_rgn_init();
+ wdt_register_restore();
/* restore clk_ddrc_bpll_src_en gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index d6e5726..97f202c 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -451,7 +451,7 @@
uint32_t spsr;
ns_ep_info = bl31_plat_get_next_image_ep_info(NON_SECURE);
- if (!ep_info) {
+ if (ns_ep_info == NULL) {
NOTICE("Trusty: non-secure image missing.\n");
return -1;
}