diff --git a/plat/nvidia/tegra/include/drivers/bpmp.h b/plat/nvidia/tegra/include/drivers/bpmp.h
index 27f57df..03da6f6 100644
--- a/plat/nvidia/tegra/include/drivers/bpmp.h
+++ b/plat/nvidia/tegra/include/drivers/bpmp.h
@@ -10,25 +10,25 @@
 #include <stdint.h>
 
 /* macro to enable clock to the Atomics block */
-#define CAR_ENABLE_ATOMICS	(1UL << 16)
+#define CAR_ENABLE_ATOMICS	(1U << 16)
 
 /* command to get the channel base addresses from bpmp */
-#define ATOMIC_CMD_GET		4UL
+#define ATOMIC_CMD_GET		4U
 
 /* Hardware IRQ # used to signal bpmp of an incoming command */
-#define INT_SHR_SEM_OUTBOX_FULL	6UL
+#define INT_SHR_SEM_OUTBOX_FULL	6U
 
 /* macros to decode the bpmp's state */
-#define CH_MASK(ch)		(0x3UL << ((ch) * 2UL))
-#define MA_FREE(ch)		(0x2UL << ((ch) * 2UL))
-#define MA_ACKD(ch)		(0x3UL << ((ch) * 2UL))
+#define CH_MASK(ch)		((uint32_t)0x3 << ((ch) * 2U))
+#define MA_FREE(ch)		((uint32_t)0x2 << ((ch) * 2U))
+#define MA_ACKD(ch)		((uint32_t)0x3 << ((ch) * 2U))
 
 /* response from bpmp to indicate it has powered up */
-#define SIGN_OF_LIFE		0xAAAAAAAAUL
+#define SIGN_OF_LIFE		0xAAAAAAAAU
 
 /* flags to indicate bpmp driver's state */
-#define BPMP_INIT_COMPLETE	0xBEEFF00DUL
-#define BPMP_INIT_PENDING	0xDEADBEEFUL
+#define BPMP_INIT_COMPLETE	0xBEEFF00DU
+#define BPMP_INIT_PENDING	0xDEADBEEFU
 
 /* requests serviced by the bpmp */
 #define MRQ_PING		0
@@ -64,14 +64,14 @@
 #define TEGRA_PM_SC7		23
 
 /* flag to indicate if entry into a CCx power state is allowed */
-#define BPMP_CCx_ALLOWED	0UL
+#define BPMP_CCx_ALLOWED	0U
 
 /* number of communication channels to interact with the bpmp */
 #define NR_CHANNELS		4U
 
 /* flag to ask bpmp to acknowledge command packet */
-#define NO_ACK			(0UL << 0UL)
-#define DO_ACK			(1UL << 0UL)
+#define NO_ACK			(0U << 0U)
+#define DO_ACK			(1U << 0U)
 
 /* size of the command/response data */
 #define MSG_DATA_MAX_SZ		120U
diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index 4c21b97..7eb2952 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -17,177 +17,177 @@
  * StreamID to indicate no SMMU translations (requests to be steered on the
  * SMMU bypass path)
  ******************************************************************************/
-#define MC_STREAM_ID_MAX			0x7F
+#define MC_STREAM_ID_MAX			0x7FU
 
 /*******************************************************************************
  * Stream ID Override Config registers
  ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_CFG_PTCR		0x000
-#define MC_STREAMID_OVERRIDE_CFG_AFIR		0x070
-#define MC_STREAMID_OVERRIDE_CFG_HDAR		0x0A8
-#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR	0x0B0
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD	0x0E0
-#define MC_STREAMID_OVERRIDE_CFG_SATAR		0x0F8
-#define MC_STREAMID_OVERRIDE_CFG_MPCORER	0x138
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR	0x158
-#define MC_STREAMID_OVERRIDE_CFG_AFIW		0x188
-#define MC_STREAMID_OVERRIDE_CFG_HDAW		0x1A8
-#define MC_STREAMID_OVERRIDE_CFG_MPCOREW	0x1C8
-#define MC_STREAMID_OVERRIDE_CFG_SATAW		0x1E8
-#define MC_STREAMID_OVERRIDE_CFG_ISPRA		0x220
-#define MC_STREAMID_OVERRIDE_CFG_ISPWA		0x230
-#define MC_STREAMID_OVERRIDE_CFG_ISPWB		0x238
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR	0x250
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW	0x258
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR	0x260
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW	0x268
-#define MC_STREAMID_OVERRIDE_CFG_TSECSRD	0x2A0
-#define MC_STREAMID_OVERRIDE_CFG_TSECSWR	0x2A8
-#define MC_STREAMID_OVERRIDE_CFG_GPUSRD		0x2C0
-#define MC_STREAMID_OVERRIDE_CFG_GPUSWR		0x2C8
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA	0x300
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA	0x308
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCR		0x310
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB	0x318
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA	0x320
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA	0x328
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCW		0x330
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB	0x338
-#define MC_STREAMID_OVERRIDE_CFG_VICSRD		0x360
-#define MC_STREAMID_OVERRIDE_CFG_VICSWR		0x368
-#define MC_STREAMID_OVERRIDE_CFG_VIW		0x390
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD	0x3C0
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR	0x3C8
-#define MC_STREAMID_OVERRIDE_CFG_APER		0x3D0
-#define MC_STREAMID_OVERRIDE_CFG_APEW		0x3D8
-#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD	0x3F0
-#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR	0x3F8
-#define MC_STREAMID_OVERRIDE_CFG_SESRD		0x400
-#define MC_STREAMID_OVERRIDE_CFG_SESWR		0x408
-#define MC_STREAMID_OVERRIDE_CFG_ETRR		0x420
-#define MC_STREAMID_OVERRIDE_CFG_ETRW		0x428
-#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB	0x430
-#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB	0x438
-#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2	0x440
-#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2	0x448
-#define MC_STREAMID_OVERRIDE_CFG_AXISR		0x460
-#define MC_STREAMID_OVERRIDE_CFG_AXISW		0x468
-#define MC_STREAMID_OVERRIDE_CFG_EQOSR		0x470
-#define MC_STREAMID_OVERRIDE_CFG_EQOSW		0x478
-#define MC_STREAMID_OVERRIDE_CFG_UFSHCR		0x480
-#define MC_STREAMID_OVERRIDE_CFG_UFSHCW		0x488
-#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR	0x490
-#define MC_STREAMID_OVERRIDE_CFG_BPMPR		0x498
-#define MC_STREAMID_OVERRIDE_CFG_BPMPW		0x4A0
-#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR	0x4A8
-#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW	0x4B0
-#define MC_STREAMID_OVERRIDE_CFG_AONR		0x4B8
-#define MC_STREAMID_OVERRIDE_CFG_AONW		0x4C0
-#define MC_STREAMID_OVERRIDE_CFG_AONDMAR	0x4C8
-#define MC_STREAMID_OVERRIDE_CFG_AONDMAW	0x4D0
-#define MC_STREAMID_OVERRIDE_CFG_SCER		0x4D8
-#define MC_STREAMID_OVERRIDE_CFG_SCEW		0x4E0
-#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR	0x4E8
-#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW	0x4F0
-#define MC_STREAMID_OVERRIDE_CFG_APEDMAR	0x4F8
-#define MC_STREAMID_OVERRIDE_CFG_APEDMAW	0x500
-#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1	0x508
-#define MC_STREAMID_OVERRIDE_CFG_VICSRD1	0x510
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1	0x518
+#define MC_STREAMID_OVERRIDE_CFG_PTCR		0x000U
+#define MC_STREAMID_OVERRIDE_CFG_AFIR		0x070U
+#define MC_STREAMID_OVERRIDE_CFG_HDAR		0x0A8U
+#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR	0x0B0U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD	0x0E0U
+#define MC_STREAMID_OVERRIDE_CFG_SATAR		0x0F8U
+#define MC_STREAMID_OVERRIDE_CFG_MPCORER	0x138U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR	0x158U
+#define MC_STREAMID_OVERRIDE_CFG_AFIW		0x188U
+#define MC_STREAMID_OVERRIDE_CFG_HDAW		0x1A8U
+#define MC_STREAMID_OVERRIDE_CFG_MPCOREW	0x1C8U
+#define MC_STREAMID_OVERRIDE_CFG_SATAW		0x1E8U
+#define MC_STREAMID_OVERRIDE_CFG_ISPRA		0x220U
+#define MC_STREAMID_OVERRIDE_CFG_ISPWA		0x230U
+#define MC_STREAMID_OVERRIDE_CFG_ISPWB		0x238U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR	0x250U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW	0x258U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR	0x260U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW	0x268U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSRD	0x2A0U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSWR	0x2A8U
+#define MC_STREAMID_OVERRIDE_CFG_GPUSRD		0x2C0U
+#define MC_STREAMID_OVERRIDE_CFG_GPUSWR		0x2C8U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA	0x300U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA	0x308U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCR		0x310U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB	0x318U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA	0x320U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA	0x328U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCW		0x330U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB	0x338U
+#define MC_STREAMID_OVERRIDE_CFG_VICSRD		0x360U
+#define MC_STREAMID_OVERRIDE_CFG_VICSWR		0x368U
+#define MC_STREAMID_OVERRIDE_CFG_VIW		0x390U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD	0x3C0U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR	0x3C8U
+#define MC_STREAMID_OVERRIDE_CFG_APER		0x3D0U
+#define MC_STREAMID_OVERRIDE_CFG_APEW		0x3D8U
+#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD	0x3F0U
+#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR	0x3F8U
+#define MC_STREAMID_OVERRIDE_CFG_SESRD		0x400U
+#define MC_STREAMID_OVERRIDE_CFG_SESWR		0x408U
+#define MC_STREAMID_OVERRIDE_CFG_ETRR		0x420U
+#define MC_STREAMID_OVERRIDE_CFG_ETRW		0x428U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB	0x430U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB	0x438U
+#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2	0x440U
+#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2	0x448U
+#define MC_STREAMID_OVERRIDE_CFG_AXISR		0x460U
+#define MC_STREAMID_OVERRIDE_CFG_AXISW		0x468U
+#define MC_STREAMID_OVERRIDE_CFG_EQOSR		0x470U
+#define MC_STREAMID_OVERRIDE_CFG_EQOSW		0x478U
+#define MC_STREAMID_OVERRIDE_CFG_UFSHCR		0x480U
+#define MC_STREAMID_OVERRIDE_CFG_UFSHCW		0x488U
+#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR	0x490U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPR		0x498U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPW		0x4A0U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR	0x4A8U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW	0x4B0U
+#define MC_STREAMID_OVERRIDE_CFG_AONR		0x4B8U
+#define MC_STREAMID_OVERRIDE_CFG_AONW		0x4C0U
+#define MC_STREAMID_OVERRIDE_CFG_AONDMAR	0x4C8U
+#define MC_STREAMID_OVERRIDE_CFG_AONDMAW	0x4D0U
+#define MC_STREAMID_OVERRIDE_CFG_SCER		0x4D8U
+#define MC_STREAMID_OVERRIDE_CFG_SCEW		0x4E0U
+#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR	0x4E8U
+#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW	0x4F0U
+#define MC_STREAMID_OVERRIDE_CFG_APEDMAR	0x4F8U
+#define MC_STREAMID_OVERRIDE_CFG_APEDMAW	0x500U
+#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1	0x508U
+#define MC_STREAMID_OVERRIDE_CFG_VICSRD1	0x510U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1	0x518U
 
 /*******************************************************************************
  * Macro to calculate Security cfg register addr from StreamID Override register
  ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + sizeof(uint32_t))
+#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
 
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV		(0UL << 4)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV	(1UL << 4)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV		(2UL << 4)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV	(3UL << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV		(0U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV	(1U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV		(2U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV	(3U << 4)
 
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL		(0UL << 8)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL	(1UL << 8)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL		(2UL << 8)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL	(3UL << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL		(0U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL	(1U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL		(2U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL	(3U << 8)
 
-#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO				(0UL << 12)
-#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID		(1UL << 12)
+#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO				(0U << 12)
+#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID		(1U << 12)
 
 /*******************************************************************************
  * Memory Controller transaction override config registers
  ******************************************************************************/
-#define MC_TXN_OVERRIDE_CONFIG_HDAR		0x10a8
-#define MC_TXN_OVERRIDE_CONFIG_BPMPW		0x14a0
-#define MC_TXN_OVERRIDE_CONFIG_PTCR		0x1000
-#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR	0x1490
-#define MC_TXN_OVERRIDE_CONFIG_EQOSW		0x1478
-#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR		0x13f8
-#define MC_TXN_OVERRIDE_CONFIG_ISPRA		0x1220
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA		0x1328
-#define MC_TXN_OVERRIDE_CONFIG_VICSRD		0x1360
-#define MC_TXN_OVERRIDE_CONFIG_MPCOREW		0x11c8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSRD		0x12c0
-#define MC_TXN_OVERRIDE_CONFIG_AXISR		0x1460
-#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW		0x14f0
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCW		0x1330
-#define MC_TXN_OVERRIDE_CONFIG_EQOSR		0x1470
-#define MC_TXN_OVERRIDE_CONFIG_APEDMAR		0x14f8
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD		0x10e0
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB		0x1318
-#define MC_TXN_OVERRIDE_CONFIG_VICSRD1		0x1510
-#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR		0x14a8
-#define MC_TXN_OVERRIDE_CONFIG_VIW		0x1390
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA		0x1308
-#define MC_TXN_OVERRIDE_CONFIG_AXISW		0x1468
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR	0x1260
-#define MC_TXN_OVERRIDE_CONFIG_UFSHCR		0x1480
-#define MC_TXN_OVERRIDE_CONFIG_TSECSWR		0x12a8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSWR		0x12c8
-#define MC_TXN_OVERRIDE_CONFIG_SATAR		0x10f8
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW	0x1258
-#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB		0x1438
-#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2		0x1440
-#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR		0x14e8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2		0x1448
-#define MC_TXN_OVERRIDE_CONFIG_AONDMAW		0x14d0
-#define MC_TXN_OVERRIDE_CONFIG_APEDMAW		0x1500
-#define MC_TXN_OVERRIDE_CONFIG_AONW		0x14c0
-#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR	0x10b0
-#define MC_TXN_OVERRIDE_CONFIG_ETRR		0x1420
-#define MC_TXN_OVERRIDE_CONFIG_SESWR		0x1408
-#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD		0x13f0
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD		0x13c0
-#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB		0x1430
-#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW		0x14b0
-#define MC_TXN_OVERRIDE_CONFIG_APER		0x13d0
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1	0x1518
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR	0x1250
-#define MC_TXN_OVERRIDE_CONFIG_ISPWA		0x1230
-#define MC_TXN_OVERRIDE_CONFIG_SESRD		0x1400
-#define MC_TXN_OVERRIDE_CONFIG_SCER		0x14d8
-#define MC_TXN_OVERRIDE_CONFIG_AONR		0x14b8
-#define MC_TXN_OVERRIDE_CONFIG_MPCORER		0x1138
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA		0x1320
-#define MC_TXN_OVERRIDE_CONFIG_HDAW		0x11a8
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR		0x13c8
-#define MC_TXN_OVERRIDE_CONFIG_UFSHCW		0x1488
-#define MC_TXN_OVERRIDE_CONFIG_AONDMAR		0x14c8
-#define MC_TXN_OVERRIDE_CONFIG_SATAW		0x11e8
-#define MC_TXN_OVERRIDE_CONFIG_ETRW		0x1428
-#define MC_TXN_OVERRIDE_CONFIG_VICSWR		0x1368
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR		0x1158
-#define MC_TXN_OVERRIDE_CONFIG_AFIR		0x1070
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB		0x1338
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA		0x1300
-#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1	0x1508
-#define MC_TXN_OVERRIDE_CONFIG_ISPWB		0x1238
-#define MC_TXN_OVERRIDE_CONFIG_BPMPR		0x1498
-#define MC_TXN_OVERRIDE_CONFIG_APEW		0x13d8
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCR		0x1310
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW	0x1268
-#define MC_TXN_OVERRIDE_CONFIG_TSECSRD		0x12a0
-#define MC_TXN_OVERRIDE_CONFIG_AFIW		0x1188
-#define MC_TXN_OVERRIDE_CONFIG_SCEW		0x14e0
+#define MC_TXN_OVERRIDE_CONFIG_HDAR		0x10a8U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPW		0x14a0U
+#define MC_TXN_OVERRIDE_CONFIG_PTCR		0x1000U
+#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR	0x1490U
+#define MC_TXN_OVERRIDE_CONFIG_EQOSW		0x1478U
+#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR		0x13f8U
+#define MC_TXN_OVERRIDE_CONFIG_ISPRA		0x1220U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA		0x1328U
+#define MC_TXN_OVERRIDE_CONFIG_VICSRD		0x1360U
+#define MC_TXN_OVERRIDE_CONFIG_MPCOREW		0x11c8U
+#define MC_TXN_OVERRIDE_CONFIG_GPUSRD		0x12c0U
+#define MC_TXN_OVERRIDE_CONFIG_AXISR		0x1460U
+#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW		0x14f0U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCW		0x1330U
+#define MC_TXN_OVERRIDE_CONFIG_EQOSR		0x1470U
+#define MC_TXN_OVERRIDE_CONFIG_APEDMAR		0x14f8U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD		0x10e0U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB		0x1318U
+#define MC_TXN_OVERRIDE_CONFIG_VICSRD1		0x1510U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR		0x14a8U
+#define MC_TXN_OVERRIDE_CONFIG_VIW		0x1390U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA		0x1308U
+#define MC_TXN_OVERRIDE_CONFIG_AXISW		0x1468U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR	0x1260U
+#define MC_TXN_OVERRIDE_CONFIG_UFSHCR		0x1480U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSWR		0x12a8U
+#define MC_TXN_OVERRIDE_CONFIG_GPUSWR		0x12c8U
+#define MC_TXN_OVERRIDE_CONFIG_SATAR		0x10f8U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW	0x1258U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB		0x1438U
+#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2		0x1440U
+#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR		0x14e8U
+#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2		0x1448U
+#define MC_TXN_OVERRIDE_CONFIG_AONDMAW		0x14d0U
+#define MC_TXN_OVERRIDE_CONFIG_APEDMAW		0x1500U
+#define MC_TXN_OVERRIDE_CONFIG_AONW		0x14c0U
+#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR	0x10b0U
+#define MC_TXN_OVERRIDE_CONFIG_ETRR		0x1420U
+#define MC_TXN_OVERRIDE_CONFIG_SESWR		0x1408U
+#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD		0x13f0U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD		0x13c0U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB		0x1430U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW		0x14b0U
+#define MC_TXN_OVERRIDE_CONFIG_APER		0x13d0U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1	0x1518U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR	0x1250U
+#define MC_TXN_OVERRIDE_CONFIG_ISPWA		0x1230U
+#define MC_TXN_OVERRIDE_CONFIG_SESRD		0x1400U
+#define MC_TXN_OVERRIDE_CONFIG_SCER		0x14d8U
+#define MC_TXN_OVERRIDE_CONFIG_AONR		0x14b8U
+#define MC_TXN_OVERRIDE_CONFIG_MPCORER		0x1138U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA		0x1320U
+#define MC_TXN_OVERRIDE_CONFIG_HDAW		0x11a8U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR		0x13c8U
+#define MC_TXN_OVERRIDE_CONFIG_UFSHCW		0x1488U
+#define MC_TXN_OVERRIDE_CONFIG_AONDMAR		0x14c8U
+#define MC_TXN_OVERRIDE_CONFIG_SATAW		0x11e8U
+#define MC_TXN_OVERRIDE_CONFIG_ETRW		0x1428U
+#define MC_TXN_OVERRIDE_CONFIG_VICSWR		0x1368U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR		0x1158U
+#define MC_TXN_OVERRIDE_CONFIG_AFIR		0x1070U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB		0x1338U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA		0x1300U
+#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1	0x1508U
+#define MC_TXN_OVERRIDE_CONFIG_ISPWB		0x1238U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPR		0x1498U
+#define MC_TXN_OVERRIDE_CONFIG_APEW		0x13d8U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCR		0x1310U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW	0x1268U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSRD		0x12a0U
+#define MC_TXN_OVERRIDE_CONFIG_AFIW		0x1188U
+#define MC_TXN_OVERRIDE_CONFIG_SCEW		0x14e0U
 
 /*******************************************************************************
  * Structure to hold the transaction override settings to use to override
@@ -223,12 +223,12 @@
 	int override_client_ns_flag;
 } mc_streamid_security_cfg_t;
 
-#define OVERRIDE_DISABLE				1
-#define OVERRIDE_ENABLE					0
-#define CLIENT_FLAG_SECURE				0
-#define CLIENT_FLAG_NON_SECURE				1
-#define CLIENT_INPUTS_OVERRIDE				1
-#define CLIENT_INPUTS_NO_OVERRIDE			0
+#define OVERRIDE_DISABLE				1U
+#define OVERRIDE_ENABLE					0U
+#define CLIENT_FLAG_SECURE				0U
+#define CLIENT_FLAG_NON_SECURE				1U
+#define CLIENT_INPUTS_OVERRIDE				1U
+#define CLIENT_INPUTS_NO_OVERRIDE			0U
 
 #define mc_make_sec_cfg(off, ns, ovrrd, access) \
 	{ \
@@ -257,70 +257,70 @@
 /*******************************************************************************
  * Memory Controller SMMU Bypass config register
  ******************************************************************************/
-#define MC_SMMU_BYPASS_CONFIG			0x1820
-#define MC_SMMU_BYPASS_CTRL_MASK		0x3
-#define MC_SMMU_BYPASS_CTRL_SHIFT		0
-#define MC_SMMU_CTRL_TBU_BYPASS_ALL		(0 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_RSVD			(1 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID	(2 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_BYPASS_NONE		(3 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT	(1 << 31)
+#define MC_SMMU_BYPASS_CONFIG			0x1820U
+#define MC_SMMU_BYPASS_CTRL_MASK		0x3U
+#define MC_SMMU_BYPASS_CTRL_SHIFT		0U
+#define MC_SMMU_CTRL_TBU_BYPASS_ALL		(0U << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_RSVD			(1U << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID	(2U << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_BYPASS_NONE		(3U << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT	(1U << 31)
 #define MC_SMMU_BYPASS_CONFIG_SETTINGS		(MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
 						 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
 
-#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID	(1 << 0)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV	(2 << 4)
-#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT	(1 << 12)
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID	(1U << 0)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV	(2U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT	(1U << 12)
 
 /*******************************************************************************
  * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
  * MC_TXN_OVERRIDE_CONFIG_{module} registers
  ******************************************************************************/
-#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT	0
-#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID	1
-#define MC_TXN_OVERRIDE_CGID_TAG_ZERO		2
-#define MC_TXN_OVERRIDE_CGID_TAG_ADR		3
-#define MC_TXN_OVERRIDE_CGID_TAG_MASK		3
+#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT	0U
+#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID	1U
+#define MC_TXN_OVERRIDE_CGID_TAG_ZERO		2U
+#define MC_TXN_OVERRIDE_CGID_TAG_ADR		3U
+#define MC_TXN_OVERRIDE_CGID_TAG_MASK		3U
 
 /*******************************************************************************
  * Memory Controller Reset Control registers
  ******************************************************************************/
-#define MC_CLIENT_HOTRESET_CTRL0			0x200
-#define  MC_CLIENT_HOTRESET_CTRL0_RESET_VAL		0
-#define  MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB		(1 << 0)
-#define  MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB		(1 << 6)
-#define  MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB		(1 << 7)
-#define  MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB	(1 << 8)
-#define  MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB	(1 << 9)
-#define  MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB	(1 << 11)
-#define  MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB	(1 << 15)
-#define  MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB		(1 << 17)
-#define  MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB		(1 << 18)
-#define  MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB	(1 << 19)
-#define  MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB	(1 << 20)
-#define  MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB	(1 << 22)
-#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB	(1 << 29)
-#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB	(1 << 30)
-#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB	(1 << 31)
-#define MC_CLIENT_HOTRESET_STATUS0			0x204
-#define MC_CLIENT_HOTRESET_CTRL1			0x970
-#define  MC_CLIENT_HOTRESET_CTRL1_RESET_VAL		0
-#define  MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB	(1 << 0)
-#define  MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB		(1 << 2)
-#define  MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB	(1 << 5)
-#define  MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB		(1 << 6)
-#define  MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB		(1 << 7)
-#define  MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB	(1 << 8)
-#define  MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB		(1 << 12)
-#define  MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB	(1 << 13)
-#define  MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB	(1 << 18)
-#define  MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB	(1 << 19)
-#define  MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB	(1 << 20)
-#define  MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB	(1 << 21)
-#define  MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB	(1 << 22)
-#define  MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB		(1 << 23)
-#define  MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB		(1 << 24)
-#define MC_CLIENT_HOTRESET_STATUS1			0x974
+#define MC_CLIENT_HOTRESET_CTRL0			0x200U
+#define  MC_CLIENT_HOTRESET_CTRL0_RESET_VAL		0U
+#define  MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB		(1U << 0)
+#define  MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB		(1U << 6)
+#define  MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB		(1U << 7)
+#define  MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB	(1U << 8)
+#define  MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB	(1U << 9)
+#define  MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB	(1U << 11)
+#define  MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB	(1U << 15)
+#define  MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB		(1U << 17)
+#define  MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB		(1U << 18)
+#define  MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB	(1U << 19)
+#define  MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB	(1U << 20)
+#define  MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB	(1U << 22)
+#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB	(1U << 29)
+#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB	(1U << 30)
+#define  MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB	(1U << 31)
+#define MC_CLIENT_HOTRESET_STATUS0			0x204U
+#define MC_CLIENT_HOTRESET_CTRL1			0x970U
+#define  MC_CLIENT_HOTRESET_CTRL1_RESET_VAL		0U
+#define  MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB	(1U << 0)
+#define  MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB		(1U << 2)
+#define  MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB	(1U << 5)
+#define  MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB		(1U << 6)
+#define  MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB		(1U << 7)
+#define  MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB	(1U << 8)
+#define  MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB		(1U << 12)
+#define  MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB	(1U << 13)
+#define  MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB	(1U << 18)
+#define  MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB	(1U << 19)
+#define  MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB	(1U << 20)
+#define  MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB	(1U << 21)
+#define  MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB	(1U << 22)
+#define  MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB		(1U << 23)
+#define  MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB		(1U << 24)
+#define MC_CLIENT_HOTRESET_STATUS1			0x974U
 
 /*******************************************************************************
  * Memory Controller's PCFIFO client configuration registers
@@ -396,7 +396,7 @@
 }
 
 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
-	(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
+	((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
 	 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
 
 #define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h
index 0f38e3d..41b0c51 100644
--- a/plat/nvidia/tegra/include/drivers/smmu.h
+++ b/plat/nvidia/tegra/include/drivers/smmu.h
@@ -586,12 +586,12 @@
 /*******************************************************************************
  * SMMU Global Aux. Control Register
  ******************************************************************************/
-#define SMMU_CBn_ACTLR_CPRE_BIT			(1UL << 1UL)
+#define SMMU_CBn_ACTLR_CPRE_BIT			(1ULL << 1U)
 
 /*******************************************************************************
  * SMMU configuration constants
  ******************************************************************************/
-#define ID1_PAGESIZE				(1U << 31)
+#define ID1_PAGESIZE				(1U << 31U)
 #define ID1_NUMPAGENDXB_SHIFT			28U
 #define ID1_NUMPAGENDXB_MASK			7U
 #define ID1_NUMS2CB_SHIFT			16U
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 4cc7802..19d1250 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -118,7 +118,7 @@
 /*******************************************************************************
  * Tegra General Purpose Centralised DMA constants
  ******************************************************************************/
-#define TEGRA_GPCDMA_BASE		U(0x2610000)
+#define TEGRA_GPCDMA_BASE		ULL(0x2610000)
 
 /*******************************************************************************
  * Tegra Memory Controller constants
diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index ee76b66..e621050 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -164,7 +164,7 @@
 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64c)
 
 /* SMMU configuration registers*/
-#define MC_SMMU_PPCS_ASID_0		0x270UL
+#define MC_SMMU_PPCS_ASID_0		0x270U
 #define  PPCS_SMMU_ENABLE		(0x1U << 31)
 
 /*******************************************************************************