commit 0de6e53b9270e01ec69b52a31e4a1d045dec893f
author Pritesh Raithatha <praithatha@nvidia.com> Tue Jan 24 13:49:46 2017 +0530
committer Varun Wadekar <vwadekar@nvidia.com> Thu Apr 13 12:35:14 2017 -0700
tree 40e702d54955b685b900f1e0ea8ae401fe677968
parent c88654f16236b5b0e4d7ea7b1b9bf75fe3f08502

Tegra: smmu: support for multiple devices

This patch adds flexibility to the code to initialise multiple SMMU
devices. The base address macro name has been changed to make it
explicit that we support multiple SMMUs.

Change-Id: Id4854fb010ebeb699512d79c769de24050c2ad69
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/include/drivers/smmu.h

diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h
index a59b06b..61ad5f0 100644
--- a/plat/nvidia/tegra/include/drivers/smmu.h
+++ b/plat/nvidia/tegra/include/drivers/smmu.h
@@ -643,7 +643,7 @@
 
 #define smmu_make_gnsr0_sec_cfg(name) \
 	{ \
-		.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_ ## name, \
+		.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_ ## name, \
 		.val = 0x00000000, \
 	}
 
@@ -653,37 +653,37 @@
  */
 #define smmu_make_gnsr0_nsec_cfg(name) \
 	{ \
-		.reg = TEGRA_SMMU_BASE + 0x400 + SMMU_GNSR0_ ## name, \
+		.reg = TEGRA_SMMU0_BASE + 0x400 + SMMU_GNSR0_ ## name, \
 		.val = 0x00000000, \
 	}
 
 #define smmu_make_gnsr0_smr_cfg(n) \
 	{ \
-		.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_SMR ## n, \
+		.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_SMR ## n, \
 		.val = 0x00000000, \
 	}
 
 #define smmu_make_gnsr0_s2cr_cfg(n) \
 	{ \
-		.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_S2CR ## n, \
+		.reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_S2CR ## n, \
 		.val = 0x00000000, \
 	}
 
 #define smmu_make_gnsr1_cbar_cfg(n) \
 	{ \
-		.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
+		.reg = TEGRA_SMMU0_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
 		.val = 0x00000000, \
 	}
 
 #define smmu_make_gnsr1_cba2r_cfg(n) \
 	{ \
-		.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
+		.reg = TEGRA_SMMU0_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
 		.val = 0x00000000, \
 	}
 
 #define make_smmu_cb_cfg(name, n) \
 	{ \
-		.reg = TEGRA_SMMU_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
+		.reg = TEGRA_SMMU0_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
 			+ SMMU_CBn_ ## name, \
 		.val = 0x00000000, \
 	}