Merge changes I54d18f01,I4e06c8a7,Ib5fc7dcd,Id5db5558,Ib941a04a into integration
* changes:
feat(st): adapt .stm32 file creation for clang
feat(st): adapt stm32 linker scripts for clang
feat(st): update stm32 linker scripts
fix(st): mark INCBIN-generated sections as SHF_ALLOC
feat(st): remove unsupported option for clang
diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..6a89eeb
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,199 @@
+---
+AccessModifierOffset: -4
+AlignAfterOpenBracket: Align
+AlignArrayOfStructures: None
+AlignConsecutiveMacros: None
+AlignConsecutiveAssignments: None
+AlignConsecutiveBitFields: None
+AlignConsecutiveDeclarations: None
+AlignEscapedNewlines: Left
+AlignOperands: Align
+AlignTrailingComments: false
+AllowAllArgumentsOnNextLine: true
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortEnumsOnASingleLine: true
+AllowShortBlocksOnASingleLine: Never
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortFunctionsOnASingleLine: None
+AllowShortLambdasOnASingleLine: All
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterDefinitionReturnType: None
+AlwaysBreakAfterReturnType: None
+AlwaysBreakBeforeMultilineStrings: false
+AlwaysBreakTemplateDeclarations: MultiLine
+AttributeMacros:
+ - __capability
+BinPackArguments: true
+BinPackParameters: true
+BraceWrapping:
+ AfterCaseLabel: false
+ AfterClass: false
+ AfterControlStatement: Never
+ AfterEnum: false
+ AfterFunction: true
+ AfterNamespace: true
+ AfterObjCDeclaration: false
+ AfterStruct: false
+ AfterUnion: false
+ AfterExternBlock: false
+ BeforeCatch: false
+ BeforeElse: false
+ BeforeLambdaBody: false
+ BeforeWhile: false
+ IndentBraces: false
+ SplitEmptyFunction: true
+ SplitEmptyRecord: true
+ SplitEmptyNamespace: true
+BreakBeforeBinaryOperators: None
+BreakBeforeConceptDeclarations: true
+BreakBeforeBraces: Custom
+BreakBeforeInheritanceComma: false
+BreakInheritanceList: BeforeColon
+BreakBeforeTernaryOperators: false
+BreakConstructorInitializersBeforeComma: false
+BreakConstructorInitializers: BeforeComma
+BreakAfterJavaFieldAnnotations: false
+BreakStringLiterals: false
+ColumnLimit: 80
+CommentPragmas: '^ IWYU pragma:'
+QualifierAlignment: Leave
+CompactNamespaces: false
+ConstructorInitializerIndentWidth: 8
+ContinuationIndentWidth: 8
+Cpp11BracedListStyle: false
+DeriveLineEnding: true
+DerivePointerAlignment: false
+DisableFormat: false
+EmptyLineAfterAccessModifier: Never
+EmptyLineBeforeAccessModifier: LogicalBlock
+ExperimentalAutoDetectBinPacking: false
+PackConstructorInitializers: BinPack
+BasedOnStyle: ''
+ConstructorInitializerAllOnOneLineOrOnePerLine: false
+AllowAllConstructorInitializersOnNextLine: true
+FixNamespaceComments: false
+ForEachMacros:
+ - fdt_for_each_compatible_node
+ - fdt_for_each_property_offset
+ - fdt_for_each_subnode
+ - for_each_err_record_info
+ - for_each_subscriber
+IfMacros:
+ - KJ_IF_MAYBE
+IncludeBlocks: Regroup
+IncludeCategories:
+ - Regex: '^<(assert|complex|ctype|errno|fenv|float|inttypes|iso646|limits|locale|math|setjmp|signal|stdalign|stdarg|stdatomic|stdbool|stdckdint|stddef|stdint|stdio|stdlib|stdnoreturn|string|tgmath|threads|time|uchar|wchar|wctype)\.h>$'
+ Priority: 0
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^<lib/(compiler-rt|libfdt|mbedtls|zlib)/.+>$'
+ Priority: 1
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^<(platform(_def)?\.h)|(plat[_/].+)>$'
+ Priority: 2
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^<.+>$'
+ Priority: 3
+ SortPriority: 0
+ CaseSensitive: false
+ - Regex: '^".+"$'
+ Priority: 4
+ SortPriority: 0
+ CaseSensitive: false
+IncludeIsMainRegex: '(Test)?$'
+IncludeIsMainSourceRegex: ''
+IndentAccessModifiers: false
+IndentCaseLabels: false
+IndentCaseBlocks: false
+IndentGotoLabels: false
+IndentPPDirectives: None
+IndentExternBlock: AfterExternBlock
+IndentRequires: false
+IndentWidth: 8
+IndentWrappedFunctionNames: false
+InsertTrailingCommas: None
+JavaScriptQuotes: Leave
+JavaScriptWrapImports: true
+KeepEmptyLinesAtTheStartOfBlocks: false
+LambdaBodyIndentation: Signature
+MacroBlockBegin: ''
+MacroBlockEnd: ''
+MaxEmptyLinesToKeep: 1
+NamespaceIndentation: None
+ObjCBinPackProtocolList: Auto
+ObjCBlockIndentWidth: 8
+ObjCBreakBeforeNestedBlockParam: true
+ObjCSpaceAfterProperty: true
+ObjCSpaceBeforeProtocolList: true
+PenaltyBreakAssignment: 10
+PenaltyBreakBeforeFirstCallParameter: 30
+PenaltyBreakComment: 10
+PenaltyBreakFirstLessLess: 0
+PenaltyBreakOpenParenthesis: 0
+PenaltyBreakString: 10
+PenaltyBreakTemplateDeclaration: 10
+PenaltyExcessCharacter: 100
+PenaltyReturnTypeOnItsOwnLine: 60
+PenaltyIndentedWhitespace: 0
+PointerAlignment: Right
+PPIndentWidth: -1
+ReferenceAlignment: Pointer
+ReflowComments: false
+RemoveBracesLLVM: false
+SeparateDefinitionBlocks: Leave
+ShortNamespaceLines: 1
+SortIncludes: CaseInsensitive
+SortJavaStaticImport: Before
+SortUsingDeclarations: false
+SpaceAfterCStyleCast: false
+SpaceAfterLogicalNot: false
+SpaceAfterTemplateKeyword: true
+SpaceBeforeAssignmentOperators: true
+SpaceBeforeCaseColon: false
+SpaceBeforeCpp11BracedList: false
+SpaceBeforeCtorInitializerColon: true
+SpaceBeforeInheritanceColon: true
+SpaceBeforeParens: ControlStatementsExceptControlMacros
+SpaceBeforeParensOptions:
+ AfterControlStatements: true
+ AfterForeachMacros: false
+ AfterFunctionDefinitionName: false
+ AfterFunctionDeclarationName: false
+ AfterIfMacros: false
+ AfterOverloadedOperator: false
+ BeforeNonEmptyParentheses: false
+SpaceAroundPointerQualifiers: Default
+SpaceBeforeRangeBasedForLoopColon: true
+SpaceInEmptyBlock: false
+SpaceInEmptyParentheses: false
+SpacesBeforeTrailingComments: 1
+SpacesInAngles: Never
+SpacesInConditionalStatement: false
+SpacesInContainerLiterals: false
+SpacesInCStyleCastParentheses: false
+SpacesInLineCommentPrefix:
+ Minimum: 1
+ Maximum: -1
+SpacesInParentheses: false
+SpacesInSquareBrackets: false
+SpaceBeforeSquareBrackets: false
+BitFieldColonSpacing: Both
+Standard: c++03
+StatementAttributeLikeMacros:
+ - Q_EMIT
+StatementMacros:
+ - Q_UNUSED
+ - QT_REQUIRE_VERSION
+TabWidth: 8
+UseCRLF: false
+UseTab: Always
+WhitespaceSensitiveMacros:
+ - STRINGIZE
+ - PP_STRINGIZE
+ - BOOST_PP_STRINGIZE
+ - NS_SWIFT_NAME
+ - CF_SWIFT_NAME
+...
diff --git a/Makefile b/Makefile
index 6d5a0c3..75eeaee 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 2
-VERSION_MINOR := 12
+VERSION_MINOR := 13
# VERSION_PATCH is only used for LTS releases
VERSION_PATCH := 0
VERSION := ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
@@ -546,31 +546,6 @@
BL_COMMON_SOURCES += lib/extensions/pauth/pauth.c
endif
-####################################################
-# Enable required options for Memory Stack Tagging.
-####################################################
-
-# Currently, these options are enabled only for clang and armclang compiler.
-ifeq (${SUPPORT_STACK_MEMTAG},yes)
- ifdef mem_tag_arch_support
- # Check for armclang and clang compilers
- ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
- # Add "memtag" architecture feature modifier if not specified
- ifeq ( ,$(findstring memtag,$(arch-features)))
- arch-features := $(arch-features)+memtag
- endif # memtag
- ifeq ($($(ARCH)-cc-id),arm-clang)
- TF_CFLAGS += -mmemtag-stack
- else ifeq ($($(ARCH)-cc-id),llvm-clang)
- TF_CFLAGS += -fsanitize=memtag
- endif # armclang
- endif
- else
- $(error "Error: stack memory tagging is not supported for \
- architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
- endif #(mem_tag_arch_support)
-endif #(SUPPORT_STACK_MEMTAG)
-
################################################################################
# RME dependent flags configuration, Enable optional features for RME.
################################################################################
@@ -652,7 +627,7 @@
################################################################################
include ${MAKE_HELPERS_DIRECTORY}march.mk
-TF_CFLAGS += $(march-directive)
+TF_CFLAGS += $(march-directive)
ASFLAGS += $(march-directive)
# This internal flag is common option which is set to 1 for scenarios
@@ -938,6 +913,34 @@
endif
endif #(CTX_INCLUDE_PAUTH_REGS)
+# Check ENABLE_FEAT_PAUTH_LR
+ifneq (${ENABLE_FEAT_PAUTH_LR},0)
+
+# Make sure PAUTH is enabled
+ifeq (${ENABLE_PAUTH},0)
+ $(error Error: PAUTH_LR cannot be used without PAUTH (see BRANCH_PROTECTION))
+endif
+
+# Make sure SCTLR2 is enabled
+ifeq (${ENABLE_FEAT_SCTLR2},0)
+ $(error Error: PAUTH_LR cannot be used without ENABLE_FEAT_SCTLR2)
+endif
+
+# FEAT_PAUTH_LR is only supported in aarch64 state
+ifneq (${ARCH},aarch64)
+ $(error ENABLE_FEAT_PAUTH_LR requires AArch64)
+endif
+
+# Currently, FEAT_PAUTH_LR is only supported by arm/clang compilers
+# TODO implement for GCC when support is added
+ifeq ($($(ARCH)-cc-id),arm-clang)
+ arch-features := $(arch-features)+pauth-lr
+else
+ $(error Error: ENABLE_FEAT_PAUTH_LR not supported for GCC compiler)
+endif
+
+endif # ${ENABLE_FEAT_PAUTH_LR}
+
ifeq ($(FEATURE_DETECTION),1)
$(info FEATURE_DETECTION is an experimental feature)
endif #(FEATURE_DETECTION)
@@ -984,7 +987,7 @@
endif
# FEAT_RNG_TRAP is not supported in AArch32
- ifeq (${ENABLE_FEAT_RNG_TRAP},1)
+ ifneq (${ENABLE_FEAT_RNG_TRAP},0)
$(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32")
endif
@@ -1324,6 +1327,7 @@
ENABLE_TRBE_FOR_NS \
ENABLE_BTI \
ENABLE_PAUTH \
+ ENABLE_FEAT_PAUTH_LR \
ENABLE_FEAT_AMU \
ENABLE_FEAT_AMUv1p1 \
ENABLE_FEAT_CSV2_2 \
@@ -1410,6 +1414,7 @@
ENABLE_FEAT_DEBUGV8P9 \
ENABLE_FEAT_MPAM \
ENABLE_PAUTH \
+ ENABLE_FEAT_PAUTH_LR \
ENABLE_PIE \
ENABLE_PMF \
ENABLE_PSCI_STAT \
@@ -1831,7 +1836,8 @@
doc:
$(s)echo " BUILD DOCUMENTATION"
- $(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
+ $(if $(host-poetry),$(q)poetry -q install --with docs --no-root)
+ $(q)$(if $(host-poetry),poetry run )${MAKE} --no-print-directory -C ${DOCS_PATH} html
enctool: ${ENCTOOL}
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index db14ec6..fba9102 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -134,6 +134,8 @@
/* Teardown the measured boot driver */
bl1_plat_mboot_finish();
+ crypto_mod_finish();
+
bl1_prepare_next_image(image_id);
#if ENABLE_RUNTIME_INSTRUMENTATION
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index dbe9453..8ca7143 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -110,6 +110,8 @@
/* Teardown the Measured Boot backend */
bl2_plat_mboot_finish();
+ crypto_mod_finish();
+
#if !BL2_RUNS_AT_EL3
#ifndef __aarch64__
/*
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index 984fdaa..114a57d 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -90,19 +90,17 @@
* Explicitly create all bits of SPSR to get PSTATE at exception return.
*
* The code is based on "Aarch64.exceptions.takeexception" described in
- * DDI0602 revision 2023-06.
- * "https://developer.arm.com/documentation/ddi0602/2023-06/Shared-Pseudocode/
+ * DDI0602 revision 2025-03.
+ * "https://developer.arm.com/documentation/ddi0597/2025-03/Shared-Pseudocode/
* aarch64-exceptions-takeexception"
*
- * NOTE: This piece of code must be reviewed every release to ensure that
- * we keep up with new ARCH features which introduces a new SPSR bit.
+ * NOTE: This piece of code must be reviewed every release against the latest
+ * takeexception sequence to ensure that we keep up with new arch features that
+ * affect the PSTATE.
*
- * TF-A 2.12 release review
- * The latest version available is 2024-09, which has two extra features which
- * impacts generation of SPSR, since these features are not implemented in TF-A
- * at the time of release, just log the feature names here to be taken up when
- * feature support is introduced.
- * - FEAT_PAuth_LR (2023 extension)
+ * TF-A 2.13 release review
+ *
+ * Review of version 2025-03 indicates we are missing support for one feature.
* - FEAT_UINJ (2024 extension)
*/
u_register_t create_spsr(u_register_t old_spsr, unsigned int target_el)
@@ -204,6 +202,12 @@
new_spsr |= (gcscr & GCSCR_EXLOCK_EN_BIT) ? SPSR_EXLOCK_BIT_AARCH64 : 0;
}
+ /* If FEAT_PAUTH_LR present then zero the PACM bit. */
+ new_spsr |= old_spsr & SPSR_PACM_BIT_AARCH64;
+ if (is_feat_pauth_lr_present()) {
+ new_spsr &= ~SPSR_PACM_BIT_AARCH64;
+ }
+
return new_spsr;
}
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index b4e7a7a..4ea2f5b 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -51,6 +51,15 @@
.endm
func tsp_entrypoint _align=3
+ /*---------------------------------------------
+ * Save arguments x0 - x3 from BL1 for future
+ * use.
+ * ---------------------------------------------
+ */
+ mov x20, x0
+ mov x21, x1
+ mov x22, x2
+ mov x23, x3
#if ENABLE_PIE
/*
@@ -173,6 +182,16 @@
bl update_stack_protector_canary
#endif
+ /*---------------------------------------------
+ * Save arguments x0 - x3 from prio stage for
+ * future use.
+ * ---------------------------------------------
+ */
+ mov x0, x20
+ mov x1, x21
+ mov x2, x22
+ mov x3, x23
+
/* ---------------------------------------------
* Perform TSP setup
* ---------------------------------------------
diff --git a/bl32/tsp/tsp_common.c b/bl32/tsp/tsp_common.c
index e69c054..144349a 100644
--- a/bl32/tsp/tsp_common.c
+++ b/bl32/tsp/tsp_common.c
@@ -64,13 +64,14 @@
/*******************************************************************************
* Setup function for TSP.
******************************************************************************/
-void tsp_setup(void)
+void tsp_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
+ u_register_t arg3)
{
/* Enable early console if EARLY_CONSOLE flag is enabled */
plat_setup_early_console();
/* Perform early platform-specific setup. */
- tsp_early_platform_setup();
+ tsp_early_platform_setup(arg0, arg1, arg2, arg3);
/* Perform late platform-specific setup. */
tsp_plat_arch_setup();
diff --git a/changelog.yaml b/changelog.yaml
index 6e7f179..3da8af4 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -98,13 +98,16 @@
- d128
- debugv8p9
- fgt2
+ - fpmr
- gcs
- hcx
+ - mops
- mpam
- mte
- mte2
- pauth
- pmu
+ - pmuv3
- rng-trap
- sctlr2
- feat_sctlr2
@@ -135,6 +138,13 @@
deprecated:
- plat/allwinner
+ - title: AMLogic
+ scope: amlogic
+
+ subsections:
+ - title: GXL
+ scope: gxl
+
- title: Arm
scope: arm
@@ -198,6 +208,7 @@
deprecated:
- neoverse
+ - neoverse_rd
- title: TC
scope: tc
@@ -205,13 +216,6 @@
deprecated:
- plat/tc
- subsections:
- - title: TC0
- scope: tc0
-
- deprecated:
- - plat/tc0
-
- title: Corstone-1000
scope: corstone-1000
@@ -308,6 +312,9 @@
- title: MT8188
scope: mt8188
+ - title: MT8189
+ scope: mt8189
+
- title: MT8192
scope: mt8192
@@ -322,6 +329,9 @@
- plat/mediatek/mt8195
- plat/mdeiatek/mt8195
+ - title: MT8196
+ scope: mt8196
+
- title: NVIDIA
scope: nvidia
@@ -555,6 +565,12 @@
scope: rockchip
subsections:
+ - title: PX30
+ scope: px30
+
+ - title: RK3288
+ scope: rk3288
+
- title: RK3399
scope: rk3399
@@ -565,6 +581,9 @@
- title: RK3328
scope: rk3328
+ - title: RK3576
+ scope: rk3576
+
- title: RK3588
scope: rk3588
@@ -602,6 +621,12 @@
scope: stm32mp2
subsections:
+ - title: STM32MP21
+ scope: stm32mp21
+
+ - title: STM32MP23
+ scope: stm32mp23
+
- title: STM32MP25
scope: stm32mp25
@@ -723,6 +748,7 @@
scope: el3-spmc
deprecated:
+ - el3_spmc
- spmc
- title: SPMD
@@ -731,6 +757,9 @@
- title: SPM MM
scope: spm-mm
+ deprecated:
+ - spm_mm
+
- title: DRTM
scope: drtm
@@ -799,6 +828,9 @@
- title: FCONF
scope: fconf
+ - title: HOB
+ scope: hob
+
- title: MPMM
scope: mpmm
@@ -820,6 +852,9 @@
- title: Translation Tables
scope: xlat
+ deprecated:
+ - xlat_tables_v2
+
- title: C Standard Library
scope: libc
@@ -1146,6 +1181,9 @@
- title: Clock
scope: nxp-clk
+ - title: uSDHC
+ scope: nxp-mmc
+
- title: Renesas
scope: renesas-drivers
@@ -1294,31 +1332,43 @@
- fdt
subsections:
- - title: Morello
- scope: morello-fdts
+ - title: Arm
- deprecated:
- - fdts/morello
+ subsections:
+ - title: Morello
+ scope: morello-fdts
- - title: STM32MP1
- scope: stm32mp1-fdts
+ deprecated:
+ - fdts/morello
- deprecated:
- - fdts stm32mp1
+ - title: ST
subsections:
- - title: STM32MP13
- scope: stm32mp13-fdts
+ - title: STM32MP1
+ scope: stm32mp1-fdts
- - title: STM32MP15
- scope: stm32mp15-fdts
+ deprecated:
+ - fdts stm32mp1
- - title: STM32MP2
- scope: stm32mp2-fdts
+ subsections:
+ - title: STM32MP13
+ scope: stm32mp13-fdts
- subsections:
- - title: STM32MP25
- scope: stm32mp25-fdts
+ - title: STM32MP15
+ scope: stm32mp15-fdts
+
+ - title: STM32MP2
+ scope: stm32mp2-fdts
+
+ subsections:
+ - title: STM32MP21
+ scope: stm32mp21-fdts
+
+ - title: STM32MP23
+ scope: stm32mp23-fdts
+
+ - title: STM32MP25
+ scope: stm32mp25-fdts
- title: PIE
scope: pie
@@ -1403,6 +1453,9 @@
scope: tools
subsections:
+ - title: Clang-Format
+ scope: clang-format
+
- title: Dependabot
scope: dependabot
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 4d285d3..2d80b42 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -330,7 +330,7 @@
* revisions so that we catch them as they come along
*/
check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
- "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P8);
+ "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9);
/* v8.1 features */
check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
@@ -429,6 +429,7 @@
/* v9.4 features */
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
+ check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), "PAUTH_LR", 1, 1);
if (tainted) {
panic();
diff --git a/docs/about/lts.rst b/docs/about/lts.rst
index 5aa32a2..593f9dc 100644
--- a/docs/about/lts.rst
+++ b/docs/about/lts.rst
@@ -283,8 +283,9 @@
cherry-pick -x sha1-hash``.
#. Some of the patches of this list may not be taken, mainly due to false
positive. If in doubt, that can be discussed either in the “tf-a-lts” channel
- on Discord or during the LTS weekly meeting. There could also be patches to
- be taken in tf-a-ci-scripts or tf-a-tests.
+ on Discord or during the LTS weekly meeting.
+#. Some dependency patches, not listed in the CSV file, may have to be taken, to ease the
+ application of the LTS patches. This can also be discussed with the other LTS maintainers.
#. Push the stack of changes: ``git push origin
HEAD:refs/for/lts-v2.x%topic=for-lts-v2.x.y+1``. You might need the
``--no-verify`` option: ``git push origin --no-verify
@@ -298,6 +299,13 @@
present, Gerrit will automatically merge the patch. LTS maintainers will then
trigger a Jenkins job that will take care of the release (tag, mail, and
readthedocs update).
+#. Some features may also require updates in other repositories (tf-a-ci-scripts,
+ tf-a-job-configs or tf-a-tests...). For tf-a-job-configs, there are no LTS branches, but
+ dedicated scripts for each LTS version which have to be updated manually. This is the case
+ for e.g. MbedTLS updates. For tf-a-ci-scripts and tf-a-tests, there are LTS branches and patches
+ will be cherry-picked from master branch to the LTS branch the same way it is done for TF-A.
+ There is no automation for those repositories. So the patches will have to be merged manually,
+ and for tf-a-ci-scripts and tf-a-tests, tags will also have to be set manually.
Execution Plan
**************
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index a011297..10b5c16 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -73,8 +73,6 @@
:|G|: `vwadekar`_
:|M|: Yann Gautier <yann.gautier@st.com>
:|G|: `Yann-lms`_
-:|M|: Chris Palmer <palmer@google.com>
-:|G|: `noncombatant`_
:|M|: Govindraj Raja <govindraj.raja@arm.com>
:|G|: `govindraj-arm`_
@@ -113,8 +111,6 @@
:|G|: `ManishVB-Arm`_
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
:|F|: drivers/auth/
Secure Partition Manager Core (EL3 FF-A SPMC)
@@ -226,10 +222,10 @@
^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Michal Simek <michal.simek@amd.com>
:|G|: `michalsimek`_
-:|M|: Amit Nagal <amit.nagal@amd.com>
-:|G|: `amit-nagal`_
:|M|: Akshay Belsare <akshay.belsare@amd.com>
:|G|: `Akshay-Belsare`_
+:|M|: Maheedhar Sai Bollapalli <maheedharsai.bollapalli@amd.com>
+:|G|: `maheedhar-bollapalli`_
:|F|: drivers/arm/dcc/
:|F|: include/drivers/arm/dcc.h
@@ -241,6 +237,8 @@
:|G|: `madhukar-Arm`_
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: lib/psci/
:|F|: include/lib/psci/
@@ -284,6 +282,8 @@
:|G|: `bipinravi-arm`_
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: lib/cpus/
:|F|: include/lib/cpus/
@@ -293,6 +293,8 @@
:|G|: `manish-pandey-arm`_
:|M|: Olivier Deprez <olivier.deprez@arm.com>
:|G|: `odeprez`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: lib/extensions/ras/
Activity Monitors Unit (AMU) extensions
@@ -301,24 +303,32 @@
:|G|: `AlexeiFedorov`_
:|M|: Chris Kay <chris.kay@arm.com>
:|G|: `CJKay`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: lib/extensions/amu/
Memory Partitioning And Monitoring (MPAM) extensions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Manish Pandey <manish.pandey2@arm.com>
:|G|: `manish-pandey-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: lib/extensions/mpam/
Pointer Authentication (PAuth) and Branch Target Identification (BTI) extensions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
:|G|: `AlexeiFedorov`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: lib/extensions/pauth/
Statistical Profiling Extension (SPE)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Manish Pandey <manish.pandey2@arm.com>
:|G|: `manish-pandey-arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: lib/extensions/spe/
Standard C library
@@ -361,6 +371,8 @@
:|G|: `madhukar-Arm`_
:|M|: Olivier Deprez <olivier.deprez@arm.com>
:|G|: `odeprez`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: drivers/arm/gic/
Message Handling Unit (MHU) driver
@@ -399,8 +411,8 @@
:|G|: `sandrine-bailleux-arm`_
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
:|G|: `ManishVB-Arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
+:|M|: Harrison Mutai <harrison.mutai@arm.com>
+:|G|: `harrisonmutai-arm`_
:|F|: drivers/measured_boot
:|F|: include/drivers/measured_boot
:|F|: docs/components/measured_boot
@@ -429,8 +441,8 @@
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
:|G|: `sandrine-bailleux-arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
:|F|: include/lib/psa
:|F|: lib/psa
@@ -475,6 +487,8 @@
:|G|: `manish-pandey-arm`_
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
:|G|: `madhukar-Arm`_
+:|M|: Boyan Karatotev <boyan.karatotev@arm.com>
+:|G|: `loosper-arm`_
:|F|: bl1/aarch32/bl1_context_mgmt.c
:|F|: bl1/aarch64/bl1_context_mgmt.c
:|F|: bl31/bl31_context_mgmt.c
@@ -549,6 +563,8 @@
:|G|: `manish-pandey-arm`_
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
:|G|: `madhukar-Arm`_
+:|M|: Harrison Mutai <harrison.mutai@arm.com>
+:|G|: `harrisonmutai-arm`_
:|F|: plat/arm/board/fvp
Arm Juno Platform port
@@ -912,15 +928,17 @@
:|F|: docs/plat/socionext-uniphier.rst
:|F|: plat/socionext/uniphier/
-Xilinx platform port
-^^^^^^^^^^^^^^^^^^^^
+AMD-Xilinx platform port
+^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Michal Simek <michal.simek@amd.com>
:|G|: `michalsimek`_
-:|M|: Amit Nagal <amit.nagal@amd.com>
-:|G|: `amit-nagal`_
:|M|: Akshay Belsare <akshay.belsare@amd.com>
:|G|: `Akshay-Belsare`_
+:|M|: Maheedhar Sai Bollapalli <maheedharsai.bollapalli@amd.com>
+:|G|: `maheedhar-bollapalli`_
+:|F|: docs/plat/amd\*
:|F|: docs/plat/xilinx\*
+:|F|: plat/amd/
:|F|: plat/xilinx/
@@ -987,8 +1005,6 @@
:|G|: `ManishVB-Arm`_
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
-:|M|: Jimmy Brisson <jimmy.brisson@arm.com>
-:|G|: `jimmy-brisson`_
:|F|: tools/cert_create/
Encrypt_fw tool
@@ -1035,7 +1051,6 @@
.. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
.. _Akshay-Belsare: https://github.com/Akshay-Belsare
.. _AlexeiFedorov: https://github.com/AlexeiFedorov
-.. _amit-nagal: https://github.com/amit-nagal
.. _andersdellien-arm: https://github.com/andersdellien-arm
.. _Andre-ARM: https://github.com/Andre-ARM
.. _Anson-Huang: https://github.com/Anson-Huang
@@ -1075,7 +1090,6 @@
.. _jcorbier: https://github.com/jcorbier
.. _jenswi-linaro: https://github.com/jenswi-linaro
.. _JiafeiPan: https://github.com/JiafeiPan
-.. _jimmy-brisson: https://github.com/theotherjimmy
.. _joannafarley-arm: https://github.com/joannafarley-arm
.. _jslater8: https://github.com/jslater8
.. _jwerner-chromium: https://github.com/jwerner-chromium
@@ -1084,7 +1098,9 @@
.. _laurenw-arm: https://github.com/laurenw-arm
.. _leon-chen-mtk: https://github.com/leon-chen-mtk
.. _linyidi: https://github.com/linyidi
+.. _loosper-arm: https://github.com/loosper-arm
.. _madhukar-Arm: https://github.com/madhukar-Arm
+.. _maheedhar-bollapalli: https://github.com/maheedhar-bollapalli
.. _manish-pandey-arm: https://github.com/manish-pandey-arm
.. _ManishVB-Arm: https://github.com/ManishVB-Arm
.. _marcbonnici: https://github.com/marcbonnici
@@ -1100,7 +1116,6 @@
.. _MrVan: https://github.com/MrVan
.. _Neal-liu: https://github.com/neal-liu
.. _niej: https://github.com/niej
-.. _noncombatant: https://github.com/noncombatant
.. _nmenon: https://github.com/nmenon
.. _npoushin: https://github.com/npoushin
.. _odeprez: https://github.com/odeprez
diff --git a/docs/change-log.md b/docs/change-log.md
index 721e0f3..c865c34 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,6 +3,1203 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+## [2.13.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.12.0..refs/tags/v2.13.0) (2025-05-14)
+
+The threat model for context management support is not available in the release.
+
+### âš BREAKING CHANGES
+
+- **Platforms**
+
+ - **Arm**
+
+ - rename PLAT_MHU_VERSION flag
+
+ **See:** rename PLAT_MHU_VERSION flag ([a773955](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a7739550946acc0f9fd9f3360738eb046057ce28))
+
+- **Bootloader Images**
+
+ - **BL32**
+
+ - **TSP**
+
+ - The prototype for `tsp_early_platform_setup` has been
+ redefined. Platforms must update their implementations to match the new
+ function signature.
+
+ **See:** cascade boot arguments to platforms ([32d9e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32d9e8ec6c1f2889ffeb549007a7569754add5f1))
+
+- **Drivers**
+
+ - **Arm**
+
+ - **RSE**
+
+ - remove rse_comms_init
+
+ **See:** remove rse_comms_init ([91c7a95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/91c7a952bedb34f1b4c691988f9da9af02209441))
+
+### New Features
+
+- **Architecture**
+
+ - **CPU feature like FEAT_XXXX / ID register handling in general**
+
+ - add support for FEAT_PAUTH_LR ([025b1b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/025b1b816b607c7ac43a77172040c44b7750a622))
+ - add support for PMUv3p9 ([ba9e6a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba9e6a342de0a8922d75559bc3c539a5174e2004))
+ - enable FEAT_BTI to FEAT_STATE_CHECKED ([10ecd58](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10ecd58093a34e95e2dfad65b1180610f29397cc))
+ - enable FEAT_PAuth to FEAT_STATE_CHECKED ([8d9f5f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d9f5f2586d32ca19c11f65f3c6954615f3efdf6))
+ - disable FPMR trap ([a57e18e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a57e18e4337b74ce3d133a18f07fa891f0fd5fa9))
+ - enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1 ([6b8df7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b8df7b9e5cc70ef0433a99bf73db6db6002482c))
+ - setup per world MDCR_EL3 ([c95aa2e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c95aa2eb0dc7471df5f2c7a3d1cf939046bc170e))
+ - add support for FEAT_SPE_FDS ([4fd9814](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fd9814f4865efdffca17b7bbfc8d4bd244866f3))
+
+- **Platforms**
+
+ - **AMLogic**
+
+ - **GXL**
+
+ - add support for booting from U-Boot SPL/with standard params ([8dca65d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8dca65d96f787b6802b75bc72f830149293cbb6d))
+
+ - **Arm**
+
+ - add a macro for SPMC manifest base address ([eab1ed5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eab1ed54bfb6038a0c1ada79de409a5506e4dae0))
+ - add initrd props to dtb at build time ([1c08ff3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c08ff3277d47979c7897842ba683c23aa8197f7))
+ - add support for Transfer List creation ([4c5ccbf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c5ccbf43c1e34e3f2f71878f732efbe2449e9f6))
+ - convert arm platforms to expect a wakeup ([da305ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da305ec75dedca5e8e939790ab02fe7c0ba999d5))
+ - enable Linux boot from fip as BL33 ([eb8cb95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb8cb9534b58537e4ead8d1f8112ece45993c86d))
+ - migrate heap info to fw handoff ([ada4e59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ada4e59d166ab9fe7b039ed0f0b272398f71bdb9))
+ - port event log to firmware handoff ([b30d904](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b30d9043be420f6a288687cf9f282d4e578f69aa))
+ - support AArch32 booting with handoff ([abdb953](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/abdb953b00fff4aace32d9be10005b89751858d0))
+ - support boot info handoff and event log ([a852fa1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a852fa1d594f63bdc502a0c73eb77c5ce88aa02e))
+ - use provided algs for (swd/p)rotpk ([da57b6e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da57b6e3cfdb36ad96d136d17ec3d300f699fee3))
+ - use the provided hash alg to hash rotpk ([d51981e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d51981e15dd8383d727bd15e718f657f2cd2aaf5))
+
+ - **FVP**
+
+ - add StandaloneMm manifest in fvp ([8416e79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8416e7917f9c82336e900659d35038942418582f))
+ - add stub function to retrieve DLME image auth features ([1733deb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1733deb46c02444febfd25e411d09b1888ba8a7b))
+ - add stub platform function to get ACPI table region size ([5d37755](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d377555e862dd07e11022ba0a70f0150e34454b))
+ - allocate L0 GPT at the top of SRAM ([7a4a070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a4a07078b3d15648c1cbbd9f309b0c11da56165))
+ - build hob library ([8740771](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/874077132cf9a0504cccde6651c5714fa97beb07))
+ - change size of PCIe memory region 2 ([2e55a3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e55a3d74d588780e04f1632c1b9d7ad33fb5f4f))
+ - define single Root region ([665a8fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/665a8fdf3aa372862d62c34d23ffd678798a265c))
+ - give bootargs on all configs ([a507f4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a507f4f5f07253986b585e03583d40a818ebc3fb))
+ - increase BL1 RW for PSA Crypto ([51bdb70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/51bdb70fdb3719ad1eabb4e0d1037f4d89a552d6))
+ - increase bl2 mmap len for handoff ([24f7830](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24f78301288195f511528fc58b00e48f61933fa8))
+ - increase cactus-tertiary size ([dcd8d7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dcd8d7f13d5318ea3b38e6558c13e7401d57530c))
+ - increase GPT PPS to 1TB ([aeec55c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aeec55c8760f384bee46e1999287b0a757227c69))
+ - port event log to firmware handoff ([5bf0b80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5bf0b80784e29e9e77edb26b605d2c1791ecded2))
+ - set defaults for build commandline ([bf9a25f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf9a25f075c4c94a3d47bc54c1a8a7b964444ff1))
+ - support AArch32 booting with handoff ([2ab298b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ab298b58bf3096f033ec922acc163c106118f62))
+
+ - **Neoverse-RD**
+
+ - deprecate and remove RD-N1-Edge platform variants ([71ad967](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ad967333a684f66eccd0de559ad2159ca9c1bd))
+ - deprecate and remove RD-V1 platform variants ([afb3075](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afb3075592bc8cc2f130f2ed6c5871a391bf0e56))
+ - deprecate and remove SGI-575 platform ([a023201](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0232015d089c0fca1e78b1d5fb9c8be61acca67))
+ - use larger stack size when S-EL2 spmc is enabled ([82f4659](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82f46593de26d758457391d8b5036abcc533c7e3))
+
+ - **RD-V3**
+
+ - add carveout for BL32 image ([6823f5f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6823f5f520e7dfcd0812bdf8d93deb8c770de5e8))
+ - add dts files to enable hafnium as BL32 ([4d9b828](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d9b8281f35256f7367a6b76b1259d9edbefe713))
+ - define SPMC manifest base address ([12973bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12973bcc89eff3a4bb4953061d48e8805b3c6079))
+ - enable the support to fetch dynamic config ([37cc7fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/37cc7fa539d9cfbbe1fefadb2346bc7415422fec))
+ - introduce platform handler for Group0 interrupt ([4593b93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4593b932396dca2ed945ab2c95c6cc6712c3eeeb))
+
+ - **TC**
+
+ - add 'kaslr-seed' node in device tree for TC3 ([2d967e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d967e92e00fe05f0c1ecaddf414d50078050f9d))
+ - add devicetree node for AP/RSE MHU ([06fa4c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06fa4c4df28165dbf1d08158d86ef9997f099ad6))
+ - add dsu pmu node for TC4 ([50ad0cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50ad0cfda371f520c3b0452af8955aac30634431))
+ - add MCN PMU nodes in dts for TC4 ([624deb0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/624deb0825cf6b7e27165edf182bd075e58ee2ff))
+ - add SLC MSC nodes to TC4 DT ([99f6790](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99f6790cb9681d0a2960f8d30d82c20db19f6ab7))
+ - allow Android load and Boot From RAM ([932e64a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/932e64a1d79ef5ea7ed1525c45c9f11725ce5079))
+ - configure UART for TC4 FPGA ([84ca47a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/84ca47a8ac03821cfd4dbe902c0ae71621e2f12f))
+ - define MCN related macros for TC4 ([8f61c20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f61c20457c8e683b9c6b2a3f3c4ebcf4b1a5371))
+ - enable Arm SPE for TC4 ([cea55c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cea55c836f205a988634c04416082e35ac350ff9))
+ - enable DSU PMU el1 access for TC4 ([00397b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00397b30b8da9489dd8ed5f51aa976bb34165a27))
+ - enable MCN non-secure access to pmu counters on TC4 ([d1062c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1062c472a2976a03c74479eb18327e46f604f6c))
+ - enable stack protector ([d1de6b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1de6b2b57d9e52c3b08c63ae4ce2d1e6703ce70))
+ - enable trng ([2ae197a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ae197acd6a91a96619090e503521d44bee494b2))
+ - fpga: Enable support for loading FIP image to DRAM ([969b759](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/969b7591dcd94b0380116d301c2ba463dd9bfd7c))
+ - get entropy with PSA Crypto API ([8f0235f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f0235fb8f2d46ee6ca6309f8c365ad57e3a1565))
+ - increase SCP BL2 size to support optimization 0 ([3755e82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3755e82c0f2c557d38dc4111f4ccd31a9394ee25))
+ - initialize MHU channels with RSE ([0328f34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0328f3422275a3d292c9025a1a1faaf9d54aa8d9))
+ - initialize the RSE communication in earlier phase ([a3f9617](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a3f9617964ee30070855f9ba5e42ccb28dcc6a05))
+ - port BL1-BL2 interface to firmware handoff framework ([93c50ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93c50ae67fbdefd0fa2457a1b44fc538265b8fe0))
+ - port BL2-BL31 interface to firmware handoff framework ([2a36dee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a36dee8f158290cc30425df0753b6d887f12256))
+ - port BL31-BL33 interface to firmware handoff framework ([25a6bcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25a6bcd57104507c2f23760c2cc2ace43b5c00dd))
+ - print ni-tower discovery tree ([d87a856](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d87a8562306a46049560ba4387789918ecbca4b6))
+ - update CPU PMU nodes for tc4 ([1ce2c74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ce2c745a8b471dcc9e9f64e2163add566f5ce69))
+
+ - **Automotive RD**
+
+ - **RD-1 AE**
+
+ - add Generic Timer in device tree ([6e1bf7e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e1bf7e97f7389f59c2ea0d28cfeef5399db7881))
+ - add support for OP-TEE SPMC ([8b27eb7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b27eb7d91d97d707af94fff11ea02963ee2c3c0))
+
+ - **Intel**
+
+ - add FDT support for Altera products ([29d1e29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29d1e29d7cb137311529603056ce36ff268f861c))
+ - add support for query SDM config error and status ([fcf906c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf906c90088227b51a526533e71f4c8cd879778))
+ - implementation of SiPSVC-V3 protocol framework ([204d5e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/204d5e67b90b9dfaf7d7e064c048b4587a73f965))
+ - provide atf build version via smc call ([d1c58d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1c58d86496164d701d3286786db73182925d0e9))
+ - support FCS commands with SiPSVC V3 framework ([597fff5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/597fff5f8739b29fb779075be216d16acc28ab58))
+
+ - **Marvell**
+
+ - add trng driver ([6d5fad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d5fad8d9ea4011fa49556592c7a4560e7206940))
+
+ - **MediaTek**
+
+ - add gic driver ([d905b3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d905b3df300c1a822e666c5d8bd903ce16f5d507))
+ - add UFS stub implementation ([57c7351](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57c7351545befba76ae4725ef602eca0491cc5ac))
+ - add vcp driver support ([a1763ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1763ae97eab53476eef556a068de4bdf36b737a))
+ - update mtk_sip_def.h ([ead2602](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ead26026ff9f877b65011de55e3b3874e14aa137))
+
+ - **MT8189**
+
+ - add GIC driver on MT8189 ([1d193f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d193f91ea89ad525acc9ec5d78084da445d3813))
+ - add GPIO support ([cecbb93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cecbb93c1e623f163621a97a2368c72ac9068bfb))
+ - add reset and poweroff function for PSCI call ([4e40a1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4e40a1fdcf50dcfacd4331163f5a547d325714b3))
+ - disable L3C shared SRAM if the bootloader is coreboot ([7794e7c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7794e7c0b19f1fe470e62f59421d5770de1fcc95))
+ - enable cirq for Mediatek MT8189 ([83a5a0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83a5a0d1cc2d7cbb90ed9a11bb2b929a5f3b26e0))
+ - initialize platform for MT8189 ([6c60901](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c60901a4569ac2d7c5807158186d6701d3a2cf3))
+
+ - **MT8196**
+
+ - add APU kernel control operations ([5e5c57d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e5c57d52b1cfaec5182b2d01f804fae9ed54af4))
+ - add APU power on/off functions ([3ee4b2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ee4b2def6d1ee92dafb1730ff7852d8af532009))
+ - add APU power-on init flow ([0781f78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0781f7804a6922b3bb40f2b50880a9563e8ccd84))
+ - add APU RCX DevAPC setting ([f31932b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f31932b43087af86c56f919307a3ba4f7e994138))
+ - add APU SMMU hardware semaphore operations ([2d134d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d134d28f585f4bbcbf2e698443ab79b64128af2))
+ - add APUMMU setting ([e534d4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e534d4f633c30742ef7ced69abe077399b8eb5e6))
+ - add APUSYS AO DevAPC setting ([31a0b87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31a0b877566b0ebac6d11f2f8711cc11c0665e44))
+ - add CPC module for power management ([75530ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/75530ee280048a416844265f947d7a11b920d1f1))
+ - add DCM driver ([e578702](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e578702f71f99f728ca2406a89c1345132f44b78))
+ - add GPIO support ([4cb9f2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4cb9f2a5bf3a89d99f31505f830431e67a552709))
+ - add LPM v2 support ([da8cc41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da8cc41bc802555e15e280a7c7bf97bece8f69b3))
+ - add mcdi driver ([5cb0bc0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cb0bc07e3700ae9354e48adad8a990b02d7c80d))
+ - add mcusys moudles for power management ([95e974f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95e974fa15da2e5f5ff2e151d0d97390e483be98))
+ - add Mediatek EMI stub implementation for mt8196 ([39f5e27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39f5e2782061835650a80832a4a058921bd79568))
+ - add Mediatek MMinfra stub implementation ([4794746](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4794746eec6191563a97fec55c06027e42abe9bb))
+ - add mtcmos driver ([1f913a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f913a6e3a3eb6349db9a2263e15594c4dcd5766))
+ - add PMIC driver ([d4e6f98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d4e6f98d7f8b33ebd7706e8a440c568262500e21))
+ - add pwr_ctrl module for CPU power management ([4ba679d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4ba679da8b90ee15dd1234bc773854debb9b2466))
+ - add reset and poweroff function for PSCI call ([22d74da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/22d74da7cd0132b3b40c2289a3cbd152e548632c))
+ - add SMMU driver for PM ([86dd08d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86dd08d838a6a49e7915df0f20c90c3a3e003056))
+ - add smpu protection for APU secure memory ([7ed4d67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ed4d67c6351e61dd5500a0887e4d5e85b8ab764))
+ - add SPM basic features support ([fb57af7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb57af70ae8c93ebe806eb6281036a15113dc4f5))
+ - add SPM common driver support ([a24b53e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a24b53e0e581cde7b5c43607ab76ded8336dc353))
+ - add SPM common version support ([5532feb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5532feb70c699c54a21b02fada8fed59a3992786))
+ - add SPM features support ([01ce1d5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/01ce1d5d2fedb4e7db2127286080f6495a5403cf))
+ - add SPMI driver ([adf73ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/adf73ae20a7aa6f8230cb7a19551edb239db8afe))
+ - add topology module for power management ([da54c72](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da54c7243618cbb21c5269cc153f4ac2508ee76f))
+ - add vcore dvfs drivers ([f0dce79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0dce79600f239d9c2f382ba4573aba5e5126001))
+ - disable debug flag in APU driver ([31137e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31137e1b1559b6e838e9a4e4b9f74a5473ba8837))
+ - enable appropriate errata ([0d11e62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d11e62e67deb9a898b2ac5e7fbda58408df371b))
+ - enable APU on mt8196 ([f5a6aa0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f5a6aa02a9332c42712c709c6017927b99ca04c2))
+ - enable APU spmi operation ([823a57e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/823a57e11cd98ee6043e9637ff3a4cf58feb60ff))
+ - enable apusys mailbox mpu protection ([83f836c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83f836c96238c0d0765d94cc1f8ed1c179d1878c))
+ - enable apusys security control ([9059a37](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9059a375eeb20c08cdcd5e604b9fd68b47a31e7e))
+ - enable cirq for MediaTek MT8196 ([49d8c11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49d8c11285b28bddf9cdc7830ce039d4fc734f35))
+ - enable DP and eDP for mt8196 ([3e43d1d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3e43d1d317fa0f4ba6fdfc95583b8e313333769d))
+ - enable IRQ configuration ([16f94b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/16f94b91f10a5f8d52b6eb16a685881c97f7df89))
+ - enable PMIC low power setting ([e8e8768](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8e87683f2b4d8213a84475e5f981961dcc8a16b))
+ - enable vcore dvfsrc feature ([a3c218a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a3c218afd6596a46791b7f5d84a8d45d3c6977a0))
+ - fix MT8196 gpio driver ([6f891e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6f891e68964888bb9d97f83600d85e606882a8d2))
+ - initialize platform for MediaTek MT8196 ([a65fadf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65fadfbbd5919939bfe367fe3f2d3c22ca4cbf0))
+ - link prebuilt library ([e033943](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0339436614a2b86cae04dabc74efdb31e2b0fb4))
+ - refactor LPM header include paths to use lpm_v2 ([6fac00a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fac00a49099beda9caeb66d8bc35b00f0f52f10))
+ - show ERROR log if need ([1ba50c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ba50c33fcdf10d2132d6d96a5238c378b57de2f))
+ - turn on APU smpu protection ([5de1ace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5de1ace54a7088828dfaccd275ec2f1938ce7ee4))
+
+ - **NXP**
+
+ - **S32G274A**
+
+ - add console mapping ([a1e07b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1e07b399b5724e0d8f68a2e6ba6ce3102c2c424))
+ - dynamically map GIC regions ([5680f81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5680f81cecbbbb8a584dcf62bcb766a1cb25345f))
+ - dynamically map SIUL2 and fip img ([507ce7e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/507ce7ed6f5c2c34a94f18c6d66db27b163e0f2a))
+ - enable MMU for BL2 stage ([eb4d418](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb4d4185fa67edb6d137a5f7a0eb5e209b4e6299))
+ - enable MMU for BL31 stage ([e2ae6ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2ae6ceccc6fc96debbfbacfb4b288cbf78da0f2))
+ - enable SDHC clock ([47b3a82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47b3a8251f1b7948360714254f8ec22b0e23875e))
+ - increase the number of MMU regions ([0089258](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/008925861f3d6b30722895bc9701b85ec3d81215))
+ - map each image before its loading ([34fb2b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34fb2b35b9996d2afe40ad52f3a004bb90bf95f2))
+ - split early clock initialization ([61b5ef2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/61b5ef21af8bcb38d3492e15d1d3d1fbecf3cf49))
+
+ - **QEMU**
+
+ - add hob support for qemu platforms ([648d2d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/648d2d8e2dab8cf939350a1788c5204751dcc9be))
+ - add plat_rmmd_mecid_key_update() ([9c9a31e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c9a31eb9ae36cab9db58ddc5d49f82ca3cf976d))
+ - hand off TPM event log via TL ([cc58f08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc58f08fe6a53ab375322dbdec6edbe5707110b8))
+ - update for renamed struct memory_bank ([991f536](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/991f5360b68d6cdfbda2950100dbf78ac1c482cc))
+
+ - **SBSA**
+
+ - add support for RME on SBSA machine ([acb0937](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/acb09373baa1f951b68168e044ddf94d299ef44f))
+ - adjust DT memory start address when supporting RME ([99bc6cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99bc6cf518c1d6c0995d53d00670c0ac972ea64d))
+ - configure GPT based on system RAM ([d079d65](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d079d65d420d0f9edd4aa64b27305fc6537095da))
+ - configure RMM manifest based on system RAM ([fb4edc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb4edc35bc19e411ae566d1089198760042324eb))
+ - dissociate QEMU NS start address and NS_DRAM0_BASE ([26da60e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26da60e2a0e47768997b1b2079848beb9b5479c6))
+ - increase maximum FIP size ([122dbc2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/122dbc2c17494e96e7fd45ce6e03b68f8722585b))
+ - relocate DT after the RMM when RME is enabled ([17af959](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/17af9597e2b5d7cda2aaadad74b352e9805522d2))
+
+ - **QTI**
+
+ - platform support for qcs615 ([f60617d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f60617d3b1f9446d7f1528b3ac16fe6c4db9779d))
+
+ - **Raspberry Pi**
+
+ - **Raspberry Pi 3**
+
+ - add dTPM backed measured boot ([4f9894d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f9894db3572b6e375c7369bc2619cc690169604))
+ - implement eventlog handoff to BL33 ([6dfcf4e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dfcf4e1df3b4690fdf2629815d2a91294f34493))
+ - implement mboot for rpi3 ([c4c9e2b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4c9e2bc436198ee8f4544e8091c0067c4b4d9be))
+
+ - **Rockchip**
+
+ - increase FDT Buffer for Rockchip Devices ([ab99dce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab99dce4b7c8473d5bcb8c833bd410ab87b1e801))
+ - update uart baudrate for rk3399 ([6d7f1d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d7f1d4945ad3b85e33fb85eb7374d0fef2e9b64))
+
+ - **RK3576**
+
+ - support rk3576 ([036935a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/036935a8144b9c4b9f95f249ff4384945b846d40))
+
+ - **Socionext**
+
+ - **Synquacer**
+
+ - add support Hob creation ([357f28d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/357f28db6bcca7856a8cdbedfe6ce4668b06b48c))
+
+ - **ST**
+
+ - use dedicated version of DT for SP_MIN ([71ba164](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ba1647e09ca7ccecfeca417b22d1f7d023e338))
+
+ - **STM32MP1**
+
+ - rework SVC services ([39b08bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39b08bc366ff1bb08a2ab1dfd9c1eab3157fe16d))
+
+ - **STM32MP2**
+
+ - add a runtime service for STGEN configuration ([7f41506](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f41506fa7c10ba8cc393a9e67ae81bed379d07b))
+ - add common SMC runtime services ([f55b136](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f55b136abcdd2d6ba3bd5613eee8fff943de0fd1))
+ - add FWU support ([c28c0ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c28c0ca213147fff56555b038de8261fc5b92211))
+ - disable PIE by default on STM32MP2 platform ([ac9abe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac9abe7e597b1c5712a449b4a2366c859621e435))
+ - use USART1 for debug console on ultra-fly boards ([d59dd96](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d59dd96ddb2d58df989de07dc3d3fd86a1130652))
+
+ - **Texas Instruments**
+
+ - add support for TI mailbox driver ([9347ff4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9347ff4561e445d48839eac215cb452571cb8e54))
+ - introduce basic support for the AM62L ([21b14fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/21b14fd2aef32cdb8e6304b0e1383157e651a86c))
+ - introduce PSCI Driver for AM62L ([1abdc20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1abdc20b35f7b39862f91dbf1dfb462872380f71))
+
+ - **Xilinx**
+
+ - **Versal NET**
+
+ - add SDEI support ([10510c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10510c98c7501a76af16f7345225cc4225ee2cda))
+
+ - **ZynqMP**
+
+ - add pin group for lower qspi interface ([fe81d9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe81d9c959968599db8b8a5b1f150224f3315a38))
+
+ - **AMD**
+
+ - **Versal Gen 2**
+
+ - add bufferless IPI Support ([af22b19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af22b19d6b9cc3985ca61c68eb1a364dff7c4874))
+ - add dependency macro for PM ([aec66c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aec66c38c72a71cd1d37926c29ce08a25823bf89))
+ - add support for platform management ([414cf08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/414cf08b76bcf7e8fdb841c3663716d151b133a8))
+ - extended SMCCC payload for EEMI ([0cc5e21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0cc5e2105564bbcf9fae8d39869d51fb6c58ba23))
+ - is OCM configured as coherent ([c3ab09d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3ab09d1c543bda64d543557556e8e03d2b26c32))
+ - retrieve DT address from transfer list ([ea45387](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea453871ef70c116d40c950926c3c1a2c4036896))
+ - update platform version to versal2 ([4003ac0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4003ac02eb4e5b0551614710f3e99a2e23cfe799))
+
+- **Bootloader Images**
+
+ - adding psa crypto - crypto_mod_finish() ([055c97a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/055c97afb2427092766687253d6ff851ee77455e))
+
+ - **BL32**
+
+ - enable r3 usage for boot args ([3fabca7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3fabca724a724266f41a210d377d79072b36e140))
+
+ - **TSP**
+
+ - cascade boot arguments to platforms ([32d9e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32d9e8ec6c1f2889ffeb549007a7569754add5f1))
+
+- **Services**
+
+ - **FF-A**
+
+ - add FFA_MEM_PERM_GET/SET_SMC64 ([ddf72e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddf72e6a36bd6ef0958af5cfd638926861fe5c21))
+ - support FFA_MSG_SEND_DIRECT_REQ2/RESP2 ([09a580b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09a580b7961827501f94dd3dafbc27c7c5b69237))
+ ```
+ The FFA_MSG_SEND_DIRECT_REQ2/RESP2 early implementation in the EL3 SPMC is limited
+ to the use of 8 input/output registers per the SMCCC which isn't compliant to the
+ FF-A v1.2 specification mandating the use of 18 registers. This non compliance will
+ be fixed in the next release with the necessary versioning checks.
+ ```
+
+ - **RME**
+
+ - add SMMU and PCIe information to Boot manifest ([90552c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/90552c612e31ba88c6a7ad47c4081bc89d09c9c5))
+
+ - **TRP**
+
+ - test el3-rmm ide km interface ([8b3a89f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b3a89faddca3a955324adc4b48c864781e4c802))
+
+ - **RMMD**
+
+ - add FEAT_MEC support ([7e84f3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e84f3cf908c8eab1565b8e2d9a543e50de2e78e))
+ - add RMM_MECID_KEY_UPDATE call ([f801fdc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f801fdc22ef4fce3cc24fd1cbccde5772c15b633))
+ - el3-rmm ide key management interface ([2132c70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2132c707d73753338ce05f262843a91738177f5e))
+ - verify FEAT_MEC present before calling plat hoook ([609ada9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/609ada9691ca3793ad7203536fb4c95088bd3026))
+
+ - **RMM**
+
+ - add PCIe IO info to Boot manifest ([bef44f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bef44f60edaa763031bce6144c0267aefbb1f2bf))
+
+ - **SPM**
+
+ - use xfer list with Hob list in SPM_MM ([9ae5f67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ae5f67306b380c626a74782eff9e98b7f7996ee))
+
+ - **EL3 SPMC**
+
+ - ffa error handling in direct msg ([e1168bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e1168bc37563d1f18d6d2a6dc4ed468eadf673f2))
+ - support Hob list to boot S-EL0 SP ([4053a64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4053a647f6eca71e5a34bc52303a049e3324ca90))
+ - use spmd_smc_switch_state after secure interrupt ([a0a7f15](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0a7f158d2932117d57ec0d74113890a565e0cbc))
+
+ - **SPM MM**
+
+ - move mm_communication header define to general header ([b51436c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b51436c2ca4f1ceb2145dc752584df6ab1b77670))
+
+ - **DRTM**
+
+ - add platform API to retrieve ACPI tables region size ([7792bdb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7792bdbdf91a5854e580adea0f993886c3eec5df))
+ - ensure event types aligns with DRTM specification v1.1 ([8d24a30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d24a30d6073239a40eb835cb6014172080f2f06))
+ - introduce plat API for DLME authentication features ([0f7ebef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f7ebef73eb72f4627cf657fcb92f60c01001b41))
+ - log No-Action Event in Event Log for DRTM measurements ([2ec4488](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ec44880d0a47a60b851fea09b7bec0cd694e858))
+ - retrieve DLME image authentication features ([94127ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94127ae299aedf7642e598785c90961ab6e18266))
+ - update DLME data header with actual Event Log size ([9753238](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9753238fee94e97aff307a2c98d8e76bcbcfa211))
+ - validate launch features in DRTM parameters ([8666bcf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8666bcfa75c2d7b80ccd0a92b252d5308e08216c))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - add ENABLE_ERRATA_ALL flag ([593ae35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/593ae35435f855ff3e48facc6a049261c0c37ea7))
+ - add support for Alto CPU ([940ecd0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/940ecd072c695f51fc09eed1c13e50bbfa1690da))
+ - add sysreg_bit_toggle ([bb80185](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb801857eaf21365402a4748296c05cb3c6e861f))
+
+ - **EL3 Runtime**
+
+ - **RAS**
+
+ - add asynchronous error type corrected ([daeae49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/daeae495117e8e1496a44392217230ced17b39be))
+ - add eabort get helper function ([ec6f49c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec6f49c26be266e9d2b26818f35765ba9edd4e10))
+
+ - **HOB**
+
+ - copy StandaloneMm Hob creation library in edk2 ([2105831](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2105831848c4aef432f49e229c530cbda3489b10))
+ - introduce Hob creation library ([8953568](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8953568a2db48032f2a2d4065e68fd1b20980caf))
+ - modify Hob creation code imported from edk2 ([6b68b4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b68b4a42f9858102f2c804026ed1ce136e15813))
+
+ - **PSCI**
+
+ - allow cores to wake up from powerdown ([2b5e00d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b5e00d4eacbac4b315c1c2925882d0b77bc9205))
+ - remove cpu context init by index ([ef738d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef738d19d3565e44ed44a6b06c6d9ab036322ac5))
+
+ - **ROMlib**
+
+ - add PSA Crypto ROMLIB support ([cf1b7fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf1b7fe657a3215423ab397363cc4fa1a0e6399f))
+
+ - **GPT**
+
+ - statically allocate bitlocks array ([b0f1c84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0f1c84035fb25e331b21f08f3f3e8e643c3394d))
+
+ - **SMCCC**
+
+ - add FEAT_TWED to ARCH_FEATURE_AVAILABILITY ([d33ff5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d33ff5e0eec0f90cf74a442fd83faec4a03ecde5))
+ - implement SMCCC_ARCH_FEATURE_AVAILABILITY ([8db1705](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8db170524de1eb83c21ee6344d628961f9b84456))
+
+ - **C Standard Library**
+
+ - import qsort implementation ([277713e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/277713e0ae3b9a20d661cbd9e214112f67bed35b))
+
+ - **PSA**
+
+ - add interface with RSE for retrieving entropy ([1147a47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1147a470c257403466cdbd55a13823ca1652063e))
+
+ - **Firmware Handoff**
+
+ - add 32-bit variant of ep info ([7ffc1d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ffc1d6cf3c3981d74a3ac830f8a57f953b4ff03))
+ - add 32-bit variant of SRAM layout ([8001247](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8001247ce267a583ae6a24a37a77f17427bd5204))
+ - add func to check and init a tl ([f1d9459](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1d94593354a948dfc81ca569d4832afb20aaf41))
+ - add lib to sp-min sources ([79e7aae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79e7aae82dd173d1ccc63e5d553222f1d58f12f5))
+ - add Mbed-TLS heap info entry tag ([0e932b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e932b8563b6e25ae5f233a789cd420e46ae9297))
+ - add transfer entry printer ([937c513](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/937c513d5e8996d106e2661ea88786bde513ae74))
+ - common API for TPM event log handoff ([4d8b4ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d8b4ca0f5ab98e2d5d764a1530ae5fe55ba79bc))
+ - transfer entry ID for TPM event log ([9821775](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9821775657a415aac4b1d1f9c66da6390a016934))
+
+- **Drivers**
+
+ - **Authentication**
+
+ - add crypto_mod_finish() function ([0331bd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0331bd22c6082776a3d82b3cd3a1e5771643562b))
+ - add update of current_pk_oid in auth ([9c18c35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c18c35cbb21632d817ed2650ce80e5d544cac3b))
+ - add util file for current pk_oid ([1716805](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/17168053b38878f700d5c4ac11421cb96a50bc1b))
+ - extend REGISTER_CRYPTO_LIB calls ([95d49c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95d49c624f7a7784db1af6bb4de2007d2f044d61))
+ - increase mbedtls heap for PSA RSA ([2ffc28c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ffc28c833337d72b32580178ace9b466c7ebc24))
+ - introducing auth.mk ([142ee34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/142ee34ea375479282d842e1905a61436e792cd8))
+ - mbedtls psa key id mgmt ([8a7505b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a7505b008c71e61fa4e4d2b973932ec5720d526))
+
+ - **mbedTLS**
+
+ - introduce crypto lib heap info struct ([24da55e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24da55eef7f032a8b4957fd9eb53dc3b87d01997))
+ - mbedtls config update for v3.6.2 ([c307efc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c307efce85cab2336ce0786b8ac46130508b8bfa))
+ - optimize SHA256 for reduced memory footprint ([b57468b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b57468b3d029cb123b7881cefc68290cdeb31d9d))
+ - update mbedtls to version 3.6.3 ([08f8c0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/08f8c0a503b5c61d32f07edc8dae1a8179a174cd))
+
+ - **I/O**
+
+ - add generic gpio spi bit-bang driver ([3c54570](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3c54570afca013e050db3d01a4c948ae938d908a))
+
+ - **Measured Boot**
+
+ - add fw handoff event log utils ([ca39163](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ca391636ada5a382e35bdc41b930b46852a822a1))
+ - make event log lib standalone ([cb03020](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb03020e20859e61e94a2cf6a3eda86f87e796e2))
+
+ - **TPM**
+
+ - add Infineon SLB9670 GPIO SPI config ([6fa56e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fa56e93679631b0d23c88e962b9e40c97971942))
+ - add tpm drivers and framework ([36e3d87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36e3d877cd6caf51155a74936f15b461cc9b814c))
+
+ - **Arm**
+
+ - **GIC**
+
+ - add support for local chip addressing ([c89438b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c89438bcea49bf9d265e6e17f1ef13e6cfc9f62b))
+
+ - **NXP**
+
+ - **Clock**
+
+ - add a basic get_rate implementation ([bd69113](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd691136639963b61c028e55d5889997430e7fa7))
+ - add base address for PERIPH_DFS ([29f8a95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29f8a952cbbc7ee91188464cdf01b243735d41f8))
+ - add clock modules for uSDHC ([cf6d73d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf6d73d4c3b0fc4b299e6249f063b5adb5e3bedc))
+ - add clock objects for CGM dividers ([63d536f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63d536fe183bdf1c6ad99a5fd81cda7e2f32750f))
+ - add get_rate for clock muxes ([d1567da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1567da68d954be8f454ed641cbf7a08ca86f0bd))
+ - add get_rate for partition objects ([a74cf75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a74cf75f084e62888f57f7718f614bcd6e5eb50f))
+ - add get_rate for s32cc_clk ([46de0b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46de0b9c992fd4da90075b39ccff0a849a976301))
+ - add get_rate for s32cc_dfs ([2fb2550](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fb25509b800726342955194a0c6ac24299fb08e))
+ - add get_rate for s32cc_dfs_div ([8f23e76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f23e76fa5886ef9adbd867a546f291200fc2142))
+ - add get_rate for s32cc_fixed_div ([7c298eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c298ebcbf1003b98f815b86b2014112e89644d3))
+ - add get_rate for s32cc_pll ([fbebafa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbebafa518d5cbc69d0c64023f002ff6706019f2))
+ - add get_rate for s32cc_pll_out_div ([a762c50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a762c50579cb3bcae9c266e652c7c959e66fa943))
+ - dynamic map of the clock modules ([514c738](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/514c738045b5c2de0f8e99b68830322af88dad4d))
+ - enable MC_CGM dividers ([2710bda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2710bdadc4cefd45bb7056c7e4c1e20dd1dfddc4))
+ - get MC_CGM divider's parent ([1586904](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15869048b26f2ca2ebb78913ba1824532745744a))
+ - get MC_CGM divider's rate ([ad412c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad412c0d823ec1acad76f75419f40bdb09b2ad51))
+ - get parent for the fixed dividers ([35988a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35988a9db0aad69d068715ffe4d2f456aed5b508))
+ - get pll rate using get_module_rate ([43b4b29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/43b4b29fb996ee05d2ca98c7f824d6a003342215))
+ - restore pll output dividers rate ([c23dde6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c23dde6c193d26fae9b2a8e18140b90faeba3661))
+ - set MC_CGM divider's rate ([f99078a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f99078a6a09c09c93ac8f0aa679e1e85ab9658f3))
+ - set the rate for partition objects ([8501b1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8501b1fc60e3f6d01a38a3055dc0f274ecb039c6))
+
+ - **ST**
+
+ - **ST PMIC**
+
+ - add defines for NVM shadow registers ([c1222e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1222e7b8e635061690fe430e9213e86aae87920))
+
+- **Miscellaneous**
+ - add a generic EXTRACT macro ([f963578](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f963578b24906121b75375517f46c8d4d2a538fd))
+ - add EXTRACT_FIELD macro for field extraction ([af1dd6e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af1dd6e1a58957dc04747b9c87f482166022265c))
+ - implement strnlen secure and strcpy secure function ([eb08889](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb088894dc9fb08eb3da82b86ebdabe82ae45940))
+
+ - **AArch64**
+
+ - add DBGPRCR_EL1 register accessors ([bdcef87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdcef87cf5e16896688ee69aef216f7929a065c5))
+
+ - **FDTs**
+
+ - **ST**
+
+ - **STM32MP1**
+
+ - **STM32MP15**
+
+ - add Linux Automation GmbH Fairy Tux 2 ([093c738](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/093c738ab642005ca273aa6f21d306c81163012c))
+ - add Linux Automation GmbH TAC ([e67497f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e67497f9cc435e37c53b6a6361af3824247597df))
+ - add SP_MIN versions of DT files ([20544d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20544d66ccd53f8524d9d616fdab98dab88df37a))
+
+ - **STM32MP2**
+
+ - add LPDDR4 files ([64f82e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/64f82e5a06cf4aeef9da40a8d503dc3f77cdb840))
+ - add STM32MP257F-DK board support ([6a9e5ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a9e5ffda76a7625786cfe6d4246dfdcb4a9f8f1))
+ - add dual-ranked LPDDR4 config for STM32MP2 ([99adf4d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99adf4d43e09915e190b645227f41fa3ea10dd51))
+
+ - **STM32MP25**
+
+ - enable WDQS for LPDDR4 ([29917d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29917d3a12c98ebe9776c3191cb699e1687771be))
+ - update 2GB DDR configs ([388cb47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/388cb47cf0275cfc435df305a75781f2cf5a5ca7))
+ - add support for STM32MP257D-based ultra-fly-sbc board ([a4e31cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4e31cf0d96438bca564e219490f55fa2e6abeb4))
+
+- **Documentation**
+
+ - update mboot threat model with dTPM ([b00f6ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b00f6ece560696a89bf2a91289ea9ef51a768c5d))
+
+- **Build System**
+
+ - rk3399: m0: add support for new binutils versions ([6fbec46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fbec46a59de301edd9ad63af3a8a007977173cf))
+
+- **Tools**
+
+ - **Secure Partition Tool**
+
+ - add StMM memory region descriptor ([3553087](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35530877967fd943186cd0afc895f71f0976bf23))
+ - add the HOB list creation script ([cc594af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc594af66e05b5f863b00dfab939f53e558d9c23))
+ - include HOB file in the TL pkg ([32ecc0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32ecc0ef781d44f462aaeb441458d72b7dd5023d))
+ - invoke the HOB list creation code ([2d317e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d317e80c201573e9a05472ac1c96b0e6fe6e3bf))
+ - populate secure partition number in makefile ([9327361](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93273613b48048a4a884770e292e765fa85e3ad7))
+ - specify endianness for HOB bin ([49c6566](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49c656633178d21679afd467e41f43a761d4238c))
+ - transfer list to replace SP Pkg ([0fe374e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0fe374ef046f70b6e990024922034d14d418b109))
+
+ - **Transfer List Compiler**
+
+ - add --align argument ([c4c8e26](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4c8e26a69411902516d394d8ca593db435c612b))
+ - formalise random generation of TEs ([157c619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/157c61978679ca7115e06df92d481b57fa2ae1ef))
+
+### Resolved Issues
+
+- **Architecture**
+
+ - **CPU feature like FEAT_XXXX / ID register handling in general**
+
+ - add support for 128-bit sysregs to EL3 crash handler ([58fadd6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/58fadd62beba8e9fefddae884bfd34f71a183997))
+ - add feat_hcx check before enabling FEAT_MOPS ([484befb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/484befbfcbe5289fa237a96c36a2da75ff3ff2ba))
+ - avoid using mrrs/msrr for tspd ([f3e2b49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f3e2b499707c5cde85033c8ed16efe4f16de5231))
+ - improve xpaci wrapper ([787977c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/787977c3afe9d951a088a1f12959b00d8343a18d))
+ - include FEAT_MOPS declaration in aarch32 header ([8656bda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8656bdab57b22b5a65bb0480429553c084c1b0a6))
+ - replace "bti" mnemonic with hint instructions ([bdac600](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdac600bc8c61e2facdd0b872cacfb7a24045fe4))
+ - add a psb before updating context and remove context saving ([f808873](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f808873372381a401dcd86d7d45a5ee6fd164d50))
+ - add a tsb before context switching ([73d98e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/73d98e37593f4a4044dd28f52127cdc890911c0c))
+
+- **Platforms**
+
+ - **Arm**
+
+ - create build directory before key generation ([db69d11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/db69d118294f08aae86378c98aa082ac73e15b73))
+ - don't race on the build directory ([9855568](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9855568cc5ab8af9a8bee54fcc35112240e16b28))
+ - reinit secure and non-secure tls ([2948d1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2948d1f81904f02034a0d12faf9b8c7f34b05795))
+ - resolve build issue with ARM_ROTPK_LOCATION=regs option ([4569a49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4569a496fd5b41b371c676b9313b796fe8bd27c2))
+ - resolve dangling comments around macros ([523c787](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/523c78704fabfd5f35f0e6abe6df2192d33a3c95))
+ - resolve misra rule R11.6 violation ([307a533](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/307a533301881869c0f54a5145a81a6a705156b9))
+ - update tsp_early_platform_setup prototype ([9018b7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9018b7b8401ab106228842140b53502ee64f1432))
+ - use EL3_PAS in MAP_BL2_TOTAL definition ([875423d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/875423de49646402cd6a7c1850f52982a3b56299))
+
+ - **Common**
+
+ - add missing curly braces ([7e288d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e288d11a5f155de4d6ad2ab9827fd71c0c9f74e))
+ - modify function to have single return ([50029b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50029b9ac3c60371f8606fb874df9038fb6839d0))
+ - remove platform_core_pos_helper() ([96e46f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/96e46f58d54a1a711bd7474a4ea949785119798e))
+ - remove fvp_r ([2cadf21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2cadf21bc8cc58e9ed8c7ae2af6089ffdb3d0a02))
+ - remove unused vfp code ([18b129f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18b129f4c1539444f9b91655d325a013264f7312))
+ - add missing curly braces ([0eeda63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0eeda638a8a6e8d9ff0448ba7405a8a5b86d17e0))
+ - ignore the unused function return value ([fc7a720](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fc7a7208e0ccc0722bb29fcbb0cb7a3d74ff0953))
+
+ - **CSS**
+
+ - turn the redistributor off on PSCI CPU_OFF ([50009f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50009f61177421118f42d6a000611ba0e613d54b))
+
+ - **FVP**
+
+ - allow PSCI 0.2 in the device tree ([94b500d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94b500dcbb94b11c5b89657eda10e6f0b5fc87a1))
+ - exclude extend memory map TZC regions ([06cec93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06cec933def225ef64d81983829c349f47b89319))
+ - increase EventLog size for OP-TEE with multiple SPs ([d1a824e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1a824ea0e8887151d1237f3836e7e0df4d9e5bd))
+
+ - **Juno**
+
+ - resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1) ([dd566a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd566a9e565842eb97b6e14da63ba01d13d061ec))
+
+ - **Morello**
+
+ - remove stray white-space in 'morello/platform.mk' ([05533d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/05533d99922f76af82b765159bb56e6592c09cf0))
+
+ - **Neoverse-RD**
+
+ - initialize CNTFRQ_EL0 for RESET_TO_BL31 ([94a4383](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94a4383a2b7de555ac68fc4f571d08105cdb3296))
+ - initialize timer before use in smmuv3_poll ([64ff172](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/64ff172abe1edf333d41fb99aac1b4c50d85f248))
+ - set correct SVE vector lengths ([842ba2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/842ba2f22196beab45a581517ad43a6cdbf61d9a))
+
+ - **RD-N2**
+
+ - add LCA multichip data for RD-N2-Cfg2 ([289578e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/289578e610b6e4dfb62068a07bc56216e431fb17))
+ - correct RD-N2 StMM uuid format ([6fb8d8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fb8d8cf8427ebf2c63986ea3451ca835eac3aa2))
+
+ - **RD-V3**
+
+ - add console name to checksum calculation on RD-V3 ([222c87e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/222c87e75c747e4fb100a08910c5f870c473449d))
+ - add LCA multichip data for RD-V3-Cfg2 ([d0b93a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0b93a0dd04c755264355633cc77c8c1ea78ada4))
+ - correctly define plat_mboot_measure_key() ([fa0eb3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fa0eb3cf5bab4cf86671a0ec3c7b0ceab33b7666))
+ - correctly handle FP regs context saving ([ac05182](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac05182df0b7c46c70faf92058063f8498a8624a))
+ - fix comment for DRAM1 carveout size ([4e2369c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4e2369c707ba6ebd26810052532afa7d30cc4cc8))
+ - handle invalid build combination ([fe488c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe488c3796e01187fb6cffdd27a1bee1a33e0931))
+
+ - **TC**
+
+ - define status to fix SPM tests ([8d4d190](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d4d190915af07750cfc0c05b79c4ebd4bc1df4f))
+ - eliminate unneeded MbedTLS dependency ([22220e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/22220e69f996b68c50dcc34cd05152a0fcb0e904))
+ - enable certificate on the last secure partition ([2e36131](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e361319ac1907009b42da657f7c55a50a9ccca0))
+ - enable Last-level cache (LLC) for tc4 ([7b41aca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b41acaf72dc208601c315189756fdb9f24f4abf))
+ - fix compilation error ([26a520b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26a520b2befb310b9ee23da108854c9d9c294c11))
+ - fix SMMU streamId for tc4 gpu ([bf223c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf223c79377ed5d94f58acd2f354e8524ed6b1c6))
+ - map mem_protect flash region ([4bfe49e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4bfe49ec4eff17ded7f7b13fe4ceaa7307a78f92))
+ - modify DPU configuration in dts for TC4 FPGA ([bb9b893](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb9b89366f580d6166d0abcd4ae8b3c45943ca1c))
+ - modify ethernet configuration for TC4 FPGA ([8dec630](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8dec63032e8d173215fc5a4b6540ecbc189cbf87))
+ - modify gpio controller base addr for TC4 FPGA ([5de9d79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5de9d79bc4b2febe3b55db47039ab2004d8cd4af))
+ - modify mmc configuration for TC4 FPGA ([ba1faaf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba1faaf117158dc1f1272192f3d8131421e96458))
+ - replace vencoder with simple panel for kernel > 6.6 ([1d2d96d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d2d96dd5cefdd8ae1872022d4b3b0d564188a29))
+ - set console baurate to 38400 for fvp as well ([5428938](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54289385f128e5ddad8d2f1be0d63a9edf685922))
+ - set system-coherency to 0(ACE-LITE) for tc4-gpu ([cada6ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cada6ca36c0a59a0050abf481ffa82a1838b1fe0))
+
+ - **Automotive RD**
+
+ - **RD-1 AE**
+
+ - fix rd1-ae device tree ([f72eeb2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f72eeb2d227702817d38b44bec8ee988f30f1fb3))
+ - rename legacy MPAM build option ([7a5e580](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a5e580957a426ba4d4db2a07449a43d04628814))
+
+ - **Intel**
+
+ - add FPGA isolation trigger when reconfiguration ([6ce576c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ce576c63d6333261f48ecee301a11e77cc5f0d0))
+ - handle cold reset via physical reset switch ([bf3877e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf3877e072af2b718454e9ee1ee16d769980378e))
+ - redesign F2SOC bridge enable and disable flow for Agilex5 ([42e9062](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42e906205ecbb3e157a802a86ae98ef392a4b6eb))
+ - this patch is used to solve DDR and VAB ([458b40d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/458b40df58d60974f2f57017c8f17663e8e0973e))
+ - update debug messages to appropriate class ([a550aeb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a550aeb39460d34e5b75421639f54b215b46e616))
+ - update ssbl naming conventions ([bf2c213](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf2c213670feb2ecc6acc316be0c0342c5a5159f))
+ - update warm reset routine and bootscratch register usage ([646a9a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/646a9a16150066eaa3146d4e2819d589333b6454))
+ - add in support for agilex5 b0 jtag id ([8a0a006](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a0a006af3362a114ed899f2cfe6c2ef0ec84061))
+
+ - **Marvell**
+
+ - **Armada**
+
+ - don't race on the UART_IMAGE ([3395bd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3395bd12bcd7595b66902c0fc70ffee0a4681eea))
+
+ - **MediaTek**
+
+ - covert MTK_BL to uppercase for the build ([c710579](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7105798eda68240093d4c2bb34fcbc09f0ea587))
+
+ - **MT8189**
+
+ - fix mt8189 platform build failure ([49d8678](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49d8678efbae57a2445af4c535f2ebd73dfb6b48))
+
+ - **MT8196**
+
+ - add whole-archive option to prebuilt library ([8f7d9bf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f7d9bfa0a15d3063f9475da9c5e579ea935ac68))
+ - fix wrong register offset of dptx on MT8196 ([b38f8f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b38f8f7a3e2f4cdd323f195d2a17a6091aa75722))
+ - remove CPU_IDLE_SRAM_BASE entry from plat_mmap ([83f37d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83f37d998123f269e7ce901b190e016d52f9ebe3))
+ - remove EC_SUSPEND_PIN initial setting ([1185526](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11855267b55fb70522ed2ac015a6a0002641412e))
+ - remove SPM support for ES chip ([ee2e99c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee2e99c3e3fc8443bf48b05fe3776e3f2aaa6b23))
+
+ - **NXP**
+
+ - imx_trdc.h header guard ([2e9198d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e9198d0e0cbe9546348dd0a71ff6c3d2061d4eb))
+
+ - **i.MX**
+
+ - **i.MX 8M**
+
+ - fix imx8mq build break ([1b65be5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b65be5943fc4f6a0382d03a4ed7393b383e56a4))
+
+ - **i.MX 8M Plus**
+
+ - apply ERRATA_A53_1530924 erratum ([e6d39da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6d39da0473b84488dd012091c8deede0adc7d87))
+
+ - **i.MX 8Q**
+
+ - fix imx8mq build break due to hab ([3a36f70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a36f70ba02e88ed20083c1278a739c6c870aae0))
+
+ - **i.MX 9**
+
+ - **i.MX93**
+
+ - trdc: restrict BLK_CTRL_S_AONMIX to secure world ([c6bf928](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c6bf92894c6c7096e380fe60c0e57b3db87ea0c7))
+
+ - **S32G274A**
+
+ - reduce the uSDHC clock to 200MHz ([9c640e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c640e09a86bdcc4cf77233c71b2ac0d36b7f9d1))
+
+ - **QEMU**
+
+ - fix register convention in BL31 for qemu ([7ad6775](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ad6775bde8fb719ab94ab7d47736fd2dd66cddc))
+ - fix RMM manifest checksum calculation ([d08dca4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d08dca4263e5286b7f9b36612dae5767aac74a63))
+ - ignore TPM error ([ddb5e2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddb5e2fd12a759270dd3566d086bbb91076ae0ae))
+ - statically allocate bitlocks array ([a32a77f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a32a77f9c7567141556a823c0b9d4d5488c95722))
+
+ - **SBSA**
+
+ - fix compilation error when accessing DT functions ([33ac6f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33ac6f99abcbb2d3b8303af5194390cafb4e6853))
+
+ - **QTI**
+
+ - **MSM8916**
+
+ - update tsp_early_platform_setup prototype ([2f02426](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2f024262e986f241fed5dbadbb7f0ab68165bb74))
+
+ - **Raspberry Pi**
+
+ - **Raspberry Pi 3**
+
+ - expose BL1_RW to BL2 map for mboot ([9acaade](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9acaaded3ca9b6966efb72e3a989f8ee753b3a44))
+ - use correct name for include guards ([5c0cbb2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c0cbb2faaa0ddfbe7c36d037918fbda13a661f6))
+
+ - **Renesas**
+
+ - **R-Car**
+
+ - use platform_def ([99fe5c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99fe5c2fd531298457214a61dafcfae15053e900))
+
+ - **Rockchip**
+
+ - pmu: Do not mark already defined functions as weak ([7f25d3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f25d3cc782337ce2fd445d39cbe295090beb5c9))
+
+ - **PX30**
+
+ - remove unused function ([ce66647](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ce666476812099bc5e27dcc1d336e712e0cd78fb))
+
+ - **RK3288**
+
+ - remove unused function ([6e38cc9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e38cc97df86ac1c45aacc9ce301f6df1fc72056))
+
+ - **RK3399**
+
+ - dram: Fix build with gcc 11 ([f86c230](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f86c230ab02ce94d54866c072e8c118095a8783e))
+ - fix unquoted .incbin for clang ([ddd70f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddd70f199bd0b09a229aa624497b86dbff5b8db5))
+ - m0: Makefile: fix outside array bounds warning ([5049f91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5049f910aec254b9656dafe6c4cf7dd3d8b91d5c))
+ - mark INCBIN-generated sections as SHF_ALLOC ([279cad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/279cad8ed38c186aebce3502f9f1ebc52e22b281))
+
+ - **RK3588**
+
+ - pmu: fix assembly symbol redefinition ([f879388](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f879388831795c948c7d5954d5ea6b1c224e6e08))
+
+ - **Socionext**
+
+ - update tsp_early_platform_setup prototype ([c45dbe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c45dbe7e5d28da67f831159830cdc835095b142b))
+
+ - **ST**
+
+ - **STM32MP2**
+
+ - correct early/crash console init ([23647bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/23647bd52c805594050c5cd0e387389760778492))
+
+ - **Texas Instruments**
+
+ - fix UNUSED_VALUE in AM62L PSCI Driver ([32302b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32302b44abc3a725b4197cec8f1411d8320542d9))
+
+ - **Xilinx**
+
+ - avoid unexpected variable update ([b3d25dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b3d25dca86ad438423e2554b0c72ea8e429c30fb))
+ - dcc console tests failing ([e14ae4b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e14ae4b30175d6c9877fd33497d43a8895f5b3d9))
+ - modify function to have single return ([906d589](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/906d58927760c70112fd8e70a7e67f2a4989e9ed))
+ - remove unused write_icc_asgi1r_el1() ([1c12cd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c12cd10fc4662141777f5b0fc0fbac2d00f50c3))
+ - resolve misra rule 10.3 violations ([72eb16b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72eb16b7f8d679e9da960185904e6e608d5c5a5c))
+ - resolve misra rule 10.4 violations ([bdba3c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdba3c84baa5c595e504ef2902832d04102a223a))
+ - resolve misra rule 11.3 violations ([c35fe29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c35fe2946b6e2b1e4e3fcf845289bcea791eb60a))
+ - resolve misra rule 14.4 violation ([a5d5cb3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5d5cb3cfc83928bee0a00dd987f2731e1b8ec56))
+ - resolve misra rule 15.7 violations ([fd44cc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fd44cc7e9b660a8baae2e8a0d3a2b3efde2e2c7e))
+ - resolve misra rule 2.2 violations ([e5adcfc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5adcfcdd143660bb9c3d56a44a42621066fca59))
+ - resolve misra rule 2.3 violations ([09abae0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09abae060d5c65ec8cb7a42a5ac75fa30eb1aabc))
+ - resolve misra rule 2.7 violations ([d87b0ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d87b0ce30189cf692a6a6e21393bde0ac5029780))
+ - resolve misra rule 8.3 violations ([3df32f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3df32f852400be6d4c1f3199c89d9f36169ede71))
+ - resolve misra rule 8.4 violations ([4b4080d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b4080d78637fd0f071e0d6860114eb9ea16dea5))
+ - resolve misra rule 8.6 violations ([eec03e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eec03e947b3855c0a19bb64d39b4627e253a22b5))
+ - runtime console to handle dt failure ([0791be8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0791be881388c32c13b5ed9e79dc640aeefaaab4))
+ - typecast expression to match data type ([50ab135](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50ab13577fd533ab99c874772e6630929506229c))
+ - typecast expressions to match data type ([83bcef3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83bcef3f509d77582e4534f75ca2b4fd3ea4ffee))
+ - typecast operands to match data type ([3a1a2da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a1a2dae10ef3058e3973715fc4406544ff4aad7))
+ - typecast operands to match data type ([7d15b94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d15b94ba3d7160c79c5c3229015f7e9373490ff))
+ - update tsp_early_platform_setup prototype ([470dd8b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/470dd8b49dab7211ca425f16fd94e8c18bbd37bf))
+
+ - **Versal**
+
+ - add unsigned suffix to match data type ([4b23240](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b2324042a292d6e1bd877daaf91c05dc888a926))
+ - handle invalid entry point in cpu hotplug scenario ([435bc14](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/435bc14a94008ab811ebac2735875a99ea6e464c))
+ - modify function to have single return ([890781d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/890781d10ce362150359c00b06c8b7e9e1ee34d2))
+ - typecast expressions to match data type ([b802b27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b802b2784c8bcaae56d450ab55ee305880293c85))
+ - typecast operands to match data type ([8e4d5c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e4d5c6db0e462ea33db2eaee4229583ace6cd6f))
+ - typecast operands to match data type ([9b89de5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b89de5fc4aa22e0cdc8e9f216135041549bbdff))
+
+ - **Versal NET**
+
+ - add missing curly braces ([9334fdf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9334fdf9718fed0f98a990f2f7f43cc40426b6dc))
+ - add unsigned suffix to match data type ([baeeadd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/baeeaddff4840028d627f21af64e6397da88a058))
+ - enable PSCI reset2 interface ([5f22f57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f22f573adbbcb30b7e1793fdcc1ba7c88eceff0))
+ - handle invalid entry point in cpu hotplug scenario ([e5e417d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5e417ddecfaedd875adf47de4ad1396dd514ab9))
+ - modify function to have single return ([5003a33](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5003a332b8e40ff93333b70a4365c1e13e8b1d10))
+ - remove_redundant_lock_defs ([19799fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19799fd8fb318682a8169d5e4fc32e41ae50c0b1))
+ - typecast expressions to match data type ([3cbe0ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3cbe0ae5b8b2f79fe87c73d160ef7e33603ae604))
+ - typecast operands to match data type ([d51c8e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d51c8e4c654a27e7487b7d15a64cec6f5eeab4e5))
+ - typecast operands to match data type ([3dc93e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3dc93e5139b262ff099c450d82433180b802a484))
+
+ - **ZynqMP**
+
+ - add missing curly braces ([e4a0c44](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4a0c44f690d0658310914bcb5ae2355808a17b7))
+ - align essential type categories ([1877bf2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1877bf2ce18092259cace97cec41ea32a97a8ed7))
+ - fix length of clock name ([f535068](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f535068c84c00da3d4af40d6b571d9df39e07264))
+ - fix syscnt frequency for QEMU ([55ae162](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55ae162fd521cbe2ba500570692785159777a0ff))
+ - handle invalid entry point in cpu hotplug scenario ([df44616](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df44616a12096c16dd497646fc06684bdc818760))
+ - modify function to have single return ([3f6d479](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f6d47945a4bd94eae2d6ad17f50b59cda551c10))
+ - typecast expression to match data type ([e2cc129](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2cc129bcc58234dcb4607fe9264c1bdf4b282ea))
+ - typecast expressions to match data type ([895e802](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/895e8029aa1f88da164966504be8fc8120c9f7a5))
+ - typecast operands to match data type ([6ae9562](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ae9562473812cce8d97f3a3f2a8ae7aafa75201))
+ - typecast operands to match data type ([2863b0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2863b0c46633d28a920ef14c68ee4a6e4842ab0b))
+
+ - **AMD**
+
+ - update transfer list args for OP-TEE ([573ec22](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/573ec2287eb616d1629b2c32fb28e894d852a78b))
+
+ - **Versal Gen 2**
+
+ - add missing curly braces ([9f51da5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9f51da5e2e6fcd81b22fb1c7f5cd5712bdc6cb3b))
+ - align QEMU APU GT frequency with silicon ([f7a380e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f7a380e23ce8c7e4835367ee71af0bdeb505baa7))
+ - enable system reset ([058edb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/058edb8fcd7d32346bda0e43389cd0903074034a))
+ - modify function to have single return ([fb2fdcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb2fdcd9536874aaff0c14f9c466214e717b0e91))
+ - pass tl address to bl32 ([1fb3446](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1fb3446ed230c1011c982eb0bf62214f8abd38b2))
+ - rename console build arg to generic ([2333ab4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2333ab4cd214150ac099ba0894bb6d1c3963d945))
+ - typecast expressions to match data type ([fbc415d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbc415d2046ca6e940323a88252fd40a68bebec4))
+ - typecast operands to match data type ([07be78d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07be78d500aaabf2401bb4b31eb3b40b677fa110))
+ - update DDR address map ([66569a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66569a76880ceb6c02fbcfe993584c67336df353))
+ - update transfer list as optional ([5cb9125](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cb9125e9654e374dff4f322c3bbaef59511fcda))
+
+- **Bootloader Images**
+
+ - **BL1**
+
+ - prevent null pointer dereference ([2d3b44e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d3b44e3073e8d6ec49dde45ec353d6f41290917))
+
+ - **BL31**
+
+ - add const qualifier ([e358089](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e358089d8382e4239a4b606b0e97cf5475da4976))
+ - add missing curly braces ([88edd9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88edd9c6a09cc867ea377c7ad968e6a17595acf5))
+
+ - **BL32**
+
+ - **TSP**
+
+ - use %u to display unsigned values ([3b06438](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b06438dd1e038a7453d3b812ca6ef2da54f6ba8))
+
+- **Services**
+
+ - avoid altering function parameters ([1a0f565](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a0f565b6240392ccb6982a15098ec288df7ea94))
+
+ - **RME**
+
+ - do not trap access to MPAM system registers in Realm mode ([d048af0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d048af0da1022a844e153093395087c724f12e40))
+ - map DEVICE0_BASE as EL3_PAS ([b577248](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b57724806143e36ae17be7e33e5792863c5c026c))
+ - remove ENABLE_PIE restriction ([e126ed1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e126ed1ae7d498110b349be5f0bbd40e3bdc32ba))
+
+ - **RMM**
+
+ - add support for BRBCR_EL2 register for feat_brbe ([41ae047](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/41ae04735284f7c97a3993dc6d2d45de3954c2b7))
+
+ - **SPM**
+
+ - **EL3 SPMC**
+
+ - fix FF-A v1.2 version check ([6feaad6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6feaad6c6e36f3bd92dd7181f08b2abc87f54240))
+ - move ERROR line inside conditional ([bbf28dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bbf28dc37d50ea8a5bf40ab3fcc2f529cbb1e024))
+
+ - **SPMD**
+
+ - check pwr mgmt status for SPMC framework response ([8723eaf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8723eaf2fea9d09526fd7e6bc544b9c3103240ac))
+ - fix build failure due to redefinition ([a869e2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a869e2dc4549e86465d485d9ec5d1c18d21c10be))
+ - prevent SIMD context loss ([8f60d99](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f60d99f44f3f75108f7cf707e8d1c8f6ef33be0))
+
+ - **SPM MM**
+
+ - prevent excessive racing ([48426cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48426cff7250486b9a00a2e0e69d53cb5ae6e413))
+
+ - **DRTM**
+
+ - add missing DLME data regions for min size requirement ([a65fa57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65fa57b129713ddaa3cdff048921368f9dacc2e))
+ - adjust Event Log size in DLME ([63d2020](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63d2020f577aadb9f600a7f1a525d427117fd11d))
+ - fix DLME data size check ([28e8f9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28e8f9d93329b45e8dc9bf6ee1f3d14bde9adda2))
+ - sort the address-map in ascending order ([7cf3784](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7cf37848140d3ba29b5967b46acbc5464b0b04b0))
+
+ - **TRNG**
+
+ - allow FEAT_RNG_TRAP in dynamic fashion ([bc30945](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc30945bb660c5be04d82bfa95f5b9caaffba3ef))
+
+ - **ERRATA ABI**
+
+ - add support for handling split workarounds ([bbff267](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bbff267b6f2777483a37781850dd1be01c16b937))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - add missing add_erratum_entry ([a74b009](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a74b0094163b0efc5525131c5b807aaea2591e9e))
+ - avoid SME related loss of context on powerdown ([45c7328](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45c7328c0b94d043745b4a44c2e14e1a77f5c347))
+ - clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset ([c9f352c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9f352c362a8d114a055bb9206c5b6391ec3b96a))
+ - declare reset errata correctly ([5cba510](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cba510ee31c520c6bd3254a4fd791d411d02152))
+ - drop esb from the Neoverse N1 ([e75eea7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e75eea749a59ba67c3eb3dfba41bd8d6770cc708))
+ - fix a typo in errata doc ([845213e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/845213ed0ddb08be79f621990db1314f4988d2e5))
+ - fix clang compilation issue ([bdaf0d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdaf0d9ba71c1fd17f5d35f8fd2a6205136116a3))
+ - remove errata setting PF_MODE to conservative ([ac9f4b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac9f4b4da6f6ef695a25aa2ed525281a89d40bf9))
+ - workaround for accessing ICH_VMCR_EL2 ([7455cd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7455cd1721ec3b8671d6a2fae879f86ecfe497fb))
+ - workaround for Cortex-A710 erratum 3701772 ([463b5b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/463b5b4a46552887c4fb70536d20f315f889add1))
+ - workaround for Cortex-A715 erratum 2804830 ([fcf2ab7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf2ab71ac00122bd382973f6e9f08e30b7eca80))
+ - workaround for Cortex-A715 erratum 3699560 ([26437af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26437afde1e7c16a5a05b8c7e0bb062efe63c3cf))
+ - workaround for Cortex-A720 erratum 3699561 ([050c4a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/050c4a38a335c721c2f6ce38c33f1aa6aa328800))
+ - workaround for Cortex-A720-AE erratum 3699562 ([af5ae9a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af5ae9a73f67dc8c9ed493846d031b052b0f22a0))
+ - workaround for Cortex-A725 erratum 3699564 ([d732300](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d732300b86238ac7166bc9bebd667a24dc3ed062))
+ - workaround for Cortex-X2 erratum 3701772 ([ae6c7c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae6c7c97d4e0f491854b34628e0fa1038668f8e4))
+ - workaround for Cortex-X3 erratum 3701769 ([77feb74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77feb745e42296c553c33bcaea5be3304168eff3))
+ - workaround for Cortex-X4 erratum 2923985 ([cc46166](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc46166144b9a3746807f1d137ff784da3013e26))
+ - workaround for Cortex-X4 erratum 2957258 ([09c1edb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09c1edb84b9d2e91ce425b4300042751b3899434))
+ - workaround for Cortex-X4 erratum 3701758 ([38401c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/38401c5388b5c3127745b758b3dc939d27041d7d))
+ - workaround for Cortex-X925 erratum 2963999 ([29bda25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29bda258d5655d2ac24dda0f73e6b0ec93c3037e))
+ - workaround for Cortex-X925 erratum 3701747 ([511148e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/511148ef5077dfb8f6bc7b9655e4ac19e16c4af0))
+ - workaround for CVE-2024-5660 for Cortex-A710 ([0d7b503](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d7b503f8a11237fa129ae7baa2d979d64b9ab68))
+ - workaround for CVE-2024-5660 for Cortex-A77 ([aed3e8b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aed3e8b59a034ddcd073f2295cf0ae70a313ccf5))
+ - workaround for CVE-2024-5660 for Cortex-A78 ([c818bf1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c818bf1d60c01e1a8953bf0051987dea4db7c4bf))
+ - workaround for CVE-2024-5660 for Cortex-A78_AE ([902dc0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/902dc0e01ffc5f215eabde8e0428ce462db18a73))
+ - workaround for CVE-2024-5660 for Cortex-A78C ([46a4cad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46a4cadb9d63f4265756d82c9e252d7760c43ae8))
+ - workaround for CVE-2024-5660 for Cortex-X1 ([26293a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26293a746319e7073dd3699be0afcd2277ad1999))
+ - workaround for CVE-2024-5660 for Cortex-X2 ([5b58142](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b58142c460b9d28740c610d51023a444583a10e))
+ - workaround for CVE-2024-5660 for Cortex-X3 ([b0d441b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0d441bdadae3b38e3a670e03341603785b39f3c))
+ - workaround for CVE-2024-5660 for Cortex-X4 ([af65cbb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af65cbb9549765917cf79ab0a819fe58773882ab))
+ - workaround for CVE-2024-5660 for Cortex-X925 ([ebc090f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ebc090fbf47a25a1ef84657d03198fc3a29d28e3))
+ - workaround for CVE-2024-5660 for Neoverse-N2 ([26e0ff9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26e0ff9d5e99b2ea0eedfd202401655ee404e52f))
+ - workaround for CVE-2024-5660 for Neoverse-V1 ([85709f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85709f66194cef32377a32f8e153316648ebb4a9))
+ - workaround for CVE-2024-5660 for Neoverse-V2 ([878464f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/878464f02a043207f29282f05109012152df569b))
+ - workaround for CVE-2024-5660 for Neoverse-V3 ([ad3da01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad3da019904302d9ecfc2cf50dfdd6d672427b5d))
+ - workaround for Neoverse-N2 erratum 3701773 ([adea6e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/adea6e52a782eeabd9027e3ca9a9847a13453cfa))
+ - workaround for Neoverse-N3 erratum 3699563 ([fded839](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fded839285bdbdb72d492a573274abe22edc9311))
+ - workaround for Neoverse-V3 erratum 2970647 ([5f32fd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f32fd2145020b0007b3f12ae6a95b734ff8e6a2))
+ - workaround for Neoverse-V3 erratum 3701767 ([e25fc9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e25fc9df25092be31e7f7a9cc740e8df661a35c1))
+ - workaround for Cortex-A510 erratum 2971420 ([f2bd352](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f2bd35282066f512c26d859aa086cff13955d76b))
+
+ - **EL3 Runtime**
+
+ - add const qualifier ([54c9c68](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54c9c68a49bc7b3aaa29207f798b1973e3cdb542))
+ - add missing curly braces ([858dc35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/858dc35cfde12ddf6250ed393298fa85d01b77d5))
+ - for nested serrors, restore x30 to lower EL address ([0bc3115](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bc3115f6e7b857344c6ac034d74b0fe81d216ed))
+ - replace CTX_ESR_EL3 with CTX_DOUBLE_FAULT_ESR ([c722003](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c72200357aed49fd51dc21e45d4396f5402df811))
+ - make sure LTO doesn't garbage collect the handlers ([f8d2a0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f8d2a0e5caa1b57edf9f7a8e09f9c438a7f3b4be))
+
+ - **Context Management**
+
+ - change back owning security state when a feature is disabled ([13f4a25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/13f4a25251cc6ce0230e999f39a4668cff25dcd0))
+ - don't access a field that doesn't exist ([600717f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/600717fe5909e02a9ec9ee08bcb921a66e653d58))
+ - fix context management SYSREG128 write macros ([6595f4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6595f4cb393090992733eb5e73928424b1e9395a))
+
+ - **RAS**
+
+ - fix status synchronous error type fields ([9c17687](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c17687aabc9e64a26575d5662ef273185d9d275))
+ - fix typo in uncorrectable error type UEO ([e5cd3e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5cd3e81d11cb7f9439e5077cf9063e30fc8c2ae))
+
+ - **SIMD**
+
+ - fix base register in fpregs_context_* ([09ada2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09ada2f8d63fabd1bb01494c2466f647441107b1))
+
+ - **PSCI**
+
+ - add const qualifier ([7b97084](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b970841ad1c9925e72c170734ca30016813743d))
+ - add missing curly braces ([c7b0a28](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7b0a28d32ba78a1bec8fe1f9edbcdc215bf7b1a))
+ - avoid altering function parameters ([e64cdee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e64cdee4dad610e8f4efb873e133a5fffdea397c))
+ - check if a core is the last one in a requested power level ([71d4e03](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71d4e03444f689210803323b437ee15d537fc6ea))
+ - initialise variables ([382ba74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/382ba743a81c9b61d2ab794a22e37af0ac6128fe))
+ - modify variable conflicting with external function ([0839cfc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0839cfc980998d24740e41b44164de39b70079a1))
+
+ - **ROMlib**
+
+ - romlib build without MbedTLS ([e4a070e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4a070e3d6dd0af0e74184333b9238e70c9a7075))
+
+ - **SMCCC**
+
+ - properly set RAS feature bit ([04b80c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04b80c187db3e8d5f0aec6987f1cb2fca2df952d))
+ - register PMUv3p5 and PMUv3p7 bits with the FEATURE_AVAILABILITY call ([2bec665](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2bec665f464b1c211eac594b333656b1dfa4b3da))
+
+ - **Translation Tables**
+
+ - zeromem to clear all tables ([aaacde4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aaacde46826df1dd4a119b2a31ff626adbce5653))
+ - remove xlat_mpu ([23302d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/23302d4a53700a7e6b80a897626bee0d67fad028))
+
+ - **C Standard Library**
+
+ - add const qualifier ([b71d082](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b71d0827aeef53d0ad561da212a7deb102f48c45))
+ - explicitly check operators precedence ([277d7dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/277d7dd6c192f350bc80ccbb65c36562e59f8e07))
+ - make sure __init functions are garbage collected ([53644fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53644fa8221b5c7b726beeda78b253f39abe479b))
+ - remove __Nonnull type specifier ([7ce483e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ce483e17cf14ee285a348d0f0081c89793d010b))
+ - typecast expressions to match data type ([dd0d433](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd0d433197d470e1f50ab28f128ff336e021799f))
+ - typecast operands to match data type ([26cc285](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26cc2854609978fcd6b0450e750b3b319b2468fa))
+
+ - **Locks**
+
+ - add missing curly braces ([bd7ad5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd7ad5e684aafd12c9c5873e4776c4a14e5e5dc0))
+
+ - **PSA**
+
+ - guard Crypto APIs with CRYPTO_SUPPORT ([8a41106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a41106c83961029c2d251f390c091d398c100a6))
+ - increase psa-mbedtls heap size for rsa ([52d2934](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52d293456097beef6a3346b244d4e84f78ef2615))
+
+ - **Firmware Handoff**
+
+ - correct 8-bit modulo csum calculation ([5ca0241](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ca0241c7ac7fc07188281058e052044e8f9ec36))
+ - fix message formatting of hex values ([24e1ae2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24e1ae2f0ed3e2c2be680aad6e88313661bf57ee))
+ - fix register convention in opteed ([c0688c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0688c55bb8b924f1b660ffca1b33bd65cab9990))
+ - remove XFERLIST_TB_FW_CONFIG ([18be2db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18be2dbe001162b424e52072dee74c9b7613a4f2))
+
+- **Drivers**
+
+ - **Console**
+
+ - add missing curly braces ([9ded5e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ded5e8d8be4a5f1f3219742c3790c13156378d8))
+ - typecast expressions to match data type ([97eefd9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/97eefd9989aeb2ce2093e873ceab535df9559a59))
+
+ - **Delay Timer**
+
+ - create unique variable name ([472cccb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/472cccb5f94e26ad72b8a52ab2614203230be20f))
+
+ - **MMC**
+
+ - fix the length of the ocr defines ([e02d365](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e02d365ad9c4102cadb2d8886e3aed327a7512c9))
+ - fix the length of the response type ([7b4b3f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b4b3f243ad3ef099de9aa09a526e7ecccc09c04))
+
+ - **GUID Partition Tables Support**
+
+ - fix MBR header load ([2fac89d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fac89d1267e81e1f4bf0eacf9ea8dbacf80aacb))
+ - initialise the mbr_entry variable ([ec48d52](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec48d52e7890d8e27d1b4419a6a8952d7db777cc))
+
+ - **Arm**
+
+ - add missing curly braces ([03c6bb0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03c6bb0e3822e05da002c69086357c81f853d6f5))
+ - align essential type categories ([bec4a2c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bec4a2c9c3919c4a3012c7a10f4fa75a861f8150))
+ - typecast expression to match data type ([0f76d0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f76d0d57ec700b835e1715200f4520fde1c11c4))
+ - typecast expressions to match data type ([edecc70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/edecc70331ec5e7583972f66f0e8dc6cf039c686))
+
+ - **GIC**
+
+ - quote the correct flag on error ([df21ca0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df21ca08e65b2aeb575e54b155fce1e32908eae6))
+
+ - **GICv3**
+
+ - do not assume redistributors are powered down ([57f2d00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57f2d009fb198181c53f768233f76087ab918ce1))
+
+ - **SMMU**
+
+ - set root port CR0 GPCEN before ACCESSEN ([8cc9724](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8cc972421faf02cfdd4fea1a21fabe6e9d96e2a3))
+
+ - **Renesas**
+
+ - **R-Car3**
+
+ - disable A/B loader support by default ([1a57115](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a5711519a8e685d3db43620623f0f616317cfe9))
+
+ - **ST**
+
+ - **ST PMIC**
+
+ - remove deadcode from STPMIC2 driver ([bdbbf48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdbbf48f4db6fa64079efcd284955a3bf629b705))
+
+- **Miscellaneous**
+
+ - **AArch32**
+
+ - avoid using r12 to store boot params ([af61b50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af61b50c1077b6d936c8ed741c1d0b8e43eb2b19))
+
+ - **FDTs**
+
+ - **ST**
+
+ - **STM32MP1**
+
+ - re-enable RTC clock ([33573ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33573ea6842198cfdb5b3fdd320db9e2045855e9))
+
+ - **STM32MP15**
+
+ - update clocks config for prtt1x board family ([5aeb003](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5aeb0031558b4a9ccff9f097ae651d42d7b850a2))
+
+ - **STM32MP2**
+
+ - fix SDMMC slew rate ([575d6dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/575d6dd7af3644f7c3c9cb34e3fb57d951695023))
+
+ - **Security**
+
+ - add CVE-2024-7881 mitigation to Cortex-X3 ([b0521a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0521a164a8d61c95968e728df9af52be1a48553))
+ - add CVE-2024-7881 mitigation to Cortex-X4 ([6ce6aca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ce6acac911f11979a6cd2ee9cc9041f189c6ec7))
+ - add CVE-2024-7881 mitigation to Cortex-X925 ([520c220](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/520c2207b96d31adf508edc068bb97cd01d98da4))
+ - add CVE-2024-7881 mitigation to Neoverse-V2 ([56bb1d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56bb1d172ccee56e984559de69e8ebd8683d491b))
+ - add CVE-2024-7881 mitigation to Neoverse-V3 ([037a15f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/037a15f5c72e856b8739a2159bd0fe1fe69e1d5b))
+ - add support in cpu_ops for CVE-2024-7881 ([4caef42](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4caef42a94b4efe97b09764a7257f701ab7ff3b8))
+ - apply SMCCC_ARCH_WORKAROUND_4 to affected cpus ([8ae6b1a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ae6b1ad6c9c57b09b6d4e7ae3cbdf3aed6455b1))
+ - enable WORKAROUND_CVE_2024_7881 build option ([2372179](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2372179484741aa81d5451b20748520677205c71))
+
+ - **SDEI**
+
+ - return SDEI_EINVAL if signaling state is incorrect ([b142ede](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b142ede74ceb5fc0b2908d0e7e8e2b2b27b6b1f6))
+
+ - **TBBR**
+
+ - remove tbbr_cot_bl1_r64.c ([a2328f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a2328f2eac83aa9bc10f89d9141ab9bd66338400))
+
+- **Documentation**
+
+ - fix the indent and the build command for MT8188 ([cef56a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cef56a5c6b42b4518af8c48f48a8790542ce3930))
+ - put INIT_UNUSED_NS_EL2 docs back ([4557c0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4557c0c001ba296328e6292a5a2c973581fbeb47))
+ - update the instrumentation procedure ([9b65ffe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b65ffefd673fb2781b808024d13039151c17668))
+
+- **Build System**
+
+ - do not force PLAT in plat_helpers.mk ([422b181](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/422b181faf2fd740e08cf881880015ea47b0cb67))
+ - enable fp during fp save/restore ([5141de1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5141de14432aba7a775c0dd19ecba766d224ec39))
+ - handle invalid spd build options ([a0effb9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0effb91897ff41871cbe2366a54c6e2339246d8))
+ - include platform mk earlier ([696ed16](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/696ed16877a121d07a766af5bb4f8d73a8ac01ae))
+ - run sp_mk_gen.py with poetry ([dd81623](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd816235771e19df1fd04ef2c6f1c6d11e429fd5))
+ - update clang target for aarch64 ([af8947f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af8947fe17d3a29a47573ab0537d121d3653b53e))
+
+- **Tools**
+
+ - change data type to size_t for doimage ([fbf6555](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbf6555790ad6de635ebf9e5581c840496166306))
+
+ - **NXP Tools**
+
+ - fix create_pbl buildroot build ([634c7d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/634c7d8172b7965cf4f5d7d6470a25956ac06ab4))
+ - fix2 create_pbl buildroot build ([bfe7f80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfe7f8018947a960c287f6d8f5ac1efece7261b4))
+
+ - **Certificate Creation Tool**
+
+ - add default keysize to Brainpool ECDSA ([0da16fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0da16fe32f41387f4ad32e96a939c67a3dc8e611))
+ - load openSSL configuration before PKCS11 operations ([785c2c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/785c2c3e8671aa69269bccd3ee968bebd3777a9f))
+
+ - **Firmware Encryption Tool**
+
+ - put build_msg under LOG_LEVEL flag ([7640df6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7640df6f1ef392d664d16aa4d49c67a24421adce))
+
+ - **Renesas Tools**
+
+ - **R-Car Layout Tool**
+
+ - fix tool build ([72f4b70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72f4b70e8e8e656d88bda77605f73076474f5a55))
+
+ - **Transfer List Compiler**
+
+ - add void entries to align data ([03c2660](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03c2660f7556957262c41032064716414572833c))
+ - pass the flags from client interface ([537a25e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/537a25ef7ff6fc95221c70c9543404049143353d))
+ - relax entry addition from YAML files ([f0e15dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0e15ddca303322764e17524396cb2da2c1c5ccc))
+
+- **Dependencies**
+
+ - remove deprecated husky commands ([b47dddd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b47dddd061e92054c3b2096fc8aa9688bfef68d6))
+
## [2.12.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.11.0..refs/tags/v2.12.0) (2024-11-19)
The threat model for context management and the asymmetric CPU extension support
@@ -10792,7 +11989,7 @@
______________________________________________________________________
-*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.*
[mbed tls releases]: https://tls.mbed.org/tech-updates/releases
[pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index 1ff2037..6a07271 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -747,7 +747,10 @@
fid,x0,[63:0],UInt64,Command FID
ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
- Keyset[12]:Dir[11]:Substream[10:8]:StreamID[7:0],x3,[63:0],UInt64,IDE selective stream informationKey set: can be 0 or 1unused bits MBZ.
+ "Keyset[12]:
+ Dir[11]:
+ Substream[10:8]:
+ StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream informationKey set: can be 0 or 1unused bits MBZ.
KeqQW0,x4,[63:0],UInt64,Quad word of key [63:0]
KeqQW1,x5,[63:0],UInt64,Quad word of key [127:64]
KeqQW2,x6,[63:0],UInt64,Quad word of key [191:128]
@@ -763,7 +766,7 @@
.. csv-table:: Output values for RMM_IDE_KEY_PROG
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
@@ -777,10 +780,10 @@
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key programming is successful.
- ``E_RMM_FAULT``,Key programming is not successful.
- ``E_RMM_INVAL``,Key programming arguments are incorrect.
- ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6
+ ``E_RMM_OK``,The Key programming is successful.
+ ``E_RMM_FAULT``,The Key programming is not successful.
+ ``E_RMM_INVAL``,The Key programming arguments are incorrect.
+ ``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
@@ -811,7 +814,10 @@
fid,x0,[63:0],UInt64,Command FID
ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
- Keyset[12]:Dir[11]:Substream[10:8]:StreamID[7:0],x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
+ "Keyset[12]:
+ Dir[11]:
+ Substream[10:8]:
+ StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
request_id,x4,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
cookie,x5,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
@@ -821,7 +827,7 @@
.. csv-table:: Output values for RMM_IDE_KEY_SET_GO
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
@@ -835,9 +841,9 @@
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key set go is successful.
- ``E_RMM_FAULT``,Key set go is not successful.
- ``E_RMM_INVAL``,incorrect arguments.
+ ``E_RMM_OK``,The Key set go is successful.
+ ``E_RMM_FAULT``,The Key set go is not successful.
+ ``E_RMM_INVAL``,Incorrect arguments.
``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
@@ -869,7 +875,10 @@
fid,x0,[63:0],UInt64,Command FID
ecam_address,x1,[63:0],UInt64,Used to identify the root complex(RC)
rp_id,x2,[63:0],UInt64,Used to identify the root port within the root complex(RC)
- Keyset[12]:Dir[11]:Substream[10:8]:StreamID[7:0],x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
+ "Keyset[12]:
+ Dir[11]:
+ Substream[10:8]:
+ StreamID[7:0]",x3,[63:0],UInt64,IDE selective stream information. Key set can be 0 or 1. Unused bits MBZ.
request_id,x4,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
cookie,x5,[63:0],UInt64,Used only in non-blocking mode. Ignored in blocking mode.
@@ -879,7 +888,7 @@
.. csv-table:: Output values for RMM_IDE_KEY_SET_STOP
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
@@ -893,9 +902,9 @@
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key set go is successful.
- ``E_RMM_FAULT``,Key set go is not successful.
- ``E_RMM_INVAL``,incorrect arguments.
+ ``E_RMM_OK``,The Key set stop is successful.
+ ``E_RMM_FAULT``,The Key set stop is not successful.
+ ``E_RMM_INVAL``,Incorrect arguments.
``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
``E_RMM_AGAIN``,Returned only for non-blocking mode. IDE-KM interface is busy or request is full. Retry required.
``E_RMM_INPROGRESS``,Returned only for non-blocking mode. The caller must issue RMM_IDE_KM_PULL_RESPONSE SMC to pull the response.
@@ -936,7 +945,7 @@
.. csv-table:: Output values for RMM_IDE_KM_PULL_RESPONSE
:header: "Name", "Register", "Field", "Type", "Description"
- :widths: 1 1 1 2 4
+ :widths: 1 1 1 1 5
Result,x0,[63:0],Error Code,Command return status
Result,x1,[63:0],Error Code,Retrieved response corresponding to previous IDE_KM requests.
@@ -949,16 +958,23 @@
The table below shows all the possible error codes returned in ``Result`` upon
a failure. The errors are ordered by condition check.
-.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE
+.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE(x0)
:header: "ID", "Condition"
:widths: 1 5
- ``E_RMM_OK``,Key set go is successful.
- ``E_RMM_FAULT``,Key set go is not successful.
- ``E_RMM_INVAL``,incorrect arguments.
+ ``E_RMM_OK``,Response is retrieved successfully.
+ ``E_RMM_INVAL``,Arguments to pull response SMC is not correct.
``E_RMM_UNK``,Unknown error or the SMC is not present if the version is < 0.6.
- ``E_RMM_AGAIN``,KM request is empty and no response if available.
+ ``E_RMM_AGAIN``,IDE-KM response queue is empty and no response is available.
+
+.. csv-table:: Failure conditions for RMM_IDE_KM_PULL_RESPONSE(x1)
+ :header: "ID", "Condition"
+ :widths: 1 5
+ ``E_RMM_OK``,The previous request was successful.
+ ``E_RMM_FAULT``,The previous request was not successful.
+ ``E_RMM_INVAL``,Arguments to previous request were incorrect.
+ ``E_RMM_UNK``,Previous request returned unknown error.
RMM-EL3 world switch register save restore convention
_____________________________________________________
diff --git a/docs/components/ven-el3-service.rst b/docs/components/ven-el3-service.rst
index 13449ba..8be1b39 100644
--- a/docs/components/ven-el3-service.rst
+++ b/docs/components/ven-el3-service.rst
@@ -32,9 +32,13 @@
+-----------------------------------+ Measurement Framework | | 2 - 15 are reserved for future expansion. |
| 0xC7000020 - 0xC700002F (SMC64) | (PMF) | |
+-----------------------------------+-----------------------+---------------------------------------------+
-| 0x87000030 - 0x8700FFFF (SMC32) | Reserved | | reserved for future expansion |
+| 0x87000030 - 0x8700003F (SMC32) | ACS (Architecture | | 0 in use. |
++-----------------------------------+ Compliance Suite) SMC | | 1 - 15 are reserved for future expansion. |
+| 0xC7000030 - 0xC700003F (SMC64) | handler | |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000040 - 0x8700FFFF (SMC32) | Reserved | | reserved for future expansion |
+-----------------------------------+ | |
-| 0xC7000030 - 0xC700FFFF (SMC64) | | |
+| 0xC7000040 - 0xC700FFFF (SMC64) | | |
+-----------------------------------+-----------------------+---------------------------------------------+
Source definitions for vendor-specific EL3 Monitor Service Calls used by TF-A are located in
@@ -45,6 +49,8 @@
+============================+============================+================================+
| 1 | 0 | Added Debugfs and PMF services.|
+----------------------------+----------------------------+--------------------------------+
+| 1 | 1 | Added ACS SMC handler services.|
++----------------------------+----------------------------+--------------------------------+
*Table 1: Showing different versions of Vendor-specific service and changes done with each version*
@@ -71,8 +77,16 @@
The optional DebugFS interface is accessed through Vendor specific EL3 service. Refer
to :ref:`DebugFS interface` documentation for further details and usage.
+Architecture Compliance Suite (ACS) SMC handler
+-----------------------------------------------
+
+The Architecture Compliance Suite (ACS) SMC handler allows callers to branch
+to their ACS EL3 code based on their respective use-cases.
+For more details on System ACS, `System ACS`_.
+
--------------
-*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.*
+.. _System ACS: https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
diff --git a/docs/conf.py b/docs/conf.py
index 3a7264f..6e08030 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -1,6 +1,6 @@
# -*- coding: utf-8 -*-
#
-# Copyright (c) 2019-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -14,8 +14,8 @@
project = "Trusted Firmware-A"
author = "Trusted Firmware-A contributors"
-version = "2.12.0"
-release = "2.12.0"
+version = "2.13.0"
+release = "2.13.0"
# -- General configuration ---------------------------------------------------
diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst
index 1f76770..a9d2fa9 100644
--- a/docs/design_documents/measured_boot.rst
+++ b/docs/design_documents/measured_boot.rst
@@ -231,9 +231,9 @@
- Public key data size is passed as the third argument to this function.
- This function must return 0 on success, a signed integer error code
otherwise.
- - In TC2 platform, this function is used to calculate the hash of the given
- key and forward this hash to |RSE| alongside the measurement of the image
- which the key signs.
+ - In Total Compute platform, this function is used to calculate the hash
+ of the given key and forward this hash to |RSE| alongside the measurement
+ of the image which the key signs.
--------------
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index e5f7b30..c30caac 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -405,6 +405,12 @@
flag can take values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
+- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR``
+ extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4
+ onwards. This feature requires PAUTH to be enabled via the
+ ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align
+ with the ``ENABLE_FEAT`` mechanism. Default value is ``0``.
+
- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension.
``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This
flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
@@ -1190,11 +1196,6 @@
cluster platforms). If this option is enabled, then warm boot path
enables D-caches immediately after enabling MMU. This option defaults to 0.
-- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
- tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
- default value of this flag is ``no``. Note this option must be enabled only
- for ARM architecture greater than Armv8.5-A.
-
- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
The default value of this flag is ``0``.
@@ -1503,6 +1504,11 @@
information using HOB defined in `Platform Initialization specification`_.
This defaults to ``0``.
+- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC
+ handler code to handle SMC calls from the Architecture Compliance Suite. The
+ handler is intentionally empty to reserve the SMC section and allow
+ project-specific implementations in future ACS use cases.
+
Firmware update options
~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index 54e29dd..e11da77 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -42,7 +42,7 @@
.. code:: shell
- poetry run make doc
+ make doc
Output from the build process will be placed in: ``docs/build/html``.
@@ -55,7 +55,7 @@
.. code:: shell
- poetry run make -C docs help
+ make -C docs help
To build the documentation in PDF format, additionally ensure that the following
packages are installed:
@@ -80,9 +80,10 @@
Building rendered documentation from Poetry's virtual environment
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The command ``poetry run`` used in the steps above executes the input command
-from inside the project's virtual environment. The easiest way to activate this
-virtual environment is with the ``poetry shell`` command.
+If Poetry is installed, the ``doc`` target wraps its build steps with ``poetry
+run``, which runs the specified command within the project's virtual
+environment. The easiest way to activate this environment manually is by using
+the ``poetry shell`` command.
Running ``poetry shell`` from the directory containing this project, activates
the same virtual environment. This creates a sub-shell through which you can
@@ -91,7 +92,7 @@
.. code:: shell
poetry shell
- make doc
+ make -C docs html
Type ``exit`` to deactivate the virtual environment and exit this new shell. For
other use cases, please see the official `Poetry`_ documentation.
@@ -121,7 +122,7 @@
--------------
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
.. _Sphinx: http://www.sphinx-doc.org/en/master/
.. _Poetry: https://python-poetry.org/docs/
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index 9640a24..45c1922 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -31,40 +31,14 @@
The following source trees and binaries were used:
-- `TF-A v2.12-rc0`_
-- `TFTF v2.12-rc0`_
+- `TF-A v2.13-rc0`_
+- `TFTF v2.13-rc0`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
<Runtime Instrumentation Methodology>`
-page for more details.
-
-Procedure
----------
-
-#. Build TFTF with runtime instrumentation enabled:
-
- .. code:: shell
-
- make CROSS_COMPILE=aarch64-none-elf- PLAT=juno \
- TESTS=runtime-instrumentation all
-
-#. Fetch Juno's SCP binary from TF-A's archive:
-
- .. code:: shell
-
- curl --fail --connect-timeout 5 --retry 5 -sLS -o scp_bl2.bin \
- https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/juno/release/juno-bl2.bin
-
-#. Build TF-A with the following build options:
-
- .. code:: shell
-
- make CROSS_COMPILE=aarch64-none-elf- PLAT=juno \
- BL33="/path/to/tftf.bin" SCP_BL2="scp_bl2.bin" \
- ENABLE_RUNTIME_INSTRUMENTATION=1 fiptool all fip
-
-#. Load the following images onto the development board: ``fip.bin``,
- ``scp_bl2.bin``.
+page for more details. The tests were ran using the
+`tf-psci-lava-instr/juno-enable-runtime-instr,juno-instrumentation:juno-tftf`
+configuration in CI.
Results
-------
@@ -73,6 +47,25 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
+ parallel (v2.13)
+
+ +---------+------+------------------+-------------------+--------------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+------------------+-------------------+--------------------+
+ | 0 | 0 | 333.0 (-52.92%) | 23.92 (-40.11%) | 138.88 |
+ +---------+------+------------------+-------------------+--------------------+
+ | 0 | 1 | 630.9 (+145.95%) | 253.72 (-46.56%) | 136.94 (+1987.50%) |
+ +---------+------+------------------+-------------------+--------------------+
+ | 1 | 0 | 184.74 (+71.92%) | 23.16 (-95.39%) | 80.24 (+1283.45%) |
+ +---------+------+------------------+-------------------+--------------------+
+ | 1 | 1 | 481.14 | 18.56 (-88.25%) | 76.5 (+1520.76%) |
+ +---------+------+------------------+-------------------+--------------------+
+ | 1 | 2 | 933.88 (+67.76%) | 289.58 (+189.64%) | 76.34 (+1510.55%) |
+ +---------+------+------------------+-------------------+--------------------+
+ | 1 | 3 | 1112.48 | 238.42 (+753.94%) | 76.38 |
+ +---------+------+------------------+-------------------+--------------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
parallel (v2.12)
+---------+------+-------------------+------------------+--------------------+
@@ -92,23 +85,23 @@
+---------+------+-------------------+------------------+--------------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- parallel (v2.11)
+ serial (v2.13)
- +---------+------+-------------------+--------------------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-------------------+--------------------+-------------+
- | 0 | 0 | 112.98 (-53.44%) | 26.16 (-89.33%) | 5.48 |
- +---------+------+-------------------+--------------------+-------------+
- | 0 | 1 | 411.18 | 438.88 (+1572.56%) | 138.54 |
- +---------+------+-------------------+--------------------+-------------+
- | 1 | 0 | 261.82 (+150.88%) | 474.06 (+1649.30%) | 5.6 |
- +---------+------+-------------------+--------------------+-------------+
- | 1 | 1 | 714.76 (+86.84%) | 26.44 | 4.48 |
- +---------+------+-------------------+--------------------+-------------+
- | 1 | 2 | 862.66 | 149.34 (-45.00%) | 4.38 |
- +---------+------+-------------------+--------------------+-------------+
- | 1 | 3 | 1045.12 | 98.12 (-55.76%) | 79.74 |
- +---------+------+-------------------+--------------------+-------------+
+ +---------+------+------------------+-----------------+-------------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+------------------+-----------------+-------------------+
+ | 0 | 0 | 244.08 | 24.48 (-40.00%) | 137.64 |
+ +---------+------+------------------+-----------------+-------------------+
+ | 0 | 1 | 244.2 | 23.84 (-41.57%) | 137.86 |
+ +---------+------+------------------+-----------------+-------------------+
+ | 1 | 0 | 294.78 | 23.54 | 76.62 |
+ +---------+------+------------------+-----------------+-------------------+
+ | 1 | 1 | 180.1 (+74.72%) | 21.14 | 77.12 (+1533.90%) |
+ +---------+------+------------------+-----------------+-------------------+
+ | 1 | 2 | 180.54 (+75.25%) | 20.8 | 76.76 (+1554.31%) |
+ +---------+------+------------------+-----------------+-------------------+
+ | 1 | 3 | 180.6 (+75.44%) | 21.2 | 76.86 (+1542.31%) |
+ +---------+------+------------------+-----------------+-------------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
serial (v2.12)
@@ -129,29 +122,29 @@
| 1 | 3 | 100.96 | 22.54 | 4.38 |
+---------+------+-----------+-----------------+-------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- serial (v2.11)
-
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 244.42 | 27.42 | 138.12 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 245.02 | 27.34 | 138.08 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 297.66 | 26.2 | 77.68 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 108.02 | 21.94 | 4.52 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 107.48 | 21.88 | 4.46 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 107.52 | 21.86 | 4.46 |
- +---------+------+-----------+--------+-------------+
-
``CPU_SUSPEND`` to power level 0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
+ parallel (v2.13)
+
+ +---------+------+-------------------+-----------------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-------------------+-----------------+-------------+
+ | 0 | 0 | 703.06 | 16.86 (-47.87%) | 7.98 |
+ +---------+------+-------------------+-----------------+-------------+
+ | 0 | 1 | 851.88 | 16.4 (-49.41%) | 8.04 |
+ +---------+------+-------------------+-----------------+-------------+
+ | 1 | 0 | 407.4 (+58.99%) | 15.1 (-26.20%) | 7.2 |
+ +---------+------+-------------------+-----------------+-------------+
+ | 1 | 1 | 110.98 (-72.67%) | 15.46 | 6.56 |
+ +---------+------+-------------------+-----------------+-------------+
+ | 1 | 2 | 554.54 | 15.4 | 6.94 |
+ +---------+------+-------------------+-----------------+-------------+
+ | 1 | 3 | 258.96 (+143.06%) | 15.56 (-25.05%) | 6.64 |
+ +---------+------+-------------------+-----------------+-------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
parallel (v2.12)
+--------------------------------------------------------------------+
@@ -172,24 +165,23 @@
| 1 | 3 | 523.36 (+391.23%) | 19.0 | 7.3 |
+---------+------+-------------------+-----------------+-------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
- parallel (v2.11)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.13)
- +---------+------+-------------------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-------------------+--------+-------------+
- | 0 | 0 | 704.46 | 19.28 | 7.86 |
- +---------+------+-------------------+--------+-------------+
- | 0 | 1 | 853.66 | 18.78 | 7.82 |
- +---------+------+-------------------+--------+-------------+
- | 1 | 0 | 556.52 (+425.51%) | 19.06 | 7.82 |
- +---------+------+-------------------+--------+-------------+
- | 1 | 1 | 113.28 (-70.47%) | 19.28 | 7.48 |
- +---------+------+-------------------+--------+-------------+
- | 1 | 2 | 260.62 (-50.22%) | 19.8 | 7.26 |
- +---------+------+-------------------+--------+-------------+
- | 1 | 3 | 408.16 (+66.94%) | 19.82 | 7.38 |
- +---------+------+-------------------+--------+-------------+
+ +---------+------+-----------+-----------------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-----------+-----------------+-------------+
+ | 0 | 0 | 106.12 | 17.1 (-48.24%) | 5.26 |
+ +---------+------+-----------+-----------------+-------------+
+ | 0 | 1 | 106.88 | 17.06 (-47.08%) | 5.28 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 0 | 294.36 | 15.6 | 4.56 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 1 | 103.26 | 15.44 | 4.46 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 2 | 103.7 | 15.26 | 4.5 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 3 | 103.68 | 15.72 | 4.5 |
+ +---------+------+-----------+-----------------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.12)
@@ -209,30 +201,30 @@
| 1 | 3 | 97.52 | 19.46 | 4.26 |
+---------+------+-----------+-----------------+-------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
-
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 106.78 | 19.2 | 5.32 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 107.44 | 19.64 | 5.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 295.82 | 19.14 | 4.34 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 104.34 | 19.18 | 4.28 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 103.96 | 19.34 | 4.4 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 104.32 | 19.18 | 4.34 |
- +---------+------+-----------+--------+-------------+
-
``CPU_OFF`` on all non-lead CPUs
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.13)
+
+ +---------+------+-----------+-----------------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-----------+-----------------+-------------+
+ | 0 | 0 | 243.02 | 26.42 (-39.51%) | 137.58 |
+ +---------+------+-----------+-----------------+-------------+
+ | 0 | 1 | 244.24 | 26.32 (-38.93%) | 137.88 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 0 | 182.36 | 23.66 | 78.0 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 1 | 108.18 | 22.68 | 4.42 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 2 | 108.34 | 21.72 | 4.24 |
+ +---------+------+-----------+-----------------+-------------+
+ | 1 | 3 | 108.22 | 21.68 | 4.34 |
+ +---------+------+-----------+-----------------+-------------+
+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.12)
+---------+------+-----------+-----------------+-------------+
@@ -251,61 +243,43 @@
| 1 | 3 | 101.08 | 26.74 | 4.4 |
+---------+------+-----------+-----------------+-------------+
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
-
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 243.62 | 29.84 | 137.66 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 243.88 | 29.54 | 137.8 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 183.26 | 26.22 | 77.76 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 107.64 | 26.74 | 4.34 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 107.52 | 25.9 | 4.32 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 107.74 | 25.8 | 4.34 |
- +---------+------+-----------+--------+-------------+
-
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.12)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.13)
+-------------+--------+--------------+
| Cluster | Core | Latency |
+-------------+--------+--------------+
| 0 | 0 | 1.0 |
+-------------+--------+--------------+
- | 0 | 1 | 1.02 |
+ | 0 | 1 | 1.06 |
+-------------+--------+--------------+
- | 1 | 0 | 0.52 |
+ | 1 | 0 | 0.6 |
+-------------+--------+--------------+
- | 1 | 1 | 0.94 |
+ | 1 | 1 | 1.0 |
+-------------+--------+--------------+
- | 1 | 2 | 0.94 |
+ | 1 | 2 | 0.98 |
+-------------+--------+--------------+
- | 1 | 3 | 0.92 |
+ | 1 | 3 | 1.0 |
+-------------+--------+--------------+
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.11)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.12)
+-------------+--------+--------------+
| Cluster | Core | Latency |
+-------------+--------+--------------+
- | 0 | 0 | 1.26 |
+ | 0 | 0 | 1.0 |
+-------------+--------+--------------+
- | 0 | 1 | 0.96 |
+ | 0 | 1 | 1.02 |
+-------------+--------+--------------+
- | 1 | 0 | 0.54 |
+ | 1 | 0 | 0.52 |
+-------------+--------+--------------+
| 1 | 1 | 0.94 |
+-------------+--------+--------------+
- | 1 | 2 | 0.92 |
+ | 1 | 2 | 0.94 |
+-------------+--------+--------------+
- | 1 | 3 | 1.02 |
+ | 1 | 3 | 0.92 |
+-------------+--------+--------------+
Annotated Historic Results
@@ -526,9 +500,9 @@
--------------
-*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.*
.. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
-.. _TF-A v2.12-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.12-rc0
-.. _TFTF v2.12-rc0: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/?h=v2.12-rc0
+.. _TF-A v2.13-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.13-rc0
+.. _TFTF v2.13-rc0: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/?h=v2.13-rc0
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index 178d8e6..196cdb1 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -4,87 +4,16 @@
For this test we used the N1 System Development Platform (`N1SDP`_), which
contains an SoC consisting of two dual-core Arm N1 clusters.
-The following source trees and binaries were used:
+The following source trees were used:
-- `TF-A v2.12-rc0`_
-- `TFTF v2.12-rc0`_
-- SCP/MCP `Prebuilt Images`_
+- `TF-A v2.13-rc0`_
+- `TFTF v2.13-rc0`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
-<Runtime Instrumentation Methodology>` page for more details.
-
-Procedure
----------
-
-#. Build TFTF with runtime instrumentation enabled:
-
- .. code:: shell
-
- make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
- TESTS=runtime-instrumentation all
-
-#. Build TF-A with the following build options:
-
- .. code:: shell
-
- make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
- ENABLE_RUNTIME_INSTRUMENTATION=1 fiptool all
-
-#. Fetch the SCP firmware images:
-
- .. code:: shell
-
- curl --fail --connect-timeout 5 --retry 5 \
- -sLS -o build/n1sdp/release/scp_rom.bin \
- https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-bl1.bin
- curl --fail --connect-timeout 5 \
- --retry 5 -sLS -o build/n1sdp/release/scp_ram.bin \
- https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-bl2.bin
-
-#. Fetch the MCP firmware images:
-
- .. code:: shell
-
- curl --fail --connect-timeout 5 --retry 5 \
- -sLS -o build/n1sdp/release/mcp_rom.bin \
- https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-mcp-bl1.bin
- curl --fail --connect-timeout 5 --retry 5 \
- -sLS -o build/n1sdp/release/mcp_ram.bin \
- https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-mcp-bl2.bin
-
-#. Using the fiptool, create a new FIP package and append the SCP ram image onto
- it.
-
- .. code:: shell
-
- ./tools/fiptool/fiptool create --blob \
- uuid=cfacc2c4-15e8-4668-82be-430a38fad705,file=build/n1sdp/release/bl1.bin \
- --scp-fw build/n1sdp/release/scp_ram.bin build/n1sdp/release/scp_fw.bin
-
-#. Append the MCP image to the FIP.
-
- .. code:: shell
-
- ./tools/fiptool/fiptool create \
- --blob uuid=54464222-a4cf-4bf8-b1b6-cee7dade539e,file=build/n1sdp/release/mcp_ram.bin \
- build/n1sdp/release/mcp_fw.bin
-
-#. Then, add TFTF as the Non-Secure workload in the FIP image:
-
- .. code:: shell
-
- make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
- ENABLE_RUNTIME_INSTRUMENTATION=1 SCP_BL2=/dev/null \
- BL33=<path/to/tftf.bin> fip
-
-#. Load the following images onto the development board: ``fip.bin``,
- ``scp_rom.bin``, ``scp_ram.bin``, ``mcp_rom.bin``, and ``mcp_ram.bin``.
-
-.. note::
-
- These instructions presume you have a complete firmware stack. The N1SDP
- `user guide`_ provides a detailed explanation on how to get setup from
- scratch.
+<Runtime Instrumentation Methodology>` page for more details. The tests were ran
+using the
+`tf-psci-lava-instr/n1sdp-runtime-instrumentation,n1sdp-runtime-instrumentation:n1sdp-fip.tftf-firmware`
+configuration in CI.
Results
-------
@@ -92,6 +21,20 @@
``CPU_SUSPEND`` to deepest power level
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.13)
+
+ +---------+------+----------------+-----------------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+-----------------+----------------+
+ | 0 | 0 | 3.32 | 13.42 (-45.40%) | 0.28 (-69.57%) |
+ +---------+------+----------------+-----------------+----------------+
+ | 0 | 0 | 4.02 (-35.78%) | 18.14 (-52.88%) | 0.28 |
+ +---------+------+----------------+-----------------+----------------+
+ | 1 | 0 | 2.7 (-27.42%) | 17.38 (-49.36%) | 0.26 |
+ +---------+------+----------------+-----------------+----------------+
+ | 1 | 0 | 2.96 | 10.86 (-73.64%) | 0.26 |
+ +---------+------+----------------+-----------------+----------------+
+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.12)
+---------+------+----------------+--------+----------------+
@@ -106,19 +49,19 @@
| 1 | 0 | 3.28 | 42.36 | 0.3 |
+---------+------+----------------+--------+----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.11)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.13)
- +---------+------+----------------+--------+----------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+----------------+--------+----------------+
- | 0 | 0 | 3.0 (+41.51%) | 23.14 | 1.2 (+185.71%) |
- +---------+------+----------------+--------+----------------+
- | 0 | 0 | 4.6 | 35.86 | 0.3 |
- +---------+------+----------------+--------+----------------+
- | 1 | 0 | 3.68 (+33.33%) | 33.36 | 0.3 |
- +---------+------+----------------+--------+----------------+
- | 1 | 0 | 3.7 (+40.15%) | 38.1 | 0.28 |
- +---------+------+----------------+--------+----------------+
+ +---------+------+-----------+-----------------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-----------+-----------------+----------------+
+ | 0 | 0 | 1.62 | 10.14 (-58.10%) | 0.3 |
+ +---------+------+-----------+-----------------+----------------+
+ | 0 | 0 | 1.86 | 10.62 (-56.44%) | 0.28 (-26.32%) |
+ +---------+------+-----------+-----------------+----------------+
+ | 1 | 0 | 1.8 | 10.16 (-57.84%) | 0.32 |
+ +---------+------+-----------+-----------------+----------------+
+ | 1 | 0 | 2.16 | 10.6 (-56.84%) | 0.5 (+56.25%) |
+ +---------+------+-----------+-----------------+----------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.12)
@@ -134,23 +77,23 @@
| 1 | 0 | 2.24 | 23.84 | 0.36 |
+---------+------+-----------+--------+-------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.11)
-
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.7 | 22.46 | 0.3 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.28 | 22.5 | 0.3 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 2.14 | 21.5 | 0.32 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 2.24 | 22.66 | 0.3 |
- +---------+------+-----------+--------+-------------+
-
``CPU_SUSPEND`` to power level 0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.13)
+
+ +---------+------+----------------+-----------------+---------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+-----------------+---------------+
+ | 0 | 0 | 0.8 (-57.45%) | 11.98 (-61.75%) | 0.26 |
+ +---------+------+----------------+-----------------+---------------+
+ | 0 | 0 | 1.54 (-30.63%) | 16.44 (-53.74%) | 0.26 |
+ +---------+------+----------------+-----------------+---------------+
+ | 1 | 0 | 1.62 (-30.77%) | 16.1 (-53.92%) | 0.3 |
+ +---------+------+----------------+-----------------+---------------+
+ | 1 | 0 | 1.8 | 10.54 (-55.30%) | 0.2 (-33.33%) |
+ +---------+------+----------------+-----------------+---------------+
+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.12)
+---------+------+-----------+--------+----------------+
@@ -165,19 +108,19 @@
| 1 | 0 | 2.08 | 23.38 | 0.28 |
+---------+------+-----------+--------+----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.11)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.13)
- +---------+------+----------------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+----------------+--------+-------------+
- | 0 | 0 | 0.94 (-37.33%) | 30.36 | 0.3 |
- +---------+------+----------------+--------+-------------+
- | 0 | 0 | 2.12 | 33.12 | 0.28 |
- +---------+------+----------------+--------+-------------+
- | 1 | 0 | 2.08 | 32.56 | 0.3 |
- +---------+------+----------------+--------+-------------+
- | 1 | 0 | 2.14 | 21.92 | 0.28 |
- +---------+------+----------------+--------+-------------+
+ +---------+------+----------------+-----------------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+-----------------+----------------+
+ | 0 | 0 | 1.44 | 9.9 (-58.05%) | 0.3 |
+ +---------+------+----------------+-----------------+----------------+
+ | 0 | 0 | 1.74 (-25.64%) | 10.4 (-56.23%) | 0.28 (-33.33%) |
+ +---------+------+----------------+-----------------+----------------+
+ | 1 | 0 | 1.8 | 10.04 (-57.71%) | 0.34 |
+ +---------+------+----------------+-----------------+----------------+
+ | 1 | 0 | 1.96 | 10.46 (-56.23%) | 0.44 |
+ +---------+------+----------------+-----------------+----------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.12)
@@ -193,26 +136,26 @@
| 1 | 0 | 2.16 | 23.92 | 0.34 |
+---------+------+-----------+--------+----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
-
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.64 | 21.88 | 0.34 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.42 | 21.76 | 0.34 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 2.02 | 21.14 | 0.32 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 2.18 | 22.3 | 0.34 |
- +---------+------+-----------+--------+-------------+
-
``CPU_OFF`` on all non-lead CPUs
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.13)
+
+ +---------+------+-----------+-----------------+---------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-----------+-----------------+---------------+
+ | 0 | 0 | 1.64 | 10.24 (-57.72%) | 0.3 |
+ +---------+------+-----------+-----------------+---------------+
+ | 0 | 0 | 13.92 | 17.7 (-43.74%) | 0.3 |
+ +---------+------+-----------+-----------------+---------------+
+ | 1 | 0 | 13.54 | 16.74 (-44.90%) | 0.3 (-37.50%) |
+ +---------+------+-----------+-----------------+---------------+
+ | 1 | 0 | 14.12 | 18.28 (-41.93%) | 0.3 (-44.44%) |
+ +---------+------+-----------+-----------------+---------------+
+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.12)
+---------+------+-----------+--------+----------------+
@@ -227,22 +170,21 @@
| 1 | 0 | 14.18 | 31.82 | 0.68 |
+---------+------+-----------+--------+----------------+
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
-
- +---------+------+-----------+--------+----------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+----------------+
- | 0 | 0 | 1.96 | 22.44 | 0.38 |
- +---------+------+-----------+--------+----------------+
- | 0 | 0 | 13.76 | 30.34 | 0.26 |
- +---------+------+-----------+--------+----------------+
- | 1 | 0 | 13.46 | 28.28 | 0.24 |
- +---------+------+-----------+--------+----------------+
- | 1 | 0 | 13.84 | 30.06 | 0.28 (-60.00%) |
- +---------+------+-----------+--------+----------------+
-
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.13)
+
+ +----------+------+-------------------+
+ | Cluster | Core | Latency |
+ +----------+------+-------------------+
+ | 0 | 0 | 0.12 |
+ +----------+------+-------------------+
+ | 0 | 0 | 0.2 (-28.57%) |
+ +----------+------+-------------------+
+ | 1 | 0 | 0.2 |
+ +----------+------+-------------------+
+ | 1 | 0 | 0.24 (-25.00%) |
+ +----------+------+-------------------+
.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.12)
@@ -258,26 +200,11 @@
| 1 | 0 | 0.26 |
+----------+------+-------------------+
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.11)
-
- +-------------+--------+--------------+
- | Cluster | Core | Latency |
- +-------------+--------+--------------+
- | 0 | 0 | 0.12 |
- +-------------+--------+--------------+
- | 0 | 0 | 0.24 |
- +-------------+--------+--------------+
- | 1 | 0 | 0.2 |
- +-------------+--------+--------------+
- | 1 | 0 | 0.26 |
- +-------------+--------+--------------+
-
--------------
-*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2025, Arm Limited. All rights reserved.*
-.. _TF-A v2.12-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.12-rc0
-.. _TFTF v2.12-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.12-rc0
+.. _TF-A v2.13-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.13-rc0
+.. _TFTF v2.13-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.13-rc0
.. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
-.. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/
.. _N1SDP: https://developer.arm.com/documentation/101489/latest
diff --git a/docs/plat/arm/fvp/fvp-build-options.rst b/docs/plat/arm/fvp/fvp-build-options.rst
index 79dc0dc..8edcdb7 100644
--- a/docs/plat/arm/fvp/fvp-build-options.rst
+++ b/docs/plat/arm/fvp/fvp-build-options.rst
@@ -41,6 +41,9 @@
HW_CONFIG blob instead of the DTS file. This option is useful to override
the default HW_CONFIG selected by the build system.
+- ``FVP_HW_CONFIG_ADDR`` : Specify the memory address in which to load the
+ HW_CONFIG. The default value is ``0x82000000``.
+
- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
inactive/fused CPU cores as read-only. The default value of this option
is ``0``, which means the redistributor pages of all CPU cores are marked
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index 1e37696..e241f57 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -56,7 +56,7 @@
#. Obtain SCP binaries (Juno)
- This version of TF-A is tested with SCP version 2.15.0 on Juno. You can
+ This version of TF-A is tested with SCP version 2.14.0 on Juno. You can
download pre-built SCP binaries (``scp_bl1.bin`` and ``scp_bl2.bin``)
from `TF-A downloads page`_. Alternatively, you can `build
the binaries from source`_.
@@ -241,11 +241,11 @@
--------------
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
.. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/
.. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst
-.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.15.0/juno/
+.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.14.0/juno/
.. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
.. _Juno Getting Started Guide: https://developer.arm.com/documentation/den0928/f/?lang=en
diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst
index 467738c..d57b48e 100644
--- a/docs/plat/arm/tc/index.rst
+++ b/docs/plat/arm/tc/index.rst
@@ -17,12 +17,8 @@
the Total Compute platform number. The platforms support the CPU variants
listed as below:
-- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
-- TC1 has support for Cortex A510, Cortex A715 and Cortex X3. (Note TC1 is now deprecated)
-- TC2 has support for Cortex A520, Cortex A720 and Cortex x4. (Note TC2 is now deprecated)
- TC3 has support for Cortex A520, Cortex A725 and Cortex x925.
-
Boot Sequence
-------------
@@ -59,6 +55,6 @@
--------------
-*Copyright (c) 2020-2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2020-2025, Arm Limited. All rights reserved.*
.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index d0d6889..a30f55d 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -72,7 +72,7 @@
+----------------+----------------+--------------------+--------------------+
| Platform | Vendor | Deprecated version | Deleted version |
+================+================+====================+====================+
-| TC2 | Arm | 2.12 | TBD |
+| TC2 | Arm | 2.12 | 2.13 |
| | | | |
+----------------+----------------+--------------------+--------------------+
| fvp_r | Arm | 2.13 | 2.13 |
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 87bb6a5..e64b989 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst
@@ -12,6 +12,43 @@
STM32MP2 Versions
-----------------
+Here are the variants for STM32MP2:
+- STM32MP21
+- STM32MP23
+- STM32MP25
+
+STM32MP21 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP21 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - CSI - LTDC
+- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP23 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP23 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - H264 - 3D GPU - AI / NN - LVDS / DSI
+- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP25 Versions
+~~~~~~~~~~~~~~~~~~
The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
@@ -70,6 +107,10 @@
- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
| Default: 1
+- | ``STM32MP21``: to select STM32MP21 variant configuration.
+ | Default: 0
+- | ``STM32MP23``: to select STM32MP23 variant configuration.
+ | Default: 0
- | ``STM32MP25``: to select STM32MP25 variant configuration.
| Default: 1
@@ -154,4 +195,4 @@
.. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
.. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
-*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
+*Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/xilinx-versal-net.rst b/docs/plat/xilinx-versal-net.rst
index d22a46d..acb67a6 100644
--- a/docs/plat/xilinx-versal-net.rst
+++ b/docs/plat/xilinx-versal-net.rst
@@ -24,6 +24,11 @@
make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net VERSAL_NET_CONSOLE=dcc bl31
```
+To build TF-A with SDEI_SUPPORT:
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net SDEI_SUPPORT=1 bl31
+```
+
Xilinx Versal NET platform specific build options
-------------------------------------------------
diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst
index 7185d91..a654a0b 100644
--- a/docs/plat/xilinx-versal.rst
+++ b/docs/plat/xilinx-versal.rst
@@ -59,6 +59,57 @@
- `6` : SGI 6 (Default)
- `7` : SGI 7
+Configurable Stack Size
+-----------------------
+
+The stack size in TF-A for the Versal platform is configurable.
+The custom package can define the desired stack size as per the requirement in
+the makefile as follows:
+
+.. code-block:: shell
+
+ PLATFORM_STACK_SIZE := <value>
+
+ $(eval $(call add_define,PLATFORM_STACK_SIZE))
+
+CUSTOM SIP Service Support
+--------------------------
+
+- Dedicated SMC FID ``VERSAL_SIP_SVC_CUSTOM(0x82002000)`` (32-bit) /
+ ``(0xC2002000)`` (64-bit) is used by a custom package for providing
+ CUSTOM SIP service.
+
+- By default, the platform provides a bare minimum definition for
+ ``custom_smc_handler`` in this service.
+
+- To use this service, the custom package should implement its own SMC handler
+ named ``custom_smc_handler``. Once the custom package is included in the
+ TF-A build, its definition of ``custom_smc_handler`` is enabled.
+
+Custom Package Makefile Fragment Inclusion in TF-A Build
+--------------------------------------------------------
+
+- Custom package is not directly part of the TF-A source.
+
+- ``<CUSTOM_PKG_PATH>`` is the location where the user clones a
+ custom package locally.
+
+- The custom package must implement a makefile fragment named
+ ``custom_pkg.mk`` so it can be included in the TF-A build.
+
+- ``custom_pkg.mk`` should specify all the rules to include custom package
+ specific header files, dependent libraries, and source files that are
+ required to be part of the TF-A build.
+
+- When ``<CUSTOM_PKG_PATH>`` is specified in the TF-A build command,
+ ``custom_pkg.mk`` is included from ``<CUSTOM_PKG_PATH>``.
+
+- Example TF-A build command:
+
+.. code-block:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=versal RESET_TO_BL31=1 bl31 CUSTOM_PKG_PATH=<...>
+
# PLM->TF-A Parameter Passing
------------------------------
The PLM populates a data structure with image information for the TF-A. The TF-A
diff --git a/docs/process/commit-style.rst b/docs/process/commit-style.rst
index c287599..97b4b44 100644
--- a/docs/process/commit-style.rst
+++ b/docs/process/commit-style.rst
@@ -36,6 +36,9 @@
[optional footer(s)]
+Note that the type, the scope and the first letter of the description (also
+called subject by the commitlint checker) must be lower case.
+
The following example commit message demonstrates the use of the
``refactor`` type and the ``amu`` scope:
@@ -144,7 +147,7 @@
--------------
-*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.*
.. _Conventional Commits: https://www.conventionalcommits.org/en/v1.0.0
.. _Gerrit Change-Ids documentation: https://review.trustedfirmware.org/Documentation/user-changeid.html
diff --git a/docs/sbom.cdx.json b/docs/sbom.cdx.json
new file mode 100644
index 0000000..795e5d5
--- /dev/null
+++ b/docs/sbom.cdx.json
@@ -0,0 +1,47 @@
+{
+ "bomFormat": "CycloneDX",
+ "specVersion": "1.6",
+ "version": 1,
+ "metadata": {
+ "authors": [
+ {
+ "name": "@VCS_SBOM_AUTHORS@"
+ }
+ ]
+ },
+ "components": [
+ {
+ "type": "library",
+ "bom-ref": "pkg:github/TrustedFirmware-A/trusted-firmware-a@@VCS_TAG@",
+ "cpe": "cpe:2.3:a:trustedfirmware.org:trusted-firmware-a:@VCS_TAG@:*:*:*:*:*:*:*",
+ "name": "trusted-firmware-a",
+ "version": "@VCS_VERSION@",
+ "description": "Reference implementation of secure software for Arm A-Profile architectures",
+ "authors": [
+ {
+ "name": "@VCS_AUTHORS@"
+ }
+ ],
+ "supplier": {
+ "name": "trustedfirmware.org"
+ },
+ "licenses": [
+ {
+ "license": {
+ "id": "BSD-3-Clause"
+ }
+ }
+ ],
+ "externalReferences": [
+ {
+ "type": "vcs",
+ "url": "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
+ },
+ {
+ "type": "vcs",
+ "url": "https://github.com/TrustedFirmware-A/trusted-firmware-a"
+ }
+ ]
+ }
+ ]
+}
diff --git a/drivers/arm/gic/v2/gicv2_base.c b/drivers/arm/gic/v2/gicv2_base.c
index 317375f..c51c195 100644
--- a/drivers/arm/gic/v2/gicv2_base.c
+++ b/drivers/arm/gic/v2/gicv2_base.c
@@ -12,7 +12,7 @@
#include <plat/common/platform.h>
#if USE_GIC_DRIVER != 2
-#error "This file should only be used with GENERIC_GIC_DRIVER=2"
+#error "This file should only be used with USE_GIC_DRIVER=2"
#endif
/******************************************************************************
diff --git a/drivers/arm/gic/v3/gicv3_base.c b/drivers/arm/gic/v3/gicv3_base.c
index 3c97b01..57f2314 100644
--- a/drivers/arm/gic/v3/gicv3_base.c
+++ b/drivers/arm/gic/v3/gicv3_base.c
@@ -16,7 +16,7 @@
#include <plat/common/platform.h>
#if USE_GIC_DRIVER != 3
-#error "This file should only be used with GENERIC_GIC_DRIVER=3"
+#error "This file should only be used with USE_GIC_DRIVER=3"
#endif
/* The GICv3 driver only needs to be initialized in EL3 */
diff --git a/drivers/auth/auth.mk b/drivers/auth/auth.mk
new file mode 100644
index 0000000..a23c59b
--- /dev/null
+++ b/drivers/auth/auth.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+AUTH_SRC_DIR := drivers/auth/
+
+AUTH_SOURCES := ${AUTH_SRC_DIR}auth_mod.c \
+ ${AUTH_SRC_DIR}auth_util.c \
+ ${AUTH_SRC_DIR}crypto_mod.c \
+ ${AUTH_SRC_DIR}img_parser_mod.c
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 8c5ff9d..05a8f45 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <common/tbbr/cot_def.h>
#include <drivers/auth/auth_common.h>
#include <drivers/auth/auth_mod.h>
+#include <drivers/auth/auth_util.h>
#include <drivers/auth/crypto_mod.h>
#include <drivers/auth/img_parser_mod.h>
#include <drivers/fwu/fwu.h>
@@ -188,6 +189,18 @@
return rc;
}
+ /*
+ * Set Zero-OID for ROTPK(subject key) as a the certificate
+ * does not hold Key-OID information for ROTPK.
+ */
+ if (param->pk->cookie != NULL) {
+ pk_oid = param->pk->cookie;
+ } else {
+ pk_oid = ZERO_OID;
+ }
+
+ set_current_pk_oid(pk_oid);
+
/* Get the public key from the parent. If there is no parent (NULL),
* the certificate has been signed with the ROTPK, so we have to get
* the PK from the platform */
@@ -268,16 +281,6 @@
}
/*
- * Set Zero-OID for ROTPK(subject key) as a the certificate
- * does not hold Key-OID information for ROTPK.
- */
- if (param->pk->cookie != NULL) {
- pk_oid = param->pk->cookie;
- } else {
- pk_oid = ZERO_OID;
- }
-
- /*
* Public key is verified at this stage, notify platform
* to measure and publish it.
*/
diff --git a/drivers/auth/auth_util.c b/drivers/auth/auth_util.c
new file mode 100644
index 0000000..c12d2c3
--- /dev/null
+++ b/drivers/auth/auth_util.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <drivers/auth/auth_util.h>
+
+static const char *current_pk_oid;
+
+const char *get_current_pk_oid(void)
+{
+ return current_pk_oid;
+}
+
+void set_current_pk_oid(const char *pk_oid)
+{
+ current_pk_oid = pk_oid;
+}
diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c
index e36b285..882ca8e 100644
--- a/drivers/auth/crypto_mod.c
+++ b/drivers/auth/crypto_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -187,3 +187,12 @@
key_len, key_flags, iv, iv_len, tag,
tag_len);
}
+
+/* Perform end of psa crypto usage calls to finish */
+void crypto_mod_finish(void)
+{
+ if (crypto_lib_desc.finish != NULL) {
+ crypto_lib_desc.finish();
+ INFO("Finished using crypto library '%s'\n", crypto_lib_desc.name);
+ }
+}
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 8fe426b..98a9510 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -417,19 +417,19 @@
#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
#if TF_MBEDTLS_USE_AES_GCM
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
- auth_decrypt, NULL);
+ auth_decrypt, NULL, NULL);
#else
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
- NULL, NULL);
+ NULL, NULL, NULL);
#endif
#elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY
#if TF_MBEDTLS_USE_AES_GCM
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
- auth_decrypt, NULL);
+ auth_decrypt, NULL, NULL);
#else
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
- NULL, NULL);
+ NULL, NULL, NULL);
#endif
#elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY
-REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL);
+REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL, NULL);
#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 0e4b57e..34987e4 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,8 +21,10 @@
#include <psa/crypto_values.h>
#include <common/debug.h>
+#include <drivers/auth/auth_util.h>
#include <drivers/auth/crypto_mod.h>
#include <drivers/auth/mbedtls/mbedtls_common.h>
+#include <drivers/auth/mbedtls/mbedtls_psa_crypto.h>
#include <plat/common/platform.h>
#define LIB_NAME "mbed TLS PSA"
@@ -36,6 +38,9 @@
#define SIZE_OF_ASN1_LEN 1U
#define SIZE_OF_ASN1_TAG 1U
+/* Global cache for keys */
+key_cache_t key_cache[MAX_CACHED_KEYS] = {0};
+
#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
/*
@@ -103,6 +108,49 @@
#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+/* Destroy all psa key ids created in a loop */
+static void destroy_key_ids(void)
+{
+ for (int i = 0; i < MAX_CACHED_KEYS; i++) {
+ if (key_cache[i].valid) {
+ psa_destroy_key(key_cache[i].key_id);
+ }
+ }
+}
+
+/* Retrieve cached key ID, algorithm, and key attributes */
+static bool get_cached_psa_key_info(const char *pk_oid, psa_key_id_t *key_id,
+ psa_algorithm_t *psa_alg, psa_key_attributes_t *psa_key_attr)
+{
+ for (int i = 0; i < MAX_CACHED_KEYS; i++) {
+ if (key_cache[i].valid &&
+ (strlen(key_cache[i].pk_oid) == strlen(pk_oid)) &&
+ (strncmp(key_cache[i].pk_oid, pk_oid, strlen(pk_oid)) == 0)) {
+ *key_id = key_cache[i].key_id;
+ *psa_alg = key_cache[i].psa_alg;
+ *psa_key_attr = key_cache[i].psa_key_attr;
+ return true;
+ }
+ }
+ return false;
+}
+
+/* Store key ID, algorithm, and key attributes in the cache */
+static int cache_psa_key_info(const char *pk_oid, psa_key_id_t key_id, psa_algorithm_t psa_alg,
+ psa_key_attributes_t psa_key_attr)
+{
+ for (int i = 0; i < MAX_CACHED_KEYS; i++) {
+ if (!key_cache[i].valid) {
+ key_cache[i].pk_oid = pk_oid;
+ key_cache[i].key_id = key_id;
+ key_cache[i].psa_alg = psa_alg;
+ key_cache[i].psa_key_attr = psa_key_attr;
+ key_cache[i].valid = true;
+ return CRYPTO_SUCCESS;
+ }
+ }
+ return CRYPTO_ERR_SIGNATURE;
+}
/*
* NOTE: This has been made internal in mbedtls 3.6.0 and the mbedtls team has
@@ -201,41 +249,52 @@
psa_key_id_t psa_key_id;
mbedtls_pk_type_t pk_alg;
psa_algorithm_t psa_alg;
+ const char *pk_oid = get_current_pk_oid();
__unused unsigned char reformatted_sig[ECDSA_SIG_BUFFER_SIZE] = {0};
unsigned char *local_sig_ptr;
size_t local_sig_len;
- /* Load the key into the PSA key store. */
- initialize_pk_context(&pk, &pk_initialized);
+ /* Check if key, algorithm, and key attributes are already cached */
+ if (!get_cached_psa_key_info(pk_oid, &psa_key_id, &psa_alg, &psa_key_attr)) {
+ /* Load the key into the PSA key store. */
+ initialize_pk_context(&pk, &pk_initialized);
- p = (unsigned char *) pk_ptr;
- end = p + pk_len;
- rc = mbedtls_pk_parse_subpubkey(&p, end, &pk);
- if (rc != 0) {
- rc = CRYPTO_ERR_SIGNATURE;
- goto end2;
- }
+ p = (unsigned char *) pk_ptr;
+ end = p + pk_len;
+ rc = mbedtls_pk_parse_subpubkey(&p, end, &pk);
+ if (rc != 0) {
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end2;
+ }
- rc = mbedtls_pk_get_psa_attributes(&pk, PSA_KEY_USAGE_VERIFY_MESSAGE, &psa_key_attr);
- if (rc != 0) {
- rc = CRYPTO_ERR_SIGNATURE;
- goto end2;
- }
+ rc = mbedtls_pk_get_psa_attributes(&pk, PSA_KEY_USAGE_VERIFY_MESSAGE,
+ &psa_key_attr);
+ if (rc != 0) {
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end2;
+ }
- rc = construct_psa_alg(sig_alg, sig_alg_len, &pk_alg, &psa_alg);
- if (rc != CRYPTO_SUCCESS) {
- goto end2;
- }
- psa_set_key_algorithm(&psa_key_attr, psa_alg);
+ rc = construct_psa_alg(sig_alg, sig_alg_len, &pk_alg, &psa_alg);
+ if (rc != CRYPTO_SUCCESS) {
+ goto end2;
+ }
+ psa_set_key_algorithm(&psa_key_attr, psa_alg);
- rc = mbedtls_pk_import_into_psa(&pk, &psa_key_attr, &psa_key_id);
- if (rc != 0) {
- rc = CRYPTO_ERR_SIGNATURE;
- goto end2;
- }
+ rc = mbedtls_pk_import_into_psa(&pk, &psa_key_attr, &psa_key_id);
+ if (rc != 0) {
+ rc = CRYPTO_ERR_SIGNATURE;
+ goto end2;
+ }
- /* Optimize mbedtls heap usage by freeing the pk context now. */
- cleanup_pk_context(&pk, &pk_initialized);
+ /* Cache the key, algorithm, and key attributes for future use */
+ rc = cache_psa_key_info(pk_oid, psa_key_id, psa_alg, psa_key_attr);
+ if (rc != CRYPTO_SUCCESS) {
+ goto end2;
+ }
+
+ /* Optimize mbedtls heap usage by freeing the pk context now. */
+ cleanup_pk_context(&pk, &pk_initialized);
+ }
/* Extract the signature from sig_ptr. */
p = (unsigned char *) sig_ptr;
@@ -249,7 +308,7 @@
#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
- if (pk_alg == MBEDTLS_PK_ECDSA) {
+ if (PSA_ALG_IS_ECDSA(psa_alg)) {
/* Convert the DER ASN.1 signature to raw format. */
size_t key_bits = psa_get_key_bits(&psa_key_attr);
@@ -271,16 +330,11 @@
psa_status = psa_verify_message(psa_key_id, psa_alg,
data_ptr, data_len,
local_sig_ptr, local_sig_len);
- if (psa_status == PSA_SUCCESS) {
- /* The signature has been successfully verified. */
- rc = CRYPTO_SUCCESS;
- } else {
- rc = CRYPTO_ERR_SIGNATURE;
- }
+
+ rc = (psa_status == PSA_SUCCESS) ? CRYPTO_SUCCESS : CRYPTO_ERR_SIGNATURE;
end1:
- /* Destroy the key from the PSA subsystem. */
- psa_destroy_key(psa_key_id);
+ return rc;
end2:
/* Free the pk context, if it is initialized. */
cleanup_pk_context(&pk, &pk_initialized);
@@ -365,6 +419,18 @@
* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
*/
+/*
+ * Finish crypto usage by destroying the psa_key_ids
+ */
+static void finish(void)
+{
+#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
+CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+ /* Destroy the psa_key_ids */
+ destroy_key_ids();
+#endif
+}
+
#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
/*
@@ -524,19 +590,19 @@
#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
#if TF_MBEDTLS_USE_AES_GCM
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
- auth_decrypt, NULL);
+ auth_decrypt, NULL, finish);
#else
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash,
- NULL, NULL);
+ NULL, NULL, finish);
#endif
#elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY
#if TF_MBEDTLS_USE_AES_GCM
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
- auth_decrypt, NULL);
+ auth_decrypt, NULL, finish);
#else
REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL,
- NULL, NULL);
+ NULL, NULL, finish);
#endif
#elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY
-REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL);
+REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL, finish);
#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 49dfc07..f6a27dc 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,9 +15,22 @@
#include <drivers/delay_timer.h>
#include <drivers/mmc.h>
#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <imx_usdhc.h>
+/* These masks represent the commands which involve a data transfer. */
+#define ADTC_MASK_SD (BIT_32(6U) | BIT_32(17U) | BIT_32(18U) |\
+ BIT_32(24U) | BIT_32(25U))
+#define ADTC_MASK_ACMD (BIT_64(51U))
+
+struct imx_usdhc_device_data {
+ uint32_t addr;
+ uint32_t blk_size;
+ uint32_t blks;
+ bool valid;
+};
+
static void imx_usdhc_initialize(void);
static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
@@ -34,27 +48,85 @@
};
static imx_usdhc_params_t imx_usdhc_params;
+static struct imx_usdhc_device_data imx_usdhc_data;
+
+static bool imx_usdhc_is_buf_valid(void)
+{
+ return imx_usdhc_data.valid;
+}
+
+static bool imx_usdhc_is_buf_multiblk(void)
+{
+ return imx_usdhc_data.blks > 1U;
+}
+
+static void imx_usdhc_inval_buf_data(void)
+{
+ imx_usdhc_data.valid = false;
+}
+
+static int imx_usdhc_save_buf_data(uintptr_t buf, size_t size)
+{
+ uint32_t block_size;
+ uint64_t blks;
+
+ if (size <= MMC_BLOCK_SIZE) {
+ block_size = (uint32_t)size;
+ } else {
+ block_size = MMC_BLOCK_SIZE;
+ }
+
+ if (buf > UINT32_MAX) {
+ return -EOVERFLOW;
+ }
+
+ imx_usdhc_data.addr = (uint32_t)buf;
+ imx_usdhc_data.blk_size = block_size;
+ blks = size / block_size;
+ imx_usdhc_data.blks = (uint32_t)blks;
+
+ imx_usdhc_data.valid = true;
+
+ return 0;
+}
+
+static void imx_usdhc_write_buf_data(void)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+ uint32_t addr, blks, blk_size;
+
+ addr = imx_usdhc_data.addr;
+ blks = imx_usdhc_data.blks;
+ blk_size = imx_usdhc_data.blk_size;
+
+ mmio_write_32(reg_base + DSADDR, addr);
+ mmio_write_32(reg_base + BLKATT, BLKATT_BLKCNT(blks) |
+ BLKATT_BLKSIZE(blk_size));
+}
#define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
-static void imx_usdhc_set_clk(int clk)
+static void imx_usdhc_set_clk(unsigned int clk)
{
- int div = 1;
- int pre_div = 1;
unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int pre_div = 1U, div = 1U;
assert(clk > 0);
while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
pre_div *= 2;
- while (sdhc_clk / div > clk && div < 16)
+ while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) {
div++;
+ }
pre_div >>= 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
+ while ((mmio_read_32(reg_base + PSTATE) & PSTATE_SDSTB) == 0U) {
+ }
+
mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
udelay(10000);
@@ -107,15 +179,85 @@
#define FSL_CMD_RETRIES 1000
+static bool is_data_transfer_to_card(const struct mmc_cmd *cmd)
+{
+ unsigned int cmd_idx = cmd->cmd_idx;
+
+ return (cmd_idx == MMC_CMD(24)) || (cmd_idx == MMC_CMD(25));
+}
+
+static bool is_data_transfer_cmd(const struct mmc_cmd *cmd)
+{
+ uintptr_t reg_base = imx_usdhc_params.reg_base;
+ unsigned int cmd_idx = cmd->cmd_idx;
+ uint32_t xfer_type;
+
+ xfer_type = mmio_read_32(reg_base + XFERTYPE);
+
+ if (XFERTYPE_GET_CMD(xfer_type) == MMC_CMD(55)) {
+ return (ADTC_MASK_ACMD & BIT_64(cmd_idx)) != 0ULL;
+ }
+
+ if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) {
+ return true;
+ }
+
+ return false;
+}
+
+static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype)
+{
+ *xfertype = XFERTYPE_CMD(cmd->cmd_idx);
+
+ switch (cmd->resp_type) {
+ case MMC_RESPONSE_R2:
+ *xfertype |= XFERTYPE_RSPTYP_136;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ case MMC_RESPONSE_R4:
+ *xfertype |= XFERTYPE_RSPTYP_48;
+ break;
+ case MMC_RESPONSE_R6:
+ *xfertype |= XFERTYPE_RSPTYP_48;
+ *xfertype |= XFERTYPE_CICEN;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ case MMC_RESPONSE_R1B:
+ *xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+ *xfertype |= XFERTYPE_CICEN;
+ *xfertype |= XFERTYPE_CCCEN;
+ break;
+ default:
+ ERROR("Invalid CMD response: %u\n", cmd->resp_type);
+ return -EINVAL;
+ }
+
+ if (data) {
+ *xfertype |= XFERTYPE_DPSEL;
+ }
+
+ return 0;
+}
+
static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
{
uintptr_t reg_base = imx_usdhc_params.reg_base;
- unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
+ unsigned int mixctl = 0;
unsigned int cmd_retries = 0;
+ uint32_t xfertype;
+ bool data;
+ int err = 0;
assert(cmd);
+ data = is_data_transfer_cmd(cmd);
+
+ err = get_xfr_type(cmd, data, &xfertype);
+ if (err != 0) {
+ return err;
+ }
+
/* clear all irq status */
mmio_write_32(reg_base + INTSTAT, 0xffffffff);
@@ -128,56 +270,23 @@
;
mmio_write_32(reg_base + INTSIGEN, 0);
- udelay(1000);
-
- switch (cmd->cmd_idx) {
- case MMC_CMD(12):
- xfertype |= XFERTYPE_CMDTYP_ABORT;
- break;
- case MMC_CMD(18):
- multiple = 1;
- /* for read op */
- /* fallthrough */
- case MMC_CMD(17):
- case MMC_CMD(8):
- mixctl |= MIXCTRL_DTDSEL;
- data = 1;
- break;
- case MMC_CMD(25):
- multiple = 1;
- /* for data op flag */
- /* fallthrough */
- case MMC_CMD(24):
- data = 1;
- break;
- default:
- break;
- }
-
- if (multiple) {
- mixctl |= MIXCTRL_MSBSEL;
- mixctl |= MIXCTRL_BCEN;
- }
if (data) {
- xfertype |= XFERTYPE_DPSEL;
mixctl |= MIXCTRL_DMAEN;
}
- if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2)
- xfertype |= XFERTYPE_RSPTYP_48;
- else if (cmd->resp_type & MMC_RSP_136)
- xfertype |= XFERTYPE_RSPTYP_136;
- else if (cmd->resp_type & MMC_RSP_BUSY)
- xfertype |= XFERTYPE_RSPTYP_48_BUSY;
-
- if (cmd->resp_type & MMC_RSP_CMD_IDX)
- xfertype |= XFERTYPE_CICEN;
+ if (!is_data_transfer_to_card(cmd)) {
+ mixctl |= MIXCTRL_DTDSEL;
+ }
- if (cmd->resp_type & MMC_RSP_CRC)
- xfertype |= XFERTYPE_CCCEN;
+ if ((cmd->cmd_idx != MMC_CMD(55)) && imx_usdhc_is_buf_valid()) {
+ if (imx_usdhc_is_buf_multiblk()) {
+ mixctl |= MIXCTRL_MSBSEL | MIXCTRL_BCEN;
+ }
- xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
+ imx_usdhc_write_buf_data();
+ imx_usdhc_inval_buf_data();
+ }
/* Send the command */
mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
@@ -269,17 +378,13 @@
static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
{
- uintptr_t reg_base = imx_usdhc_params.reg_base;
-
- mmio_write_32(reg_base + DSADDR, buf);
- mmio_write_32(reg_base + BLKATT,
- (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
-
- return 0;
+ flush_dcache_range(buf, size);
+ return imx_usdhc_save_buf_data(buf, size);
}
static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
{
+ inv_dcache_range(buf, size);
return 0;
}
@@ -291,13 +396,24 @@
void imx_usdhc_init(imx_usdhc_params_t *params,
struct mmc_device_info *mmc_dev_info)
{
+ int ret __maybe_unused;
+
assert((params != 0) &&
((params->reg_base & MMC_BLOCK_MASK) == 0) &&
- (params->clk_rate > 0) &&
((params->bus_width == MMC_BUS_WIDTH_1) ||
(params->bus_width == MMC_BUS_WIDTH_4) ||
(params->bus_width == MMC_BUS_WIDTH_8)));
+#if PLAT_XLAT_TABLES_DYNAMIC
+ ret = mmap_add_dynamic_region(params->reg_base, params->reg_base,
+ PAGE_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE);
+ if (ret != 0) {
+ ERROR("Failed to map the uSDHC registers\n");
+ panic();
+ }
+#endif
+
memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
params->flags, mmc_dev_info);
diff --git a/drivers/imx/usdhc/imx_usdhc.h b/drivers/imx/usdhc/imx_usdhc.h
index e063316..bb0ef01 100644
--- a/drivers/imx/usdhc/imx_usdhc.h
+++ b/drivers/imx/usdhc/imx_usdhc.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,8 +12,8 @@
typedef struct imx_usdhc_params {
uintptr_t reg_base;
- int clk_rate;
- int bus_width;
+ unsigned int clk_rate;
+ unsigned int bus_width;
unsigned int flags;
} imx_usdhc_params_t;
@@ -20,115 +21,119 @@
struct mmc_device_info *mmc_dev_info);
/* iMX MMC registers definition */
-#define DSADDR 0x000
-#define BLKATT 0x004
-#define CMDARG 0x008
-#define CMDRSP0 0x010
-#define CMDRSP1 0x014
-#define CMDRSP2 0x018
-#define CMDRSP3 0x01c
+#define DSADDR 0x000U
+#define BLKATT 0x004U
+#define BLKATT_BLKCNT(x) (((x) << 16U) & GENMASK_32(31U, 16U))
+#define BLKATT_BLKSIZE(x) ((x) & GENMASK_32(12U, 0U))
+#define CMDARG 0x008U
+#define CMDRSP0 0x010U
+#define CMDRSP1 0x014U
+#define CMDRSP2 0x018U
+#define CMDRSP3 0x01cU
-#define XFERTYPE 0x00c
-#define XFERTYPE_CMD(x) (((x) & 0x3f) << 24)
-#define XFERTYPE_CMDTYP_ABORT (3 << 22)
-#define XFERTYPE_DPSEL BIT(21)
-#define XFERTYPE_CICEN BIT(20)
-#define XFERTYPE_CCCEN BIT(19)
-#define XFERTYPE_RSPTYP_136 BIT(16)
-#define XFERTYPE_RSPTYP_48 BIT(17)
-#define XFERTYPE_RSPTYP_48_BUSY (BIT(16) | BIT(17))
+#define XFERTYPE 0x00cU
+#define XFERTYPE_CMD(x) (((x) & 0x3fU) << 24U)
+#define XFERTYPE_GET_CMD(x) (((x) & GENMASK_32(29U, 24U)) >> 24U)
+#define XFERTYPE_CMDTYP_ABORT (3U << 22U)
+#define XFERTYPE_DPSEL BIT_32(21U)
+#define XFERTYPE_CICEN BIT_32(20U)
+#define XFERTYPE_CCCEN BIT_32(19U)
+#define XFERTYPE_RSPTYP_136 BIT_32(16U)
+#define XFERTYPE_RSPTYP_48 BIT_32(17U)
+#define XFERTYPE_RSPTYP_48_BUSY (BIT_32(16U) | BIT_32(17U))
-#define PSTATE 0x024
-#define PSTATE_DAT0 BIT(24)
-#define PSTATE_DLA BIT(2)
-#define PSTATE_CDIHB BIT(1)
-#define PSTATE_CIHB BIT(0)
+#define PSTATE 0x024U
+#define PSTATE_DAT0 BIT_32(24U)
+#define PSTATE_SDSTB BIT_32(3U)
+#define PSTATE_DLA BIT_32(2U)
+#define PSTATE_CDIHB BIT_32(1U)
+#define PSTATE_CIHB BIT_32(0U)
-#define PROTCTRL 0x028
-#define PROTCTRL_LE BIT(5)
-#define PROTCTRL_WIDTH_4 BIT(1)
-#define PROTCTRL_WIDTH_8 BIT(2)
-#define PROTCTRL_WIDTH_MASK 0x6
+#define PROTCTRL 0x028U
+#define PROTCTRL_LE BIT_32(5U)
+#define PROTCTRL_WIDTH_4 BIT_32(1U)
+#define PROTCTRL_WIDTH_8 BIT_32(2U)
+#define PROTCTRL_WIDTH_MASK 0x6U
-#define SYSCTRL 0x02c
-#define SYSCTRL_RSTD BIT(26)
-#define SYSCTRL_RSTC BIT(25)
-#define SYSCTRL_RSTA BIT(24)
-#define SYSCTRL_CLOCK_MASK 0x0000fff0
-#define SYSCTRL_TIMEOUT_MASK 0x000f0000
-#define SYSCTRL_TIMEOUT(x) ((0xf & (x)) << 16)
+#define SYSCTRL 0x02cU
+#define SYSCTRL_RSTD BIT_32(26U)
+#define SYSCTRL_RSTC BIT_32(25U)
+#define SYSCTRL_RSTA BIT_32(24U)
+#define SYSCTRL_CLOCK_MASK GENMASK_32(15U, 4U)
+#define SYSCTRL_TIMEOUT_MASK GENMASK_32(19U, 16U)
+#define SYSCTRL_TIMEOUT(x) ((0xfU & (x)) << 16U)
-#define INTSTAT 0x030
-#define INTSTAT_DMAE BIT(28)
-#define INTSTAT_DEBE BIT(22)
-#define INTSTAT_DCE BIT(21)
-#define INTSTAT_DTOE BIT(20)
-#define INTSTAT_CIE BIT(19)
-#define INTSTAT_CEBE BIT(18)
-#define INTSTAT_CCE BIT(17)
-#define INTSTAT_DINT BIT(3)
-#define INTSTAT_BGE BIT(2)
-#define INTSTAT_TC BIT(1)
-#define INTSTAT_CC BIT(0)
+#define INTSTAT 0x030U
+#define INTSTAT_DMAE BIT_32(28U)
+#define INTSTAT_DEBE BIT_32(22U)
+#define INTSTAT_DCE BIT_32(21U)
+#define INTSTAT_DTOE BIT_32(20U)
+#define INTSTAT_CIE BIT_32(19U)
+#define INTSTAT_CEBE BIT_32(18U)
+#define INTSTAT_CCE BIT_32(17U)
+#define INTSTAT_DINT BIT_32(3U)
+#define INTSTAT_BGE BIT_32(2U)
+#define INTSTAT_TC BIT_32(1U)
+#define INTSTAT_CC BIT_32(0U)
#define CMD_ERR (INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
#define DATA_ERR (INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
INTSTAT_DTOE)
#define DATA_COMPLETE (INTSTAT_DINT | INTSTAT_TC)
-#define INTSTATEN 0x034
-#define INTSTATEN_DEBE BIT(22)
-#define INTSTATEN_DCE BIT(21)
-#define INTSTATEN_DTOE BIT(20)
-#define INTSTATEN_CIE BIT(19)
-#define INTSTATEN_CEBE BIT(18)
-#define INTSTATEN_CCE BIT(17)
-#define INTSTATEN_CTOE BIT(16)
-#define INTSTATEN_CINT BIT(8)
-#define INTSTATEN_BRR BIT(5)
-#define INTSTATEN_BWR BIT(4)
-#define INTSTATEN_DINT BIT(3)
-#define INTSTATEN_TC BIT(1)
-#define INTSTATEN_CC BIT(0)
+#define INTSTATEN 0x034U
+#define INTSTATEN_DEBE BIT_32(22U)
+#define INTSTATEN_DCE BIT_32(21U)
+#define INTSTATEN_DTOE BIT_32(20U)
+#define INTSTATEN_CIE BIT_32(19U)
+#define INTSTATEN_CEBE BIT_32(18U)
+#define INTSTATEN_CCE BIT_32(17U)
+#define INTSTATEN_CTOE BIT_32(16U)
+#define INTSTATEN_CINT BIT_32(8U)
+#define INTSTATEN_BRR BIT_32(5U)
+#define INTSTATEN_BWR BIT_32(4U)
+#define INTSTATEN_DINT BIT_32(3U)
+#define INTSTATEN_TC BIT_32(1U)
+#define INTSTATEN_CC BIT_32(0U)
#define EMMC_INTSTATEN_BITS (INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
INTSTATEN_DEBE)
-#define INTSIGEN 0x038
+#define INTSIGEN 0x038U
-#define WATERMARKLEV 0x044
-#define WMKLV_RD_MASK 0xff
-#define WMKLV_WR_MASK 0x00ff0000
+#define WATERMARKLEV 0x044U
+#define WMKLV_RD_MASK GENMASK_32(7U, 0U)
+#define WMKLV_WR_MASK GENMASK_32(23U, 16U)
#define WMKLV_MASK (WMKLV_RD_MASK | WMKLV_WR_MASK)
-#define MIXCTRL 0x048
-#define MIXCTRL_MSBSEL BIT(5)
-#define MIXCTRL_DTDSEL BIT(4)
-#define MIXCTRL_DDREN BIT(3)
-#define MIXCTRL_AC12EN BIT(2)
-#define MIXCTRL_BCEN BIT(1)
-#define MIXCTRL_DMAEN BIT(0)
-#define MIXCTRL_DATMASK 0x7f
+#define MIXCTRL 0x048U
+#define MIXCTRL_MSBSEL BIT_32(5U)
+#define MIXCTRL_DTDSEL BIT_32(4U)
+#define MIXCTRL_DDREN BIT_32(3U)
+#define MIXCTRL_AC12EN BIT_32(2U)
+#define MIXCTRL_BCEN BIT_32(1U)
+#define MIXCTRL_DMAEN BIT_32(0U)
+#define MIXCTRL_DATMASK 0x7fU
-#define DLLCTRL 0x060
+#define DLLCTRL 0x060U
-#define CLKTUNECTRLSTS 0x068
+#define CLKTUNECTRLSTS 0x068U
-#define VENDSPEC 0x0c0
-#define VENDSPEC_RSRV1 BIT(29)
-#define VENDSPEC_CARD_CLKEN BIT(14)
-#define VENDSPEC_PER_CLKEN BIT(13)
-#define VENDSPEC_AHB_CLKEN BIT(12)
-#define VENDSPEC_IPG_CLKEN BIT(11)
-#define VENDSPEC_AC12_CHKBUSY BIT(3)
-#define VENDSPEC_EXTDMA BIT(0)
+#define VENDSPEC 0x0c0U
+#define VENDSPEC_RSRV1 BIT_32(29U)
+#define VENDSPEC_CARD_CLKEN BIT_32(14U)
+#define VENDSPEC_PER_CLKEN BIT_32(13U)
+#define VENDSPEC_AHB_CLKEN BIT_32(12U)
+#define VENDSPEC_IPG_CLKEN BIT_32(11U)
+#define VENDSPEC_AC12_CHKBUSY BIT_32(3U)
+#define VENDSPEC_EXTDMA BIT_32(0U)
#define VENDSPEC_INIT (VENDSPEC_RSRV1 | VENDSPEC_CARD_CLKEN | \
VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
VENDSPEC_EXTDMA)
-#define MMCBOOT 0x0c4
+#define MMCBOOT 0x0c4U
#define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
#define mmio_clrbits32(addr, clear) mmio_write_32(addr, mmio_read_32(addr) & ~(clear))
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index f12da0e..117ac73 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -12,7 +12,6 @@
#include <drivers/marvell/amb_adec.h>
#include <drivers/marvell/iob.h>
#include <drivers/marvell/mochi/cp110_setup.h>
-#include <drivers/rambus/trng_ip_76.h>
#include <efuse_def.h>
#include <plat_marvell.h>
@@ -107,13 +106,6 @@
#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF
#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F
-/*******************************************************************************
- * TRNG Configuration
- ******************************************************************************/
-#define MVEBU_TRNG_BASE (0x760000)
-#define MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD MVEBU_AP_LDX_220_189_EFUSE_OFFS
-#define MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET 13 /* LD0[202] */
-
enum axi_attr {
AXI_ADUNIT_ATTR = 0,
AXI_COMUNIT_ATTR,
@@ -388,36 +380,6 @@
init_amb_adec(base);
}
-static void cp110_trng_init(uintptr_t base)
-{
- static bool done;
- int ret;
- uint32_t reg_val, efuse;
-
- /* Set access to LD0 */
- reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
- reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
- mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
-
- /* Obtain the AP LD0 bit defining TRNG presence */
- efuse = mmio_read_32(MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD);
- efuse >>= MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET;
- efuse &= 1;
-
- if (efuse == 0) {
- VERBOSE("TRNG is not present, skipping");
- return;
- }
-
- if (!done) {
- ret = eip76_rng_probe(base + MVEBU_TRNG_BASE);
- if (ret != 0) {
- ERROR("Failed to init TRNG @ 0x%lx\n", base);
- return;
- }
- done = true;
- }
-}
void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
{
INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
@@ -445,9 +407,6 @@
/* Reset RTC if needed */
cp110_rtc_init(cp110_base);
-
- /* TRNG init - for CP0 only */
- cp110_trng_init(cp110_base);
}
/* Do the minimal setup required to configure the CP in BLE */
diff --git a/drivers/marvell/trng.c b/drivers/marvell/trng.c
new file mode 100644
index 0000000..34a3e38
--- /dev/null
+++ b/drivers/marvell/trng.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2025, Marvell Technology Group Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mvebu_def.h>
+
+/* Bind to first CP110's EIP-76 engine only */
+#define CP110_TRNG_REGS_BASE (MVEBU_CP_REGS_BASE(0) + 0x760000U)
+
+/* EIP-76 Register Definitions */
+#define CP110_TRNG_OUTPUT_REG(n) (CP110_TRNG_REGS_BASE + ((n) * 0x4U))
+#define CP110_TRNG_STAT_N_ACK_REG (CP110_TRNG_REGS_BASE + 0x10U)
+#define CP110_TRNG_CONTROL_REG (CP110_TRNG_REGS_BASE + 0x14U)
+#define CP110_TRNG_CONFIG_REG (CP110_TRNG_REGS_BASE + 0x18U)
+#define CP110_TRNG_FRO_ENABLE_REG (CP110_TRNG_REGS_BASE + 0x20U)
+#define CP110_TRNG_FRO_DETUNE_REG (CP110_TRNG_REGS_BASE + 0x24U)
+
+/* CP110_TRNG_STAT_N_ACK_REG */
+#define CP110_TRNG_READY BIT(0)
+
+/* CP110_TRNG_CONTROL_REG */
+#define CP110_TRNG_EN BIT(10)
+
+/* CP110_TRNG_CONFIG_REG */
+#define CP110_TRNG_NOISE_BLOCKS_SHIFT 0U
+#define CP110_TRNG_NOISE_BLOCKS_MASK (0xFFU << CP110_TRNG_NOISE_BLOCKS_SHIFT)
+#define CP110_TRNG_SAMPLE_CYCLES_SHIFT 16U
+#define CP110_TRNG_SAMPLE_CYCLES_MASK (0xFFU << CP110_TRNG_SAMPLE_CYCLES_SHIFT)
+
+/* CP110_TRNG_FRO_ENABLE_REG */
+#define CP110_TRNG_FRO_EN_SHIFT 0U
+#define CP110_TRNG_FRO_EN_MASK (0xFFFFFFU << CP110_TRNG_FRO_EN_SHIFT)
+
+#define CP110_TRNG_MAX_OUTPUTS 4U
+
+/* maximum busy wait */
+#define CP110_TRNG_MAX_RETRIES 3U
+
+static void mv_trng_init(void)
+{
+ uint32_t val;
+
+ val = (0x5U << CP110_TRNG_NOISE_BLOCKS_SHIFT) & CP110_TRNG_NOISE_BLOCKS_MASK;
+ val |= (0x22U << CP110_TRNG_SAMPLE_CYCLES_SHIFT) & CP110_TRNG_SAMPLE_CYCLES_MASK;
+ mmio_write_32(CP110_TRNG_CONFIG_REG, val);
+
+ mmio_write_32(CP110_TRNG_FRO_DETUNE_REG, 0U);
+ mmio_write_32(CP110_TRNG_FRO_ENABLE_REG, CP110_TRNG_FRO_EN_MASK);
+
+ mmio_write_32(CP110_TRNG_CONTROL_REG, CP110_TRNG_EN);
+}
+
+int mv_trng_get_random32(uint32_t *rand, uint8_t num)
+{
+ uint32_t val;
+ uint8_t i;
+
+ if (num > CP110_TRNG_MAX_OUTPUTS) {
+ return -1;
+ }
+
+ val = mmio_read_32(CP110_TRNG_CONTROL_REG);
+ if ((val & CP110_TRNG_EN) != 0U) {
+ /* Flush the staled output data */
+ val = mmio_read_32(CP110_TRNG_STAT_N_ACK_REG);
+ if ((val & CP110_TRNG_READY) != 0U) {
+ mmio_write_32(CP110_TRNG_STAT_N_ACK_REG, CP110_TRNG_READY);
+ }
+ } else {
+ mv_trng_init();
+ /* Necessary delay for the warm-up */
+ udelay(200U);
+ }
+
+
+ for (i = 0U; i < CP110_TRNG_MAX_RETRIES; i++) {
+ val = mmio_read_32(CP110_TRNG_STAT_N_ACK_REG);
+ if ((val & CP110_TRNG_READY) != 0U) {
+ break;
+ }
+ udelay(1U);
+ }
+
+ if (i == CP110_TRNG_MAX_RETRIES) {
+ return -1;
+ }
+
+ for (i = 0U; i < num; i++) {
+ rand[i] = mmio_read_32(CP110_TRNG_OUTPUT_REG(i));
+ }
+
+ return 0;
+}
diff --git a/drivers/measured_boot/event_log/event_handoff.c b/drivers/measured_boot/event_log/event_handoff.c
new file mode 100644
index 0000000..238ea27
--- /dev/null
+++ b/drivers/measured_boot/event_log/event_handoff.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <common/debug.h>
+#include <drivers/measured_boot/event_log/event_handoff.h>
+
+#include <platform_def.h>
+
+static uint8_t *get_log_ptr(struct transfer_list_entry *te, size_t offset)
+{
+ uint8_t *base_ptr = transfer_list_entry_data(te);
+
+ if (base_ptr == NULL) {
+ return NULL;
+ }
+
+ return base_ptr + offset;
+}
+
+uint8_t *transfer_list_event_log_extend(struct transfer_list_header *tl,
+ size_t req_size, size_t *free)
+{
+ struct transfer_list_entry *existing_entry;
+ struct transfer_list_entry *new_entry;
+ uint8_t *old_data;
+ size_t existing_offset;
+ size_t old_size;
+
+ if (tl == NULL || free == NULL || req_size == 0) {
+ ERROR("Invalid arguments to event log extend.\n");
+ return NULL;
+ }
+
+ existing_entry = transfer_list_find(tl, TL_TAG_TPM_EVLOG);
+ existing_offset = EVENT_LOG_RESERVED_BYTES;
+
+ if (existing_entry != NULL) {
+ existing_offset = existing_entry->data_size;
+
+ if (transfer_list_set_data_size(tl, existing_entry,
+ req_size + existing_offset)) {
+ VERBOSE("TPM event log entry resized: new space %zu bytes at offset %zu\n",
+ req_size, existing_offset);
+
+ *free = existing_entry->data_size - existing_offset;
+
+ return get_log_ptr(existing_entry, existing_offset);
+ }
+ }
+
+ /* Add new entry (resize failed or no existing entry) */
+ new_entry = transfer_list_add(tl, TL_TAG_TPM_EVLOG,
+ req_size + existing_offset, NULL);
+
+ if (new_entry == NULL) {
+ ERROR("Failed to add TPM event log entry to transfer list.\n");
+ return NULL;
+ }
+
+ VERBOSE("New TPM event log entry added at %p\n",
+ transfer_list_entry_data(new_entry));
+
+ if (existing_entry != NULL) {
+ old_data = transfer_list_entry_data(existing_entry);
+ old_size = existing_offset;
+
+ VERBOSE("Copying existing event log (%zu bytes) to new entry at %p\n",
+ old_size, transfer_list_entry_data(new_entry));
+
+ memmove(transfer_list_entry_data(new_entry), old_data,
+ old_size);
+
+ transfer_list_rem(tl, existing_entry);
+ }
+
+ *free = new_entry->data_size - existing_offset;
+
+ return get_log_ptr(new_entry, existing_offset);
+}
+
+uint8_t *transfer_list_event_log_finish(struct transfer_list_header *tl,
+ uintptr_t cursor)
+{
+ uintptr_t entry_data_base;
+ size_t final_log_size;
+ struct transfer_list_entry *entry;
+
+ entry = transfer_list_find(tl, TL_TAG_TPM_EVLOG);
+ entry_data_base = (uintptr_t)transfer_list_entry_data(entry);
+
+ if (cursor < entry_data_base ||
+ cursor >= entry_data_base + entry->data_size) {
+ ERROR("Invalid cursor: outside event log bounds.\n");
+ return NULL;
+ }
+
+ final_log_size = cursor - entry_data_base;
+
+ if (!transfer_list_set_data_size(tl, entry, final_log_size)) {
+ ERROR("Unable to resize event log TE.\n");
+ return NULL;
+ }
+
+ transfer_list_update_checksum(tl);
+
+ VERBOSE("TPM event log finalized: trimmed to %zu bytes",
+ final_log_size - EVENT_LOG_RESERVED_BYTES);
+
+ /* Ensure changes are visible to the next stage. */
+ flush_dcache_range((uintptr_t)tl, tl->size);
+
+ return get_log_ptr(entry, EVENT_LOG_RESERVED_BYTES);
+}
diff --git a/drivers/measured_boot/event_log/event_log.mk b/drivers/measured_boot/event_log/event_log.mk
index df3460f..09c15da 100644
--- a/drivers/measured_boot/event_log/event_log.mk
+++ b/drivers/measured_boot/event_log/event_log.mk
@@ -47,3 +47,8 @@
EVENT_LOG_SOURCES := ${EVENT_LOG_SRC_DIR}event_log.c \
${EVENT_LOG_SRC_DIR}event_print.c
+
+
+ifeq (${TRANSFER_LIST}, 1)
+EVENT_LOG_SOURCES += ${EVENT_LOG_SRC_DIR}/event_handoff.c
+endif
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 92182a0..ac9d99a 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -19,7 +19,7 @@
#define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ)
#define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ)
#define S32CC_PERIPH_DFS_PHI3_FREQ (800U * MHZ)
-#define S32CC_USDHC_FREQ (400U * MHZ)
+#define S32CC_USDHC_FREQ (200U * MHZ)
static int setup_fxosc(void)
{
diff --git a/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c b/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
index 408d974..f607d8b 100644
--- a/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
+++ b/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
@@ -120,4 +120,4 @@
/*
* Register crypto library descriptor
*/
-REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, NULL, NULL);
+REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, NULL, NULL, NULL);
diff --git a/drivers/rambus/trng_ip_76.c b/drivers/rambus/trng_ip_76.c
deleted file mode 100644
index 8de12e9..0000000
--- a/drivers/rambus/trng_ip_76.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved.
- *
- * Based on Linux kernel omap-rng.c - RNG driver for TI OMAP CPU family
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2005 (c) MontaVista Software, Inc.
- *
- * Mostly based on original driver:
- *
- * Copyright (C) 2005 Nokia Corporation
- * Author: Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <drivers/rambus/trng_ip_76.h>
-#include <lib/mmio.h>
-#include <lib/spinlock.h>
-#include <lib/utils.h>
-
-#define RNG_REG_STATUS_RDY (1 << 0)
-
-#define RNG_REG_INTACK_RDY_MASK (1 << 0)
-
-#define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
-
-#define RNG_CONFIG_NOISE_BLOCKS(val) ((0xff & (val)) << 0)
-#define RNG_CONFIG_NOISE_BLK_VAL 0x5
-
-#define RNG_CONFIG_SAMPLE_CYCLES(val) ((0xff & (val)) << 16)
-#define RNG_CONFIG_SAMPLE_CYCLES_VAL 0x22
-
-#define RNG_REG_FRO_ENABLE_MASK 0xffffff
-#define RNG_REG_FRO_DETUNE_MASK 0x0
-
-#define EIP76_RNG_OUTPUT_SIZE 0x10
-#define EIP76_RNG_WAIT_ROUNDS 10
-
-#define RNG_HW_IS_EIP76(ver) ((ver) & (0xff == 0x4C))
-#define RNG_HW_VER_MAJOR(ver) (((ver) & (0xf << 24)) >> 24)
-#define RNG_HW_VER_MINOR(ver) (((ver) & (0xf << 20)) >> 20)
-#define RNG_HW_VER_PATCH(ver) (((ver) & (0xf << 16)) >> 16)
-
-
-enum {
- RNG_OUTPUT_0_REG = 0,
- RNG_OUTPUT_1_REG,
- RNG_OUTPUT_2_REG,
- RNG_OUTPUT_3_REG,
- RNG_STATUS_REG,
- RNG_INTMASK_REG,
- RNG_INTACK_REG,
- RNG_CONTROL_REG,
- RNG_CONFIG_REG,
- RNG_ALARMCNT_REG,
- RNG_FROENABLE_REG,
- RNG_FRODETUNE_REG,
- RNG_ALARMMASK_REG,
- RNG_ALARMSTOP_REG,
- RNG_REV_REG
-};
-
-static uint16_t reg_map_eip76[] = {
- [RNG_OUTPUT_0_REG] = 0x0,
- [RNG_OUTPUT_1_REG] = 0x4,
- [RNG_OUTPUT_2_REG] = 0x8,
- [RNG_OUTPUT_3_REG] = 0xc,
- [RNG_STATUS_REG] = 0x10,
- [RNG_INTACK_REG] = 0x10,
- [RNG_CONTROL_REG] = 0x14,
- [RNG_CONFIG_REG] = 0x18,
- [RNG_ALARMCNT_REG] = 0x1c,
- [RNG_FROENABLE_REG] = 0x20,
- [RNG_FRODETUNE_REG] = 0x24,
- [RNG_ALARMMASK_REG] = 0x28,
- [RNG_ALARMSTOP_REG] = 0x2c,
- [RNG_REV_REG] = 0x7c,
-};
-
-struct eip76_rng_dev {
- uintptr_t base;
- uint16_t *regs;
-};
-
-/* Locals */
-static struct eip76_rng_dev eip76_dev;
-static spinlock_t rng_lock;
-
-static inline uint32_t eip76_rng_read(struct eip76_rng_dev *dev, uint16_t reg)
-{
- return mmio_read_32(dev->base + dev->regs[reg]);
-}
-
-static inline void eip76_rng_write(struct eip76_rng_dev *dev,
- uint16_t reg, uint32_t val)
-{
- mmio_write_32(dev->base + dev->regs[reg], val);
-}
-
-static void eip76_rng_init(struct eip76_rng_dev *dev)
-{
- uint32_t val;
-
- /* Return if RNG is already running. */
- if (eip76_rng_read(dev, RNG_CONTROL_REG) &
- RNG_CONTROL_ENABLE_TRNG_MASK) {
- return;
- }
-
- /* This field sets the number of 512-bit blocks of raw Noise Source
- * output data that must be processed by either the Conditioning
- * Function or the SP 800-90 DRBG ‘BC_DF’ functionality to yield
- * a ‘full entropy’ output value. As according to [SP 800-90B draft]
- * the amount of entropy input to this functionality must be twice
- * the amount that is output and the 8-bit samples output by the Noise
- * Source are supposed to have one bit of entropy each, the settings
- * for this field are as follows:
- * - SHA-1 Conditioning Function:
- * generates 160 bits output, requiring 2560 sample bits,
- * equivalent to 5 blocks of raw Noise Source input.
- * - SHA-256 Conditioning Function:
- * generates 256 bits output, requiring 4096 sample bits, equivalent
- * to 8 blocks of raw Noise Source input. Note that two blocks of 256
- * bits are needed to start or re-seed the SP 800-90 DRBG
- * (in the EIP-76d-*-SHA2 configurations)
- * - SP 800-90 DRBG ‘BC_DF’ functionality:
- * generates 384 bits output, requiring 6144 sample bits, equivalent
- * to 12 blocks of raw Noise Source input.
- * This field can only be modified when ‘enable_trng’ in TRNG_CONTROL
- * is ‘0’ or when either of the ‘test_known_noise’ or ‘test_cond_func’
- * bits in TRNG_TEST is ‘1’. Value 0 in this field selects 256 blocks
- * of 512 bits to be processed.
- */
- val = RNG_CONFIG_NOISE_BLOCKS(RNG_CONFIG_NOISE_BLK_VAL);
-
- /* This field sets the number of FRO samples that are XOR-ed together
- * into one bit to be shifted into the main shift register.
- * This value must be such that there is at least one bit of entropy
- * (in total) in each 8 bits that are shifted.
- * This field can only be modified when ‘enable_trng’ in TRNG_CONTROL
- * is ‘0’ or when either of the ‘test_known_noise’ or ‘test_cond_func’
- * bits in TRNG_TEST is ‘1’. Value 0 in this field selects 65536 FRO
- * samples to be XOR-ed together
- */
- val |= RNG_CONFIG_SAMPLE_CYCLES(RNG_CONFIG_SAMPLE_CYCLES_VAL);
- eip76_rng_write(dev, RNG_CONFIG_REG, val);
-
- /* Enable all available FROs */
- eip76_rng_write(dev, RNG_FRODETUNE_REG, RNG_REG_FRO_DETUNE_MASK);
- eip76_rng_write(dev, RNG_FROENABLE_REG, RNG_REG_FRO_ENABLE_MASK);
-
- /* Enable TRNG */
- eip76_rng_write(dev, RNG_CONTROL_REG, RNG_CONTROL_ENABLE_TRNG_MASK);
-}
-
-int32_t eip76_rng_read_rand_buf(void *data, bool wait)
-{
- uint32_t i, present;
-
- if (!eip76_dev.base) /* not initialized */
- return -1;
-
- for (i = 0; i < EIP76_RNG_WAIT_ROUNDS; i++) {
- present = eip76_rng_read(&eip76_dev, RNG_STATUS_REG) &
- RNG_REG_STATUS_RDY;
- if (present || !wait) {
- break;
- }
-
- udelay(10);
- }
-
- if (present != 0U) {
- return 0;
- }
-
- memcpy(data,
- (void *)(eip76_dev.base + eip76_dev.regs[RNG_OUTPUT_0_REG]),
- EIP76_RNG_OUTPUT_SIZE);
-
- eip76_rng_write(&eip76_dev, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
-
- return EIP76_RNG_OUTPUT_SIZE;
-}
-
-int32_t eip76_rng_probe(uintptr_t base_addr)
-{
- uint32_t ver;
-
- eip76_dev.base = base_addr;
- eip76_dev.regs = reg_map_eip76;
-
- eip76_rng_init(&eip76_dev);
-
- ver = eip76_rng_read(&eip76_dev, RNG_REV_REG);
-
- INFO("%s Random Number Generator HW ver. %01x.%01x.%01x\n",
- RNG_HW_IS_EIP76(ver) ? "TRNG-IP-76" : "Unknown",
- RNG_HW_VER_MAJOR(ver), RNG_HW_VER_MINOR(ver),
- RNG_HW_VER_PATCH(ver));
-
- return 0;
-}
-
-int32_t eip76_rng_get_random(uint8_t *data, uint32_t len)
-{
- static uint8_t rand[EIP76_RNG_OUTPUT_SIZE];
- static uint8_t pos;
- uint32_t i;
- int32_t ret = 0;
-
- if (!data)
- return -1;
-
- spin_lock(&rng_lock);
-
- for (i = 0; i < len; i++) {
- if (pos >= EIP76_RNG_OUTPUT_SIZE) {
- pos = 0;
- }
-
- if (pos != 0U) {
- ret = eip76_rng_read_rand_buf(rand, true);
- }
-
- /* Only advance FIFO index if it is non zero or
- * the update from TRNG HW was successful
- */
- if (pos || ret > 0) {
- data[i] = rand[pos++];
- ret = 0;
- } else {
- ret = -1;
- break;
- }
- }
-
- spin_unlock(&rng_lock);
-
- return ret;
-}
diff --git a/drivers/renesas/common/scif/scif.S b/drivers/renesas/common/scif/scif.S
index 72b5b4b..22ade9b 100644
--- a/drivers/renesas/common/scif/scif.S
+++ b/drivers/renesas/common/scif/scif.S
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,18 +9,13 @@
#include <asm_macros.S>
#include <console_macros.S>
#include <drivers/renesas/rcar/console/console.h>
+#include <platform_def.h>
#define SCIF_INTERNAL_CLK 0
#define SCIF_EXTARNAL_CLK 1
#define SCIF_CLK SCIF_INTERNAL_CLK
-/* product register */
-#define PRR (0xFFF00044)
-#define PRR_PRODUCT_MASK (0x00007F00)
-#define PRR_CUT_MASK (0x000000FF)
#define PRR_PRODUCT_H3_VER_10 (0x00004F00)
-#define PRR_PRODUCT_E3 (0x00005700)
-#define PRR_PRODUCT_D3 (0x00005800)
/* module stop */
#define CPG_BASE (0xE6150000)
@@ -60,7 +56,6 @@
#endif
/* mode pin */
-#define RST_MODEMR (0xE6160060)
#define MODEMR_MD12 (0x00001000)
#define SCSMR_CA_MASK (1 << 7)
diff --git a/drivers/st/bsec/bsec3.c b/drivers/st/bsec/bsec3.c
index 3fdaf16..03d8928 100644
--- a/drivers/st/bsec/bsec3.c
+++ b/drivers/st/bsec/bsec3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,18 +30,6 @@
#define BSEC_OTP_BANK_SHIFT U(5)
#define BSEC_TIMEOUT_VALUE U(0x800000) /* ~7sec @1.2GHz */
-/* Magic use to indicated valid SHADOW = 'B' 'S' 'E' 'C' */
-#define BSEC_MAGIC U(0x42534543)
-
-#define OTP_MAX_SIZE (STM32MP2_OTP_MAX_ID + U(1))
-
-struct bsec_shadow {
- uint32_t magic;
- uint32_t state;
- uint32_t value[OTP_MAX_SIZE];
- uint32_t status[OTP_MAX_SIZE];
-};
-
static uint32_t otp_bank(uint32_t otp)
{
if (otp > STM32MP2_OTP_MAX_ID) {
@@ -167,7 +155,7 @@
ERROR("BSEC reset critical error 0x%x\n", status);
panic();
}
- if ((status & BSEC_OTPSR_FUSEOK) != BSEC_OTPSR_FUSEOK) {
+ if ((status & BSEC_OTPSR_INIT_DONE) != BSEC_OTPSR_INIT_DONE) {
ERROR("BSEC reset critical error 0x%x\n", status);
panic();
}
@@ -467,8 +455,8 @@
uint32_t status = bsec_get_status();
uint32_t bsec_sr = mmio_read_32(BSEC_BASE + BSEC_SR);
- if ((status & BSEC_OTPSR_FUSEOK) == BSEC_OTPSR_FUSEOK) {
- /* NVSTATE is only valid if FUSEOK */
+ if ((status & BSEC_OTPSR_INIT_DONE) == BSEC_OTPSR_INIT_DONE) {
+ /* NVSTATE is only valid if INIT_DONE */
uint32_t nvstates = (bsec_sr & BSEC_SR_NVSTATE_MASK) >> BSEC_SR_NVSTATE_SHIFT;
if (nvstates == BSEC_SR_NVSTATE_OPEN) {
diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c
index 12839f1..1266e00 100644
--- a/drivers/st/clk/clk-stm32mp2.c
+++ b/drivers/st/clk/clk-stm32mp2.c
@@ -105,7 +105,9 @@
_SPDIFSYMB,
_CK_PLL1,
_CK_PLL2,
+#if !STM32MP21
_CK_PLL3,
+#endif /* !STM32MP21 */
_CK_PLL4,
_CK_PLL5,
_CK_PLL6,
@@ -180,6 +182,9 @@
_CK_ICN_APB2,
_CK_ICN_APB3,
_CK_ICN_APB4,
+#if STM32MP21
+ _CK_ICN_APB5,
+#endif /* STM32MP21 */
_CK_ICN_APBDBG,
_CK_BKPSRAM,
_CK_BSEC,
@@ -200,51 +205,82 @@
_CK_GPIOG,
_CK_GPIOH,
_CK_GPIOI,
+#if !STM32MP21
_CK_GPIOJ,
_CK_GPIOK,
+#endif /* !STM32MP21 */
_CK_GPIOZ,
+#if STM32MP21
+ _CK_HASH1,
+ _CK_HASH2,
+#else /* STM32MP21 */
_CK_HASH,
+#endif /* STM32MP21 */
_CK_I2C1,
_CK_I2C2,
+#if !STM32MP23
_CK_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
_CK_I2C4,
_CK_I2C5,
_CK_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
_CK_I2C7,
_CK_I2C8,
+#endif /* !STM32MP21 */
_CK_IWDG1,
_CK_IWDG2,
_CK_OSPI1,
+#if !STM32MP21
_CK_OSPI2,
_CK_OSPIIOM,
+#endif /* !STM32MP21 */
_CK_PKA,
_CK_RETRAM,
+#if STM32MP21
+ _CK_RNG1,
+ _CK_RNG2,
+#else /* STM32MP21 */
_CK_RNG,
+#endif /* STM32MP21 */
_CK_RTC,
_CK_SAES,
_CK_SDMMC1,
_CK_SDMMC2,
_CK_SRAM1,
+#if !STM32MP21
_CK_SRAM2,
+#endif /* !STM32MP21 */
_CK_STGEN,
_CK_SYSCPU1,
_CK_SYSRAM,
_CK_UART4,
_CK_UART5,
_CK_UART7,
+#if STM32MP25
_CK_UART8,
_CK_UART9,
+#endif /* STM32MP25 */
_CK_USART1,
_CK_USART2,
_CK_USART3,
_CK_USART6,
+#if STM32MP21
+ _CK_USBHEHCI,
+ _CK_USBHOHCI,
+#else /* STM32MP21 */
_CK_USB2EHCI,
_CK_USB2OHCI,
+#endif /* STM32MP21 */
_CK_USB2PHY1,
_CK_USB2PHY2,
+#if !STM32MP21
_CK_USB3DR,
_CK_USB3PCIEPHY,
_CK_USBTC,
+#endif /* !STM32MP21 */
CK_LAST
};
@@ -271,6 +307,7 @@
_CK_FLEXGEN_58, _CK_HSE
};
+#if !STM32MP21
static const uint16_t usb3pciphy_src[] = {
_CK_FLEXGEN_34, _CK_HSE
};
@@ -278,6 +315,7 @@
static const uint16_t d3per_src[] = {
_CK_MSI, _CK_LSI, _CK_LSE
};
+#endif /* !STM32MP21 */
#define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\
.id_parents = src,\
@@ -290,7 +328,7 @@
},\
}
-static const struct parent_cfg parent_mp25[] = {
+static const struct parent_cfg parent_mp2[] = {
MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2),
MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2),
MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2),
@@ -303,8 +341,10 @@
MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
+#if !STM32MP21
MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2),
+#endif /* !STM32MP21 */
};
/* GATES */
@@ -324,15 +364,26 @@
GATE_SYSRAM,
GATE_RETRAM,
GATE_SRAM1,
+#if !STM32MP21
GATE_SRAM2,
+#endif /* !STM32MP21 */
GATE_DDRPHYC,
GATE_SYSCPU1,
GATE_CRC,
+#if !STM32MP21
GATE_OSPIIOM,
+#endif /* !STM32MP21 */
GATE_BKPSRAM,
+#if STM32MP21
+ GATE_HASH1,
+ GATE_HASH2,
+ GATE_RNG1,
+ GATE_RNG2,
+#else /* STM32MP21 */
GATE_HASH,
GATE_RNG,
+#endif /* STM32MP21 */
GATE_CRYP1,
GATE_CRYP2,
GATE_SAES,
@@ -347,18 +398,27 @@
GATE_GPIOG,
GATE_GPIOH,
GATE_GPIOI,
+#if !STM32MP21
GATE_GPIOJ,
GATE_GPIOK,
+#endif /* !STM32MP21 */
GATE_GPIOZ,
GATE_RTC,
GATE_DDRCP,
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ GATE_USBHOHCI,
+ GATE_USBHEHCI,
+#else /* STM32MP21 */
GATE_USB2OHCI,
GATE_USB2EHCI,
+#endif /* STM32MP21 */
+#if !STM32MP21
GATE_USB3DR,
+#endif /* !STM32MP21 */
GATE_BSEC,
GATE_IWDG1,
@@ -373,22 +433,34 @@
GATE_UART5,
GATE_I2C1,
GATE_I2C2,
+#if !STM32MP23
GATE_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
GATE_I2C5,
GATE_I2C4,
GATE_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
GATE_I2C7,
+#endif /* !STM32MP21 */
GATE_USART1,
GATE_USART6,
GATE_UART7,
+#if STM32MP25
GATE_UART8,
GATE_UART9,
+#endif /* STM32MP25 */
GATE_STGEN,
+#if !STM32MP21
GATE_USB3PCIEPHY,
GATE_USBTC,
GATE_I2C8,
+#endif /* !STM32MP21 */
GATE_OSPI1,
+#if !STM32MP21
GATE_OSPI2,
+#endif /* !STM32MP21 */
GATE_FMC,
GATE_SDMMC1,
GATE_SDMMC2,
@@ -403,30 +475,57 @@
.set_clr = (_offset_clr),\
}
-static const struct gate_cfg gates_mp25[LAST_GATE] = {
+static const struct gate_cfg gates_mp2[LAST_GATE] = {
GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
+#if STM32MP21
+ GATE_CFG(GATE_LSI, RCC_LSICR, 0, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
+#if STM32MP21
+ GATE_CFG(GATE_MSI, RCC_OCENSETR, 2, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0),
+#endif /* STM32MP21 */
+#if STM32MP21
+ GATE_CFG(GATE_LSI_RDY, RCC_LSICR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
+#if STM32MP21
+ GATE_CFG(GATE_MSI_RDY, RCC_OCRDYR, 2, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0),
GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0),
GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCAPBCFGR, 1, 0),
GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0),
GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0),
+#if STM32MP21
+ GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0),
+ GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0),
+ GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0),
+ GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
@@ -440,16 +539,23 @@
GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0),
GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0),
GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0),
GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0),
GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0),
GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0),
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ GATE_CFG(GATE_USBHOHCI, RCC_USBHCFGR, 1, 0),
+ GATE_CFG(GATE_USBHEHCI, RCC_USBHCFGR, 1, 0),
+#else /* STM32MP21 */
GATE_CFG(GATE_USB2OHCI, RCC_USB2CFGR, 1, 0),
GATE_CFG(GATE_USB2EHCI, RCC_USB2CFGR, 1, 0),
GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
+#endif /* STM32MP21 */
GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0),
GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
@@ -461,22 +567,34 @@
GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
+#if !STM32MP23
GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
+#endif /* !STM32MP23 */
+#if STM32MP25
GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
+#endif /* STM32MP25 */
+#if !STM32MP21
GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
+#if STM32MP25
GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
+#endif /* STM32MP25 */
GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),
GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
+#if !STM32MP21
GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0),
+#endif /* !STM32MP21 */
GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0),
GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
@@ -499,11 +617,14 @@
.bitrdy = _bitrdy,\
}
-static const struct div_cfg dividers_mp25[] = {
+static const struct div_cfg dividers_mp2[] = {
DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
+#if STM32MP21
+ DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
+#endif /* STM32MP21 */
DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
@@ -520,7 +641,7 @@
NB_OSCILLATOR
};
-static struct clk_oscillator_data stm32mp25_osc_data[] = {
+static struct clk_oscillator_data stm32mp2_osc_data[] = {
OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
NULL, NULL, NULL),
@@ -551,7 +672,7 @@
static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
{
if (id < NB_OSCILLATOR) {
- return stm32mp25_osc_data[id].name;
+ return stm32mp2_osc_data[id].name;
}
return NULL;
@@ -590,10 +711,12 @@
.reg_pllxcfgr1 = (_reg),\
}
-static const struct stm32_clk_pll stm32mp25_clk_pll[_PLL_NB] = {
+static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = {
CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1),
+#if !STM32MP21
CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1),
+#endif /* !STM32MP21 */
CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1),
CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1),
CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1),
@@ -603,7 +726,7 @@
static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
{
- return &stm32mp25_clk_pll[idx];
+ return &stm32mp2_clk_pll[idx];
}
static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,
@@ -958,6 +1081,7 @@
#define RCC_16_MHZ UL(16000000)
#ifdef IMAGE_BL2
+#if !STM32MP21
static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
unsigned long prate)
{
@@ -982,12 +1106,16 @@
return ret;
}
+#endif /* !STM32MP21 */
#endif /* IMAGE_BL2 */
static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,
int id __unused,
unsigned long prate __unused)
{
+#if STM32MP21
+ return RCC_16_MHZ;
+#else /* STM32MP21 */
uintptr_t address = priv->base + RCC_BDCR;
if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) {
@@ -995,6 +1123,7 @@
} else {
return RCC_16_MHZ;
}
+#endif /* STM32MP21 */
}
static const struct stm32_clk_ops clk_stm32_osc_msi_ops = {
@@ -1039,10 +1168,10 @@
STM32_OSC_MSI_OPS,
STM32_RTC_OPS,
- MP25_LAST_OPS
+ MP2_LAST_OPS
};
-static const struct stm32_clk_ops *ops_array_mp25[MP25_LAST_OPS] = {
+static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = {
[NO_OPS] = NULL,
[FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
[GATE_OPS] = &clk_gate_ops,
@@ -1061,7 +1190,7 @@
[STM32_RTC_OPS] = &clk_stm32_rtc_ops
};
-static const struct clk_stm32 stm32mp25_clk[CK_LAST] = {
+static const struct clk_stm32 stm32mp2_clk[CK_LAST] = {
CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ),
/* ROOT CLOCKS */
@@ -1081,7 +1210,9 @@
CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
+#if !STM32MP21
CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
+#endif /* !STM32MP21 */
CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
@@ -1158,21 +1289,35 @@
STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2),
STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3),
STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4),
+#if STM32MP21
+ STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5),
+#endif /* STM32MP21 */
STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG),
/* KERNEL CLOCK */
STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM),
STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM),
STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1),
+#if !STM32MP21
STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC),
STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1),
STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC),
+#if !STM32MP21
STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM),
+#if STM32MP21
+ STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1),
+ STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2),
+ STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1),
+ STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2),
+#else /* STM32MP21 */
STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH),
STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG),
+#endif /* STM32MP21 */
STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1),
STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2),
STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES),
@@ -1187,18 +1332,27 @@
STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG),
STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH),
STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI),
+#if !STM32MP21
STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ),
STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ),
STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC),
STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP),
/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+ STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI),
+ STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI),
+#else /* STM32MP21 */
STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI),
STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI),
+#endif /* STM32MP21 */
+#if !STM32MP21
STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC),
STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1),
@@ -1211,24 +1365,41 @@
STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4),
STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3),
STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5),
+#if STM32MP21
+ STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1),
+ STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2),
+ STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1),
+ STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6),
+ STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7),
+ STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3),
+#else /* STM32MP21 */
STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1),
STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2),
+#if STM32MP25
STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3),
STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5),
STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4),
STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6),
+#endif /* STM32MP25 */
STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7),
STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1),
STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6),
STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7),
+#if STM32MP25
STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8),
STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9),
+#endif /* STM32MP25 */
+#endif /* STM32MP21 */
STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN),
+#if !STM32MP21
STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY),
STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC),
STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1),
+#if !STM32MP21
STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2),
+#endif /* !STM32MP21 */
STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC),
STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1),
STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2),
@@ -1240,7 +1411,9 @@
CLKSRC_CA35SS,
CLKSRC_PLL1,
CLKSRC_PLL2,
+#if !STM32MP21
CLKSRC_PLL3,
+#endif /* !STM32MP21 */
CLKSRC_PLL4,
CLKSRC_PLL5,
CLKSRC_PLL6,
@@ -1656,6 +1829,11 @@
int err;
for (i = _PLL1; i < _PLL_NB; i++) {
+#if STM32MP21
+ if (i == _PLL3) {
+ continue;
+ }
+#endif
err = clk_stm32_pll_init(priv, i);
if (err) {
return err;
@@ -1886,6 +2064,7 @@
static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)
{
+#if !STM32MP21
struct stm32_clk_platdata *pdata = priv->pdata;
struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
int err;
@@ -1896,6 +2075,7 @@
osci->freq / 1000000U);
panic();
}
+#endif /* !STM32MP21 */
_clk_stm32_enable(priv, _CK_MSI);
}
@@ -2204,6 +2384,11 @@
int subnode = 0;
int err = 0;
+#if STM32MP21
+ if (i == _PLL3) {
+ continue;
+ }
+#endif
snprintf(name, sizeof(name), "st,pll-%u", i + 1);
subnode = fdt_subnode_offset(fdt, node, name);
@@ -2266,49 +2451,53 @@
}
#endif /* IMAGE_BL2 */
-static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR];
+static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR];
-static struct stm32_pll_dt_cfg mp25_pll[_PLL_NB];
+static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB];
#define DT_FLEXGEN_CLK_MAX 64
-static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX];
+static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX];
+#if STM32MP21
+#define DT_BUS_CLK_MAX 7
+#else /* STM32MP21 */
#define DT_BUS_CLK_MAX 6
-static uint32_t mp25_busclk[DT_BUS_CLK_MAX];
+#endif /* STM32MP21 */
+static uint32_t mp2_busclk[DT_BUS_CLK_MAX];
#define DT_KERNEL_CLK_MAX 20
-static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX];
+static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX];
-static struct stm32_clk_platdata stm32mp25_pdata = {
- .osci = mp25_osci,
+static struct stm32_clk_platdata stm32mp2_pdata = {
+ .osci = mp2_osci,
.nosci = NB_OSCILLATOR,
- .pll = mp25_pll,
+ .pll = mp2_pll,
.npll = _PLL_NB,
- .flexgen = mp25_flexgen,
+ .flexgen = mp2_flexgen,
.nflexgen = DT_FLEXGEN_CLK_MAX,
- .busclk = mp25_busclk,
+ .busclk = mp2_busclk,
.nbusclk = DT_BUS_CLK_MAX,
- .kernelclk = mp25_kernelclk,
+ .kernelclk = mp2_kernelclk,
.nkernelclk = DT_KERNEL_CLK_MAX,
};
-static uint8_t refcounts_mp25[CK_LAST];
+static uint8_t refcounts_mp2[CK_LAST];
-static struct stm32_clk_priv stm32mp25_clock_data = {
+static struct stm32_clk_priv stm32mp2_clock_data = {
.base = RCC_BASE,
- .num = ARRAY_SIZE(stm32mp25_clk),
- .clks = stm32mp25_clk,
- .parents = parent_mp25,
- .nb_parents = ARRAY_SIZE(parent_mp25),
- .gates = gates_mp25,
- .nb_gates = ARRAY_SIZE(gates_mp25),
- .div = dividers_mp25,
- .nb_div = ARRAY_SIZE(dividers_mp25),
- .osci_data = stm32mp25_osc_data,
- .nb_osci_data = ARRAY_SIZE(stm32mp25_osc_data),
- .gate_refcounts = refcounts_mp25,
- .pdata = &stm32mp25_pdata,
- .ops_array = ops_array_mp25,
+ .num = ARRAY_SIZE(stm32mp2_clk),
+ .clks = stm32mp2_clk,
+ .parents = parent_mp2,
+ .nb_parents = ARRAY_SIZE(parent_mp2),
+ .gates = gates_mp2,
+ .nb_gates = ARRAY_SIZE(gates_mp2),
+ .div = dividers_mp2,
+ .nb_div = ARRAY_SIZE(dividers_mp2),
+ .osci_data = stm32mp2_osc_data,
+ .nb_osci_data = ARRAY_SIZE(stm32mp2_osc_data),
+ .gate_refcounts = refcounts_mp2,
+ .pdata = &stm32mp2_pdata,
+ .ops_array = ops_array_mp2,
};
int stm32mp2_clk_init(void)
@@ -2317,13 +2506,13 @@
int ret;
#ifdef IMAGE_BL2
- ret = stm32_clk_parse_fdt(&stm32mp25_pdata);
+ ret = stm32_clk_parse_fdt(&stm32mp2_pdata);
if (ret != 0) {
return ret;
}
#endif
- ret = clk_stm32_init(&stm32mp25_clock_data, base);
+ ret = clk_stm32_init(&stm32mp2_clock_data, base);
if (ret != 0) {
return ret;
}
diff --git a/drivers/st/crypto/stm32_saes.c b/drivers/st/crypto/stm32_saes.c
index f4da571..547ff89 100644
--- a/drivers/st/crypto/stm32_saes.c
+++ b/drivers/st/crypto/stm32_saes.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -211,9 +211,11 @@
uint64_t timeout;
/* Reset IP */
- mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
- udelay(SAES_RESET_DELAY);
- mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+ if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) != _SAES_SR_BUSY) {
+ mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+ udelay(SAES_RESET_DELAY);
+ mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+ }
timeout = timeout_init_us(SAES_TIMEOUT_US);
while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) {
diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c
index a2a4082..8efb7cf 100644
--- a/drivers/st/ddr/stm32mp2_ddr_helpers.c
+++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -363,8 +363,6 @@
mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
- /* TODO: check if ddr_sr_exit_loop() is needed here */
-
return 0;
}
@@ -390,13 +388,6 @@
return ddr_sr_exit_loop();
}
-uint32_t ddr_get_io_calibration_val(void)
-{
- /* TODO create related service */
-
- return 0U;
-}
-
int ddr_sr_entry(bool standby)
{
int ret = -EINVAL;
diff --git a/drivers/st/ddr/stm32mp2_ram.c b/drivers/st/ddr/stm32mp2_ram.c
index 95f05e7..2b0e317 100644
--- a/drivers/st/ddr/stm32mp2_ram.c
+++ b/drivers/st/ddr/stm32mp2_ram.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -142,9 +142,6 @@
ERROR("DDR rw test: can't access memory @ 0x%lx\n", uret);
panic();
}
-
- /* TODO Restore area overwritten by training */
- //stm32_restore_ddr_training_area();
} else {
size_t retsize;
diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c
index 98968d5..4aa5c73 100644
--- a/drivers/st/ddr/stm32mp_ddr.c
+++ b/drivers/st/ddr/stm32mp_ddr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,7 +44,7 @@
ddr_registers[type].name, i);
panic();
} else {
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
if (desc[i].qd) {
stm32mp_ddr_start_sw_done(priv->ctl);
}
@@ -52,7 +52,7 @@
value = *((uint32_t *)((uintptr_t)param +
desc[i].par_offset));
mmio_write_32(ptr, value);
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
if (desc[i].qd) {
stm32mp_ddr_wait_sw_done_ack(priv->ctl);
}
@@ -277,9 +277,9 @@
/* Toggle rfshctl3.refresh_update_level */
rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);
if ((rfshctl3 & refresh_update_level) == refresh_update_level) {
- mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
- } else {
mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
+ } else {
+ mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
refresh_update_level = 0U;
}
@@ -293,7 +293,7 @@
if (timeout_elapsed(timeout)) {
panic();
}
- } while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) != refresh_update_level);
+ } while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) == refresh_update_level);
VERBOSE("[0x%lx] rfshctl3 = 0x%x\n", (uintptr_t)&ctl->rfshctl3, rfshctl3);
}
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 44d7c09..2d64de3 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -282,7 +282,7 @@
clk_disable(clock);
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
if (status == DT_SECURE) {
stm32mp_register_secure_gpio(bank, pin);
#if !IMAGE_BL2
diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c
index 74451d7..3d78c20 100644
--- a/drivers/st/iwdg/stm32_iwdg.c
+++ b/drivers/st/iwdg/stm32_iwdg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,7 +33,6 @@
uintptr_t base;
unsigned long clock;
uint8_t flags;
- int num_irq;
};
static struct stm32_iwdg_instance stm32_iwdg[IWDG_MAX_INSTANCE];
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 66988d7..e07d9e7 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -129,7 +129,7 @@
#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
#endif
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
#define SDMMC_FIFO_SIZE 64U
#else
#define SDMMC_FIFO_SIZE 1024U
diff --git a/drivers/st/regulator/regulator_fixed.c b/drivers/st/regulator/regulator_fixed.c
index 6c9d3b1..6b14b5d 100644
--- a/drivers/st/regulator/regulator_fixed.c
+++ b/drivers/st/regulator/regulator_fixed.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,6 @@
struct fixed_data {
char name[FIXED_NAME_LEN];
- uint16_t volt;
struct regul_description desc;
};
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
deleted file mode 100644
index fa16dcd..0000000
--- a/fdts/tc2.dts
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/dts-v1/;
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <platform_def.h>
-
-#if TARGET_FLAVOUR_FVP
-#define LIT_CAPACITY 406
-#define MID_CAPACITY 912
-#else /* TARGET_FLAVOUR_FPGA */
-#define LIT_CAPACITY 280
-#define MID_CAPACITY 775
-/* this is an area optimized configuration of the big core */
-#define BIG2_CAPACITY 930
-#endif /* TARGET_FLAVOUR_FPGA */
-#define BIG_CAPACITY 1024
-
-#define MHU_TX_ADDR 45000000 /* hex */
-#define MHU_TX_COMPAT "arm,mhuv2-tx","arm,primecell"
-#define MHU_TX_INT_NAME "mhu_tx"
-
-#define MHU_RX_ADDR 45010000 /* hex */
-#define MHU_RX_COMPAT "arm,mhuv2-rx","arm,primecell"
-#define MHU_OFFSET 0x1000
-#define MHU_MBOX_CELLS 2
-#define MHU_RX_INT_NUM 317
-#define MHU_RX_INT_NAME "mhu_rx"
-
-#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
-#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a720-pmu"
-#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x4-pmu"
-
-#define DSU_MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
-
-#define DPU_ADDR 2cc00000
-#define DPU_IRQ 69
-
-#define ETHERNET_ADDR 18000000
-#define ETHERNET_INT 109
-
-#define SYS_REGS_ADDR 1c010000
-
-#define MMC_ADDR 1c050000
-#define MMC_INT_0 107
-#define MMC_INT_1 108
-
-#define RTC_ADDR 1c170000
-#define RTC_INT 100
-
-#define KMI_0_ADDR 1c060000
-#define KMI_0_INT 197
-#define KMI_1_ADDR 1c070000
-#define KMI_1_INT 103
-
-#define VIRTIO_BLOCK_ADDR 1c130000
-#define VIRTIO_BLOCK_INT 204
-
-#include "tc-common.dtsi"
-#if TARGET_FLAVOUR_FVP
-#include "tc-fvp.dtsi"
-#else
-#include "tc-fpga.dtsi"
-#endif /* TARGET_FLAVOUR_FVP */
-#include "tc-base.dtsi"
-
-/ {
- cpus {
-#if TARGET_FLAVOUR_FPGA
- cpu-map {
- cluster0 {
- core8 {
- cpu = <&CPU8>;
- };
- core9 {
- cpu = <&CPU9>;
- };
- core10 {
- cpu = <&CPU10>;
- };
- core11 {
- cpu = <&CPU11>;
- };
- core12 {
- cpu = <&CPU12>;
- };
- core13 {
- cpu = <&CPU13>;
- };
- };
- };
-#endif
-
- CPU2:cpu@200 {
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
- };
-
- CPU3:cpu@300 {
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
- };
-
- CPU6:cpu@600 {
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- };
-
- CPU7:cpu@700 {
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- };
-
-#if TARGET_FLAVOUR_FPGA
- CPU8:cpu@800 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x800>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- };
-
- CPU9:cpu@900 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x900>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- };
-
- CPU10:cpu@A00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xA00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- };
-
- CPU11:cpu@B00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xB00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- };
-
- CPU12:cpu@C00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xC00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
- };
-
- CPU13:cpu@D00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xD00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
- };
-#endif
- };
-
-#if TARGET_FLAVOUR_FPGA
- ete8 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU8>;
- };
-
- ete9 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU9>;
- };
-
- ete10 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU10>;
- };
-
- ete11 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU11>;
- };
-
- ete12 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU12>;
- };
-
- ete13 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU13>;
- };
-#endif /* TARGET_FLAVOUR_FPGA */
-
- cmn-pmu {
- compatible = "arm,ci-700";
- reg = <0x0 0x50000000 0x0 0x10000000>;
- interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>;
- };
-
- mbox_db_rx: mhu@MHU_RX_ADDR {
- arm,mhuv2-protocols = <0 1>;
- };
-
- mbox_db_tx: mhu@MHU_TX_ADDR {
- arm,mhuv2-protocols = <0 1>;
- };
-
- firmware {
- /*
- * TC2 does not have a P2A channel, but wiring one was needed to make Linux work
- * (by chance). At the time the SCMI driver did not support bidirectional
- * mailboxes so as a workaround, the A2P channel was wired for TX communication
- * and the synchronous replies would be read asyncrhonously as if coming from
- * the P2A channel, while being the actual A2P channel.
- *
- * This will not work with kernels > 5.15, but keep it around to keep TC2
- * working with its target kernel. Newer kernels will still work, but SCMI
- * won't as they check that the two regions are distinct.
- */
- scmi {
- mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0>;
- shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_a2p>;
- };
- };
-
- gic: interrupt-controller@GIC_CTRL_ADDR {
- ppi-partitions {
- ppi_partition_little: interrupt-partition-0 {
- affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
- };
-
-#if TARGET_FLAVOUR_FVP
- ppi_partition_mid: interrupt-partition-1 {
- affinity = <&CPU4>, <&CPU5>, <&CPU6>;
- };
-
- ppi_partition_big: interrupt-partition-2 {
- affinity = <&CPU7>;
- };
-#elif TARGET_FLAVOUR_FPGA
- ppi_partition_mid: interrupt-partition-1 {
- affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>, <&CPU8>;
- };
-
- ppi_partition_big: interrupt-partition-2 {
- affinity = <&CPU9>, <&CPU10>, <&CPU11>, <&CPU12>, <&CPU13>;
- };
-#endif
- };
- };
-
- spe-pmu-big {
- status = "okay";
- };
-
- smmu_700: iommu@3f000000 {
- status = "okay";
- };
-
- dp0: display@DPU_ADDR {
-#if TC_SCMI_PD_CTRL_EN
- power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
-#endif
- iommus = <&smmu_700 0x100>;
- };
-
- gpu: gpu@2d000000 {
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
- <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
- interrupt-names = "JOB", "MMU", "GPU";
- iommus = <&smmu_700 0x200>;
- };
-};
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 3707520..e8c4054 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -251,7 +251,7 @@
#define ID_AA64DFR0_PMUVER_SHIFT U(8)
#define ID_AA64DFR0_PMUVER_MASK U(0xf)
#define ID_AA64DFR0_PMUVER_PMUV3 U(1)
-#define ID_AA64DFR0_PMUVER_PMUV3P8 U(8)
+#define ID_AA64DFR0_PMUVER_PMUV3P9 U(9)
#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
/* ID_AA64DFR0_EL1.SEBEP definitions */
@@ -606,6 +606,11 @@
#define SCTLR_EPAN_BIT (ULL(1) << 57)
#define SCTLR_RESET_VAL SCTLR_EL3_RES1
+#define SCTLR2_EnPACM_BIT (ULL(1) << 7)
+
+/* SCTLR2 currently has no RES1 fields so reset to 0 */
+#define SCTLR2_RESET_VAL ULL(0)
+
/* CPACR_EL1 definitions */
#define CPACR_EL1_FPEN(x) ((x) << 20)
#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
@@ -664,6 +669,7 @@
/* MDCR_EL3 definitions */
#define MDCR_EBWE_BIT (ULL(1) << 43)
+#define MDCR_EnPMS3_BIT (ULL(1) << 42)
#define MDCR_E3BREC_BIT (ULL(1) << 38)
#define MDCR_E3BREW_BIT (ULL(1) << 37)
#define MDCR_EnPMSN_BIT (ULL(1) << 36)
@@ -696,6 +702,7 @@
#define MDCR_NSPBE_BIT (ULL(1) << 11)
#define MDCR_TDOSA_BIT (ULL(1) << 10)
#define MDCR_TDA_BIT (ULL(1) << 9)
+#define MDCR_EnPM2_BIT (ULL(1) << 7)
#define MDCR_TPM_BIT (ULL(1) << 6)
#define MDCR_RLTE_BIT (ULL(1) << 0)
#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT
@@ -855,6 +862,7 @@
#define SPSR_PPEND_BIT BIT(33)
#define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34)
#define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT)
+#define SPSR_PACM_BIT_AARCH64 BIT_64(35)
#define DISABLE_ALL_EXCEPTIONS \
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
@@ -1531,6 +1539,7 @@
/*******************************************************************************
* FEAT_SCTLR2 - Extension to SCTLR_ELx Registers
******************************************************************************/
+#define SCTLR2_EL3 S3_6_C1_C0_3
#define SCTLR2_EL2 S3_4_C1_C0_3
#define SCTLR2_EL1 S3_0_C1_C0_3
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index e3068d1..757ce06 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -146,6 +146,8 @@
* +----------------------------+
* | FEAT_MOPS |
* +----------------------------+
+ * | FEAT_PAUTH_LR |
+ * +----------------------------+
*/
__attribute__((always_inline))
@@ -196,6 +198,35 @@
CREATE_FEATURE_SUPPORTED(feat_pauth, is_feat_pauth_present, ENABLE_PAUTH)
CREATE_FEATURE_SUPPORTED(ctx_pauth, is_feat_pauth_present, CTX_INCLUDE_PAUTH_REGS)
+/*
+ * FEAT_PAUTH_LR
+ * This feature has a non-standard discovery method so define this function
+ * manually then call use the CREATE_FEATURE_SUPPORTED macro with it. This
+ * feature is enabled with ENABLE_PAUTH when present.
+ */
+__attribute__((always_inline))
+static inline bool is_feat_pauth_lr_present(void)
+{
+ /*
+ * FEAT_PAUTH_LR support is indicated by up to 3 fields, if one or more
+ * of these is 0b0110 then the feature is present.
+ * 1) id_aa64isr1_el1.api
+ * 2) id_aa64isr1_el1.apa
+ * 3) id_aa64isr2_el1.apa3
+ */
+ if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_API_SHIFT, ID_AA64ISAR1_API_MASK) == 0b0110) {
+ return true;
+ }
+ if (ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_APA_SHIFT, ID_AA64ISAR1_APA_MASK) == 0b0110) {
+ return true;
+ }
+ if (ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_APA3_SHIFT, ID_AA64ISAR2_APA3_MASK) == 0b0110) {
+ return true;
+ }
+ return false;
+}
+CREATE_FEATURE_SUPPORTED(feat_pauth_lr, is_feat_pauth_lr_present, ENABLE_FEAT_PAUTH_LR)
+
/* FEAT_TTST: Small translation tables */
CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
ID_AA64MMFR2_EL1_ST_MASK, 1U)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 9419583..c885424 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -240,12 +240,11 @@
******************************************************************************/
static inline u_register_t xpaci(u_register_t arg)
{
- register u_register_t x0 asm("x0") = arg;
+ __asm__ (".arch armv8.3-a\n"
+ "xpaci %0\n"
+ : "+r" (arg));
- /* `xpaci x0` for compatibility with older compiler and/or older -march */
- __asm__ (".arch armv8.3-a; xpaci %0\n" : "+r" (x0));
-
- return x0;
+ return arg;
}
void flush_dcache_range(uintptr_t addr, size_t size);
@@ -733,6 +732,7 @@
/* FEAT_SCTLR2 Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el3, SCTLR2_EL3)
/* FEAT_LS64_ACCDATA Registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(accdata_el1, ACCDATA_EL1)
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index da51bf8..8f1651d 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -230,7 +230,7 @@
*/
.macro read reg:req
#if ENABLE_BTI
- bti j
+ BTI j
#endif
mrs x0, \reg
ret
@@ -241,7 +241,7 @@
*/
.macro write reg:req
#if ENABLE_BTI
- bti j
+ BTI j
#endif
msr \reg, x1
ret
@@ -351,6 +351,11 @@
tst \reg, \clobber
.endm
+ .macro is_feat_sctlr2_present_asm reg:req
+ mrs \reg, ID_AA64MMFR3_EL1
+ ands \reg, \reg, #(ID_AA64MMFR3_EL1_SCTLR2_MASK << ID_AA64MMFR3_EL1_SCTLR2_SHIFT)
+ .endm
+
.macro call_reset_handler
#if !(defined(IMAGE_BL2) && ENABLE_RME)
/* ---------------------------------------------------------------------
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 07dffb1..fce0f2c 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -45,6 +45,16 @@
msr sctlr_el3, x0
isb
+#if ENABLE_FEAT_SCTLR2
+#if ENABLE_FEAT_SCTLR2 > 1
+ is_feat_sctlr2_present_asm x1
+ beq feat_sctlr2_not_supported\@
+#endif
+ mov x1, #SCTLR2_RESET_VAL
+ msr SCTLR2_EL3, x1
+feat_sctlr2_not_supported\@:
+#endif
+
#ifdef IMAGE_BL31
/* ---------------------------------------------------------------------
* Initialise the per-cpu cache pointer to the CPU.
diff --git a/include/bl32/tsp/platform_tsp.h b/include/bl32/tsp/platform_tsp.h
index fe8a2c9..81a1a40 100644
--- a/include/bl32/tsp/platform_tsp.h
+++ b/include/bl32/tsp/platform_tsp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +10,8 @@
/*******************************************************************************
* Mandatory TSP functions (only if platform contains a TSP)
******************************************************************************/
-void tsp_early_platform_setup(void);
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3);
void tsp_plat_arch_setup(void);
void tsp_platform_setup(void);
diff --git a/include/bl32/tsp/tsp.h b/include/bl32/tsp/tsp.h
index a63abf1..bc152e5 100644
--- a/include/bl32/tsp/tsp.h
+++ b/include/bl32/tsp/tsp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -106,7 +106,8 @@
tsp_vector_isn_t abort_yield_smc_entry;
} tsp_vectors_t;
-void tsp_setup(void);
+void tsp_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
+ u_register_t arg3);
#endif /* __ASSEMBLER__ */
diff --git a/include/common/asm_macros_common.S b/include/common/asm_macros_common.S
index fd0ea81..9172b55 100644
--- a/include/common/asm_macros_common.S
+++ b/include/common/asm_macros_common.S
@@ -7,6 +7,20 @@
#define ASM_MACROS_COMMON_S
/*
+ * Provide a wrapper for the "bti" instructions using the more
+ * compatible "hint" encoding, otherwise older toolchains would reject
+ * this when not compiled for a BTI capable machine (-march=armv8.5-a).
+ */
+ .macro BTI _targets
+ .ifc \_targets, j
+ hint #36
+ .endif
+ .ifc \_targets, jc
+ hint #38
+ .endif
+ .endm
+
+ /*
* This macro is used to create a function label and place the
* code into a separate text section based on the function name
* to enable elimination of unused code during linking. It also adds
@@ -42,7 +56,7 @@
/* When Branch Target Identification is enabled, insert "bti jc"
* instruction to enable indirect calls and branches
*/
- bti jc
+ BTI jc
#endif
.endm
diff --git a/include/drivers/auth/auth_util.h b/include/drivers/auth/auth_util.h
new file mode 100644
index 0000000..546669f
--- /dev/null
+++ b/include/drivers/auth/auth_util.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AUTH_UTIL_H
+#define AUTH_UTIL_H
+
+const char *get_current_pk_oid(void);
+void set_current_pk_oid(const char *pk_oid);
+
+#endif /* AUTH_UTIL_H */
diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h
index bec19da..fd49b2d 100644
--- a/include/drivers/auth/crypto_mod.h
+++ b/include/drivers/auth/crypto_mod.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -79,6 +79,12 @@
unsigned int key_flags, const void *iv,
unsigned int iv_len, const void *tag,
unsigned int tag_len);
+
+ /*
+ * Finish using the crypto library,
+ * anything to be done to wrap up crypto usage done here.
+ */
+ void (*finish)(void);
} crypto_lib_desc_t;
/* Public functions */
@@ -118,9 +124,17 @@
int crypto_mod_convert_pk(void *full_pk_ptr, unsigned int full_pk_len,
void **hashed_pk_ptr, unsigned int *hashed_pk_len);
+#if CRYPTO_SUPPORT
+void crypto_mod_finish(void);
+#else
+static inline void crypto_mod_finish(void)
+{
+}
+#endif /* CRYPTO_SUPPORT */
+
/* Macro to register a cryptographic library */
#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
- _calc_hash, _auth_decrypt, _convert_pk) \
+ _calc_hash, _auth_decrypt, _convert_pk, _finish) \
const crypto_lib_desc_t crypto_lib_desc = { \
.name = _name, \
.init = _init, \
@@ -128,7 +142,8 @@
.verify_hash = _verify_hash, \
.calc_hash = _calc_hash, \
.auth_decrypt = _auth_decrypt, \
- .convert_pk = _convert_pk \
+ .convert_pk = _convert_pk, \
+ .finish = _finish \
}
extern const crypto_lib_desc_t crypto_lib_desc;
diff --git a/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
index 00b1f34..c88f21c 100644
--- a/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Ltd. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,11 +27,15 @@
#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
/*
- * Override heap size for PSA Crypto when RSA key size > 2048.
+ * Override heap size for PSA Crypto for RSA keys.
*/
-#if TF_MBEDTLS_USE_RSA && TF_MBEDTLS_KEY_SIZE > 2048
-#undef TF_MBEDTLS_HEAP_SIZE
-#define TF_MBEDTLS_HEAP_SIZE U(12 * 1024)
+#if TF_MBEDTLS_USE_RSA
+ #undef TF_MBEDTLS_HEAP_SIZE
+ #if TF_MBEDTLS_KEY_SIZE > 2048
+ #define TF_MBEDTLS_HEAP_SIZE U(12 * 1024)
+ #elif TF_MBEDTLS_KEY_SIZE <= 2048
+ #define TF_MBEDTLS_HEAP_SIZE U(9 * 1024)
+ #endif
#endif
#endif /* PSA_MBEDTLS_CONFIG_H */
diff --git a/include/drivers/auth/mbedtls/mbedtls_psa_crypto.h b/include/drivers/auth/mbedtls/mbedtls_psa_crypto.h
new file mode 100644
index 0000000..85c854d
--- /dev/null
+++ b/include/drivers/auth/mbedtls/mbedtls_psa_crypto.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MBEDTLS_PSA_CRYPTO_H
+#define MBEDTLS_PSA_CRYPTO_H
+
+#define MAX_CACHED_KEYS 10
+
+typedef struct key_cache_s {
+ const char *pk_oid; /* Store OID of the public key */
+ psa_key_id_t key_id; /* PSA key ID */
+ psa_algorithm_t psa_alg; /* PSA Algorithm associated with the key */
+ psa_key_attributes_t psa_key_attr; /* PSA key attributes associated with the key */
+ bool valid; /* Whether this cache entry is valid */
+} key_cache_t;
+
+#endif /* MBEDTLS_PSA_CRYPTO_H */
diff --git a/include/drivers/marvell/trng.h b/include/drivers/marvell/trng.h
new file mode 100644
index 0000000..e4f39f4
--- /dev/null
+++ b/include/drivers/marvell/trng.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Marvell Technology Group Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TRNG_H__
+#define __TRNG_H__
+
+#include <stdint.h>
+
+int mv_trng_get_random32(uint32_t *rand, uint8_t num);
+
+#endif /* __TRNG_H__ */
diff --git a/include/drivers/measured_boot/event_log/event_handoff.h b/include/drivers/measured_boot/event_log/event_handoff.h
new file mode 100644
index 0000000..e969d1f
--- /dev/null
+++ b/include/drivers/measured_boot/event_log/event_handoff.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef HANDOFF_H
+#define HANDOFF_H
+
+#include <stdint.h>
+
+#include <lib/transfer_list.h>
+
+/**
+ * Initializes or extends the TPM event log in the transfer list.
+ *
+ * If an event log entry exists, attempts to resize it. Otherwise, adds a new entry.
+ * Copies old data if needed. Updates free to reflect available space.
+ *
+ * @param tl Pointer to the transfer list header.
+ * @param req_size Requested size (bytes)
+ * @param free Available size (bytes)
+ * @return Pointer to writable space in the log, or NULL on failure.
+ */
+uint8_t *transfer_list_event_log_extend(struct transfer_list_header *tl,
+ size_t req_size, size_t *free);
+
+/**
+ * Finalizes the event log after writing is complete.
+ *
+ * Resizes the event log to match actual data written, updates checksum,
+ * and flushes cache for the next stage.
+ *
+ * @param tl Pointer to the transfer list header.
+ * @param cursor End offset of written log data.
+ * @return Pointer to finalized log data (past reserved bytes), or NULL.
+ */
+uint8_t *transfer_list_event_log_finish(struct transfer_list_header *tl,
+ uintptr_t cursor);
+
+#define EVENT_LOG_RESERVED_BYTES U(4)
+
+#endif /* HANDOFF_H */
diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
index 50e4721..b5adfdc 100644
--- a/include/drivers/measured_boot/event_log/event_log.h
+++ b/include/drivers/measured_boot/event_log/event_log.h
@@ -11,6 +11,7 @@
#include <stdint.h>
#include <drivers/auth/crypto_mod.h>
+#include "event_handoff.h"
#include "tcg.h"
/*
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index e94693d..454a85a 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -19,29 +19,29 @@
#define MMC_ACMD(_x) U(_x)
-#define OCR_POWERUP BIT(31)
-#define OCR_HCS BIT(30)
-#define OCR_BYTE_MODE (U(0) << 29)
-#define OCR_SECTOR_MODE (U(2) << 29)
-#define OCR_ACCESS_MODE_MASK (U(3) << 29)
-#define OCR_3_5_3_6 BIT(23)
-#define OCR_3_4_3_5 BIT(22)
-#define OCR_3_3_3_4 BIT(21)
-#define OCR_3_2_3_3 BIT(20)
-#define OCR_3_1_3_2 BIT(19)
-#define OCR_3_0_3_1 BIT(18)
-#define OCR_2_9_3_0 BIT(17)
-#define OCR_2_8_2_9 BIT(16)
-#define OCR_2_7_2_8 BIT(15)
-#define OCR_VDD_MIN_2V7 GENMASK(23, 15)
-#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
-#define OCR_VDD_MIN_1V7 BIT(7)
+#define OCR_POWERUP BIT_32(31U)
+#define OCR_HCS BIT_32(30U)
+#define OCR_BYTE_MODE (U(0) << 29U)
+#define OCR_SECTOR_MODE (U(2) << 29U)
+#define OCR_ACCESS_MODE_MASK (U(3) << 29U)
+#define OCR_3_5_3_6 BIT_32(23U)
+#define OCR_3_4_3_5 BIT_32(22U)
+#define OCR_3_3_3_4 BIT_32(21U)
+#define OCR_3_2_3_3 BIT_32(20U)
+#define OCR_3_1_3_2 BIT_32(19U)
+#define OCR_3_0_3_1 BIT_32(18U)
+#define OCR_2_9_3_0 BIT_32(17U)
+#define OCR_2_8_2_9 BIT_32(16U)
+#define OCR_2_7_2_8 BIT_32(15U)
+#define OCR_VDD_MIN_2V7 GENMASK_32(23U, 15U)
+#define OCR_VDD_MIN_2V0 GENMASK_32(14U, 8U)
+#define OCR_VDD_MIN_1V7 BIT_32(7U)
-#define MMC_RSP_48 BIT(0)
-#define MMC_RSP_136 BIT(1) /* 136 bit response */
-#define MMC_RSP_CRC BIT(2) /* expect valid crc */
-#define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */
-#define MMC_RSP_BUSY BIT(4) /* device may be busy */
+#define MMC_RSP_48 BIT_32(0U)
+#define MMC_RSP_136 BIT_32(1U) /* 136 bit response */
+#define MMC_RSP_CRC BIT_32(2U) /* expect valid crc */
+#define MMC_RSP_CMD_IDX BIT_32(3U) /* response contains cmd idx */
+#define MMC_RSP_BUSY BIT_32(4U) /* device may be busy */
/* JEDEC 4.51 chapter 6.12 */
#define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
diff --git a/include/drivers/nxp/trdc/imx_trdc.h b/include/drivers/nxp/trdc/imx_trdc.h
index 0b41fcf..3ee60f9 100644
--- a/include/drivers/nxp/trdc/imx_trdc.h
+++ b/include/drivers/nxp/trdc/imx_trdc.h
@@ -5,7 +5,7 @@
*/
#ifndef IMX_TRDC_H
-#define IMX_XRDC_H
+#define IMX_TRDC_H
#define MBC_BLK_ALL U(255)
#define MRC_REG_ALL U(16)
diff --git a/include/drivers/rambus/trng_ip_76.h b/include/drivers/rambus/trng_ip_76.h
deleted file mode 100644
index 6de8fc7..0000000
--- a/include/drivers/rambus/trng_ip_76.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-#ifndef __TRNG_IP_76_H__
-#define __TRNG_IP_76_H__
-
-#include <stdbool.h>
-#include <stdint.h>
-
-int32_t eip76_rng_read_rand_buf(void *data, bool wait);
-int32_t eip76_rng_probe(uintptr_t base_addr);
-int32_t eip76_rng_get_random(uint8_t *data, uint32_t len);
-
-#endif /* __TRNG_IP_76_H__ */
diff --git a/include/drivers/st/bsec3_reg.h b/include/drivers/st/bsec3_reg.h
index 177e30b..4263f76 100644
--- a/include/drivers/st/bsec3_reg.h
+++ b/include/drivers/st/bsec3_reg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -84,7 +84,7 @@
/* BSEC_OTPSR register fields */
#define BSEC_OTPSR_BUSY BIT_32(0)
-#define BSEC_OTPSR_FUSEOK BIT_32(1)
+#define BSEC_OTPSR_INIT_DONE BIT_32(1)
#define BSEC_OTPSR_HIDEUP BIT_32(2)
#define BSEC_OTPSR_OTPNVIR BIT_32(4)
#define BSEC_OTPSR_OTPERR BIT_32(5)
diff --git a/include/drivers/st/stm32mp21_pwr.h b/include/drivers/st/stm32mp21_pwr.h
new file mode 100644
index 0000000..570f079
--- /dev/null
+++ b/include/drivers/st/stm32mp21_pwr.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_PWR_H
+#define STM32MP21_PWR_H
+
+#include <lib/utils_def.h>
+
+#define PWR_CR1 U(0x00)
+#define PWR_CR2 U(0x04)
+#define PWR_CR3 U(0x08)
+#define PWR_CR7 U(0x18)
+#define PWR_CR8 U(0x1C)
+#define PWR_CR9 U(0x20)
+#define PWR_CR10 U(0x24)
+#define PWR_CR11 U(0x28)
+#define PWR_BDCR U(0x38)
+#define PWR_CPU1CR U(0x40)
+#define PWR_CPU2CR U(0x44)
+#define PWR_D1CR U(0x4C)
+#define PWR_D2CR U(0x50)
+#define PWR_WKUPCR1 U(0x60)
+#define PWR_WKUPCR2 U(0x64)
+#define PWR_WKUPCR3 U(0x68)
+#define PWR_WKUPCR4 U(0x6C)
+#define PWR_WKUPCR5 U(0x70)
+#define PWR_WKUPCR6 U(0x74)
+#define PWR_RSECCFGR U(0x100)
+#define PWR_RPRIVCFGR U(0x104)
+#define PWR_R0CIDCFGR U(0x108)
+#define PWR_R1CIDCFGR U(0x10C)
+#define PWR_R2CIDCFGR U(0x110)
+#define PWR_R3CIDCFGR U(0x114)
+#define PWR_R4CIDCFGR U(0x118)
+#define PWR_R5CIDCFGR U(0x11C)
+#define PWR_R6CIDCFGR U(0x120)
+#define PWR_WIOSECCFGR U(0x180)
+#define PWR_WIOPRIVCFGR U(0x184)
+#define PWR_WIO1CIDCFGR U(0x188)
+#define PWR_WIO1SEMCR U(0x18C)
+#define PWR_WIO2CIDCFGR U(0x190)
+#define PWR_WIO2SEMCR U(0x194)
+#define PWR_WIO3CIDCFGR U(0x198)
+#define PWR_WIO3SEMCR U(0x19C)
+#define PWR_WIO4CIDCFGR U(0x1A0)
+#define PWR_WIO4SEMCR U(0x1A4)
+#define PWR_WIO5CIDCFGR U(0x1A8)
+#define PWR_WIO5SEMCR U(0x1AC)
+#define PWR_WIO6CIDCFGR U(0x1B0)
+#define PWR_WIO6SEMCR U(0x1B4)
+#define PWR_CPU1D1SR U(0x200)
+#define PWR_CPU2D2SR U(0x204)
+#define PWR_DBGR U(0x308)
+#define PWR_VERR U(0x3F4)
+#define PWR_IPIDR U(0x3F8)
+#define PWR_SIDR U(0x3FC)
+
+/* PWR_CR1 register fields */
+#define PWR_CR1_VDDIO3VMEN BIT(0)
+#define PWR_CR1_USB33VMEN BIT(2)
+#define PWR_CR1_AVMEN BIT(4)
+#define PWR_CR1_VDDIO3SV BIT(8)
+#define PWR_CR1_USB33SV BIT(10)
+#define PWR_CR1_ASV BIT(12)
+#define PWR_CR1_VDDIO3RDY BIT(16)
+#define PWR_CR1_USB33RDY BIT(18)
+#define PWR_CR1_ARDY BIT(20)
+#define PWR_CR1_VDDIOVRSEL BIT(24)
+#define PWR_CR1_VDDIO3VRSEL BIT(25)
+#define PWR_CR1_GPVMO BIT(31)
+
+/* PWR_CR2 register fields */
+#define PWR_CR2_MONEN BIT(0)
+#define PWR_CR2_VBATL BIT(8)
+#define PWR_CR2_VBATH BIT(9)
+#define PWR_CR2_TEMPL BIT(10)
+#define PWR_CR2_TEMPH BIT(11)
+
+/* PWR_CR3 register fields */
+#define PWR_CR3_PVDEN BIT(0)
+#define PWR_CR3_PVDO BIT(8)
+
+/* PWR_CR7 register fields */
+#define PWR_CR7_VDDIO2VMEN BIT(0)
+#define PWR_CR7_VDDIO2SV BIT(8)
+#define PWR_CR7_VDDIO2RDY BIT(16)
+#define PWR_CR7_VDDIO2VRSEL BIT(24)
+#define PWR_CR7_VDDIO2VRSTBY BIT(25)
+
+/* PWR_CR8 register fields */
+#define PWR_CR8_VDDIO1VMEN BIT(0)
+#define PWR_CR8_VDDIO1SV BIT(8)
+#define PWR_CR8_VDDIO1RDY BIT(16)
+#define PWR_CR8_VDDIO1VRSEL BIT(24)
+#define PWR_CR8_VDDIO1VRSTBY BIT(25)
+
+/* PWR_CR9 register fields */
+#define PWR_CR9_BKPRBSEN BIT(0)
+
+/* PWR_CR10 register fields */
+#define PWR_CR10_RETRBSEN_MASK GENMASK_32(1, 0)
+#define PWR_CR10_RETRBSEN_SHIFT 0
+#define PWR_CR10_RETRBSEN_DISABLE 0U
+#define PWR_CR10_RETRBSEN_STANDBY_VBAT 1U
+#define PWR_CR10_RETRBSEN_STANDBY 2U
+
+/* PWR_CR11 register fields */
+#define PWR_CR11_DDRRETDIS BIT(0)
+
+/* PWR_BDCR register fields */
+#define PWR_BDCR_DBP BIT(0)
+
+/* PWR_CPU1CR register fields */
+#define PWR_CPU1CR_PDDS_D2 BIT(0)
+#define PWR_CPU1CR_PDDS_D1 BIT(1)
+#define PWR_CPU1CR_VBF BIT(4)
+#define PWR_CPU1CR_STOPF BIT(5)
+#define PWR_CPU1CR_SBF BIT(6)
+#define PWR_CPU1CR_SBF_D1 BIT(7)
+#define PWR_CPU1CR_CSSF BIT(9)
+#define PWR_CPU1CR_STANDBYWFIL2 BIT(15)
+#define PWR_CPU1CR_LPDS_D1 BIT(16)
+#define PWR_CPU1CR_LVDS_D1 BIT(17)
+
+/* PWR_CPU2CR register fields */
+#define PWR_CPU2CR_PDDS_D2 BIT(0)
+#define PWR_CPU2CR_VBF BIT(4)
+#define PWR_CPU2CR_STOPF BIT(5)
+#define PWR_CPU2CR_SBF BIT(6)
+#define PWR_CPU2CR_SBF_D2 BIT(7)
+#define PWR_CPU2CR_CSSF BIT(9)
+#define PWR_CPU2CR_DEEPSLEEP BIT(15)
+#define PWR_CPU2CR_LPDS_D2 BIT(16)
+#define PWR_CPU2CR_LVDS_D2 BIT(17)
+
+/* PWR_D1CR register fields */
+#define PWR_D1CR_LPCFG_D1 BIT(0)
+#define PWR_D1CR_POPL_D1_MASK GENMASK_32(12, 8)
+#define PWR_D1CR_POPL_D1_SHIFT 8
+
+/* PWR_D2CR register fields */
+#define PWR_D2CR_LPCFG_D2 BIT(0)
+#define PWR_D2CR_POPL_D2_MASK GENMASK_32(12, 8)
+#define PWR_D2CR_POPL_D2_SHIFT 8
+#define PWR_D2CR_LPLVDLY_D2_MASK GENMASK_32(18, 16)
+#define PWR_D2CR_LPLVDLY_D2_SHIFT 16
+#define PWR_D2CR_PODH_D2_MASK GENMASK_32(27, 24)
+#define PWR_D2CR_PODH_D2_SHIFT 24
+
+/* PWR_WKUPCR1 register fields */
+#define PWR_WKUPCR1_WKUPC BIT(0)
+#define PWR_WKUPCR1_WKUPP BIT(8)
+#define PWR_WKUPCR1_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR1_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR1_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR1_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR1_WKUPF BIT(31)
+
+/* PWR_WKUPCR2 register fields */
+#define PWR_WKUPCR2_WKUPC BIT(0)
+#define PWR_WKUPCR2_WKUPP BIT(8)
+#define PWR_WKUPCR2_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR2_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR2_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR2_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR2_WKUPF BIT(31)
+
+/* PWR_WKUPCR3 register fields */
+#define PWR_WKUPCR3_WKUPC BIT(0)
+#define PWR_WKUPCR3_WKUPP BIT(8)
+#define PWR_WKUPCR3_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR3_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR3_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR3_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR3_WKUPF BIT(31)
+
+/* PWR_WKUPCR4 register fields */
+#define PWR_WKUPCR4_WKUPC BIT(0)
+#define PWR_WKUPCR4_WKUPP BIT(8)
+#define PWR_WKUPCR4_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR4_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR4_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR4_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR4_WKUPF BIT(31)
+
+/* PWR_WKUPCR5 register fields */
+#define PWR_WKUPCR5_WKUPC BIT(0)
+#define PWR_WKUPCR5_WKUPP BIT(8)
+#define PWR_WKUPCR5_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR5_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR5_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR5_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR5_WKUPF BIT(31)
+
+/* PWR_WKUPCR6 register fields */
+#define PWR_WKUPCR6_WKUPC BIT(0)
+#define PWR_WKUPCR6_WKUPP BIT(8)
+#define PWR_WKUPCR6_WKUPPUPD_MASK GENMASK_32(13, 12)
+#define PWR_WKUPCR6_WKUPPUPD_SHIFT 12
+#define PWR_WKUPCR6_WKUPENCPU1 BIT(16)
+#define PWR_WKUPCR6_WKUPENCPU2 BIT(17)
+#define PWR_WKUPCR6_WKUPF BIT(31)
+
+/* PWR_RSECCFGR register fields */
+#define PWR_RSECCFGR_RSEC0 BIT(0)
+#define PWR_RSECCFGR_RSEC1 BIT(1)
+#define PWR_RSECCFGR_RSEC2 BIT(2)
+#define PWR_RSECCFGR_RSEC3 BIT(3)
+#define PWR_RSECCFGR_RSEC4 BIT(4)
+#define PWR_RSECCFGR_RSEC5 BIT(5)
+#define PWR_RSECCFGR_RSEC6 BIT(6)
+
+/* PWR_RPRIVCFGR register fields */
+#define PWR_RPRIVCFGR_RPRIV0 BIT(0)
+#define PWR_RPRIVCFGR_RPRIV1 BIT(1)
+#define PWR_RPRIVCFGR_RPRIV2 BIT(2)
+#define PWR_RPRIVCFGR_RPRIV3 BIT(3)
+#define PWR_RPRIVCFGR_RPRIV4 BIT(4)
+#define PWR_RPRIVCFGR_RPRIV5 BIT(5)
+#define PWR_RPRIVCFGR_RPRIV6 BIT(6)
+
+/* PWR_R0CIDCFGR register fields */
+#define PWR_R0CIDCFGR_CFEN BIT(0)
+#define PWR_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R0CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R1CIDCFGR register fields */
+#define PWR_R1CIDCFGR_CFEN BIT(0)
+#define PWR_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R1CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R2CIDCFGR register fields */
+#define PWR_R2CIDCFGR_CFEN BIT(0)
+#define PWR_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R2CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R3CIDCFGR register fields */
+#define PWR_R3CIDCFGR_CFEN BIT(0)
+#define PWR_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R3CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R4CIDCFGR register fields */
+#define PWR_R4CIDCFGR_CFEN BIT(0)
+#define PWR_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R4CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R5CIDCFGR register fields */
+#define PWR_R5CIDCFGR_CFEN BIT(0)
+#define PWR_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R5CIDCFGR_SCID_SHIFT 4
+
+/* PWR_R6CIDCFGR register fields */
+#define PWR_R6CIDCFGR_CFEN BIT(0)
+#define PWR_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_R6CIDCFGR_SCID_SHIFT 4
+
+/* PWR_WIOSECCFGR register fields */
+#define PWR_WIOSECCFGR_WIOSEC1 BIT(0)
+#define PWR_WIOSECCFGR_WIOSEC2 BIT(1)
+#define PWR_WIOSECCFGR_WIOSEC3 BIT(2)
+#define PWR_WIOSECCFGR_WIOSEC4 BIT(3)
+#define PWR_WIOSECCFGR_WIOSEC5 BIT(4)
+#define PWR_WIOSECCFGR_WIOSEC6 BIT(5)
+
+/* PWR_WIOPRIVCFGR register fields */
+#define PWR_WIOPRIVCFGR_WIOPRIV1 BIT(0)
+#define PWR_WIOPRIVCFGR_WIOPRIV2 BIT(1)
+#define PWR_WIOPRIVCFGR_WIOPRIV3 BIT(2)
+#define PWR_WIOPRIVCFGR_WIOPRIV4 BIT(3)
+#define PWR_WIOPRIVCFGR_WIOPRIV5 BIT(4)
+#define PWR_WIOPRIVCFGR_WIOPRIV6 BIT(5)
+
+/* PWR_WIO1CIDCFGR register fields */
+#define PWR_WIO1CIDCFGR_CFEN BIT(0)
+#define PWR_WIO1CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO1CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO1CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO1CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO1CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO1CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO1CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO1CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO1CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO1CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO1SEMCR register fields */
+#define PWR_WIO1SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO1SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO2CIDCFGR register fields */
+#define PWR_WIO2CIDCFGR_CFEN BIT(0)
+#define PWR_WIO2CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO2CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO2CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO2CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO2CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO2CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO2CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO2CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO2CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO2CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO2SEMCR register fields */
+#define PWR_WIO2SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO2SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO3CIDCFGR register fields */
+#define PWR_WIO3CIDCFGR_CFEN BIT(0)
+#define PWR_WIO3CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO3CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO3CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO3CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO3CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO3CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO3CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO3CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO3CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO3CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO3SEMCR register fields */
+#define PWR_WIO3SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO3SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO4CIDCFGR register fields */
+#define PWR_WIO4CIDCFGR_CFEN BIT(0)
+#define PWR_WIO4CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO4CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO4CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO4CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO4CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO4CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO4CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO4CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO4CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO4CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO4SEMCR register fields */
+#define PWR_WIO4SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO4SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO5CIDCFGR register fields */
+#define PWR_WIO5CIDCFGR_CFEN BIT(0)
+#define PWR_WIO5CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO5CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO5CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO5CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO5CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO5CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO5CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO5CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO5CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO5CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO5SEMCR register fields */
+#define PWR_WIO5SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO5SEMCR_SEMCID_SHIFT 4
+
+/* PWR_WIO6CIDCFGR register fields */
+#define PWR_WIO6CIDCFGR_CFEN BIT(0)
+#define PWR_WIO6CIDCFGR_SEM_EN BIT(1)
+#define PWR_WIO6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO6CIDCFGR_SCID_SHIFT 4
+#define PWR_WIO6CIDCFGR_SEMWLC0 BIT(16)
+#define PWR_WIO6CIDCFGR_SEMWLC1 BIT(17)
+#define PWR_WIO6CIDCFGR_SEMWLC2 BIT(18)
+#define PWR_WIO6CIDCFGR_SEMWLC3 BIT(19)
+#define PWR_WIO6CIDCFGR_SEMWLC4 BIT(20)
+#define PWR_WIO6CIDCFGR_SEMWLC5 BIT(21)
+#define PWR_WIO6CIDCFGR_SEMWLC6 BIT(22)
+#define PWR_WIO6CIDCFGR_SEMWLC7 BIT(23)
+
+/* PWR_WIO6SEMCR register fields */
+#define PWR_WIO6SEMCR_SEM_MUTEX BIT(0)
+#define PWR_WIO6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define PWR_WIO6SEMCR_SEMCID_SHIFT 4
+
+/* PWR_CPU1D1SR register fields */
+#define PWR_CPU1D1SR_HOLD_BOOT BIT(0)
+#define PWR_CPU1D1SR_CSTATE_MASK GENMASK_32(3, 2)
+#define PWR_CPU1D1SR_CSTATE_SHIFT 2
+#define PWR_CPU1D1SR_DSTATE_MASK GENMASK_32(10, 8)
+#define PWR_CPU1D1SR_DSTATE_SHIFT 8
+
+/* PWR_CPU2D2SR register fields */
+#define PWR_CPU2D2SR_HOLD_BOOT BIT(0)
+#define PWR_CPU2D2SR_WFBEN BIT(1)
+#define PWR_CPU2D2SR_CSTATE_MASK GENMASK_32(3, 2)
+#define PWR_CPU2D2SR_CSTATE_SHIFT 2
+#define PWR_CPU2D2SR_DSTATE_MASK GENMASK_32(10, 8)
+#define PWR_CPU2D2SR_DSTATE_SHIFT 8
+
+/* PWR_DBGR register fields */
+#define PWR_DBGR_VDDIOKRETRAM BIT(16)
+#define PWR_DBGR_VDDIOKBKPRAM BIT(17)
+
+/* PWR_VERR register fields */
+#define PWR_VERR_MINREV_MASK GENMASK_32(3, 0)
+#define PWR_VERR_MINREV_SHIFT 0
+#define PWR_VERR_MAJREV_MASK GENMASK_32(7, 4)
+#define PWR_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP21_PWR_H */
+
diff --git a/include/drivers/st/stm32mp21_rcc.h b/include/drivers/st/stm32mp21_rcc.h
new file mode 100644
index 0000000..a3787d0
--- /dev/null
+++ b/include/drivers/st/stm32mp21_rcc.h
@@ -0,0 +1,4668 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_RCC_H
+#define STM32MP21_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_SECCFGR0 U(0x0)
+#define RCC_SECCFGR1 U(0x4)
+#define RCC_SECCFGR2 U(0x8)
+#define RCC_SECCFGR3 U(0xC)
+#define RCC_PRIVCFGR0 U(0x10)
+#define RCC_PRIVCFGR1 U(0x14)
+#define RCC_PRIVCFGR2 U(0x18)
+#define RCC_PRIVCFGR3 U(0x1C)
+#define RCC_RCFGLOCKR0 U(0x20)
+#define RCC_RCFGLOCKR1 U(0x24)
+#define RCC_RCFGLOCKR2 U(0x28)
+#define RCC_RCFGLOCKR3 U(0x2C)
+#define RCC_R0CIDCFGR U(0x30)
+#define RCC_R0SEMCR U(0x34)
+#define RCC_R1CIDCFGR U(0x38)
+#define RCC_R1SEMCR U(0x3C)
+#define RCC_R2CIDCFGR U(0x40)
+#define RCC_R2SEMCR U(0x44)
+#define RCC_R3CIDCFGR U(0x48)
+#define RCC_R3SEMCR U(0x4C)
+#define RCC_R4CIDCFGR U(0x50)
+#define RCC_R4SEMCR U(0x54)
+#define RCC_R5CIDCFGR U(0x58)
+#define RCC_R5SEMCR U(0x5C)
+#define RCC_R6CIDCFGR U(0x60)
+#define RCC_R6SEMCR U(0x64)
+#define RCC_R7CIDCFGR U(0x68)
+#define RCC_R7SEMCR U(0x6C)
+#define RCC_R8CIDCFGR U(0x70)
+#define RCC_R8SEMCR U(0x74)
+#define RCC_R9CIDCFGR U(0x78)
+#define RCC_R9SEMCR U(0x7C)
+#define RCC_R10CIDCFGR U(0x80)
+#define RCC_R10SEMCR U(0x84)
+#define RCC_R11CIDCFGR U(0x88)
+#define RCC_R11SEMCR U(0x8C)
+#define RCC_R12CIDCFGR U(0x90)
+#define RCC_R12SEMCR U(0x94)
+#define RCC_R13CIDCFGR U(0x98)
+#define RCC_R13SEMCR U(0x9C)
+#define RCC_R14CIDCFGR U(0xA0)
+#define RCC_R14SEMCR U(0xA4)
+#define RCC_R15CIDCFGR U(0xA8)
+#define RCC_R15SEMCR U(0xAC)
+#define RCC_R16CIDCFGR U(0xB0)
+#define RCC_R16SEMCR U(0xB4)
+#define RCC_R17CIDCFGR U(0xB8)
+#define RCC_R17SEMCR U(0xBC)
+#define RCC_R18CIDCFGR U(0xC0)
+#define RCC_R18SEMCR U(0xC4)
+#define RCC_R19CIDCFGR U(0xC8)
+#define RCC_R19SEMCR U(0xCC)
+#define RCC_R20CIDCFGR U(0xD0)
+#define RCC_R20SEMCR U(0xD4)
+#define RCC_R21CIDCFGR U(0xD8)
+#define RCC_R21SEMCR U(0xDC)
+#define RCC_R22CIDCFGR U(0xE0)
+#define RCC_R22SEMCR U(0xE4)
+#define RCC_R23CIDCFGR U(0xE8)
+#define RCC_R23SEMCR U(0xEC)
+#define RCC_R24CIDCFGR U(0xF0)
+#define RCC_R24SEMCR U(0xF4)
+#define RCC_R25CIDCFGR U(0xF8)
+#define RCC_R25SEMCR U(0xFC)
+#define RCC_R26CIDCFGR U(0x100)
+#define RCC_R26SEMCR U(0x104)
+#define RCC_R27CIDCFGR U(0x108)
+#define RCC_R27SEMCR U(0x10C)
+#define RCC_R28CIDCFGR U(0x110)
+#define RCC_R28SEMCR U(0x114)
+#define RCC_R29CIDCFGR U(0x118)
+#define RCC_R29SEMCR U(0x11C)
+#define RCC_R30CIDCFGR U(0x120)
+#define RCC_R30SEMCR U(0x124)
+#define RCC_R31CIDCFGR U(0x128)
+#define RCC_R31SEMCR U(0x12C)
+#define RCC_R32CIDCFGR U(0x130)
+#define RCC_R32SEMCR U(0x134)
+#define RCC_R33CIDCFGR U(0x138)
+#define RCC_R33SEMCR U(0x13C)
+#define RCC_R34CIDCFGR U(0x140)
+#define RCC_R34SEMCR U(0x144)
+#define RCC_R35CIDCFGR U(0x148)
+#define RCC_R35SEMCR U(0x14C)
+#define RCC_R36CIDCFGR U(0x150)
+#define RCC_R36SEMCR U(0x154)
+#define RCC_R37CIDCFGR U(0x158)
+#define RCC_R37SEMCR U(0x15C)
+#define RCC_R38CIDCFGR U(0x160)
+#define RCC_R38SEMCR U(0x164)
+#define RCC_R39CIDCFGR U(0x168)
+#define RCC_R39SEMCR U(0x16C)
+#define RCC_R40CIDCFGR U(0x170)
+#define RCC_R40SEMCR U(0x174)
+#define RCC_R41CIDCFGR U(0x178)
+#define RCC_R41SEMCR U(0x17C)
+#define RCC_R42CIDCFGR U(0x180)
+#define RCC_R42SEMCR U(0x184)
+#define RCC_R43CIDCFGR U(0x188)
+#define RCC_R43SEMCR U(0x18C)
+#define RCC_R44CIDCFGR U(0x190)
+#define RCC_R44SEMCR U(0x194)
+#define RCC_R45CIDCFGR U(0x198)
+#define RCC_R45SEMCR U(0x19C)
+#define RCC_R46CIDCFGR U(0x1A0)
+#define RCC_R46SEMCR U(0x1A4)
+#define RCC_R47CIDCFGR U(0x1A8)
+#define RCC_R47SEMCR U(0x1AC)
+#define RCC_R48CIDCFGR U(0x1B0)
+#define RCC_R48SEMCR U(0x1B4)
+#define RCC_R49CIDCFGR U(0x1B8)
+#define RCC_R49SEMCR U(0x1BC)
+#define RCC_R50CIDCFGR U(0x1C0)
+#define RCC_R50SEMCR U(0x1C4)
+#define RCC_R51CIDCFGR U(0x1C8)
+#define RCC_R51SEMCR U(0x1CC)
+#define RCC_R52CIDCFGR U(0x1D0)
+#define RCC_R52SEMCR U(0x1D4)
+#define RCC_R53CIDCFGR U(0x1D8)
+#define RCC_R53SEMCR U(0x1DC)
+#define RCC_R54CIDCFGR U(0x1E0)
+#define RCC_R54SEMCR U(0x1E4)
+#define RCC_R55CIDCFGR U(0x1E8)
+#define RCC_R55SEMCR U(0x1EC)
+#define RCC_R56CIDCFGR U(0x1F0)
+#define RCC_R56SEMCR U(0x1F4)
+#define RCC_R57CIDCFGR U(0x1F8)
+#define RCC_R57SEMCR U(0x1FC)
+#define RCC_R58CIDCFGR U(0x200)
+#define RCC_R58SEMCR U(0x204)
+#define RCC_R59CIDCFGR U(0x208)
+#define RCC_R59SEMCR U(0x20C)
+#define RCC_R60CIDCFGR U(0x210)
+#define RCC_R60SEMCR U(0x214)
+#define RCC_R61CIDCFGR U(0x218)
+#define RCC_R61SEMCR U(0x21C)
+#define RCC_R62CIDCFGR U(0x220)
+#define RCC_R62SEMCR U(0x224)
+#define RCC_R63CIDCFGR U(0x228)
+#define RCC_R63SEMCR U(0x22C)
+#define RCC_R64CIDCFGR U(0x230)
+#define RCC_R64SEMCR U(0x234)
+#define RCC_R65CIDCFGR U(0x238)
+#define RCC_R65SEMCR U(0x23C)
+#define RCC_R66CIDCFGR U(0x240)
+#define RCC_R66SEMCR U(0x244)
+#define RCC_R67CIDCFGR U(0x248)
+#define RCC_R67SEMCR U(0x24C)
+#define RCC_R68CIDCFGR U(0x250)
+#define RCC_R68SEMCR U(0x254)
+#define RCC_R69CIDCFGR U(0x258)
+#define RCC_R69SEMCR U(0x25C)
+#define RCC_R70CIDCFGR U(0x260)
+#define RCC_R70SEMCR U(0x264)
+#define RCC_R71CIDCFGR U(0x268)
+#define RCC_R71SEMCR U(0x26C)
+#define RCC_R72CIDCFGR U(0x270)
+#define RCC_R72SEMCR U(0x274)
+#define RCC_R73CIDCFGR U(0x278)
+#define RCC_R73SEMCR U(0x27C)
+#define RCC_R74CIDCFGR U(0x280)
+#define RCC_R74SEMCR U(0x284)
+#define RCC_R75CIDCFGR U(0x288)
+#define RCC_R75SEMCR U(0x28C)
+#define RCC_R76CIDCFGR U(0x290)
+#define RCC_R76SEMCR U(0x294)
+#define RCC_R77CIDCFGR U(0x298)
+#define RCC_R77SEMCR U(0x29C)
+#define RCC_R78CIDCFGR U(0x2A0)
+#define RCC_R78SEMCR U(0x2A4)
+#define RCC_R79CIDCFGR U(0x2A8)
+#define RCC_R79SEMCR U(0x2AC)
+#define RCC_R80CIDCFGR U(0x2B0)
+#define RCC_R80SEMCR U(0x2B4)
+#define RCC_R81CIDCFGR U(0x2B8)
+#define RCC_R81SEMCR U(0x2BC)
+#define RCC_R82CIDCFGR U(0x2C0)
+#define RCC_R82SEMCR U(0x2C4)
+#define RCC_R83CIDCFGR U(0x2C8)
+#define RCC_R83SEMCR U(0x2CC)
+#define RCC_R84CIDCFGR U(0x2D0)
+#define RCC_R84SEMCR U(0x2D4)
+#define RCC_R85CIDCFGR U(0x2D8)
+#define RCC_R85SEMCR U(0x2DC)
+#define RCC_R86CIDCFGR U(0x2E0)
+#define RCC_R86SEMCR U(0x2E4)
+#define RCC_R87CIDCFGR U(0x2E8)
+#define RCC_R87SEMCR U(0x2EC)
+#define RCC_R88CIDCFGR U(0x2F0)
+#define RCC_R88SEMCR U(0x2F4)
+#define RCC_R89CIDCFGR U(0x2F8)
+#define RCC_R89SEMCR U(0x2FC)
+#define RCC_R90CIDCFGR U(0x300)
+#define RCC_R90SEMCR U(0x304)
+#define RCC_R91CIDCFGR U(0x308)
+#define RCC_R91SEMCR U(0x30C)
+#define RCC_R92CIDCFGR U(0x310)
+#define RCC_R92SEMCR U(0x314)
+#define RCC_R93CIDCFGR U(0x318)
+#define RCC_R93SEMCR U(0x31C)
+#define RCC_R94CIDCFGR U(0x320)
+#define RCC_R94SEMCR U(0x324)
+#define RCC_R95CIDCFGR U(0x328)
+#define RCC_R95SEMCR U(0x32C)
+#define RCC_R96CIDCFGR U(0x330)
+#define RCC_R96SEMCR U(0x334)
+#define RCC_R97CIDCFGR U(0x338)
+#define RCC_R97SEMCR U(0x33C)
+#define RCC_R98CIDCFGR U(0x340)
+#define RCC_R98SEMCR U(0x344)
+#define RCC_R99CIDCFGR U(0x348)
+#define RCC_R99SEMCR U(0x34C)
+#define RCC_R100CIDCFGR U(0x350)
+#define RCC_R100SEMCR U(0x354)
+#define RCC_R101CIDCFGR U(0x358)
+#define RCC_R101SEMCR U(0x35C)
+#define RCC_R102CIDCFGR U(0x360)
+#define RCC_R102SEMCR U(0x364)
+#define RCC_R103CIDCFGR U(0x368)
+#define RCC_R103SEMCR U(0x36C)
+#define RCC_R104CIDCFGR U(0x370)
+#define RCC_R104SEMCR U(0x374)
+#define RCC_R105CIDCFGR U(0x378)
+#define RCC_R105SEMCR U(0x37C)
+#define RCC_R106CIDCFGR U(0x380)
+#define RCC_R106SEMCR U(0x384)
+#define RCC_R107CIDCFGR U(0x388)
+#define RCC_R107SEMCR U(0x38C)
+#define RCC_R108CIDCFGR U(0x390)
+#define RCC_R108SEMCR U(0x394)
+#define RCC_R109CIDCFGR U(0x398)
+#define RCC_R109SEMCR U(0x39C)
+#define RCC_R110CIDCFGR U(0x3A0)
+#define RCC_R110SEMCR U(0x3A4)
+#define RCC_R111CIDCFGR U(0x3A8)
+#define RCC_R111SEMCR U(0x3AC)
+#define RCC_R112CIDCFGR U(0x3B0)
+#define RCC_R112SEMCR U(0x3B4)
+#define RCC_R113CIDCFGR U(0x3B8)
+#define RCC_R113SEMCR U(0x3BC)
+#define RCC_GRSTCSETR U(0x400)
+#define RCC_C1RSTCSETR U(0x404)
+#define RCC_C2RSTCSETR U(0x40C)
+#define RCC_HWRSTSCLRR U(0x410)
+#define RCC_C1HWRSTSCLRR U(0x414)
+#define RCC_C2HWRSTSCLRR U(0x418)
+#define RCC_C1BOOTRSTSSETR U(0x41C)
+#define RCC_C1BOOTRSTSCLRR U(0x420)
+#define RCC_C2BOOTRSTSSETR U(0x424)
+#define RCC_C2BOOTRSTSCLRR U(0x428)
+#define RCC_C1SREQSETR U(0x42C)
+#define RCC_C1SREQCLRR U(0x430)
+#define RCC_CPUBOOTCR U(0x434)
+#define RCC_STBYBOOTCR U(0x438)
+#define RCC_LEGBOOTCR U(0x43C)
+#define RCC_BDCR U(0x440)
+#define RCC_RDCR U(0x44C)
+#define RCC_C1MSRDCR U(0x450)
+#define RCC_PWRLPDLYCR U(0x454)
+#define RCC_C1CIESETR U(0x458)
+#define RCC_C1CIFCLRR U(0x45C)
+#define RCC_C2CIESETR U(0x460)
+#define RCC_C2CIFCLRR U(0x464)
+#define RCC_IWDGC1FZSETR U(0x468)
+#define RCC_IWDGC1FZCLRR U(0x46C)
+#define RCC_IWDGC1CFGSETR U(0x470)
+#define RCC_IWDGC1CFGCLRR U(0x474)
+#define RCC_IWDGC2FZSETR U(0x478)
+#define RCC_IWDGC2FZCLRR U(0x47C)
+#define RCC_IWDGC2CFGSETR U(0x480)
+#define RCC_IWDGC2CFGCLRR U(0x484)
+#define RCC_MCO1CFGR U(0x488)
+#define RCC_MCO2CFGR U(0x48C)
+#define RCC_OCENSETR U(0x490)
+#define RCC_OCENCLRR U(0x494)
+#define RCC_OCRDYR U(0x498)
+#define RCC_HSICFGR U(0x49C)
+#define RCC_MSICFGR U(0x4A0)
+#define RCC_LSICR U(0x4A4)
+#define RCC_RTCDIVR U(0x4A8)
+#define RCC_APB1DIVR U(0x4AC)
+#define RCC_APB2DIVR U(0x4B0)
+#define RCC_APB3DIVR U(0x4B4)
+#define RCC_APB4DIVR U(0x4B8)
+#define RCC_APB5DIVR U(0x4BC)
+#define RCC_APBDBGDIVR U(0x4C0)
+#define RCC_TIMG1PRER U(0x4C8)
+#define RCC_TIMG2PRER U(0x4CC)
+#define RCC_LSMCUDIVR U(0x4D0)
+#define RCC_DDRCPCFGR U(0x4D4)
+#define RCC_DDRCAPBCFGR U(0x4D8)
+#define RCC_DDRPHYCAPBCFGR U(0x4DC)
+#define RCC_DDRPHYCCFGR U(0x4E0)
+#define RCC_DDRCFGR U(0x4E4)
+#define RCC_DDRITFCFGR U(0x4E8)
+#define RCC_SYSRAMCFGR U(0x4F0)
+#define RCC_SRAM1CFGR U(0x4F8)
+#define RCC_RETRAMCFGR U(0x500)
+#define RCC_BKPSRAMCFGR U(0x504)
+#define RCC_OSPI1CFGR U(0x514)
+#define RCC_FMCCFGR U(0x51C)
+#define RCC_DBGCFGR U(0x520)
+#define RCC_STMCFGR U(0x524)
+#define RCC_ETRCFGR U(0x528)
+#define RCC_GPIOACFGR U(0x52C)
+#define RCC_GPIOBCFGR U(0x530)
+#define RCC_GPIOCCFGR U(0x534)
+#define RCC_GPIODCFGR U(0x538)
+#define RCC_GPIOECFGR U(0x53C)
+#define RCC_GPIOFCFGR U(0x540)
+#define RCC_GPIOGCFGR U(0x544)
+#define RCC_GPIOHCFGR U(0x548)
+#define RCC_GPIOICFGR U(0x54C)
+#define RCC_GPIOZCFGR U(0x558)
+#define RCC_HPDMA1CFGR U(0x55C)
+#define RCC_HPDMA2CFGR U(0x560)
+#define RCC_HPDMA3CFGR U(0x564)
+#define RCC_IPCC1CFGR U(0x570)
+#define RCC_RTCCFGR U(0x578)
+#define RCC_SYSCPU1CFGR U(0x580)
+#define RCC_BSECCFGR U(0x584)
+#define RCC_PLL2CFGR1 U(0x590)
+#define RCC_PLL2CFGR2 U(0x594)
+#define RCC_PLL2CFGR3 U(0x598)
+#define RCC_PLL2CFGR4 U(0x59C)
+#define RCC_PLL2CFGR5 U(0x5A0)
+#define RCC_PLL2CFGR6 U(0x5A8)
+#define RCC_PLL2CFGR7 U(0x5AC)
+#define RCC_HSIFMONCR U(0x5E0)
+#define RCC_HSIFVALR U(0x5E4)
+#define RCC_MSIFMONCR U(0x5E8)
+#define RCC_MSIFVALR U(0x5EC)
+#define RCC_TIM1CFGR U(0x700)
+#define RCC_TIM2CFGR U(0x704)
+#define RCC_TIM3CFGR U(0x708)
+#define RCC_TIM4CFGR U(0x70C)
+#define RCC_TIM5CFGR U(0x710)
+#define RCC_TIM6CFGR U(0x714)
+#define RCC_TIM7CFGR U(0x718)
+#define RCC_TIM8CFGR U(0x71C)
+#define RCC_TIM10CFGR U(0x720)
+#define RCC_TIM11CFGR U(0x724)
+#define RCC_TIM12CFGR U(0x728)
+#define RCC_TIM13CFGR U(0x72C)
+#define RCC_TIM14CFGR U(0x730)
+#define RCC_TIM15CFGR U(0x734)
+#define RCC_TIM16CFGR U(0x738)
+#define RCC_TIM17CFGR U(0x73C)
+#define RCC_LPTIM1CFGR U(0x744)
+#define RCC_LPTIM2CFGR U(0x748)
+#define RCC_LPTIM3CFGR U(0x74C)
+#define RCC_LPTIM4CFGR U(0x750)
+#define RCC_LPTIM5CFGR U(0x754)
+#define RCC_SPI1CFGR U(0x758)
+#define RCC_SPI2CFGR U(0x75C)
+#define RCC_SPI3CFGR U(0x760)
+#define RCC_SPI4CFGR U(0x764)
+#define RCC_SPI5CFGR U(0x768)
+#define RCC_SPI6CFGR U(0x76C)
+#define RCC_SPDIFRXCFGR U(0x778)
+#define RCC_USART1CFGR U(0x77C)
+#define RCC_USART2CFGR U(0x780)
+#define RCC_USART3CFGR U(0x784)
+#define RCC_UART4CFGR U(0x788)
+#define RCC_UART5CFGR U(0x78C)
+#define RCC_USART6CFGR U(0x790)
+#define RCC_UART7CFGR U(0x794)
+#define RCC_LPUART1CFGR U(0x7A0)
+#define RCC_I2C1CFGR U(0x7A4)
+#define RCC_I2C2CFGR U(0x7A8)
+#define RCC_I2C3CFGR U(0x7AC)
+#define RCC_SAI1CFGR U(0x7C4)
+#define RCC_SAI2CFGR U(0x7C8)
+#define RCC_SAI3CFGR U(0x7CC)
+#define RCC_SAI4CFGR U(0x7D0)
+#define RCC_MDF1CFGR U(0x7D8)
+#define RCC_FDCANCFGR U(0x7E0)
+#define RCC_HDPCFGR U(0x7E4)
+#define RCC_ADC1CFGR U(0x7E8)
+#define RCC_ADC2CFGR U(0x7EC)
+#define RCC_ETH1CFGR U(0x7F0)
+#define RCC_ETH2CFGR U(0x7F4)
+#define RCC_USBHCFGR U(0x7FC)
+#define RCC_USB2PHY1CFGR U(0x800)
+#define RCC_OTGCFGR U(0x808)
+#define RCC_USB2PHY2CFGR U(0x80C)
+#define RCC_STGENCFGR U(0x824)
+#define RCC_SDMMC1CFGR U(0x830)
+#define RCC_SDMMC2CFGR U(0x834)
+#define RCC_SDMMC3CFGR U(0x838)
+#define RCC_LTDCCFGR U(0x840)
+#define RCC_CSICFGR U(0x858)
+#define RCC_DCMIPPCFGR U(0x85C)
+#define RCC_DCMIPSSICFGR U(0x860)
+#define RCC_RNG1CFGR U(0x870)
+#define RCC_RNG2CFGR U(0x874)
+#define RCC_PKACFGR U(0x878)
+#define RCC_SAESCFGR U(0x87C)
+#define RCC_HASH1CFGR U(0x880)
+#define RCC_HASH2CFGR U(0x884)
+#define RCC_CRYP1CFGR U(0x888)
+#define RCC_CRYP2CFGR U(0x88C)
+#define RCC_IWDG1CFGR U(0x894)
+#define RCC_IWDG2CFGR U(0x898)
+#define RCC_IWDG3CFGR U(0x89C)
+#define RCC_IWDG4CFGR U(0x8A0)
+#define RCC_WWDG1CFGR U(0x8A4)
+#define RCC_VREFCFGR U(0x8AC)
+#define RCC_DTSCFGR U(0x8B0)
+#define RCC_CRCCFGR U(0x8B4)
+#define RCC_SERCCFGR U(0x8B8)
+#define RCC_DDRPERFMCFGR U(0x8C0)
+#define RCC_I3C1CFGR U(0x8C8)
+#define RCC_I3C2CFGR U(0x8CC)
+#define RCC_I3C3CFGR U(0x8D0)
+#define RCC_MUXSELCFGR U(0x1000)
+#define RCC_XBAR0CFGR U(0x1018)
+#define RCC_XBAR1CFGR U(0x101C)
+#define RCC_XBAR2CFGR U(0x1020)
+#define RCC_XBAR3CFGR U(0x1024)
+#define RCC_XBAR4CFGR U(0x1028)
+#define RCC_XBAR5CFGR U(0x102C)
+#define RCC_XBAR6CFGR U(0x1030)
+#define RCC_XBAR7CFGR U(0x1034)
+#define RCC_XBAR8CFGR U(0x1038)
+#define RCC_XBAR9CFGR U(0x103C)
+#define RCC_XBAR10CFGR U(0x1040)
+#define RCC_XBAR11CFGR U(0x1044)
+#define RCC_XBAR12CFGR U(0x1048)
+#define RCC_XBAR13CFGR U(0x104C)
+#define RCC_XBAR14CFGR U(0x1050)
+#define RCC_XBAR15CFGR U(0x1054)
+#define RCC_XBAR16CFGR U(0x1058)
+#define RCC_XBAR17CFGR U(0x105C)
+#define RCC_XBAR18CFGR U(0x1060)
+#define RCC_XBAR19CFGR U(0x1064)
+#define RCC_XBAR20CFGR U(0x1068)
+#define RCC_XBAR21CFGR U(0x106C)
+#define RCC_XBAR22CFGR U(0x1070)
+#define RCC_XBAR23CFGR U(0x1074)
+#define RCC_XBAR24CFGR U(0x1078)
+#define RCC_XBAR25CFGR U(0x107C)
+#define RCC_XBAR26CFGR U(0x1080)
+#define RCC_XBAR27CFGR U(0x1084)
+#define RCC_XBAR28CFGR U(0x1088)
+#define RCC_XBAR29CFGR U(0x108C)
+#define RCC_XBAR30CFGR U(0x1090)
+#define RCC_XBAR31CFGR U(0x1094)
+#define RCC_XBAR32CFGR U(0x1098)
+#define RCC_XBAR33CFGR U(0x109C)
+#define RCC_XBAR34CFGR U(0x10A0)
+#define RCC_XBAR35CFGR U(0x10A4)
+#define RCC_XBAR36CFGR U(0x10A8)
+#define RCC_XBAR37CFGR U(0x10AC)
+#define RCC_XBAR38CFGR U(0x10B0)
+#define RCC_XBAR39CFGR U(0x10B4)
+#define RCC_XBAR40CFGR U(0x10B8)
+#define RCC_XBAR41CFGR U(0x10BC)
+#define RCC_XBAR42CFGR U(0x10C0)
+#define RCC_XBAR43CFGR U(0x10C4)
+#define RCC_XBAR44CFGR U(0x10C8)
+#define RCC_XBAR45CFGR U(0x10CC)
+#define RCC_XBAR46CFGR U(0x10D0)
+#define RCC_XBAR47CFGR U(0x10D4)
+#define RCC_XBAR48CFGR U(0x10D8)
+#define RCC_XBAR49CFGR U(0x10DC)
+#define RCC_XBAR50CFGR U(0x10E0)
+#define RCC_XBAR51CFGR U(0x10E4)
+#define RCC_XBAR52CFGR U(0x10E8)
+#define RCC_XBAR53CFGR U(0x10EC)
+#define RCC_XBAR54CFGR U(0x10F0)
+#define RCC_XBAR55CFGR U(0x10F4)
+#define RCC_XBAR56CFGR U(0x10F8)
+#define RCC_XBAR57CFGR U(0x10FC)
+#define RCC_XBAR58CFGR U(0x1100)
+#define RCC_XBAR59CFGR U(0x1104)
+#define RCC_XBAR60CFGR U(0x1108)
+#define RCC_XBAR61CFGR U(0x110C)
+#define RCC_XBAR62CFGR U(0x1110)
+#define RCC_XBAR63CFGR U(0x1114)
+#define RCC_PREDIV0CFGR U(0x1118)
+#define RCC_PREDIV1CFGR U(0x111C)
+#define RCC_PREDIV2CFGR U(0x1120)
+#define RCC_PREDIV3CFGR U(0x1124)
+#define RCC_PREDIV4CFGR U(0x1128)
+#define RCC_PREDIV5CFGR U(0x112C)
+#define RCC_PREDIV6CFGR U(0x1130)
+#define RCC_PREDIV7CFGR U(0x1134)
+#define RCC_PREDIV8CFGR U(0x1138)
+#define RCC_PREDIV9CFGR U(0x113C)
+#define RCC_PREDIV10CFGR U(0x1140)
+#define RCC_PREDIV11CFGR U(0x1144)
+#define RCC_PREDIV12CFGR U(0x1148)
+#define RCC_PREDIV13CFGR U(0x114C)
+#define RCC_PREDIV14CFGR U(0x1150)
+#define RCC_PREDIV15CFGR U(0x1154)
+#define RCC_PREDIV16CFGR U(0x1158)
+#define RCC_PREDIV17CFGR U(0x115C)
+#define RCC_PREDIV18CFGR U(0x1160)
+#define RCC_PREDIV19CFGR U(0x1164)
+#define RCC_PREDIV20CFGR U(0x1168)
+#define RCC_PREDIV21CFGR U(0x116C)
+#define RCC_PREDIV22CFGR U(0x1170)
+#define RCC_PREDIV23CFGR U(0x1174)
+#define RCC_PREDIV24CFGR U(0x1178)
+#define RCC_PREDIV25CFGR U(0x117C)
+#define RCC_PREDIV26CFGR U(0x1180)
+#define RCC_PREDIV27CFGR U(0x1184)
+#define RCC_PREDIV28CFGR U(0x1188)
+#define RCC_PREDIV29CFGR U(0x118C)
+#define RCC_PREDIV30CFGR U(0x1190)
+#define RCC_PREDIV31CFGR U(0x1194)
+#define RCC_PREDIV32CFGR U(0x1198)
+#define RCC_PREDIV33CFGR U(0x119C)
+#define RCC_PREDIV34CFGR U(0x11A0)
+#define RCC_PREDIV35CFGR U(0x11A4)
+#define RCC_PREDIV36CFGR U(0x11A8)
+#define RCC_PREDIV37CFGR U(0x11AC)
+#define RCC_PREDIV38CFGR U(0x11B0)
+#define RCC_PREDIV39CFGR U(0x11B4)
+#define RCC_PREDIV40CFGR U(0x11B8)
+#define RCC_PREDIV41CFGR U(0x11BC)
+#define RCC_PREDIV42CFGR U(0x11C0)
+#define RCC_PREDIV43CFGR U(0x11C4)
+#define RCC_PREDIV44CFGR U(0x11C8)
+#define RCC_PREDIV45CFGR U(0x11CC)
+#define RCC_PREDIV46CFGR U(0x11D0)
+#define RCC_PREDIV47CFGR U(0x11D4)
+#define RCC_PREDIV48CFGR U(0x11D8)
+#define RCC_PREDIV49CFGR U(0x11DC)
+#define RCC_PREDIV50CFGR U(0x11E0)
+#define RCC_PREDIV51CFGR U(0x11E4)
+#define RCC_PREDIV52CFGR U(0x11E8)
+#define RCC_PREDIV53CFGR U(0x11EC)
+#define RCC_PREDIV54CFGR U(0x11F0)
+#define RCC_PREDIV55CFGR U(0x11F4)
+#define RCC_PREDIV56CFGR U(0x11F8)
+#define RCC_PREDIV57CFGR U(0x11FC)
+#define RCC_PREDIV58CFGR U(0x1200)
+#define RCC_PREDIV59CFGR U(0x1204)
+#define RCC_PREDIV60CFGR U(0x1208)
+#define RCC_PREDIV61CFGR U(0x120C)
+#define RCC_PREDIV62CFGR U(0x1210)
+#define RCC_PREDIV63CFGR U(0x1214)
+#define RCC_PREDIVSR1 U(0x1218)
+#define RCC_PREDIVSR2 U(0x121C)
+#define RCC_FINDIV0CFGR U(0x1224)
+#define RCC_FINDIV1CFGR U(0x1228)
+#define RCC_FINDIV2CFGR U(0x122C)
+#define RCC_FINDIV3CFGR U(0x1230)
+#define RCC_FINDIV4CFGR U(0x1234)
+#define RCC_FINDIV5CFGR U(0x1238)
+#define RCC_FINDIV6CFGR U(0x123C)
+#define RCC_FINDIV7CFGR U(0x1240)
+#define RCC_FINDIV8CFGR U(0x1244)
+#define RCC_FINDIV9CFGR U(0x1248)
+#define RCC_FINDIV10CFGR U(0x124C)
+#define RCC_FINDIV11CFGR U(0x1250)
+#define RCC_FINDIV12CFGR U(0x1254)
+#define RCC_FINDIV13CFGR U(0x1258)
+#define RCC_FINDIV14CFGR U(0x125C)
+#define RCC_FINDIV15CFGR U(0x1260)
+#define RCC_FINDIV16CFGR U(0x1264)
+#define RCC_FINDIV17CFGR U(0x1268)
+#define RCC_FINDIV18CFGR U(0x126C)
+#define RCC_FINDIV19CFGR U(0x1270)
+#define RCC_FINDIV20CFGR U(0x1274)
+#define RCC_FINDIV21CFGR U(0x1278)
+#define RCC_FINDIV22CFGR U(0x127C)
+#define RCC_FINDIV23CFGR U(0x1280)
+#define RCC_FINDIV24CFGR U(0x1284)
+#define RCC_FINDIV25CFGR U(0x1288)
+#define RCC_FINDIV26CFGR U(0x128C)
+#define RCC_FINDIV27CFGR U(0x1290)
+#define RCC_FINDIV28CFGR U(0x1294)
+#define RCC_FINDIV29CFGR U(0x1298)
+#define RCC_FINDIV30CFGR U(0x129C)
+#define RCC_FINDIV31CFGR U(0x12A0)
+#define RCC_FINDIV32CFGR U(0x12A4)
+#define RCC_FINDIV33CFGR U(0x12A8)
+#define RCC_FINDIV34CFGR U(0x12AC)
+#define RCC_FINDIV35CFGR U(0x12B0)
+#define RCC_FINDIV36CFGR U(0x12B4)
+#define RCC_FINDIV37CFGR U(0x12B8)
+#define RCC_FINDIV38CFGR U(0x12BC)
+#define RCC_FINDIV39CFGR U(0x12C0)
+#define RCC_FINDIV40CFGR U(0x12C4)
+#define RCC_FINDIV41CFGR U(0x12C8)
+#define RCC_FINDIV42CFGR U(0x12CC)
+#define RCC_FINDIV43CFGR U(0x12D0)
+#define RCC_FINDIV44CFGR U(0x12D4)
+#define RCC_FINDIV45CFGR U(0x12D8)
+#define RCC_FINDIV46CFGR U(0x12DC)
+#define RCC_FINDIV47CFGR U(0x12E0)
+#define RCC_FINDIV48CFGR U(0x12E4)
+#define RCC_FINDIV49CFGR U(0x12E8)
+#define RCC_FINDIV50CFGR U(0x12EC)
+#define RCC_FINDIV51CFGR U(0x12F0)
+#define RCC_FINDIV52CFGR U(0x12F4)
+#define RCC_FINDIV53CFGR U(0x12F8)
+#define RCC_FINDIV54CFGR U(0x12FC)
+#define RCC_FINDIV55CFGR U(0x1300)
+#define RCC_FINDIV56CFGR U(0x1304)
+#define RCC_FINDIV57CFGR U(0x1308)
+#define RCC_FINDIV58CFGR U(0x130C)
+#define RCC_FINDIV59CFGR U(0x1310)
+#define RCC_FINDIV60CFGR U(0x1314)
+#define RCC_FINDIV61CFGR U(0x1318)
+#define RCC_FINDIV62CFGR U(0x131C)
+#define RCC_FINDIV63CFGR U(0x1320)
+#define RCC_FINDIVSR1 U(0x1324)
+#define RCC_FINDIVSR2 U(0x1328)
+#define RCC_FCALCOBS0CFGR U(0x1340)
+#define RCC_FCALCOBS1CFGR U(0x1344)
+#define RCC_FCALCREFCFGR U(0x1348)
+#define RCC_FCALCCR1 U(0x134C)
+#define RCC_FCALCCR2 U(0x1354)
+#define RCC_FCALCSR U(0x1358)
+#define RCC_PLL4CFGR1 U(0x1360)
+#define RCC_PLL4CFGR2 U(0x1364)
+#define RCC_PLL4CFGR3 U(0x1368)
+#define RCC_PLL4CFGR4 U(0x136C)
+#define RCC_PLL4CFGR5 U(0x1370)
+#define RCC_PLL4CFGR6 U(0x1378)
+#define RCC_PLL4CFGR7 U(0x137C)
+#define RCC_PLL5CFGR1 U(0x1388)
+#define RCC_PLL5CFGR2 U(0x138C)
+#define RCC_PLL5CFGR3 U(0x1390)
+#define RCC_PLL5CFGR4 U(0x1394)
+#define RCC_PLL5CFGR5 U(0x1398)
+#define RCC_PLL5CFGR6 U(0x13A0)
+#define RCC_PLL5CFGR7 U(0x13A4)
+#define RCC_PLL6CFGR1 U(0x13B0)
+#define RCC_PLL6CFGR2 U(0x13B4)
+#define RCC_PLL6CFGR3 U(0x13B8)
+#define RCC_PLL6CFGR4 U(0x13BC)
+#define RCC_PLL6CFGR5 U(0x13C0)
+#define RCC_PLL6CFGR6 U(0x13C8)
+#define RCC_PLL6CFGR7 U(0x13CC)
+#define RCC_PLL7CFGR1 U(0x13D8)
+#define RCC_PLL7CFGR2 U(0x13DC)
+#define RCC_PLL7CFGR3 U(0x13E0)
+#define RCC_PLL7CFGR4 U(0x13E4)
+#define RCC_PLL7CFGR5 U(0x13E8)
+#define RCC_PLL7CFGR6 U(0x13F0)
+#define RCC_PLL7CFGR7 U(0x13F4)
+#define RCC_PLL8CFGR1 U(0x1400)
+#define RCC_PLL8CFGR2 U(0x1404)
+#define RCC_PLL8CFGR3 U(0x1408)
+#define RCC_PLL8CFGR4 U(0x140C)
+#define RCC_PLL8CFGR5 U(0x1410)
+#define RCC_PLL8CFGR6 U(0x1418)
+#define RCC_PLL8CFGR7 U(0x141C)
+#define RCC_VERR U(0xFFF4)
+#define RCC_IDR U(0xFFF8)
+#define RCC_SIDR U(0xFFFC)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET U(4)
+
+/* RCC_SECCFGR3 register fields */
+#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0)
+#define RCC_SECCFGR3_SEC_SHIFT 0
+
+/* RCC_PRIVCFGR3 register fields */
+#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0)
+#define RCC_PRIVCFGR3_PRIV_SHIFT 0
+
+/* RCC_RCFGLOCKR3 register fields */
+#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0)
+#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0
+
+/* RCC_R0CIDCFGR register fields */
+#define RCC_R0CIDCFGR_CFEN BIT(0)
+#define RCC_R0CIDCFGR_SEM_EN BIT(1)
+#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R0CIDCFGR_SCID_SHIFT 4
+#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R0SEMCR register fields */
+#define RCC_R0SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R0SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R1CIDCFGR register fields */
+#define RCC_R1CIDCFGR_CFEN BIT(0)
+#define RCC_R1CIDCFGR_SEM_EN BIT(1)
+#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R1CIDCFGR_SCID_SHIFT 4
+#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R1SEMCR register fields */
+#define RCC_R1SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R1SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R2CIDCFGR register fields */
+#define RCC_R2CIDCFGR_CFEN BIT(0)
+#define RCC_R2CIDCFGR_SEM_EN BIT(1)
+#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R2CIDCFGR_SCID_SHIFT 4
+#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R2SEMCR register fields */
+#define RCC_R2SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R2SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R3CIDCFGR register fields */
+#define RCC_R3CIDCFGR_CFEN BIT(0)
+#define RCC_R3CIDCFGR_SEM_EN BIT(1)
+#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R3CIDCFGR_SCID_SHIFT 4
+#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R3SEMCR register fields */
+#define RCC_R3SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R3SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R4CIDCFGR register fields */
+#define RCC_R4CIDCFGR_CFEN BIT(0)
+#define RCC_R4CIDCFGR_SEM_EN BIT(1)
+#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R4CIDCFGR_SCID_SHIFT 4
+#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R4SEMCR register fields */
+#define RCC_R4SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R4SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R5CIDCFGR register fields */
+#define RCC_R5CIDCFGR_CFEN BIT(0)
+#define RCC_R5CIDCFGR_SEM_EN BIT(1)
+#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R5CIDCFGR_SCID_SHIFT 4
+#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R5SEMCR register fields */
+#define RCC_R5SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R5SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R6CIDCFGR register fields */
+#define RCC_R6CIDCFGR_CFEN BIT(0)
+#define RCC_R6CIDCFGR_SEM_EN BIT(1)
+#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R6CIDCFGR_SCID_SHIFT 4
+#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R6SEMCR register fields */
+#define RCC_R6SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R6SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R7CIDCFGR register fields */
+#define RCC_R7CIDCFGR_CFEN BIT(0)
+#define RCC_R7CIDCFGR_SEM_EN BIT(1)
+#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R7CIDCFGR_SCID_SHIFT 4
+#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R7SEMCR register fields */
+#define RCC_R7SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R7SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R8CIDCFGR register fields */
+#define RCC_R8CIDCFGR_CFEN BIT(0)
+#define RCC_R8CIDCFGR_SEM_EN BIT(1)
+#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R8CIDCFGR_SCID_SHIFT 4
+#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R8SEMCR register fields */
+#define RCC_R8SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R8SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R9CIDCFGR register fields */
+#define RCC_R9CIDCFGR_CFEN BIT(0)
+#define RCC_R9CIDCFGR_SEM_EN BIT(1)
+#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R9CIDCFGR_SCID_SHIFT 4
+#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R9SEMCR register fields */
+#define RCC_R9SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R9SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R10CIDCFGR register fields */
+#define RCC_R10CIDCFGR_CFEN BIT(0)
+#define RCC_R10CIDCFGR_SEM_EN BIT(1)
+#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R10CIDCFGR_SCID_SHIFT 4
+#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R10SEMCR register fields */
+#define RCC_R10SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R10SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R11CIDCFGR register fields */
+#define RCC_R11CIDCFGR_CFEN BIT(0)
+#define RCC_R11CIDCFGR_SEM_EN BIT(1)
+#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R11CIDCFGR_SCID_SHIFT 4
+#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R11SEMCR register fields */
+#define RCC_R11SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R11SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R12CIDCFGR register fields */
+#define RCC_R12CIDCFGR_CFEN BIT(0)
+#define RCC_R12CIDCFGR_SEM_EN BIT(1)
+#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R12CIDCFGR_SCID_SHIFT 4
+#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R12SEMCR register fields */
+#define RCC_R12SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R12SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R13CIDCFGR register fields */
+#define RCC_R13CIDCFGR_CFEN BIT(0)
+#define RCC_R13CIDCFGR_SEM_EN BIT(1)
+#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R13CIDCFGR_SCID_SHIFT 4
+#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R13SEMCR register fields */
+#define RCC_R13SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R13SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R14CIDCFGR register fields */
+#define RCC_R14CIDCFGR_CFEN BIT(0)
+#define RCC_R14CIDCFGR_SEM_EN BIT(1)
+#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R14CIDCFGR_SCID_SHIFT 4
+#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R14SEMCR register fields */
+#define RCC_R14SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R14SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R15CIDCFGR register fields */
+#define RCC_R15CIDCFGR_CFEN BIT(0)
+#define RCC_R15CIDCFGR_SEM_EN BIT(1)
+#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R15CIDCFGR_SCID_SHIFT 4
+#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R15SEMCR register fields */
+#define RCC_R15SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R15SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R16CIDCFGR register fields */
+#define RCC_R16CIDCFGR_CFEN BIT(0)
+#define RCC_R16CIDCFGR_SEM_EN BIT(1)
+#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R16CIDCFGR_SCID_SHIFT 4
+#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R16SEMCR register fields */
+#define RCC_R16SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R16SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R17CIDCFGR register fields */
+#define RCC_R17CIDCFGR_CFEN BIT(0)
+#define RCC_R17CIDCFGR_SEM_EN BIT(1)
+#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R17CIDCFGR_SCID_SHIFT 4
+#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R17SEMCR register fields */
+#define RCC_R17SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R17SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R18CIDCFGR register fields */
+#define RCC_R18CIDCFGR_CFEN BIT(0)
+#define RCC_R18CIDCFGR_SEM_EN BIT(1)
+#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R18CIDCFGR_SCID_SHIFT 4
+#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R18SEMCR register fields */
+#define RCC_R18SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R18SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R19CIDCFGR register fields */
+#define RCC_R19CIDCFGR_CFEN BIT(0)
+#define RCC_R19CIDCFGR_SEM_EN BIT(1)
+#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R19CIDCFGR_SCID_SHIFT 4
+#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R19SEMCR register fields */
+#define RCC_R19SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R19SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R20CIDCFGR register fields */
+#define RCC_R20CIDCFGR_CFEN BIT(0)
+#define RCC_R20CIDCFGR_SEM_EN BIT(1)
+#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R20CIDCFGR_SCID_SHIFT 4
+#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R20SEMCR register fields */
+#define RCC_R20SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R20SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R21CIDCFGR register fields */
+#define RCC_R21CIDCFGR_CFEN BIT(0)
+#define RCC_R21CIDCFGR_SEM_EN BIT(1)
+#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R21CIDCFGR_SCID_SHIFT 4
+#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R21SEMCR register fields */
+#define RCC_R21SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R21SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R22CIDCFGR register fields */
+#define RCC_R22CIDCFGR_CFEN BIT(0)
+#define RCC_R22CIDCFGR_SEM_EN BIT(1)
+#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R22CIDCFGR_SCID_SHIFT 4
+#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R22SEMCR register fields */
+#define RCC_R22SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R22SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R23CIDCFGR register fields */
+#define RCC_R23CIDCFGR_CFEN BIT(0)
+#define RCC_R23CIDCFGR_SEM_EN BIT(1)
+#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R23CIDCFGR_SCID_SHIFT 4
+#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R23SEMCR register fields */
+#define RCC_R23SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R23SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R24CIDCFGR register fields */
+#define RCC_R24CIDCFGR_CFEN BIT(0)
+#define RCC_R24CIDCFGR_SEM_EN BIT(1)
+#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R24CIDCFGR_SCID_SHIFT 4
+#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R24SEMCR register fields */
+#define RCC_R24SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R24SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R25CIDCFGR register fields */
+#define RCC_R25CIDCFGR_CFEN BIT(0)
+#define RCC_R25CIDCFGR_SEM_EN BIT(1)
+#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R25CIDCFGR_SCID_SHIFT 4
+#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R25SEMCR register fields */
+#define RCC_R25SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R25SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R26CIDCFGR register fields */
+#define RCC_R26CIDCFGR_CFEN BIT(0)
+#define RCC_R26CIDCFGR_SEM_EN BIT(1)
+#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R26CIDCFGR_SCID_SHIFT 4
+#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R26SEMCR register fields */
+#define RCC_R26SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R26SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R27CIDCFGR register fields */
+#define RCC_R27CIDCFGR_CFEN BIT(0)
+#define RCC_R27CIDCFGR_SEM_EN BIT(1)
+#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R27CIDCFGR_SCID_SHIFT 4
+#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R27SEMCR register fields */
+#define RCC_R27SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R27SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R28CIDCFGR register fields */
+#define RCC_R28CIDCFGR_CFEN BIT(0)
+#define RCC_R28CIDCFGR_SEM_EN BIT(1)
+#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R28CIDCFGR_SCID_SHIFT 4
+#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R28SEMCR register fields */
+#define RCC_R28SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R28SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R29CIDCFGR register fields */
+#define RCC_R29CIDCFGR_CFEN BIT(0)
+#define RCC_R29CIDCFGR_SEM_EN BIT(1)
+#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R29CIDCFGR_SCID_SHIFT 4
+#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R29SEMCR register fields */
+#define RCC_R29SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R29SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R30CIDCFGR register fields */
+#define RCC_R30CIDCFGR_CFEN BIT(0)
+#define RCC_R30CIDCFGR_SEM_EN BIT(1)
+#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R30CIDCFGR_SCID_SHIFT 4
+#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R30SEMCR register fields */
+#define RCC_R30SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R30SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R31CIDCFGR register fields */
+#define RCC_R31CIDCFGR_CFEN BIT(0)
+#define RCC_R31CIDCFGR_SEM_EN BIT(1)
+#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R31CIDCFGR_SCID_SHIFT 4
+#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R31SEMCR register fields */
+#define RCC_R31SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R31SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R32CIDCFGR register fields */
+#define RCC_R32CIDCFGR_CFEN BIT(0)
+#define RCC_R32CIDCFGR_SEM_EN BIT(1)
+#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R32CIDCFGR_SCID_SHIFT 4
+#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R32SEMCR register fields */
+#define RCC_R32SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R32SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R33CIDCFGR register fields */
+#define RCC_R33CIDCFGR_CFEN BIT(0)
+#define RCC_R33CIDCFGR_SEM_EN BIT(1)
+#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R33CIDCFGR_SCID_SHIFT 4
+#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R33SEMCR register fields */
+#define RCC_R33SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R33SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R34CIDCFGR register fields */
+#define RCC_R34CIDCFGR_CFEN BIT(0)
+#define RCC_R34CIDCFGR_SEM_EN BIT(1)
+#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R34CIDCFGR_SCID_SHIFT 4
+#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R34SEMCR register fields */
+#define RCC_R34SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R34SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R35CIDCFGR register fields */
+#define RCC_R35CIDCFGR_CFEN BIT(0)
+#define RCC_R35CIDCFGR_SEM_EN BIT(1)
+#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R35CIDCFGR_SCID_SHIFT 4
+#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R35SEMCR register fields */
+#define RCC_R35SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R35SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R36CIDCFGR register fields */
+#define RCC_R36CIDCFGR_CFEN BIT(0)
+#define RCC_R36CIDCFGR_SEM_EN BIT(1)
+#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R36CIDCFGR_SCID_SHIFT 4
+#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R36SEMCR register fields */
+#define RCC_R36SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R36SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R37CIDCFGR register fields */
+#define RCC_R37CIDCFGR_CFEN BIT(0)
+#define RCC_R37CIDCFGR_SEM_EN BIT(1)
+#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R37CIDCFGR_SCID_SHIFT 4
+#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R37SEMCR register fields */
+#define RCC_R37SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R37SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R38CIDCFGR register fields */
+#define RCC_R38CIDCFGR_CFEN BIT(0)
+#define RCC_R38CIDCFGR_SEM_EN BIT(1)
+#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R38CIDCFGR_SCID_SHIFT 4
+#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R38SEMCR register fields */
+#define RCC_R38SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R38SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R39CIDCFGR register fields */
+#define RCC_R39CIDCFGR_CFEN BIT(0)
+#define RCC_R39CIDCFGR_SEM_EN BIT(1)
+#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R39CIDCFGR_SCID_SHIFT 4
+#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R39SEMCR register fields */
+#define RCC_R39SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R39SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R40CIDCFGR register fields */
+#define RCC_R40CIDCFGR_CFEN BIT(0)
+#define RCC_R40CIDCFGR_SEM_EN BIT(1)
+#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R40CIDCFGR_SCID_SHIFT 4
+#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R40SEMCR register fields */
+#define RCC_R40SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R40SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R41CIDCFGR register fields */
+#define RCC_R41CIDCFGR_CFEN BIT(0)
+#define RCC_R41CIDCFGR_SEM_EN BIT(1)
+#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R41CIDCFGR_SCID_SHIFT 4
+#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R41SEMCR register fields */
+#define RCC_R41SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R41SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R42CIDCFGR register fields */
+#define RCC_R42CIDCFGR_CFEN BIT(0)
+#define RCC_R42CIDCFGR_SEM_EN BIT(1)
+#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R42CIDCFGR_SCID_SHIFT 4
+#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R42SEMCR register fields */
+#define RCC_R42SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R42SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R43CIDCFGR register fields */
+#define RCC_R43CIDCFGR_CFEN BIT(0)
+#define RCC_R43CIDCFGR_SEM_EN BIT(1)
+#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R43CIDCFGR_SCID_SHIFT 4
+#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R43SEMCR register fields */
+#define RCC_R43SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R43SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R44CIDCFGR register fields */
+#define RCC_R44CIDCFGR_CFEN BIT(0)
+#define RCC_R44CIDCFGR_SEM_EN BIT(1)
+#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R44CIDCFGR_SCID_SHIFT 4
+#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R44SEMCR register fields */
+#define RCC_R44SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R44SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R45CIDCFGR register fields */
+#define RCC_R45CIDCFGR_CFEN BIT(0)
+#define RCC_R45CIDCFGR_SEM_EN BIT(1)
+#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R45CIDCFGR_SCID_SHIFT 4
+#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R45SEMCR register fields */
+#define RCC_R45SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R45SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R46CIDCFGR register fields */
+#define RCC_R46CIDCFGR_CFEN BIT(0)
+#define RCC_R46CIDCFGR_SEM_EN BIT(1)
+#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R46CIDCFGR_SCID_SHIFT 4
+#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R46SEMCR register fields */
+#define RCC_R46SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R46SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R47CIDCFGR register fields */
+#define RCC_R47CIDCFGR_CFEN BIT(0)
+#define RCC_R47CIDCFGR_SEM_EN BIT(1)
+#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R47CIDCFGR_SCID_SHIFT 4
+#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R47SEMCR register fields */
+#define RCC_R47SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R47SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R48CIDCFGR register fields */
+#define RCC_R48CIDCFGR_CFEN BIT(0)
+#define RCC_R48CIDCFGR_SEM_EN BIT(1)
+#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R48CIDCFGR_SCID_SHIFT 4
+#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R48SEMCR register fields */
+#define RCC_R48SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R48SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R49CIDCFGR register fields */
+#define RCC_R49CIDCFGR_CFEN BIT(0)
+#define RCC_R49CIDCFGR_SEM_EN BIT(1)
+#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R49CIDCFGR_SCID_SHIFT 4
+#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R49SEMCR register fields */
+#define RCC_R49SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R49SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R50CIDCFGR register fields */
+#define RCC_R50CIDCFGR_CFEN BIT(0)
+#define RCC_R50CIDCFGR_SEM_EN BIT(1)
+#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R50CIDCFGR_SCID_SHIFT 4
+#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R50SEMCR register fields */
+#define RCC_R50SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R50SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R51CIDCFGR register fields */
+#define RCC_R51CIDCFGR_CFEN BIT(0)
+#define RCC_R51CIDCFGR_SEM_EN BIT(1)
+#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R51CIDCFGR_SCID_SHIFT 4
+#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R51SEMCR register fields */
+#define RCC_R51SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R51SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R52CIDCFGR register fields */
+#define RCC_R52CIDCFGR_CFEN BIT(0)
+#define RCC_R52CIDCFGR_SEM_EN BIT(1)
+#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R52CIDCFGR_SCID_SHIFT 4
+#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R52SEMCR register fields */
+#define RCC_R52SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R52SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R53CIDCFGR register fields */
+#define RCC_R53CIDCFGR_CFEN BIT(0)
+#define RCC_R53CIDCFGR_SEM_EN BIT(1)
+#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R53CIDCFGR_SCID_SHIFT 4
+#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R53SEMCR register fields */
+#define RCC_R53SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R53SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R54CIDCFGR register fields */
+#define RCC_R54CIDCFGR_CFEN BIT(0)
+#define RCC_R54CIDCFGR_SEM_EN BIT(1)
+#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R54CIDCFGR_SCID_SHIFT 4
+#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R54SEMCR register fields */
+#define RCC_R54SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R54SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R55CIDCFGR register fields */
+#define RCC_R55CIDCFGR_CFEN BIT(0)
+#define RCC_R55CIDCFGR_SEM_EN BIT(1)
+#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R55CIDCFGR_SCID_SHIFT 4
+#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R55SEMCR register fields */
+#define RCC_R55SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R55SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R56CIDCFGR register fields */
+#define RCC_R56CIDCFGR_CFEN BIT(0)
+#define RCC_R56CIDCFGR_SEM_EN BIT(1)
+#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R56CIDCFGR_SCID_SHIFT 4
+#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R56SEMCR register fields */
+#define RCC_R56SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R56SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R57CIDCFGR register fields */
+#define RCC_R57CIDCFGR_CFEN BIT(0)
+#define RCC_R57CIDCFGR_SEM_EN BIT(1)
+#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R57CIDCFGR_SCID_SHIFT 4
+#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R57SEMCR register fields */
+#define RCC_R57SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R57SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R58CIDCFGR register fields */
+#define RCC_R58CIDCFGR_CFEN BIT(0)
+#define RCC_R58CIDCFGR_SEM_EN BIT(1)
+#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R58CIDCFGR_SCID_SHIFT 4
+#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R58SEMCR register fields */
+#define RCC_R58SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R58SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R59CIDCFGR register fields */
+#define RCC_R59CIDCFGR_CFEN BIT(0)
+#define RCC_R59CIDCFGR_SEM_EN BIT(1)
+#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R59CIDCFGR_SCID_SHIFT 4
+#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R59SEMCR register fields */
+#define RCC_R59SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R59SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R60CIDCFGR register fields */
+#define RCC_R60CIDCFGR_CFEN BIT(0)
+#define RCC_R60CIDCFGR_SEM_EN BIT(1)
+#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R60CIDCFGR_SCID_SHIFT 4
+#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R60SEMCR register fields */
+#define RCC_R60SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R60SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R61CIDCFGR register fields */
+#define RCC_R61CIDCFGR_CFEN BIT(0)
+#define RCC_R61CIDCFGR_SEM_EN BIT(1)
+#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R61CIDCFGR_SCID_SHIFT 4
+#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R61SEMCR register fields */
+#define RCC_R61SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R61SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R62CIDCFGR register fields */
+#define RCC_R62CIDCFGR_CFEN BIT(0)
+#define RCC_R62CIDCFGR_SEM_EN BIT(1)
+#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R62CIDCFGR_SCID_SHIFT 4
+#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R62SEMCR register fields */
+#define RCC_R62SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R62SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R63CIDCFGR register fields */
+#define RCC_R63CIDCFGR_CFEN BIT(0)
+#define RCC_R63CIDCFGR_SEM_EN BIT(1)
+#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R63CIDCFGR_SCID_SHIFT 4
+#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R63SEMCR register fields */
+#define RCC_R63SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R63SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R64CIDCFGR register fields */
+#define RCC_R64CIDCFGR_CFEN BIT(0)
+#define RCC_R64CIDCFGR_SEM_EN BIT(1)
+#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R64CIDCFGR_SCID_SHIFT 4
+#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R64SEMCR register fields */
+#define RCC_R64SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R64SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R65CIDCFGR register fields */
+#define RCC_R65CIDCFGR_CFEN BIT(0)
+#define RCC_R65CIDCFGR_SEM_EN BIT(1)
+#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R65CIDCFGR_SCID_SHIFT 4
+#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R65SEMCR register fields */
+#define RCC_R65SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R65SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R66CIDCFGR register fields */
+#define RCC_R66CIDCFGR_CFEN BIT(0)
+#define RCC_R66CIDCFGR_SEM_EN BIT(1)
+#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R66CIDCFGR_SCID_SHIFT 4
+#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R66SEMCR register fields */
+#define RCC_R66SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R66SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R67CIDCFGR register fields */
+#define RCC_R67CIDCFGR_CFEN BIT(0)
+#define RCC_R67CIDCFGR_SEM_EN BIT(1)
+#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R67CIDCFGR_SCID_SHIFT 4
+#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R67SEMCR register fields */
+#define RCC_R67SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R67SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R68CIDCFGR register fields */
+#define RCC_R68CIDCFGR_CFEN BIT(0)
+#define RCC_R68CIDCFGR_SEM_EN BIT(1)
+#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R68CIDCFGR_SCID_SHIFT 4
+#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R68SEMCR register fields */
+#define RCC_R68SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R68SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R69CIDCFGR register fields */
+#define RCC_R69CIDCFGR_CFEN BIT(0)
+#define RCC_R69CIDCFGR_SEM_EN BIT(1)
+#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R69CIDCFGR_SCID_SHIFT 4
+#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R69SEMCR register fields */
+#define RCC_R69SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R69SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R70CIDCFGR register fields */
+#define RCC_R70CIDCFGR_CFEN BIT(0)
+#define RCC_R70CIDCFGR_SEM_EN BIT(1)
+#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R70CIDCFGR_SCID_SHIFT 4
+#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R70SEMCR register fields */
+#define RCC_R70SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R70SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R71CIDCFGR register fields */
+#define RCC_R71CIDCFGR_CFEN BIT(0)
+#define RCC_R71CIDCFGR_SEM_EN BIT(1)
+#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R71CIDCFGR_SCID_SHIFT 4
+#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R71SEMCR register fields */
+#define RCC_R71SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R71SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R72CIDCFGR register fields */
+#define RCC_R72CIDCFGR_CFEN BIT(0)
+#define RCC_R72CIDCFGR_SEM_EN BIT(1)
+#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R72CIDCFGR_SCID_SHIFT 4
+#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R72SEMCR register fields */
+#define RCC_R72SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R72SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R73CIDCFGR register fields */
+#define RCC_R73CIDCFGR_CFEN BIT(0)
+#define RCC_R73CIDCFGR_SEM_EN BIT(1)
+#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R73CIDCFGR_SCID_SHIFT 4
+#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R73SEMCR register fields */
+#define RCC_R73SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R73SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R74CIDCFGR register fields */
+#define RCC_R74CIDCFGR_CFEN BIT(0)
+#define RCC_R74CIDCFGR_SEM_EN BIT(1)
+#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R74CIDCFGR_SCID_SHIFT 4
+#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R74SEMCR register fields */
+#define RCC_R74SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R74SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R75CIDCFGR register fields */
+#define RCC_R75CIDCFGR_CFEN BIT(0)
+#define RCC_R75CIDCFGR_SEM_EN BIT(1)
+#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R75CIDCFGR_SCID_SHIFT 4
+#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R75SEMCR register fields */
+#define RCC_R75SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R75SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R76CIDCFGR register fields */
+#define RCC_R76CIDCFGR_CFEN BIT(0)
+#define RCC_R76CIDCFGR_SEM_EN BIT(1)
+#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R76CIDCFGR_SCID_SHIFT 4
+#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R76SEMCR register fields */
+#define RCC_R76SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R76SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R77CIDCFGR register fields */
+#define RCC_R77CIDCFGR_CFEN BIT(0)
+#define RCC_R77CIDCFGR_SEM_EN BIT(1)
+#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R77CIDCFGR_SCID_SHIFT 4
+#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R77SEMCR register fields */
+#define RCC_R77SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R77SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R78CIDCFGR register fields */
+#define RCC_R78CIDCFGR_CFEN BIT(0)
+#define RCC_R78CIDCFGR_SEM_EN BIT(1)
+#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R78CIDCFGR_SCID_SHIFT 4
+#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R78SEMCR register fields */
+#define RCC_R78SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R78SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R79CIDCFGR register fields */
+#define RCC_R79CIDCFGR_CFEN BIT(0)
+#define RCC_R79CIDCFGR_SEM_EN BIT(1)
+#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R79CIDCFGR_SCID_SHIFT 4
+#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R79SEMCR register fields */
+#define RCC_R79SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R79SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R80CIDCFGR register fields */
+#define RCC_R80CIDCFGR_CFEN BIT(0)
+#define RCC_R80CIDCFGR_SEM_EN BIT(1)
+#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R80CIDCFGR_SCID_SHIFT 4
+#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R80SEMCR register fields */
+#define RCC_R80SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R80SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R81CIDCFGR register fields */
+#define RCC_R81CIDCFGR_CFEN BIT(0)
+#define RCC_R81CIDCFGR_SEM_EN BIT(1)
+#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R81CIDCFGR_SCID_SHIFT 4
+#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R81SEMCR register fields */
+#define RCC_R81SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R81SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R82CIDCFGR register fields */
+#define RCC_R82CIDCFGR_CFEN BIT(0)
+#define RCC_R82CIDCFGR_SEM_EN BIT(1)
+#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R82CIDCFGR_SCID_SHIFT 4
+#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R82SEMCR register fields */
+#define RCC_R82SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R82SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R83CIDCFGR register fields */
+#define RCC_R83CIDCFGR_CFEN BIT(0)
+#define RCC_R83CIDCFGR_SEM_EN BIT(1)
+#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R83CIDCFGR_SCID_SHIFT 4
+#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R83SEMCR register fields */
+#define RCC_R83SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R83SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R84CIDCFGR register fields */
+#define RCC_R84CIDCFGR_CFEN BIT(0)
+#define RCC_R84CIDCFGR_SEM_EN BIT(1)
+#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R84CIDCFGR_SCID_SHIFT 4
+#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R84SEMCR register fields */
+#define RCC_R84SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R84SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R85CIDCFGR register fields */
+#define RCC_R85CIDCFGR_CFEN BIT(0)
+#define RCC_R85CIDCFGR_SEM_EN BIT(1)
+#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R85CIDCFGR_SCID_SHIFT 4
+#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R85SEMCR register fields */
+#define RCC_R85SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R85SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R86CIDCFGR register fields */
+#define RCC_R86CIDCFGR_CFEN BIT(0)
+#define RCC_R86CIDCFGR_SEM_EN BIT(1)
+#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R86CIDCFGR_SCID_SHIFT 4
+#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R86SEMCR register fields */
+#define RCC_R86SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R86SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R87CIDCFGR register fields */
+#define RCC_R87CIDCFGR_CFEN BIT(0)
+#define RCC_R87CIDCFGR_SEM_EN BIT(1)
+#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R87CIDCFGR_SCID_SHIFT 4
+#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R87SEMCR register fields */
+#define RCC_R87SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R87SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R88CIDCFGR register fields */
+#define RCC_R88CIDCFGR_CFEN BIT(0)
+#define RCC_R88CIDCFGR_SEM_EN BIT(1)
+#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R88CIDCFGR_SCID_SHIFT 4
+#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R88SEMCR register fields */
+#define RCC_R88SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R88SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R89CIDCFGR register fields */
+#define RCC_R89CIDCFGR_CFEN BIT(0)
+#define RCC_R89CIDCFGR_SEM_EN BIT(1)
+#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R89CIDCFGR_SCID_SHIFT 4
+#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R89SEMCR register fields */
+#define RCC_R89SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R89SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R90CIDCFGR register fields */
+#define RCC_R90CIDCFGR_CFEN BIT(0)
+#define RCC_R90CIDCFGR_SEM_EN BIT(1)
+#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R90CIDCFGR_SCID_SHIFT 4
+#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R90SEMCR register fields */
+#define RCC_R90SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R90SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R91CIDCFGR register fields */
+#define RCC_R91CIDCFGR_CFEN BIT(0)
+#define RCC_R91CIDCFGR_SEM_EN BIT(1)
+#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R91CIDCFGR_SCID_SHIFT 4
+#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R91SEMCR register fields */
+#define RCC_R91SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R91SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R92CIDCFGR register fields */
+#define RCC_R92CIDCFGR_CFEN BIT(0)
+#define RCC_R92CIDCFGR_SEM_EN BIT(1)
+#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R92CIDCFGR_SCID_SHIFT 4
+#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R92SEMCR register fields */
+#define RCC_R92SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R92SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R93CIDCFGR register fields */
+#define RCC_R93CIDCFGR_CFEN BIT(0)
+#define RCC_R93CIDCFGR_SEM_EN BIT(1)
+#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R93CIDCFGR_SCID_SHIFT 4
+#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R93SEMCR register fields */
+#define RCC_R93SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R93SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R94CIDCFGR register fields */
+#define RCC_R94CIDCFGR_CFEN BIT(0)
+#define RCC_R94CIDCFGR_SEM_EN BIT(1)
+#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R94CIDCFGR_SCID_SHIFT 4
+#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R94SEMCR register fields */
+#define RCC_R94SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R94SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R95CIDCFGR register fields */
+#define RCC_R95CIDCFGR_CFEN BIT(0)
+#define RCC_R95CIDCFGR_SEM_EN BIT(1)
+#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R95CIDCFGR_SCID_SHIFT 4
+#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R95SEMCR register fields */
+#define RCC_R95SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R95SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R96CIDCFGR register fields */
+#define RCC_R96CIDCFGR_CFEN BIT(0)
+#define RCC_R96CIDCFGR_SEM_EN BIT(1)
+#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R96CIDCFGR_SCID_SHIFT 4
+#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R96SEMCR register fields */
+#define RCC_R96SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R96SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R97CIDCFGR register fields */
+#define RCC_R97CIDCFGR_CFEN BIT(0)
+#define RCC_R97CIDCFGR_SEM_EN BIT(1)
+#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R97CIDCFGR_SCID_SHIFT 4
+#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R97SEMCR register fields */
+#define RCC_R97SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R97SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R98CIDCFGR register fields */
+#define RCC_R98CIDCFGR_CFEN BIT(0)
+#define RCC_R98CIDCFGR_SEM_EN BIT(1)
+#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R98CIDCFGR_SCID_SHIFT 4
+#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R98SEMCR register fields */
+#define RCC_R98SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R98SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R99CIDCFGR register fields */
+#define RCC_R99CIDCFGR_CFEN BIT(0)
+#define RCC_R99CIDCFGR_SEM_EN BIT(1)
+#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R99CIDCFGR_SCID_SHIFT 4
+#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R99SEMCR register fields */
+#define RCC_R99SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R99SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R100CIDCFGR register fields */
+#define RCC_R100CIDCFGR_CFEN BIT(0)
+#define RCC_R100CIDCFGR_SEM_EN BIT(1)
+#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R100CIDCFGR_SCID_SHIFT 4
+#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R100SEMCR register fields */
+#define RCC_R100SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R100SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R101CIDCFGR register fields */
+#define RCC_R101CIDCFGR_CFEN BIT(0)
+#define RCC_R101CIDCFGR_SEM_EN BIT(1)
+#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R101CIDCFGR_SCID_SHIFT 4
+#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R101SEMCR register fields */
+#define RCC_R101SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R101SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R102CIDCFGR register fields */
+#define RCC_R102CIDCFGR_CFEN BIT(0)
+#define RCC_R102CIDCFGR_SEM_EN BIT(1)
+#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R102CIDCFGR_SCID_SHIFT 4
+#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R102SEMCR register fields */
+#define RCC_R102SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R102SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R103CIDCFGR register fields */
+#define RCC_R103CIDCFGR_CFEN BIT(0)
+#define RCC_R103CIDCFGR_SEM_EN BIT(1)
+#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R103CIDCFGR_SCID_SHIFT 4
+#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R103SEMCR register fields */
+#define RCC_R103SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R103SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R104CIDCFGR register fields */
+#define RCC_R104CIDCFGR_CFEN BIT(0)
+#define RCC_R104CIDCFGR_SEM_EN BIT(1)
+#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R104CIDCFGR_SCID_SHIFT 4
+#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R104SEMCR register fields */
+#define RCC_R104SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R104SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R105CIDCFGR register fields */
+#define RCC_R105CIDCFGR_CFEN BIT(0)
+#define RCC_R105CIDCFGR_SEM_EN BIT(1)
+#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R105CIDCFGR_SCID_SHIFT 4
+#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R105SEMCR register fields */
+#define RCC_R105SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R105SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R106CIDCFGR register fields */
+#define RCC_R106CIDCFGR_CFEN BIT(0)
+#define RCC_R106CIDCFGR_SEM_EN BIT(1)
+#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R106CIDCFGR_SCID_SHIFT 4
+#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R106SEMCR register fields */
+#define RCC_R106SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R106SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R107CIDCFGR register fields */
+#define RCC_R107CIDCFGR_CFEN BIT(0)
+#define RCC_R107CIDCFGR_SEM_EN BIT(1)
+#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R107CIDCFGR_SCID_SHIFT 4
+#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R107SEMCR register fields */
+#define RCC_R107SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R107SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R108CIDCFGR register fields */
+#define RCC_R108CIDCFGR_CFEN BIT(0)
+#define RCC_R108CIDCFGR_SEM_EN BIT(1)
+#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R108CIDCFGR_SCID_SHIFT 4
+#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R108SEMCR register fields */
+#define RCC_R108SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R108SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R109CIDCFGR register fields */
+#define RCC_R109CIDCFGR_CFEN BIT(0)
+#define RCC_R109CIDCFGR_SEM_EN BIT(1)
+#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R109CIDCFGR_SCID_SHIFT 4
+#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R109SEMCR register fields */
+#define RCC_R109SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R109SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R110CIDCFGR register fields */
+#define RCC_R110CIDCFGR_CFEN BIT(0)
+#define RCC_R110CIDCFGR_SEM_EN BIT(1)
+#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R110CIDCFGR_SCID_SHIFT 4
+#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R110SEMCR register fields */
+#define RCC_R110SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R110SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R111CIDCFGR register fields */
+#define RCC_R111CIDCFGR_CFEN BIT(0)
+#define RCC_R111CIDCFGR_SEM_EN BIT(1)
+#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R111CIDCFGR_SCID_SHIFT 4
+#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R111SEMCR register fields */
+#define RCC_R111SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R111SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R112CIDCFGR register fields */
+#define RCC_R112CIDCFGR_CFEN BIT(0)
+#define RCC_R112CIDCFGR_SEM_EN BIT(1)
+#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R112CIDCFGR_SCID_SHIFT 4
+#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R112SEMCR register fields */
+#define RCC_R112SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R112SEMCR_SEMCID_SHIFT 4
+
+/* RCC_R113CIDCFGR register fields */
+#define RCC_R113CIDCFGR_CFEN BIT(0)
+#define RCC_R113CIDCFGR_SEM_EN BIT(1)
+#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_R113CIDCFGR_SCID_SHIFT 4
+#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_R113SEMCR register fields */
+#define RCC_R113SEMCR_SEM_MUTEX BIT(0)
+#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_R113SEMCR_SEMCID_SHIFT 4
+
+/* RCC_RxCIDCFGR register fields */
+#define RCC_RxCIDCFGR_CFEN BIT(0)
+#define RCC_RxCIDCFGR_SEM_EN BIT(1)
+#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4)
+#define RCC_RxCIDCFGR_SCID_SHIFT 4
+#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16)
+#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16
+
+/* RCC_RxSEMCR register fields */
+#define RCC_RxSEMCR_SEM_MUTEX BIT(0)
+#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4)
+#define RCC_RxSEMCR_SEMCID_SHIFT 4
+
+/* RCC_GRSTCSETR register fields */
+#define RCC_GRSTCSETR_SYSRST BIT(0)
+
+/* RCC_C1RSTCSETR register fields */
+#define RCC_C1RSTCSETR_C1RST BIT(0)
+
+/* RCC_C2RSTCSETR register fields */
+#define RCC_C2RSTCSETR_C2RST BIT(0)
+
+/* RCC_CxRSTCSETR register fields */
+#define RCC_CxRSTCSETR_CxRST BIT(0)
+
+/* RCC_HWRSTSCLRR register fields */
+#define RCC_HWRSTSCLRR_PORRSTF BIT(0)
+#define RCC_HWRSTSCLRR_BORRSTF BIT(1)
+#define RCC_HWRSTSCLRR_PADRSTF BIT(2)
+#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_HWRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5)
+#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6)
+#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7)
+#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8)
+#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9)
+#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10)
+#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12)
+#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13)
+#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14)
+
+/* RCC_C1HWRSTSCLRR register fields */
+#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0)
+#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1)
+
+/* RCC_C2HWRSTSCLRR register fields */
+#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0)
+
+/* RCC_C1BOOTRSTSSETR register fields */
+#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C1BOOTRSTSCLRR register fields */
+#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5)
+#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13)
+#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20)
+#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
+#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF)
+
+/* RCC_C2BOOTRSTSSETR register fields */
+#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23)
+
+/* RCC_C2BOOTRSTSCLRR register fields */
+#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0)
+#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1)
+#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2)
+#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3)
+#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4)
+#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6)
+#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7)
+#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8)
+#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9)
+#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10)
+#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11)
+#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14)
+#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19)
+#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21)
+#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+
+/* RCC_C1SREQSETR register fields */
+#define RCC_C1SREQSETR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQSETR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQSETR_STPREQ_MASK GENMASK_32(1, 0)
+#define RCC_C1SREQSETR_ESLPREQ BIT(16)
+
+/* RCC_C1SREQCLRR register fields */
+#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0)
+#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1)
+#define RCC_C1SREQCLRR_STPREQ_MASK GENMASK_32(1, 0)
+#define RCC_C1SREQCLRR_ESLPREQ BIT(16)
+
+/* RCC_CPUBOOTCR register fields */
+#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0)
+#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1)
+
+/* RCC_STBYBOOTCR register fields */
+#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1)
+#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2)
+#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4)
+#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5)
+#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8)
+
+/* RCC_LEGBOOTCR register fields */
+#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0)
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON BIT(0)
+#define RCC_BDCR_LSEBYP BIT(1)
+#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_LSEDIGBYP BIT(3)
+#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT 4
+#define RCC_BDCR_LSECSSON BIT(6)
+#define RCC_BDCR_LSEGFON BIT(7)
+#define RCC_BDCR_LSECSSD BIT(8)
+#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT 16
+#define RCC_BDCR_RTCCKEN BIT(20)
+#define RCC_BDCR_VSWRST BIT(31)
+
+/* RCC_RDCR register fields */
+#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16)
+#define RCC_RDCR_MRD_SHIFT 16
+#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24)
+#define RCC_RDCR_EADLY_SHIFT 24
+
+/* RCC_C1MSRDCR register fields */
+#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0)
+#define RCC_C1MSRDCR_C1MSRD_SHIFT 0
+#define RCC_C1MSRDCR_C1MSRST BIT(8)
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0
+#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24)
+
+/* RCC_C1CIESETR register fields */
+#define RCC_C1CIESETR_LSIRDYIE BIT(0)
+#define RCC_C1CIESETR_LSERDYIE BIT(1)
+#define RCC_C1CIESETR_HSIRDYIE BIT(2)
+#define RCC_C1CIESETR_HSERDYIE BIT(3)
+#define RCC_C1CIESETR_MSIRDYIE BIT(4)
+#define RCC_C1CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C1CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C1CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C1CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C1CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C1CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C1CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C1CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C1CIESETR_LSECSSIE BIT(16)
+#define RCC_C1CIESETR_WKUPIE BIT(20)
+
+/* RCC_C1CIFCLRR register fields */
+#define RCC_C1CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C1CIFCLRR_LSERDYF BIT(1)
+#define RCC_C1CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C1CIFCLRR_HSERDYF BIT(3)
+#define RCC_C1CIFCLRR_MSIRDYF BIT(4)
+#define RCC_C1CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C1CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C1CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C1CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C1CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C1CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C1CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C1CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C1CIFCLRR_LSECSSF BIT(16)
+#define RCC_C1CIFCLRR_WKUPF BIT(20)
+
+/* RCC_C2CIESETR register fields */
+#define RCC_C2CIESETR_LSIRDYIE BIT(0)
+#define RCC_C2CIESETR_LSERDYIE BIT(1)
+#define RCC_C2CIESETR_HSIRDYIE BIT(2)
+#define RCC_C2CIESETR_HSERDYIE BIT(3)
+#define RCC_C2CIESETR_MSIRDYIE BIT(4)
+#define RCC_C2CIESETR_PLL1RDYIE BIT(5)
+#define RCC_C2CIESETR_PLL2RDYIE BIT(6)
+#define RCC_C2CIESETR_PLL3RDYIE BIT(7)
+#define RCC_C2CIESETR_PLL4RDYIE BIT(8)
+#define RCC_C2CIESETR_PLL5RDYIE BIT(9)
+#define RCC_C2CIESETR_PLL6RDYIE BIT(10)
+#define RCC_C2CIESETR_PLL7RDYIE BIT(11)
+#define RCC_C2CIESETR_PLL8RDYIE BIT(12)
+#define RCC_C2CIESETR_LSECSSIE BIT(16)
+#define RCC_C2CIESETR_WKUPIE BIT(20)
+
+/* RCC_C2CIFCLRR register fields */
+#define RCC_C2CIFCLRR_LSIRDYF BIT(0)
+#define RCC_C2CIFCLRR_LSERDYF BIT(1)
+#define RCC_C2CIFCLRR_HSIRDYF BIT(2)
+#define RCC_C2CIFCLRR_HSERDYF BIT(3)
+#define RCC_C2CIFCLRR_MSIRDYF BIT(4)
+#define RCC_C2CIFCLRR_PLL1RDYF BIT(5)
+#define RCC_C2CIFCLRR_PLL2RDYF BIT(6)
+#define RCC_C2CIFCLRR_PLL3RDYF BIT(7)
+#define RCC_C2CIFCLRR_PLL4RDYF BIT(8)
+#define RCC_C2CIFCLRR_PLL5RDYF BIT(9)
+#define RCC_C2CIFCLRR_PLL6RDYF BIT(10)
+#define RCC_C2CIFCLRR_PLL7RDYF BIT(11)
+#define RCC_C2CIFCLRR_PLL8RDYF BIT(12)
+#define RCC_C2CIFCLRR_LSECSSF BIT(16)
+#define RCC_C2CIFCLRR_WKUPF BIT(20)
+
+/* RCC_CxCIESETR register fields */
+#define RCC_CxCIESETR_LSIRDYIE BIT(0)
+#define RCC_CxCIESETR_LSERDYIE BIT(1)
+#define RCC_CxCIESETR_HSIRDYIE BIT(2)
+#define RCC_CxCIESETR_HSERDYIE BIT(3)
+#define RCC_CxCIESETR_CSIRDYIE BIT(4)
+#define RCC_CxCIESETR_SHSIRDYIE BIT(5)
+#define RCC_CxCIESETR_PLL1RDYIE BIT(6)
+#define RCC_CxCIESETR_PLL2RDYIE BIT(7)
+#define RCC_CxCIESETR_PLL3RDYIE BIT(8)
+#define RCC_CxCIESETR_PLL4RDYIE BIT(9)
+#define RCC_CxCIESETR_PLL5RDYIE BIT(10)
+#define RCC_CxCIESETR_PLL6RDYIE BIT(11)
+#define RCC_CxCIESETR_PLL7RDYIE BIT(12)
+#define RCC_CxCIESETR_PLL8RDYIE BIT(13)
+#define RCC_CxCIESETR_LSECSSIE BIT(16)
+#define RCC_CxCIESETR_WKUPIE BIT(20)
+
+/* RCC_CxCIFCLRR register fields */
+#define RCC_CxCIFCLRR_LSIRDYF BIT(0)
+#define RCC_CxCIFCLRR_LSERDYF BIT(1)
+#define RCC_CxCIFCLRR_HSIRDYF BIT(2)
+#define RCC_CxCIFCLRR_HSERDYF BIT(3)
+#define RCC_CxCIFCLRR_CSIRDYF BIT(4)
+#define RCC_CxCIFCLRR_SHSIRDYF BIT(5)
+#define RCC_CxCIFCLRR_PLL1RDYF BIT(6)
+#define RCC_CxCIFCLRR_PLL2RDYF BIT(7)
+#define RCC_CxCIFCLRR_PLL3RDYF BIT(8)
+#define RCC_CxCIFCLRR_PLL4RDYF BIT(9)
+#define RCC_CxCIFCLRR_PLL5RDYF BIT(10)
+#define RCC_CxCIFCLRR_PLL6RDYF BIT(11)
+#define RCC_CxCIFCLRR_PLL7RDYF BIT(12)
+#define RCC_CxCIFCLRR_PLL8RDYF BIT(13)
+#define RCC_CxCIFCLRR_LSECSSF BIT(16)
+#define RCC_CxCIFCLRR_WKUPF BIT(20)
+
+/* RCC_IWDGC1FZSETR register fields */
+#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1FZCLRR register fields */
+#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0)
+#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1)
+
+/* RCC_IWDGC1CFGSETR register fields */
+#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC1CFGCLRR register fields */
+#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0)
+#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2)
+#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18)
+
+/* RCC_IWDGC2FZSETR register fields */
+#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2FZCLRR register fields */
+#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0)
+#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1)
+
+/* RCC_IWDGC2CFGSETR register fields */
+#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18)
+
+/* RCC_IWDGC2CFGCLRR register fields */
+#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0)
+#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2)
+#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18)
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL BIT(0)
+#define RCC_MCO1CFGR_MCO1ON BIT(8)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL BIT(0)
+#define RCC_MCO2CFGR_MCO2ON BIT(8)
+
+/* RCC_MCOxCFGR register fields */
+#define RCC_MCOxCFGR_MCOxSEL BIT(0)
+#define RCC_MCOxCFGR_MCOxON BIT(8)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION BIT(0)
+#define RCC_OCENSETR_HSIKERON BIT(1)
+#define RCC_OCENSETR_MSION BIT(2)
+#define RCC_OCENSETR_MSIKERON BIT(3)
+#define RCC_OCENSETR_HSEDIV2ON BIT(5)
+#define RCC_OCENSETR_HSEDIV2BYP BIT(6)
+#define RCC_OCENSETR_HSEDIGBYP BIT(7)
+#define RCC_OCENSETR_HSEON BIT(8)
+#define RCC_OCENSETR_HSEKERON BIT(9)
+#define RCC_OCENSETR_HSEBYP BIT(10)
+#define RCC_OCENSETR_HSECSSON BIT(11)
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION BIT(0)
+#define RCC_OCENCLRR_HSIKERON BIT(1)
+#define RCC_OCENCLRR_MSION BIT(2)
+#define RCC_OCENCLRR_MSIKERON BIT(3)
+#define RCC_OCENCLRR_HSEDIV2ON BIT(5)
+#define RCC_OCENCLRR_HSEDIV2BYP BIT(6)
+#define RCC_OCENCLRR_HSEDIGBYP BIT(7)
+#define RCC_OCENCLRR_HSEON BIT(8)
+#define RCC_OCENCLRR_HSEKERON BIT(9)
+#define RCC_OCENCLRR_HSEBYP BIT(10)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY BIT(0)
+#define RCC_OCRDYR_MSIRDY BIT(2)
+#define RCC_OCRDYR_HSERDY BIT(8)
+#define RCC_OCRDYR_CKREST BIT(25)
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT 8
+#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT 16
+
+/* RCC_MSICFGR register fields */
+#define RCC_MSICFGR_MSITRIM_MASK GENMASK_32(12, 8)
+#define RCC_MSICFGR_MSITRIM_SHIFT 8
+#define RCC_MSICFGR_MSICAL_MASK GENMASK_32(23, 16)
+#define RCC_MSICFGR_MSICAL_SHIFT 16
+
+/* RCC_LSICR register fields */
+#define RCC_LSICR_LSION BIT(0)
+#define RCC_LSICR_LSIRDY BIT(1)
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT 0
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT 0
+#define RCC_APB1DIVR_APB1DIVRDY BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT 0
+#define RCC_APB2DIVR_APB2DIVRDY BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT 0
+#define RCC_APB3DIVR_APB3DIVRDY BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT 0
+#define RCC_APB4DIVR_APB4DIVRDY BIT(31)
+
+/* RCC_APB5DIVR register fields */
+#define RCC_APB5DIVR_APB5DIV_MASK GENMASK_32(2, 0)
+#define RCC_APB5DIVR_APB5DIV_SHIFT 0
+#define RCC_APB5DIVR_APB5DIVRDY BIT(31)
+
+/* RCC_APBDBGDIVR register fields */
+#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0
+#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31)
+
+/* RCC_APBxDIVR register fields */
+#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0)
+#define RCC_APBxDIVR_APBxDIV_SHIFT 0
+#define RCC_APBxDIVR_APBxDIVRDY BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31)
+
+/* RCC_TIMGxPRER register fields */
+#define RCC_TIMGxPRER_TIMGxPRE BIT(0)
+#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31)
+
+/* RCC_LSMCUDIVR register fields */
+#define RCC_LSMCUDIVR_LSMCUDIV BIT(0)
+#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31)
+
+/* RCC_DDRCPCFGR register fields */
+#define RCC_DDRCPCFGR_DDRCPRST BIT(0)
+#define RCC_DDRCPCFGR_DDRCPEN BIT(1)
+#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2)
+
+/* RCC_DDRCAPBCFGR register fields */
+#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0)
+#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1)
+#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCAPBCFGR register fields */
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2)
+
+/* RCC_DDRPHYCCFGR register fields */
+#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1)
+
+/* RCC_DDRCFGR register fields */
+#define RCC_DDRCFGR_DDRCFGRST BIT(0)
+#define RCC_DDRCFGR_DDRCFGEN BIT(1)
+#define RCC_DDRCFGR_DDRCFGLPEN BIT(2)
+
+/* RCC_DDRITFCFGR register fields */
+#define RCC_DDRITFCFGR_DDRRST BIT(0)
+#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4)
+#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4
+#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5)
+#define RCC_DDRITFCFGR_DDRSHR BIT(8)
+#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16)
+
+/* RCC_SYSRAMCFGR register fields */
+#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1)
+#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2)
+
+/* RCC_SRAM1CFGR register fields */
+#define RCC_SRAM1CFGR_SRAM1EN BIT(1)
+#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2)
+
+/* RCC_RETRAMCFGR register fields */
+#define RCC_RETRAMCFGR_RETRAMEN BIT(1)
+#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2)
+
+/* RCC_BKPSRAMCFGR register fields */
+#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1)
+#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2)
+
+/* RCC_OSPI1CFGR register fields */
+#define RCC_OSPI1CFGR_OSPI1RST BIT(0)
+#define RCC_OSPI1CFGR_OSPI1EN BIT(1)
+#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2)
+#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8)
+#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16)
+
+/* RCC_OSPIxCFGR register fields */
+#define RCC_OSPIxCFGR_OSPIxRST BIT(0)
+#define RCC_OSPIxCFGR_OSPIxEN BIT(1)
+#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2)
+#define RCC_OSPIxCFGR_OTFDECxRST BIT(8)
+#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16)
+
+/* RCC_FMCCFGR register fields */
+#define RCC_FMCCFGR_FMCRST BIT(0)
+#define RCC_FMCCFGR_FMCEN BIT(1)
+#define RCC_FMCCFGR_FMCLPEN BIT(2)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_DBGEN BIT(8)
+#define RCC_DBGCFGR_TRACEEN BIT(9)
+#define RCC_DBGCFGR_DBGMCUEN BIT(10)
+#define RCC_DBGCFGR_DBGRST BIT(12)
+
+/* RCC_STMCFGR register fields */
+#define RCC_STMCFGR_STMEN BIT(1)
+#define RCC_STMCFGR_STMLPEN BIT(2)
+
+/* RCC_ETRCFGR register fields */
+#define RCC_ETRCFGR_ETREN BIT(1)
+#define RCC_ETRCFGR_ETRLPEN BIT(2)
+
+/* RCC_GPIOACFGR register fields */
+#define RCC_GPIOACFGR_GPIOARST BIT(0)
+#define RCC_GPIOACFGR_GPIOAEN BIT(1)
+#define RCC_GPIOACFGR_GPIOALPEN BIT(2)
+
+/* RCC_GPIOBCFGR register fields */
+#define RCC_GPIOBCFGR_GPIOBRST BIT(0)
+#define RCC_GPIOBCFGR_GPIOBEN BIT(1)
+#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2)
+
+/* RCC_GPIOCCFGR register fields */
+#define RCC_GPIOCCFGR_GPIOCRST BIT(0)
+#define RCC_GPIOCCFGR_GPIOCEN BIT(1)
+#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2)
+
+/* RCC_GPIODCFGR register fields */
+#define RCC_GPIODCFGR_GPIODRST BIT(0)
+#define RCC_GPIODCFGR_GPIODEN BIT(1)
+#define RCC_GPIODCFGR_GPIODLPEN BIT(2)
+
+/* RCC_GPIOECFGR register fields */
+#define RCC_GPIOECFGR_GPIOERST BIT(0)
+#define RCC_GPIOECFGR_GPIOEEN BIT(1)
+#define RCC_GPIOECFGR_GPIOELPEN BIT(2)
+
+/* RCC_GPIOFCFGR register fields */
+#define RCC_GPIOFCFGR_GPIOFRST BIT(0)
+#define RCC_GPIOFCFGR_GPIOFEN BIT(1)
+#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2)
+
+/* RCC_GPIOGCFGR register fields */
+#define RCC_GPIOGCFGR_GPIOGRST BIT(0)
+#define RCC_GPIOGCFGR_GPIOGEN BIT(1)
+#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2)
+
+/* RCC_GPIOHCFGR register fields */
+#define RCC_GPIOHCFGR_GPIOHRST BIT(0)
+#define RCC_GPIOHCFGR_GPIOHEN BIT(1)
+#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2)
+
+/* RCC_GPIOICFGR register fields */
+#define RCC_GPIOICFGR_GPIOIRST BIT(0)
+#define RCC_GPIOICFGR_GPIOIEN BIT(1)
+#define RCC_GPIOICFGR_GPIOILPEN BIT(2)
+
+/* RCC_GPIOZCFGR register fields */
+#define RCC_GPIOZCFGR_GPIOZRST BIT(0)
+#define RCC_GPIOZCFGR_GPIOZEN BIT(1)
+#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2)
+
+/* RCC_GPIOxCFGR register fields */
+#define RCC_GPIOxCFGR_GPIOxRST BIT(0)
+#define RCC_GPIOxCFGR_GPIOxEN BIT(1)
+#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2)
+#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3)
+
+/* RCC_HPDMA1CFGR register fields */
+#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0)
+#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1)
+#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2)
+
+/* RCC_HPDMA2CFGR register fields */
+#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0)
+#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1)
+#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2)
+
+/* RCC_HPDMA3CFGR register fields */
+#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0)
+#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1)
+#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2)
+
+/* RCC_HPDMAxCFGR register fields */
+#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0)
+#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1)
+#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2)
+
+/* RCC_IPCC1CFGR register fields */
+#define RCC_IPCC1CFGR_IPCC1RST BIT(0)
+#define RCC_IPCC1CFGR_IPCC1EN BIT(1)
+#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2)
+
+/* RCC_RTCCFGR register fields */
+#define RCC_RTCCFGR_RTCEN BIT(1)
+#define RCC_RTCCFGR_RTCLPEN BIT(2)
+
+/* RCC_SYSCPU1CFGR register fields */
+#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1)
+#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2)
+
+/* RCC_BSECCFGR register fields */
+#define RCC_BSECCFGR_BSECEN BIT(1)
+#define RCC_BSECCFGR_BSECLPEN BIT(2)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_SSMODRST BIT(0)
+#define RCC_PLL2CFGR1_PLLEN BIT(8)
+#define RCC_PLL2CFGR1_PLLRDY BIT(24)
+#define RCC_PLL2CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL2CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL2CFGR3 register fields */
+#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL2CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL2CFGR3_DACEN BIT(25)
+#define RCC_PLL2CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL2CFGR4 register fields */
+#define RCC_PLL2CFGR4_DSMEN BIT(8)
+#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL2CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL2CFGR5 register fields */
+#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL2CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL2CFGR6 register fields */
+#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL2CFGR7 register fields */
+#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_HSIFMONCR register fields */
+#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0)
+#define RCC_HSIFMONCR_HSIREF_SHIFT 0
+#define RCC_HSIFMONCR_HSIMONEN BIT(15)
+#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16)
+#define RCC_HSIFMONCR_HSIDEV_SHIFT 16
+#define RCC_HSIFMONCR_HSIMONIE BIT(30)
+#define RCC_HSIFMONCR_HSIMONF BIT(31)
+
+/* RCC_HSIFVALR register fields */
+#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0)
+#define RCC_HSIFVALR_HSIVAL_SHIFT 0
+
+/* RCC_MSIFMONCR register fields */
+#define RCC_MSIFMONCR_MSIREF_MASK GENMASK_32(8, 0)
+#define RCC_MSIFMONCR_MSIREF_SHIFT 0
+#define RCC_MSIFMONCR_MSIMONEN BIT(15)
+#define RCC_MSIFMONCR_MSIDEV_MASK GENMASK_32(20, 16)
+#define RCC_MSIFMONCR_MSIDEV_SHIFT 16
+#define RCC_MSIFMONCR_MSIMONIE BIT(30)
+#define RCC_MSIFMONCR_MSIMONF BIT(31)
+
+/* RCC_MSIFVALR register fields */
+#define RCC_MSIFVALR_MSIVAL_MASK GENMASK_32(8, 0)
+#define RCC_MSIFVALR_MSIVAL_SHIFT 0
+
+/* RCC_TIM1CFGR register fields */
+#define RCC_TIM1CFGR_TIM1RST BIT(0)
+#define RCC_TIM1CFGR_TIM1EN BIT(1)
+#define RCC_TIM1CFGR_TIM1LPEN BIT(2)
+
+/* RCC_TIM2CFGR register fields */
+#define RCC_TIM2CFGR_TIM2RST BIT(0)
+#define RCC_TIM2CFGR_TIM2EN BIT(1)
+#define RCC_TIM2CFGR_TIM2LPEN BIT(2)
+
+/* RCC_TIM3CFGR register fields */
+#define RCC_TIM3CFGR_TIM3RST BIT(0)
+#define RCC_TIM3CFGR_TIM3EN BIT(1)
+#define RCC_TIM3CFGR_TIM3LPEN BIT(2)
+
+/* RCC_TIM4CFGR register fields */
+#define RCC_TIM4CFGR_TIM4RST BIT(0)
+#define RCC_TIM4CFGR_TIM4EN BIT(1)
+#define RCC_TIM4CFGR_TIM4LPEN BIT(2)
+
+/* RCC_TIM5CFGR register fields */
+#define RCC_TIM5CFGR_TIM5RST BIT(0)
+#define RCC_TIM5CFGR_TIM5EN BIT(1)
+#define RCC_TIM5CFGR_TIM5LPEN BIT(2)
+
+/* RCC_TIM6CFGR register fields */
+#define RCC_TIM6CFGR_TIM6RST BIT(0)
+#define RCC_TIM6CFGR_TIM6EN BIT(1)
+#define RCC_TIM6CFGR_TIM6LPEN BIT(2)
+
+/* RCC_TIM7CFGR register fields */
+#define RCC_TIM7CFGR_TIM7RST BIT(0)
+#define RCC_TIM7CFGR_TIM7EN BIT(1)
+#define RCC_TIM7CFGR_TIM7LPEN BIT(2)
+
+/* RCC_TIM8CFGR register fields */
+#define RCC_TIM8CFGR_TIM8RST BIT(0)
+#define RCC_TIM8CFGR_TIM8EN BIT(1)
+#define RCC_TIM8CFGR_TIM8LPEN BIT(2)
+
+/* RCC_TIM10CFGR register fields */
+#define RCC_TIM10CFGR_TIM10RST BIT(0)
+#define RCC_TIM10CFGR_TIM10EN BIT(1)
+#define RCC_TIM10CFGR_TIM10LPEN BIT(2)
+
+/* RCC_TIM11CFGR register fields */
+#define RCC_TIM11CFGR_TIM11RST BIT(0)
+#define RCC_TIM11CFGR_TIM11EN BIT(1)
+#define RCC_TIM11CFGR_TIM11LPEN BIT(2)
+
+/* RCC_TIM12CFGR register fields */
+#define RCC_TIM12CFGR_TIM12RST BIT(0)
+#define RCC_TIM12CFGR_TIM12EN BIT(1)
+#define RCC_TIM12CFGR_TIM12LPEN BIT(2)
+
+/* RCC_TIM13CFGR register fields */
+#define RCC_TIM13CFGR_TIM13RST BIT(0)
+#define RCC_TIM13CFGR_TIM13EN BIT(1)
+#define RCC_TIM13CFGR_TIM13LPEN BIT(2)
+
+/* RCC_TIM14CFGR register fields */
+#define RCC_TIM14CFGR_TIM14RST BIT(0)
+#define RCC_TIM14CFGR_TIM14EN BIT(1)
+#define RCC_TIM14CFGR_TIM14LPEN BIT(2)
+
+/* RCC_TIM15CFGR register fields */
+#define RCC_TIM15CFGR_TIM15RST BIT(0)
+#define RCC_TIM15CFGR_TIM15EN BIT(1)
+#define RCC_TIM15CFGR_TIM15LPEN BIT(2)
+
+/* RCC_TIM16CFGR register fields */
+#define RCC_TIM16CFGR_TIM16RST BIT(0)
+#define RCC_TIM16CFGR_TIM16EN BIT(1)
+#define RCC_TIM16CFGR_TIM16LPEN BIT(2)
+
+/* RCC_TIM17CFGR register fields */
+#define RCC_TIM17CFGR_TIM17RST BIT(0)
+#define RCC_TIM17CFGR_TIM17EN BIT(1)
+#define RCC_TIM17CFGR_TIM17LPEN BIT(2)
+
+/* RCC_LPTIM1CFGR register fields */
+#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0)
+#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1)
+#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2)
+
+/* RCC_LPTIM2CFGR register fields */
+#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0)
+#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1)
+#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2)
+
+/* RCC_LPTIM3CFGR register fields */
+#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0)
+#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1)
+#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2)
+
+/* RCC_LPTIM4CFGR register fields */
+#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0)
+#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1)
+#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2)
+
+/* RCC_LPTIM5CFGR register fields */
+#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0)
+#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1)
+#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2)
+
+/* RCC_LPTIMxCFGR register fields */
+#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0)
+#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1)
+#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2)
+#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3)
+
+/* RCC_SPI1CFGR register fields */
+#define RCC_SPI1CFGR_SPI1RST BIT(0)
+#define RCC_SPI1CFGR_SPI1EN BIT(1)
+#define RCC_SPI1CFGR_SPI1LPEN BIT(2)
+
+/* RCC_SPI2CFGR register fields */
+#define RCC_SPI2CFGR_SPI2RST BIT(0)
+#define RCC_SPI2CFGR_SPI2EN BIT(1)
+#define RCC_SPI2CFGR_SPI2LPEN BIT(2)
+
+/* RCC_SPI3CFGR register fields */
+#define RCC_SPI3CFGR_SPI3RST BIT(0)
+#define RCC_SPI3CFGR_SPI3EN BIT(1)
+#define RCC_SPI3CFGR_SPI3LPEN BIT(2)
+
+/* RCC_SPI4CFGR register fields */
+#define RCC_SPI4CFGR_SPI4RST BIT(0)
+#define RCC_SPI4CFGR_SPI4EN BIT(1)
+#define RCC_SPI4CFGR_SPI4LPEN BIT(2)
+
+/* RCC_SPI5CFGR register fields */
+#define RCC_SPI5CFGR_SPI5RST BIT(0)
+#define RCC_SPI5CFGR_SPI5EN BIT(1)
+#define RCC_SPI5CFGR_SPI5LPEN BIT(2)
+
+/* RCC_SPI6CFGR register fields */
+#define RCC_SPI6CFGR_SPI6RST BIT(0)
+#define RCC_SPI6CFGR_SPI6EN BIT(1)
+#define RCC_SPI6CFGR_SPI6LPEN BIT(2)
+
+/* RCC_SPIxCFGR register fields */
+#define RCC_SPIxCFGR_SPIxRST BIT(0)
+#define RCC_SPIxCFGR_SPIxEN BIT(1)
+#define RCC_SPIxCFGR_SPIxLPEN BIT(2)
+#define RCC_SPIxCFGR_SPIxAMEN BIT(3)
+
+/* RCC_SPDIFRXCFGR register fields */
+#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0)
+#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1)
+#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2)
+
+/* RCC_USART1CFGR register fields */
+#define RCC_USART1CFGR_USART1RST BIT(0)
+#define RCC_USART1CFGR_USART1EN BIT(1)
+#define RCC_USART1CFGR_USART1LPEN BIT(2)
+
+/* RCC_USART2CFGR register fields */
+#define RCC_USART2CFGR_USART2RST BIT(0)
+#define RCC_USART2CFGR_USART2EN BIT(1)
+#define RCC_USART2CFGR_USART2LPEN BIT(2)
+
+/* RCC_USART3CFGR register fields */
+#define RCC_USART3CFGR_USART3RST BIT(0)
+#define RCC_USART3CFGR_USART3EN BIT(1)
+#define RCC_USART3CFGR_USART3LPEN BIT(2)
+
+/* RCC_UART4CFGR register fields */
+#define RCC_UART4CFGR_UART4RST BIT(0)
+#define RCC_UART4CFGR_UART4EN BIT(1)
+#define RCC_UART4CFGR_UART4LPEN BIT(2)
+
+/* RCC_UART5CFGR register fields */
+#define RCC_UART5CFGR_UART5RST BIT(0)
+#define RCC_UART5CFGR_UART5EN BIT(1)
+#define RCC_UART5CFGR_UART5LPEN BIT(2)
+
+/* RCC_USART6CFGR register fields */
+#define RCC_USART6CFGR_USART6RST BIT(0)
+#define RCC_USART6CFGR_USART6EN BIT(1)
+#define RCC_USART6CFGR_USART6LPEN BIT(2)
+
+/* RCC_UART7CFGR register fields */
+#define RCC_UART7CFGR_UART7RST BIT(0)
+#define RCC_UART7CFGR_UART7EN BIT(1)
+#define RCC_UART7CFGR_UART7LPEN BIT(2)
+
+/* RCC_USARTxCFGR register fields */
+#define RCC_USARTxCFGR_USARTxRST BIT(0)
+#define RCC_USARTxCFGR_USARTxEN BIT(1)
+#define RCC_USARTxCFGR_USARTxLPEN BIT(2)
+
+/* RCC_UARTxCFGR register fields */
+#define RCC_UARTxCFGR_UARTxRST BIT(0)
+#define RCC_UARTxCFGR_UARTxEN BIT(1)
+#define RCC_UARTxCFGR_UARTxLPEN BIT(2)
+
+/* RCC_LPUART1CFGR register fields */
+#define RCC_LPUART1CFGR_LPUART1RST BIT(0)
+#define RCC_LPUART1CFGR_LPUART1EN BIT(1)
+#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2)
+
+/* RCC_I2C1CFGR register fields */
+#define RCC_I2C1CFGR_I2C1RST BIT(0)
+#define RCC_I2C1CFGR_I2C1EN BIT(1)
+#define RCC_I2C1CFGR_I2C1LPEN BIT(2)
+
+/* RCC_I2C2CFGR register fields */
+#define RCC_I2C2CFGR_I2C2RST BIT(0)
+#define RCC_I2C2CFGR_I2C2EN BIT(1)
+#define RCC_I2C2CFGR_I2C2LPEN BIT(2)
+
+/* RCC_I2C3CFGR register fields */
+#define RCC_I2C3CFGR_I2C3RST BIT(0)
+#define RCC_I2C3CFGR_I2C3EN BIT(1)
+#define RCC_I2C3CFGR_I2C3LPEN BIT(2)
+
+/* RCC_I2CxCFGR register fields */
+#define RCC_I2CxCFGR_I2CxRST BIT(0)
+#define RCC_I2CxCFGR_I2CxEN BIT(1)
+#define RCC_I2CxCFGR_I2CxLPEN BIT(2)
+#define RCC_I2CxCFGR_I2CxAMEN BIT(3)
+
+/* RCC_SAI1CFGR register fields */
+#define RCC_SAI1CFGR_SAI1RST BIT(0)
+#define RCC_SAI1CFGR_SAI1EN BIT(1)
+#define RCC_SAI1CFGR_SAI1LPEN BIT(2)
+
+/* RCC_SAI2CFGR register fields */
+#define RCC_SAI2CFGR_SAI2RST BIT(0)
+#define RCC_SAI2CFGR_SAI2EN BIT(1)
+#define RCC_SAI2CFGR_SAI2LPEN BIT(2)
+
+/* RCC_SAI3CFGR register fields */
+#define RCC_SAI3CFGR_SAI3RST BIT(0)
+#define RCC_SAI3CFGR_SAI3EN BIT(1)
+#define RCC_SAI3CFGR_SAI3LPEN BIT(2)
+
+/* RCC_SAI4CFGR register fields */
+#define RCC_SAI4CFGR_SAI4RST BIT(0)
+#define RCC_SAI4CFGR_SAI4EN BIT(1)
+#define RCC_SAI4CFGR_SAI4LPEN BIT(2)
+
+/* RCC_SAIxCFGR register fields */
+#define RCC_SAIxCFGR_SAIxRST BIT(0)
+#define RCC_SAIxCFGR_SAIxEN BIT(1)
+#define RCC_SAIxCFGR_SAIxLPEN BIT(2)
+
+/* RCC_MDF1CFGR register fields */
+#define RCC_MDF1CFGR_MDF1RST BIT(0)
+#define RCC_MDF1CFGR_MDF1EN BIT(1)
+#define RCC_MDF1CFGR_MDF1LPEN BIT(2)
+
+/* RCC_FDCANCFGR register fields */
+#define RCC_FDCANCFGR_FDCANRST BIT(0)
+#define RCC_FDCANCFGR_FDCANEN BIT(1)
+#define RCC_FDCANCFGR_FDCANLPEN BIT(2)
+
+/* RCC_HDPCFGR register fields */
+#define RCC_HDPCFGR_HDPRST BIT(0)
+#define RCC_HDPCFGR_HDPEN BIT(1)
+
+/* RCC_ADC1CFGR register fields */
+#define RCC_ADC1CFGR_ADC1RST BIT(0)
+#define RCC_ADC1CFGR_ADC1EN BIT(1)
+#define RCC_ADC1CFGR_ADC1LPEN BIT(2)
+#define RCC_ADC1CFGR_ADC1KERSEL BIT(12)
+
+/* RCC_ADC2CFGR register fields */
+#define RCC_ADC2CFGR_ADC2RST BIT(0)
+#define RCC_ADC2CFGR_ADC2EN BIT(1)
+#define RCC_ADC2CFGR_ADC2LPEN BIT(2)
+#define RCC_ADC2CFGR_ADC2KERSEL_MASK GENMASK_32(13, 12)
+#define RCC_ADC2CFGR_ADC2KERSEL_SHIFT 12
+
+/* RCC_ETH1CFGR register fields */
+#define RCC_ETH1CFGR_ETH1RST BIT(0)
+#define RCC_ETH1CFGR_ETH1MACEN BIT(1)
+#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2)
+#define RCC_ETH1CFGR_ETH1STPEN BIT(4)
+#define RCC_ETH1CFGR_ETH1EN BIT(5)
+#define RCC_ETH1CFGR_ETH1LPEN BIT(6)
+#define RCC_ETH1CFGR_ETH1TXEN BIT(8)
+#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9)
+#define RCC_ETH1CFGR_ETH1RXEN BIT(10)
+#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11)
+
+/* RCC_ETH2CFGR register fields */
+#define RCC_ETH2CFGR_ETH2RST BIT(0)
+#define RCC_ETH2CFGR_ETH2MACEN BIT(1)
+#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2)
+#define RCC_ETH2CFGR_ETH2STPEN BIT(4)
+#define RCC_ETH2CFGR_ETH2EN BIT(5)
+#define RCC_ETH2CFGR_ETH2LPEN BIT(6)
+#define RCC_ETH2CFGR_ETH2TXEN BIT(8)
+#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9)
+#define RCC_ETH2CFGR_ETH2RXEN BIT(10)
+#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11)
+
+/* RCC_ETHxCFGR register fields */
+#define RCC_ETHxCFGR_ETHxRST BIT(0)
+#define RCC_ETHxCFGR_ETHxMACEN BIT(1)
+#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2)
+#define RCC_ETHxCFGR_ETHxSTPEN BIT(4)
+#define RCC_ETHxCFGR_ETHxEN BIT(5)
+#define RCC_ETHxCFGR_ETHxLPEN BIT(6)
+#define RCC_ETHxCFGR_ETHxTXEN BIT(8)
+#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9)
+#define RCC_ETHxCFGR_ETHxRXEN BIT(10)
+#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11)
+
+/* RCC_USBHCFGR register fields */
+#define RCC_USBHCFGR_USBHRST BIT(0)
+#define RCC_USBHCFGR_USBHEN BIT(1)
+#define RCC_USBHCFGR_USBHLPEN BIT(2)
+#define RCC_USBHCFGR_USBHSTPEN BIT(4)
+
+/* RCC_USB2PHY1CFGR register fields */
+#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_OTGCFGR register fields */
+#define RCC_OTGCFGR_OTGRST BIT(0)
+#define RCC_OTGCFGR_OTGEN BIT(1)
+#define RCC_OTGCFGR_OTGLPEN BIT(2)
+
+/* RCC_USB2PHY2CFGR register fields */
+#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0)
+#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1)
+#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2)
+#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4)
+#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15)
+
+/* RCC_USB2PHYxCFGR register fields */
+#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0)
+#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1)
+#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2)
+#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4)
+#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15)
+
+/* RCC_STGENCFGR register fields */
+#define RCC_STGENCFGR_STGENEN BIT(1)
+#define RCC_STGENCFGR_STGENLPEN BIT(2)
+#define RCC_STGENCFGR_STGENSTPEN BIT(4)
+
+/* RCC_SDMMC1CFGR register fields */
+#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_SDMMC2CFGR register fields */
+#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0)
+#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1)
+#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2)
+#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16)
+
+/* RCC_SDMMC3CFGR register fields */
+#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0)
+#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1)
+#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2)
+#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16)
+
+/* RCC_SDMMCxCFGR register fields */
+#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0)
+#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1)
+#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2)
+#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16)
+
+/* RCC_LTDCCFGR register fields */
+#define RCC_LTDCCFGR_LTDCRST BIT(0)
+#define RCC_LTDCCFGR_LTDCEN BIT(1)
+#define RCC_LTDCCFGR_LTDCLPEN BIT(2)
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSIRST BIT(0)
+#define RCC_CSICFGR_CSIEN BIT(1)
+#define RCC_CSICFGR_CSILPEN BIT(2)
+
+/* RCC_DCMIPPCFGR register fields */
+#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0)
+#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1)
+#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2)
+
+/* RCC_DCMIPSSICFGR register fields */
+#define RCC_DCMIPSSICFGR_DCMIPSSIRST BIT(0)
+#define RCC_DCMIPSSICFGR_DCMIPSSIEN BIT(1)
+#define RCC_DCMIPSSICFGR_DCMIPSSILPEN BIT(2)
+
+/* RCC_RNG1CFGR register fields */
+#define RCC_RNG1CFGR_RNG1RST BIT(0)
+#define RCC_RNG1CFGR_RNG1EN BIT(1)
+#define RCC_RNG1CFGR_RNG1LPEN BIT(2)
+
+/* RCC_RNG2CFGR register fields */
+#define RCC_RNG2CFGR_RNG2RST BIT(0)
+#define RCC_RNG2CFGR_RNG2EN BIT(1)
+#define RCC_RNG2CFGR_RNG2LPEN BIT(2)
+
+/* RCC_PKACFGR register fields */
+#define RCC_PKACFGR_PKARST BIT(0)
+#define RCC_PKACFGR_PKAEN BIT(1)
+#define RCC_PKACFGR_PKALPEN BIT(2)
+
+/* RCC_SAESCFGR register fields */
+#define RCC_SAESCFGR_SAESRST BIT(0)
+#define RCC_SAESCFGR_SAESEN BIT(1)
+#define RCC_SAESCFGR_SAESLPEN BIT(2)
+
+/* RCC_HASH1CFGR register fields */
+#define RCC_HASH1CFGR_HASH1RST BIT(0)
+#define RCC_HASH1CFGR_HASH1EN BIT(1)
+#define RCC_HASH1CFGR_HASH1LPEN BIT(2)
+
+/* RCC_HASH2CFGR register fields */
+#define RCC_HASH2CFGR_HASH2RST BIT(0)
+#define RCC_HASH2CFGR_HASH2EN BIT(1)
+#define RCC_HASH2CFGR_HASH2LPEN BIT(2)
+
+/* RCC_CRYP1CFGR register fields */
+#define RCC_CRYP1CFGR_CRYP1RST BIT(0)
+#define RCC_CRYP1CFGR_CRYP1EN BIT(1)
+#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2)
+
+/* RCC_CRYP2CFGR register fields */
+#define RCC_CRYP2CFGR_CRYP2RST BIT(0)
+#define RCC_CRYP2CFGR_CRYP2EN BIT(1)
+#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2)
+
+/* RCC_CRYPxCFGR register fields */
+#define RCC_CRYPxCFGR_CRYPxRST BIT(0)
+#define RCC_CRYPxCFGR_CRYPxEN BIT(1)
+#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2)
+
+/* RCC_IWDG1CFGR register fields */
+#define RCC_IWDG1CFGR_IWDG1EN BIT(1)
+#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2)
+
+/* RCC_IWDG2CFGR register fields */
+#define RCC_IWDG2CFGR_IWDG2EN BIT(1)
+#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2)
+
+/* RCC_IWDG3CFGR register fields */
+#define RCC_IWDG3CFGR_IWDG3EN BIT(1)
+#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2)
+
+/* RCC_IWDG4CFGR register fields */
+#define RCC_IWDG4CFGR_IWDG4EN BIT(1)
+#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2)
+
+/* RCC_IWDGxCFGR register fields */
+#define RCC_IWDGxCFGR_IWDGxEN BIT(1)
+#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2)
+
+/* RCC_WWDG1CFGR register fields */
+#define RCC_WWDG1CFGR_WWDG1RST BIT(0)
+#define RCC_WWDG1CFGR_WWDG1EN BIT(1)
+#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2)
+
+/* RCC_VREFCFGR register fields */
+#define RCC_VREFCFGR_VREFRST BIT(0)
+#define RCC_VREFCFGR_VREFEN BIT(1)
+#define RCC_VREFCFGR_VREFLPEN BIT(2)
+
+/* RCC_DTSCFGR register fields */
+#define RCC_DTSCFGR_DTSRST BIT(0)
+#define RCC_DTSCFGR_DTSEN BIT(1)
+#define RCC_DTSCFGR_DTSLPEN BIT(2)
+#define RCC_DTSCFGR_DTSKERSEL_MASK GENMASK_32(13, 12)
+#define RCC_DTSCFGR_DTSKERSEL_SHIFT 12
+
+/* RCC_CRCCFGR register fields */
+#define RCC_CRCCFGR_CRCRST BIT(0)
+#define RCC_CRCCFGR_CRCEN BIT(1)
+#define RCC_CRCCFGR_CRCLPEN BIT(2)
+
+/* RCC_SERCCFGR register fields */
+#define RCC_SERCCFGR_SERCRST BIT(0)
+#define RCC_SERCCFGR_SERCEN BIT(1)
+#define RCC_SERCCFGR_SERCLPEN BIT(2)
+
+/* RCC_DDRPERFMCFGR register fields */
+#define RCC_DDRPERFMCFGR_DDRPERFMRST BIT(0)
+#define RCC_DDRPERFMCFGR_DDRPERFMEN BIT(1)
+#define RCC_DDRPERFMCFGR_DDRPERFMLPEN BIT(2)
+
+/* RCC_I3C1CFGR register fields */
+#define RCC_I3C1CFGR_I3C1RST BIT(0)
+#define RCC_I3C1CFGR_I3C1EN BIT(1)
+#define RCC_I3C1CFGR_I3C1LPEN BIT(2)
+
+/* RCC_I3C2CFGR register fields */
+#define RCC_I3C2CFGR_I3C2RST BIT(0)
+#define RCC_I3C2CFGR_I3C2EN BIT(1)
+#define RCC_I3C2CFGR_I3C2LPEN BIT(2)
+
+/* RCC_I3C3CFGR register fields */
+#define RCC_I3C3CFGR_I3C3RST BIT(0)
+#define RCC_I3C3CFGR_I3C3EN BIT(1)
+#define RCC_I3C3CFGR_I3C3LPEN BIT(2)
+
+/* RCC_I3CxCFGR register fields */
+#define RCC_I3CxCFGR_I3CxRST BIT(0)
+#define RCC_I3CxCFGR_I3CxEN BIT(1)
+#define RCC_I3CxCFGR_I3CxLPEN BIT(2)
+#define RCC_I3CxCFGR_I3CxAMEN BIT(3)
+
+/* RCC_MUXSELCFGR register fields */
+#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(2, 0)
+#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0
+#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(6, 4)
+#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4
+#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(10, 8)
+#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8
+#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(14, 12)
+#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12
+#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(18, 16)
+#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16
+#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20)
+#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20
+#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24)
+#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24
+#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28)
+#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28
+
+/* RCC_XBAR0CFGR register fields */
+#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0
+#define RCC_XBAR0CFGR_XBAR0EN BIT(6)
+#define RCC_XBAR0CFGR_XBAR0STS BIT(7)
+
+/* RCC_XBAR1CFGR register fields */
+#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0
+#define RCC_XBAR1CFGR_XBAR1EN BIT(6)
+#define RCC_XBAR1CFGR_XBAR1STS BIT(7)
+
+/* RCC_XBAR2CFGR register fields */
+#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0
+#define RCC_XBAR2CFGR_XBAR2EN BIT(6)
+#define RCC_XBAR2CFGR_XBAR2STS BIT(7)
+
+/* RCC_XBAR3CFGR register fields */
+#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0
+#define RCC_XBAR3CFGR_XBAR3EN BIT(6)
+#define RCC_XBAR3CFGR_XBAR3STS BIT(7)
+
+/* RCC_XBAR4CFGR register fields */
+#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0
+#define RCC_XBAR4CFGR_XBAR4EN BIT(6)
+#define RCC_XBAR4CFGR_XBAR4STS BIT(7)
+
+/* RCC_XBAR5CFGR register fields */
+#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0
+#define RCC_XBAR5CFGR_XBAR5EN BIT(6)
+#define RCC_XBAR5CFGR_XBAR5STS BIT(7)
+
+/* RCC_XBAR6CFGR register fields */
+#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0
+#define RCC_XBAR6CFGR_XBAR6EN BIT(6)
+#define RCC_XBAR6CFGR_XBAR6STS BIT(7)
+
+/* RCC_XBAR7CFGR register fields */
+#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0
+#define RCC_XBAR7CFGR_XBAR7EN BIT(6)
+#define RCC_XBAR7CFGR_XBAR7STS BIT(7)
+
+/* RCC_XBAR8CFGR register fields */
+#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0
+#define RCC_XBAR8CFGR_XBAR8EN BIT(6)
+#define RCC_XBAR8CFGR_XBAR8STS BIT(7)
+
+/* RCC_XBAR9CFGR register fields */
+#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0
+#define RCC_XBAR9CFGR_XBAR9EN BIT(6)
+#define RCC_XBAR9CFGR_XBAR9STS BIT(7)
+
+/* RCC_XBAR10CFGR register fields */
+#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0
+#define RCC_XBAR10CFGR_XBAR10EN BIT(6)
+#define RCC_XBAR10CFGR_XBAR10STS BIT(7)
+
+/* RCC_XBAR11CFGR register fields */
+#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0
+#define RCC_XBAR11CFGR_XBAR11EN BIT(6)
+#define RCC_XBAR11CFGR_XBAR11STS BIT(7)
+
+/* RCC_XBAR12CFGR register fields */
+#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0
+#define RCC_XBAR12CFGR_XBAR12EN BIT(6)
+#define RCC_XBAR12CFGR_XBAR12STS BIT(7)
+
+/* RCC_XBAR13CFGR register fields */
+#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0
+#define RCC_XBAR13CFGR_XBAR13EN BIT(6)
+#define RCC_XBAR13CFGR_XBAR13STS BIT(7)
+
+/* RCC_XBAR14CFGR register fields */
+#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0
+#define RCC_XBAR14CFGR_XBAR14EN BIT(6)
+#define RCC_XBAR14CFGR_XBAR14STS BIT(7)
+
+/* RCC_XBAR15CFGR register fields */
+#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0
+#define RCC_XBAR15CFGR_XBAR15EN BIT(6)
+#define RCC_XBAR15CFGR_XBAR15STS BIT(7)
+
+/* RCC_XBAR16CFGR register fields */
+#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0
+#define RCC_XBAR16CFGR_XBAR16EN BIT(6)
+#define RCC_XBAR16CFGR_XBAR16STS BIT(7)
+
+/* RCC_XBAR17CFGR register fields */
+#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0
+#define RCC_XBAR17CFGR_XBAR17EN BIT(6)
+#define RCC_XBAR17CFGR_XBAR17STS BIT(7)
+
+/* RCC_XBAR18CFGR register fields */
+#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0
+#define RCC_XBAR18CFGR_XBAR18EN BIT(6)
+#define RCC_XBAR18CFGR_XBAR18STS BIT(7)
+
+/* RCC_XBAR19CFGR register fields */
+#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0
+#define RCC_XBAR19CFGR_XBAR19EN BIT(6)
+#define RCC_XBAR19CFGR_XBAR19STS BIT(7)
+
+/* RCC_XBAR20CFGR register fields */
+#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0
+#define RCC_XBAR20CFGR_XBAR20EN BIT(6)
+#define RCC_XBAR20CFGR_XBAR20STS BIT(7)
+
+/* RCC_XBAR21CFGR register fields */
+#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0
+#define RCC_XBAR21CFGR_XBAR21EN BIT(6)
+#define RCC_XBAR21CFGR_XBAR21STS BIT(7)
+
+/* RCC_XBAR22CFGR register fields */
+#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0
+#define RCC_XBAR22CFGR_XBAR22EN BIT(6)
+#define RCC_XBAR22CFGR_XBAR22STS BIT(7)
+
+/* RCC_XBAR23CFGR register fields */
+#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0
+#define RCC_XBAR23CFGR_XBAR23EN BIT(6)
+#define RCC_XBAR23CFGR_XBAR23STS BIT(7)
+
+/* RCC_XBAR24CFGR register fields */
+#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0
+#define RCC_XBAR24CFGR_XBAR24EN BIT(6)
+#define RCC_XBAR24CFGR_XBAR24STS BIT(7)
+
+/* RCC_XBAR25CFGR register fields */
+#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0
+#define RCC_XBAR25CFGR_XBAR25EN BIT(6)
+#define RCC_XBAR25CFGR_XBAR25STS BIT(7)
+
+/* RCC_XBAR26CFGR register fields */
+#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0
+#define RCC_XBAR26CFGR_XBAR26EN BIT(6)
+#define RCC_XBAR26CFGR_XBAR26STS BIT(7)
+
+/* RCC_XBAR27CFGR register fields */
+#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0
+#define RCC_XBAR27CFGR_XBAR27EN BIT(6)
+#define RCC_XBAR27CFGR_XBAR27STS BIT(7)
+
+/* RCC_XBAR28CFGR register fields */
+#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0
+#define RCC_XBAR28CFGR_XBAR28EN BIT(6)
+#define RCC_XBAR28CFGR_XBAR28STS BIT(7)
+
+/* RCC_XBAR29CFGR register fields */
+#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0
+#define RCC_XBAR29CFGR_XBAR29EN BIT(6)
+#define RCC_XBAR29CFGR_XBAR29STS BIT(7)
+
+/* RCC_XBAR30CFGR register fields */
+#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0
+#define RCC_XBAR30CFGR_XBAR30EN BIT(6)
+#define RCC_XBAR30CFGR_XBAR30STS BIT(7)
+
+/* RCC_XBAR31CFGR register fields */
+#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0
+#define RCC_XBAR31CFGR_XBAR31EN BIT(6)
+#define RCC_XBAR31CFGR_XBAR31STS BIT(7)
+
+/* RCC_XBAR32CFGR register fields */
+#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0
+#define RCC_XBAR32CFGR_XBAR32EN BIT(6)
+#define RCC_XBAR32CFGR_XBAR32STS BIT(7)
+
+/* RCC_XBAR33CFGR register fields */
+#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0
+#define RCC_XBAR33CFGR_XBAR33EN BIT(6)
+#define RCC_XBAR33CFGR_XBAR33STS BIT(7)
+
+/* RCC_XBAR34CFGR register fields */
+#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0
+#define RCC_XBAR34CFGR_XBAR34EN BIT(6)
+#define RCC_XBAR34CFGR_XBAR34STS BIT(7)
+
+/* RCC_XBAR35CFGR register fields */
+#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0
+#define RCC_XBAR35CFGR_XBAR35EN BIT(6)
+#define RCC_XBAR35CFGR_XBAR35STS BIT(7)
+
+/* RCC_XBAR36CFGR register fields */
+#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0
+#define RCC_XBAR36CFGR_XBAR36EN BIT(6)
+#define RCC_XBAR36CFGR_XBAR36STS BIT(7)
+
+/* RCC_XBAR37CFGR register fields */
+#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0
+#define RCC_XBAR37CFGR_XBAR37EN BIT(6)
+#define RCC_XBAR37CFGR_XBAR37STS BIT(7)
+
+/* RCC_XBAR38CFGR register fields */
+#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0
+#define RCC_XBAR38CFGR_XBAR38EN BIT(6)
+#define RCC_XBAR38CFGR_XBAR38STS BIT(7)
+
+/* RCC_XBAR39CFGR register fields */
+#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0
+#define RCC_XBAR39CFGR_XBAR39EN BIT(6)
+#define RCC_XBAR39CFGR_XBAR39STS BIT(7)
+
+/* RCC_XBAR40CFGR register fields */
+#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0
+#define RCC_XBAR40CFGR_XBAR40EN BIT(6)
+#define RCC_XBAR40CFGR_XBAR40STS BIT(7)
+
+/* RCC_XBAR41CFGR register fields */
+#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0
+#define RCC_XBAR41CFGR_XBAR41EN BIT(6)
+#define RCC_XBAR41CFGR_XBAR41STS BIT(7)
+
+/* RCC_XBAR42CFGR register fields */
+#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0
+#define RCC_XBAR42CFGR_XBAR42EN BIT(6)
+#define RCC_XBAR42CFGR_XBAR42STS BIT(7)
+
+/* RCC_XBAR43CFGR register fields */
+#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0
+#define RCC_XBAR43CFGR_XBAR43EN BIT(6)
+#define RCC_XBAR43CFGR_XBAR43STS BIT(7)
+
+/* RCC_XBAR44CFGR register fields */
+#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0
+#define RCC_XBAR44CFGR_XBAR44EN BIT(6)
+#define RCC_XBAR44CFGR_XBAR44STS BIT(7)
+
+/* RCC_XBAR45CFGR register fields */
+#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0
+#define RCC_XBAR45CFGR_XBAR45EN BIT(6)
+#define RCC_XBAR45CFGR_XBAR45STS BIT(7)
+
+/* RCC_XBAR46CFGR register fields */
+#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0
+#define RCC_XBAR46CFGR_XBAR46EN BIT(6)
+#define RCC_XBAR46CFGR_XBAR46STS BIT(7)
+
+/* RCC_XBAR47CFGR register fields */
+#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0
+#define RCC_XBAR47CFGR_XBAR47EN BIT(6)
+#define RCC_XBAR47CFGR_XBAR47STS BIT(7)
+
+/* RCC_XBAR48CFGR register fields */
+#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0
+#define RCC_XBAR48CFGR_XBAR48EN BIT(6)
+#define RCC_XBAR48CFGR_XBAR48STS BIT(7)
+
+/* RCC_XBAR49CFGR register fields */
+#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0
+#define RCC_XBAR49CFGR_XBAR49EN BIT(6)
+#define RCC_XBAR49CFGR_XBAR49STS BIT(7)
+
+/* RCC_XBAR50CFGR register fields */
+#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0
+#define RCC_XBAR50CFGR_XBAR50EN BIT(6)
+#define RCC_XBAR50CFGR_XBAR50STS BIT(7)
+
+/* RCC_XBAR51CFGR register fields */
+#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0
+#define RCC_XBAR51CFGR_XBAR51EN BIT(6)
+#define RCC_XBAR51CFGR_XBAR51STS BIT(7)
+
+/* RCC_XBAR52CFGR register fields */
+#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0
+#define RCC_XBAR52CFGR_XBAR52EN BIT(6)
+#define RCC_XBAR52CFGR_XBAR52STS BIT(7)
+
+/* RCC_XBAR53CFGR register fields */
+#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0
+#define RCC_XBAR53CFGR_XBAR53EN BIT(6)
+#define RCC_XBAR53CFGR_XBAR53STS BIT(7)
+
+/* RCC_XBAR54CFGR register fields */
+#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0
+#define RCC_XBAR54CFGR_XBAR54EN BIT(6)
+#define RCC_XBAR54CFGR_XBAR54STS BIT(7)
+
+/* RCC_XBAR55CFGR register fields */
+#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0
+#define RCC_XBAR55CFGR_XBAR55EN BIT(6)
+#define RCC_XBAR55CFGR_XBAR55STS BIT(7)
+
+/* RCC_XBAR56CFGR register fields */
+#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0
+#define RCC_XBAR56CFGR_XBAR56EN BIT(6)
+#define RCC_XBAR56CFGR_XBAR56STS BIT(7)
+
+/* RCC_XBAR57CFGR register fields */
+#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0
+#define RCC_XBAR57CFGR_XBAR57EN BIT(6)
+#define RCC_XBAR57CFGR_XBAR57STS BIT(7)
+
+/* RCC_XBAR58CFGR register fields */
+#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0
+#define RCC_XBAR58CFGR_XBAR58EN BIT(6)
+#define RCC_XBAR58CFGR_XBAR58STS BIT(7)
+
+/* RCC_XBAR59CFGR register fields */
+#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0
+#define RCC_XBAR59CFGR_XBAR59EN BIT(6)
+#define RCC_XBAR59CFGR_XBAR59STS BIT(7)
+
+/* RCC_XBAR60CFGR register fields */
+#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0
+#define RCC_XBAR60CFGR_XBAR60EN BIT(6)
+#define RCC_XBAR60CFGR_XBAR60STS BIT(7)
+
+/* RCC_XBAR61CFGR register fields */
+#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0
+#define RCC_XBAR61CFGR_XBAR61EN BIT(6)
+#define RCC_XBAR61CFGR_XBAR61STS BIT(7)
+
+/* RCC_XBAR62CFGR register fields */
+#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0
+#define RCC_XBAR62CFGR_XBAR62EN BIT(6)
+#define RCC_XBAR62CFGR_XBAR62STS BIT(7)
+
+/* RCC_XBAR63CFGR register fields */
+#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0)
+#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0
+#define RCC_XBAR63CFGR_XBAR63EN BIT(6)
+#define RCC_XBAR63CFGR_XBAR63STS BIT(7)
+
+/* RCC_XBARxCFGR register fields */
+#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0)
+#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0
+#define RCC_XBARxCFGR_XBARxEN BIT(6)
+#define RCC_XBARxCFGR_XBARxSTS BIT(7)
+
+/* RCC_PREDIV0CFGR register fields */
+#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0
+
+/* RCC_PREDIV1CFGR register fields */
+#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0
+
+/* RCC_PREDIV2CFGR register fields */
+#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0
+
+/* RCC_PREDIV3CFGR register fields */
+#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0
+
+/* RCC_PREDIV4CFGR register fields */
+#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0
+
+/* RCC_PREDIV5CFGR register fields */
+#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0
+
+/* RCC_PREDIV6CFGR register fields */
+#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0
+
+/* RCC_PREDIV7CFGR register fields */
+#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0
+
+/* RCC_PREDIV8CFGR register fields */
+#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0
+
+/* RCC_PREDIV9CFGR register fields */
+#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0
+
+/* RCC_PREDIV10CFGR register fields */
+#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0
+
+/* RCC_PREDIV11CFGR register fields */
+#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0
+
+/* RCC_PREDIV12CFGR register fields */
+#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0
+
+/* RCC_PREDIV13CFGR register fields */
+#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0
+
+/* RCC_PREDIV14CFGR register fields */
+#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0
+
+/* RCC_PREDIV15CFGR register fields */
+#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0
+
+/* RCC_PREDIV16CFGR register fields */
+#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0
+
+/* RCC_PREDIV17CFGR register fields */
+#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0
+
+/* RCC_PREDIV18CFGR register fields */
+#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0
+
+/* RCC_PREDIV19CFGR register fields */
+#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0
+
+/* RCC_PREDIV20CFGR register fields */
+#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0
+
+/* RCC_PREDIV21CFGR register fields */
+#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0
+
+/* RCC_PREDIV22CFGR register fields */
+#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0
+
+/* RCC_PREDIV23CFGR register fields */
+#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0
+
+/* RCC_PREDIV24CFGR register fields */
+#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0
+
+/* RCC_PREDIV25CFGR register fields */
+#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0
+
+/* RCC_PREDIV26CFGR register fields */
+#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0
+
+/* RCC_PREDIV27CFGR register fields */
+#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0
+
+/* RCC_PREDIV28CFGR register fields */
+#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0
+
+/* RCC_PREDIV29CFGR register fields */
+#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0
+
+/* RCC_PREDIV30CFGR register fields */
+#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0
+
+/* RCC_PREDIV31CFGR register fields */
+#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0
+
+/* RCC_PREDIV32CFGR register fields */
+#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0
+
+/* RCC_PREDIV33CFGR register fields */
+#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0
+
+/* RCC_PREDIV34CFGR register fields */
+#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0
+
+/* RCC_PREDIV35CFGR register fields */
+#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0
+
+/* RCC_PREDIV36CFGR register fields */
+#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0
+
+/* RCC_PREDIV37CFGR register fields */
+#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0
+
+/* RCC_PREDIV38CFGR register fields */
+#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0
+
+/* RCC_PREDIV39CFGR register fields */
+#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0
+
+/* RCC_PREDIV40CFGR register fields */
+#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0
+
+/* RCC_PREDIV41CFGR register fields */
+#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0
+
+/* RCC_PREDIV42CFGR register fields */
+#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0
+
+/* RCC_PREDIV43CFGR register fields */
+#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0
+
+/* RCC_PREDIV44CFGR register fields */
+#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0
+
+/* RCC_PREDIV45CFGR register fields */
+#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0
+
+/* RCC_PREDIV46CFGR register fields */
+#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0
+
+/* RCC_PREDIV47CFGR register fields */
+#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0
+
+/* RCC_PREDIV48CFGR register fields */
+#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0
+
+/* RCC_PREDIV49CFGR register fields */
+#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0
+
+/* RCC_PREDIV50CFGR register fields */
+#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0
+
+/* RCC_PREDIV51CFGR register fields */
+#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0
+
+/* RCC_PREDIV52CFGR register fields */
+#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0
+
+/* RCC_PREDIV53CFGR register fields */
+#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0
+
+/* RCC_PREDIV54CFGR register fields */
+#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0
+
+/* RCC_PREDIV55CFGR register fields */
+#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0
+
+/* RCC_PREDIV56CFGR register fields */
+#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0
+
+/* RCC_PREDIV57CFGR register fields */
+#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0
+
+/* RCC_PREDIV58CFGR register fields */
+#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0
+
+/* RCC_PREDIV59CFGR register fields */
+#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0
+
+/* RCC_PREDIV60CFGR register fields */
+#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0
+
+/* RCC_PREDIV61CFGR register fields */
+#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0
+
+/* RCC_PREDIV62CFGR register fields */
+#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0
+
+/* RCC_PREDIV63CFGR register fields */
+#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0)
+#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0
+
+/* RCC_PREDIVxCFGR register fields */
+#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0)
+#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0
+
+/* RCC_FINDIV0CFGR register fields */
+#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0
+#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6)
+
+/* RCC_FINDIV1CFGR register fields */
+#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0
+#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6)
+
+/* RCC_FINDIV2CFGR register fields */
+#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0
+#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6)
+
+/* RCC_FINDIV3CFGR register fields */
+#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0
+#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6)
+
+/* RCC_FINDIV4CFGR register fields */
+#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0
+#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6)
+
+/* RCC_FINDIV5CFGR register fields */
+#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0
+#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6)
+
+/* RCC_FINDIV6CFGR register fields */
+#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0
+#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6)
+
+/* RCC_FINDIV7CFGR register fields */
+#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0
+#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6)
+
+/* RCC_FINDIV8CFGR register fields */
+#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0
+#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6)
+
+/* RCC_FINDIV9CFGR register fields */
+#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0
+#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6)
+
+/* RCC_FINDIV10CFGR register fields */
+#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0
+#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6)
+
+/* RCC_FINDIV11CFGR register fields */
+#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0
+#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6)
+
+/* RCC_FINDIV12CFGR register fields */
+#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0
+#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6)
+
+/* RCC_FINDIV13CFGR register fields */
+#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0
+#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6)
+
+/* RCC_FINDIV14CFGR register fields */
+#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0
+#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6)
+
+/* RCC_FINDIV15CFGR register fields */
+#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0
+#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6)
+
+/* RCC_FINDIV16CFGR register fields */
+#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0
+#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6)
+
+/* RCC_FINDIV17CFGR register fields */
+#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0
+#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6)
+
+/* RCC_FINDIV18CFGR register fields */
+#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0
+#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6)
+
+/* RCC_FINDIV19CFGR register fields */
+#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0
+#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6)
+
+/* RCC_FINDIV20CFGR register fields */
+#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0
+#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6)
+
+/* RCC_FINDIV21CFGR register fields */
+#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0
+#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6)
+
+/* RCC_FINDIV22CFGR register fields */
+#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0
+#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6)
+
+/* RCC_FINDIV23CFGR register fields */
+#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0
+#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6)
+
+/* RCC_FINDIV24CFGR register fields */
+#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0
+#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6)
+
+/* RCC_FINDIV25CFGR register fields */
+#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0
+#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6)
+
+/* RCC_FINDIV26CFGR register fields */
+#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0
+#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6)
+
+/* RCC_FINDIV27CFGR register fields */
+#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0
+#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6)
+
+/* RCC_FINDIV28CFGR register fields */
+#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0
+#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6)
+
+/* RCC_FINDIV29CFGR register fields */
+#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0
+#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6)
+
+/* RCC_FINDIV30CFGR register fields */
+#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0
+#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6)
+
+/* RCC_FINDIV31CFGR register fields */
+#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0
+#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6)
+
+/* RCC_FINDIV32CFGR register fields */
+#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0
+#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6)
+
+/* RCC_FINDIV33CFGR register fields */
+#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0
+#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6)
+
+/* RCC_FINDIV34CFGR register fields */
+#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0
+#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6)
+
+/* RCC_FINDIV35CFGR register fields */
+#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0
+#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6)
+
+/* RCC_FINDIV36CFGR register fields */
+#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0
+#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6)
+
+/* RCC_FINDIV37CFGR register fields */
+#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0
+#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6)
+
+/* RCC_FINDIV38CFGR register fields */
+#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0
+#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6)
+
+/* RCC_FINDIV39CFGR register fields */
+#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0
+#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6)
+
+/* RCC_FINDIV40CFGR register fields */
+#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0
+#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6)
+
+/* RCC_FINDIV41CFGR register fields */
+#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0
+#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6)
+
+/* RCC_FINDIV42CFGR register fields */
+#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0
+#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6)
+
+/* RCC_FINDIV43CFGR register fields */
+#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0
+#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6)
+
+/* RCC_FINDIV44CFGR register fields */
+#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0
+#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6)
+
+/* RCC_FINDIV45CFGR register fields */
+#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0
+#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6)
+
+/* RCC_FINDIV46CFGR register fields */
+#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0
+#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6)
+
+/* RCC_FINDIV47CFGR register fields */
+#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0
+#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6)
+
+/* RCC_FINDIV48CFGR register fields */
+#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0
+#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6)
+
+/* RCC_FINDIV49CFGR register fields */
+#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0
+#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6)
+
+/* RCC_FINDIV50CFGR register fields */
+#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0
+#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6)
+
+/* RCC_FINDIV51CFGR register fields */
+#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0
+#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6)
+
+/* RCC_FINDIV52CFGR register fields */
+#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0
+#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6)
+
+/* RCC_FINDIV53CFGR register fields */
+#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0
+#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6)
+
+/* RCC_FINDIV54CFGR register fields */
+#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0
+#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6)
+
+/* RCC_FINDIV55CFGR register fields */
+#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0
+#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6)
+
+/* RCC_FINDIV56CFGR register fields */
+#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0
+#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6)
+
+/* RCC_FINDIV57CFGR register fields */
+#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0
+#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6)
+
+/* RCC_FINDIV58CFGR register fields */
+#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0
+#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6)
+
+/* RCC_FINDIV59CFGR register fields */
+#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0
+#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6)
+
+/* RCC_FINDIV60CFGR register fields */
+#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0
+#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6)
+
+/* RCC_FINDIV61CFGR register fields */
+#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0
+#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6)
+
+/* RCC_FINDIV62CFGR register fields */
+#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0
+#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6)
+
+/* RCC_FINDIV63CFGR register fields */
+#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0)
+#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0
+#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6)
+
+/* RCC_FINDIVxCFGR register fields */
+#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0)
+#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0
+#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6)
+
+/* RCC_FCALCOBS0CFGR register fields */
+#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15)
+#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17)
+#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25)
+#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26)
+
+/* RCC_FCALCOBS1CFGR register fields */
+#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0)
+#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8)
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8
+#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16)
+#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22
+#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26)
+#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27)
+
+/* RCC_FCALCREFCFGR register fields */
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0)
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0
+
+/* RCC_FCALCCR1 register fields */
+#define RCC_FCALCCR1_FCALCRUN BIT(0)
+
+/* RCC_FCALCCR2 register fields */
+#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3)
+#define RCC_FCALCCR2_FCALCMD_SHIFT 3
+#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11)
+#define RCC_FCALCCR2_FCALCTWC_SHIFT 11
+#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17)
+#define RCC_FCALCCR2_FCALCTYP_SHIFT 17
+
+/* RCC_FCALCSR register fields */
+#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0)
+#define RCC_FCALCSR_FVAL_SHIFT 0
+#define RCC_FCALCSR_FCALCSTS BIT(19)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_SSMODRST BIT(0)
+#define RCC_PLL4CFGR1_PLLEN BIT(8)
+#define RCC_PLL4CFGR1_PLLRDY BIT(24)
+#define RCC_PLL4CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL4CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL4CFGR3 register fields */
+#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL4CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL4CFGR3_DACEN BIT(25)
+#define RCC_PLL4CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL4CFGR4 register fields */
+#define RCC_PLL4CFGR4_DSMEN BIT(8)
+#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL4CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL4CFGR5 register fields */
+#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL4CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL4CFGR6 register fields */
+#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL4CFGR7 register fields */
+#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL5CFGR1 register fields */
+#define RCC_PLL5CFGR1_SSMODRST BIT(0)
+#define RCC_PLL5CFGR1_PLLEN BIT(8)
+#define RCC_PLL5CFGR1_PLLRDY BIT(24)
+#define RCC_PLL5CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL5CFGR2 register fields */
+#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL5CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL5CFGR3 register fields */
+#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL5CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL5CFGR3_DACEN BIT(25)
+#define RCC_PLL5CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL5CFGR4 register fields */
+#define RCC_PLL5CFGR4_DSMEN BIT(8)
+#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL5CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL5CFGR5 register fields */
+#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL5CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL5CFGR6 register fields */
+#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL5CFGR7 register fields */
+#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL6CFGR1 register fields */
+#define RCC_PLL6CFGR1_SSMODRST BIT(0)
+#define RCC_PLL6CFGR1_PLLEN BIT(8)
+#define RCC_PLL6CFGR1_PLLRDY BIT(24)
+#define RCC_PLL6CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL6CFGR2 register fields */
+#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL6CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL6CFGR3 register fields */
+#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL6CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL6CFGR3_DACEN BIT(25)
+#define RCC_PLL6CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL6CFGR4 register fields */
+#define RCC_PLL6CFGR4_DSMEN BIT(8)
+#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL6CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL6CFGR5 register fields */
+#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL6CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL6CFGR6 register fields */
+#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL6CFGR7 register fields */
+#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL7CFGR1 register fields */
+#define RCC_PLL7CFGR1_SSMODRST BIT(0)
+#define RCC_PLL7CFGR1_PLLEN BIT(8)
+#define RCC_PLL7CFGR1_PLLRDY BIT(24)
+#define RCC_PLL7CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL7CFGR2 register fields */
+#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL7CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL7CFGR3 register fields */
+#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL7CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL7CFGR3_DACEN BIT(25)
+#define RCC_PLL7CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL7CFGR4 register fields */
+#define RCC_PLL7CFGR4_DSMEN BIT(8)
+#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL7CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL7CFGR5 register fields */
+#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL7CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL7CFGR6 register fields */
+#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL7CFGR7 register fields */
+#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLL8CFGR1 register fields */
+#define RCC_PLL8CFGR1_SSMODRST BIT(0)
+#define RCC_PLL8CFGR1_PLLEN BIT(8)
+#define RCC_PLL8CFGR1_PLLRDY BIT(24)
+#define RCC_PLL8CFGR1_CKREFST BIT(28)
+
+/* RCC_PLL8CFGR2 register fields */
+#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0
+#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLL8CFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLL8CFGR3 register fields */
+#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLL8CFGR3_FRACIN_SHIFT 0
+#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLL8CFGR3_DACEN BIT(25)
+#define RCC_PLL8CFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLL8CFGR4 register fields */
+#define RCC_PLL8CFGR4_DSMEN BIT(8)
+#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLL8CFGR4_BYPASS BIT(10)
+
+/* RCC_PLL8CFGR5 register fields */
+#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0
+#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLL8CFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLL8CFGR6 register fields */
+#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLL8CFGR7 register fields */
+#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST BIT(0)
+#define RCC_PLLxCFGR1_PLLEN BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY BIT(24)
+#define RCC_PLLxCFGR1_CKREFST BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0
+#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT 16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT 0
+#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24)
+#define RCC_PLLxCFGR3_DACEN BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9)
+#define RCC_PLLxCFGR4_BYPASS BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0
+#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT 16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0)
+#define RCC_VERR_MINREV_SHIFT 0
+#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4)
+#define RCC_VERR_MAJREV_SHIFT 4
+
+#endif /* STM32MP21_RCC_H */
diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h
index d5d228c..752d3c3 100644
--- a/include/drivers/st/stm32mp25_rcc.h
+++ b/include/drivers/st/stm32mp25_rcc.h
@@ -2308,6 +2308,12 @@
#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22)
#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23)
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF | \
+ RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF)
+
/* RCC_C2BOOTRSTSSETR register fields */
#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0)
#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1)
diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h
index 9329fff..d9bf7ae 100644
--- a/include/drivers/st/stm32mp2_ddr_helpers.h
+++ b/include/drivers/st/stm32mp2_ddr_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,7 +22,6 @@
void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
void ddr_wait_lp3_mode(bool state);
int ddr_sr_exit_loop(void);
-uint32_t ddr_get_io_calibration_val(void);
int ddr_sr_entry(bool standby);
int ddr_sr_exit(void);
enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void);
diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
index 57b0668..970ff19 100644
--- a/include/drivers/st/stm32mp_ddr.h
+++ b/include/drivers/st/stm32mp_ddr.h
@@ -28,7 +28,7 @@
struct stm32mp_ddr_reg_desc {
uint16_t offset; /* Offset for base address */
uint8_t par_offset; /* Offset for parameter array */
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
bool qd; /* quasi-dynamic register if true */
#endif
};
diff --git a/include/dt-bindings/clock/st,stm32mp21-rcc.h b/include/dt-bindings/clock/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..f23c536
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp21-rcc.h
@@ -0,0 +1,429 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
+#define _DT_BINDINGS_STM32MP21_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK 0
+#define HSE_CK 1
+#define MSI_CK 2
+#define LSI_CK 3
+#define LSE_CK 4
+#define I2S_CK 5
+#define RTC_CK 6
+#define SPDIF_CK_SYMB 7
+
+/* PLL CLOCKS */
+#define PLL1_CK 8
+#define PLL2_CK 9
+#define PLL4_CK 10
+#define PLL5_CK 11
+#define PLL6_CK 12
+#define PLL7_CK 13
+#define PLL8_CK 14
+
+#define CK_CPU1 15
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1 16
+#define CK_ICN_APB2 17
+#define CK_ICN_APB3 18
+#define CK_ICN_APB4 19
+#define CK_ICN_APB5 20
+#define CK_ICN_APBDBG 21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK 22
+#define TIMG2_CK 23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU 24
+#define CK_ICN_SDMMC 25
+#define CK_ICN_DDR 26
+#define CK_ICN_DISPLAY 27
+#define CK_ICN_HSL 28
+#define CK_ICN_NIC 29
+#define CK_ICN_VID 30
+#define CK_FLEXGEN_07 31
+#define CK_FLEXGEN_08 32
+#define CK_FLEXGEN_09 33
+#define CK_FLEXGEN_10 34
+#define CK_FLEXGEN_11 35
+#define CK_FLEXGEN_12 36
+#define CK_FLEXGEN_13 37
+#define CK_FLEXGEN_14 38
+#define CK_FLEXGEN_15 39
+#define CK_FLEXGEN_16 40
+#define CK_FLEXGEN_17 41
+#define CK_FLEXGEN_18 42
+#define CK_FLEXGEN_19 43
+#define CK_FLEXGEN_20 44
+#define CK_FLEXGEN_21 45
+#define CK_FLEXGEN_22 46
+#define CK_FLEXGEN_23 47
+#define CK_FLEXGEN_24 48
+#define CK_FLEXGEN_25 49
+#define CK_FLEXGEN_26 50
+#define CK_FLEXGEN_27 51
+#define CK_FLEXGEN_28 52
+#define CK_FLEXGEN_29 53
+#define CK_FLEXGEN_30 54
+#define CK_FLEXGEN_31 55
+#define CK_FLEXGEN_32 56
+#define CK_FLEXGEN_33 57
+#define CK_FLEXGEN_34 58
+#define CK_FLEXGEN_35 59
+#define CK_FLEXGEN_36 60
+#define CK_FLEXGEN_37 61
+#define CK_FLEXGEN_38 62
+#define CK_FLEXGEN_39 63
+#define CK_FLEXGEN_40 64
+#define CK_FLEXGEN_41 65
+#define CK_FLEXGEN_42 66
+#define CK_FLEXGEN_43 67
+#define CK_FLEXGEN_44 68
+#define CK_FLEXGEN_45 69
+#define CK_FLEXGEN_46 70
+#define CK_FLEXGEN_47 71
+#define CK_FLEXGEN_48 72
+#define CK_FLEXGEN_49 73
+#define CK_FLEXGEN_50 74
+#define CK_FLEXGEN_51 75
+#define CK_FLEXGEN_52 76
+#define CK_FLEXGEN_53 77
+#define CK_FLEXGEN_54 78
+#define CK_FLEXGEN_55 79
+#define CK_FLEXGEN_56 80
+#define CK_FLEXGEN_57 81
+#define CK_FLEXGEN_58 82
+#define CK_FLEXGEN_59 83
+#define CK_FLEXGEN_60 84
+#define CK_FLEXGEN_61 85
+#define CK_FLEXGEN_62 86
+#define CK_FLEXGEN_63 87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU 88
+
+#define CK_BUS_STM 89
+#define CK_BUS_FMC 90
+#define CK_BUS_ETH1 91
+#define CK_BUS_ETH2 92
+#define CK_BUS_DDRPHYC 93
+#define CK_BUS_SYSCPU1 94
+#define CK_BUS_HPDMA1 95
+#define CK_BUS_HPDMA2 96
+#define CK_BUS_HPDMA3 97
+#define CK_BUS_ADC1 98
+#define CK_BUS_ADC2 99
+#define CK_BUS_IPCC1 100
+#define CK_BUS_DCMIPSSI 101
+#define CK_BUS_CRC 102
+#define CK_BUS_MDF1 103
+#define CK_BUS_BKPSRAM 104
+#define CK_BUS_HASH1 105
+#define CK_BUS_HASH2 106
+#define CK_BUS_RNG1 107
+#define CK_BUS_RNG2 108
+#define CK_BUS_CRYP1 109
+#define CK_BUS_CRYP2 110
+#define CK_BUS_SAES 111
+#define CK_BUS_PKA 112
+#define CK_BUS_GPIOA 113
+#define CK_BUS_GPIOB 114
+#define CK_BUS_GPIOC 115
+#define CK_BUS_GPIOD 116
+#define CK_BUS_GPIOE 117
+#define CK_BUS_GPIOF 118
+#define CK_BUS_GPIOG 119
+#define CK_BUS_GPIOH 120
+#define CK_BUS_GPIOI 121
+#define CK_BUS_GPIOZ 122
+#define CK_BUS_RTC 124
+#define CK_BUS_LPUART1 125
+#define CK_BUS_LPTIM3 126
+#define CK_BUS_LPTIM4 127
+#define CK_BUS_LPTIM5 128
+#define CK_BUS_TIM2 129
+#define CK_BUS_TIM3 130
+#define CK_BUS_TIM4 131
+#define CK_BUS_TIM5 132
+#define CK_BUS_TIM6 133
+#define CK_BUS_TIM7 134
+#define CK_BUS_TIM10 135
+#define CK_BUS_TIM11 136
+#define CK_BUS_TIM12 137
+#define CK_BUS_TIM13 138
+#define CK_BUS_TIM14 139
+#define CK_BUS_LPTIM1 140
+#define CK_BUS_LPTIM2 141
+#define CK_BUS_SPI2 142
+#define CK_BUS_SPI3 143
+#define CK_BUS_SPDIFRX 144
+#define CK_BUS_USART2 145
+#define CK_BUS_USART3 146
+#define CK_BUS_UART4 147
+#define CK_BUS_UART5 148
+#define CK_BUS_I2C1 149
+#define CK_BUS_I2C2 150
+#define CK_BUS_I2C3 151
+#define CK_BUS_I3C1 152
+#define CK_BUS_I3C2 153
+#define CK_BUS_I3C3 154
+#define CK_BUS_TIM1 155
+#define CK_BUS_TIM8 156
+#define CK_BUS_TIM15 157
+#define CK_BUS_TIM16 158
+#define CK_BUS_TIM17 159
+#define CK_BUS_SAI1 160
+#define CK_BUS_SAI2 161
+#define CK_BUS_SAI3 162
+#define CK_BUS_SAI4 163
+#define CK_BUS_USART1 164
+#define CK_BUS_USART6 165
+#define CK_BUS_UART7 166
+#define CK_BUS_FDCAN 167
+#define CK_BUS_SPI1 168
+#define CK_BUS_SPI4 169
+#define CK_BUS_SPI5 170
+#define CK_BUS_SPI6 171
+#define CK_BUS_BSEC 172
+#define CK_BUS_IWDG1 173
+#define CK_BUS_IWDG2 174
+#define CK_BUS_IWDG3 175
+#define CK_BUS_IWDG4 176
+#define CK_BUS_WWDG1 177
+#define CK_BUS_VREF 178
+#define CK_BUS_DTS 179
+#define CK_BUS_SERC 180
+#define CK_BUS_HDP 181
+#define CK_BUS_DDRPERFM 182
+#define CK_BUS_OTG 183
+#define CK_BUS_LTDC 184
+#define CK_BUS_CSI 185
+#define CK_BUS_DCMIPP 186
+#define CK_BUS_DDRC 187
+#define CK_BUS_DDRCFG 188
+#define CK_BUS_STGEN 189
+#define CK_SYSDBG 190
+#define CK_KER_TIM2 191
+#define CK_KER_TIM3 192
+#define CK_KER_TIM4 193
+#define CK_KER_TIM5 194
+#define CK_KER_TIM6 195
+#define CK_KER_TIM7 196
+#define CK_KER_TIM10 197
+#define CK_KER_TIM11 198
+#define CK_KER_TIM12 199
+#define CK_KER_TIM13 200
+#define CK_KER_TIM14 201
+#define CK_KER_TIM1 202
+#define CK_KER_TIM8 203
+#define CK_KER_TIM15 204
+#define CK_KER_TIM16 205
+#define CK_KER_TIM17 206
+#define CK_BUS_SYSRAM 207
+#define CK_BUS_RETRAM 208
+#define CK_BUS_OSPI1 209
+#define CK_BUS_OTFD1 210
+#define CK_BUS_SRAM1 211
+#define CK_BUS_SDMMC1 212
+#define CK_BUS_SDMMC2 213
+#define CK_BUS_SDMMC3 214
+#define CK_BUS_DDR 215
+#define CK_BUS_RISAF4 216
+#define CK_BUS_USBHOHCI 217
+#define CK_BUS_USBHEHCI 218
+#define CK_KER_LPTIM1 219
+#define CK_KER_LPTIM2 220
+#define CK_KER_USART2 221
+#define CK_KER_UART4 222
+#define CK_KER_USART3 223
+#define CK_KER_UART5 224
+#define CK_KER_SPI2 225
+#define CK_KER_SPI3 226
+#define CK_KER_SPDIFRX 227
+#define CK_KER_I2C1 228
+#define CK_KER_I2C2 229
+#define CK_KER_I3C1 230
+#define CK_KER_I3C2 231
+#define CK_KER_I2C3 232
+#define CK_KER_I3C3 233
+#define CK_KER_SPI1 234
+#define CK_KER_SPI4 235
+#define CK_KER_SPI5 236
+#define CK_KER_SPI6 237
+#define CK_KER_USART1 238
+#define CK_KER_USART6 239
+#define CK_KER_UART7 240
+#define CK_KER_MDF1 241
+#define CK_KER_SAI1 242
+#define CK_KER_SAI2 243
+#define CK_KER_SAI3 244
+#define CK_KER_SAI4 245
+#define CK_KER_FDCAN 246
+#define CK_KER_CSI 247
+#define CK_KER_CSITXESC 248
+#define CK_KER_CSIPHY 249
+#define CK_KER_STGEN 250
+#define CK_KER_USB2PHY2EN 251
+#define CK_KER_LPUART1 252
+#define CK_KER_LPTIM3 253
+#define CK_KER_LPTIM4 254
+#define CK_KER_LPTIM5 255
+#define CK_KER_TSDBG 256
+#define CK_KER_TPIU 257
+#define CK_BUS_ETR 258
+#define CK_BUS_SYSATB 259
+#define CK_KER_ADC1 260
+#define CK_KER_ADC2 261
+#define CK_KER_OSPI1 262
+#define CK_KER_FMC 263
+#define CK_KER_SDMMC1 264
+#define CK_KER_SDMMC2 265
+#define CK_KER_SDMMC3 266
+#define CK_KER_ETH1 267
+#define CK_KER_ETH2 268
+#define CK_KER_ETH1PTP 269
+#define CK_KER_ETH2PTP 270
+#define CK_KER_USB2PHY1 271
+#define CK_KER_USB2PHY2 272
+#define CK_MCO1 273
+#define CK_MCO2 274
+#define CK_KER_DTS 275
+#define CK_ETH1_RX 276
+#define CK_ETH1_TX 277
+#define CK_ETH1_MAC 278
+#define CK_ETH2_RX 279
+#define CK_ETH2_TX 280
+#define CK_ETH2_MAC 281
+#define CK_ETH1_STP 282
+#define CK_ETH2_STP 283
+#define CK_KER_LTDC 284
+#define HSE_DIV2_CK 285
+#define CK_DBGMCU 286
+#define CK_DAP 287
+#define CK_KER_ETR 288
+#define CK_KER_STM 289
+
+#define STM32MP21_LAST_CLK 290
+
+#define CK_SCMI_ICN_HS_MCU 0
+#define CK_SCMI_ICN_SDMMC 1
+#define CK_SCMI_ICN_DDR 2
+#define CK_SCMI_ICN_DISPLAY 3
+#define CK_SCMI_ICN_HSL 4
+#define CK_SCMI_ICN_NIC 5
+#define CK_SCMI_ICN_VID 6
+#define CK_SCMI_FLEXGEN_07 7
+#define CK_SCMI_FLEXGEN_08 8
+#define CK_SCMI_FLEXGEN_09 9
+#define CK_SCMI_FLEXGEN_10 10
+#define CK_SCMI_FLEXGEN_11 11
+#define CK_SCMI_FLEXGEN_12 12
+#define CK_SCMI_FLEXGEN_13 13
+#define CK_SCMI_FLEXGEN_14 14
+#define CK_SCMI_FLEXGEN_15 15
+#define CK_SCMI_FLEXGEN_16 16
+#define CK_SCMI_FLEXGEN_17 17
+#define CK_SCMI_FLEXGEN_18 18
+#define CK_SCMI_FLEXGEN_19 19
+#define CK_SCMI_FLEXGEN_20 20
+#define CK_SCMI_FLEXGEN_21 21
+#define CK_SCMI_FLEXGEN_22 22
+#define CK_SCMI_FLEXGEN_23 23
+#define CK_SCMI_FLEXGEN_24 24
+#define CK_SCMI_FLEXGEN_25 25
+#define CK_SCMI_FLEXGEN_26 26
+#define CK_SCMI_FLEXGEN_27 27
+#define CK_SCMI_FLEXGEN_28 28
+#define CK_SCMI_FLEXGEN_29 29
+#define CK_SCMI_FLEXGEN_30 30
+#define CK_SCMI_FLEXGEN_31 31
+#define CK_SCMI_FLEXGEN_32 32
+#define CK_SCMI_FLEXGEN_33 33
+#define CK_SCMI_FLEXGEN_34 34
+#define CK_SCMI_FLEXGEN_35 35
+#define CK_SCMI_FLEXGEN_36 36
+#define CK_SCMI_FLEXGEN_37 37
+#define CK_SCMI_FLEXGEN_38 38
+#define CK_SCMI_FLEXGEN_39 39
+#define CK_SCMI_FLEXGEN_40 40
+#define CK_SCMI_FLEXGEN_41 41
+#define CK_SCMI_FLEXGEN_42 42
+#define CK_SCMI_FLEXGEN_43 43
+#define CK_SCMI_FLEXGEN_44 44
+#define CK_SCMI_FLEXGEN_45 45
+#define CK_SCMI_FLEXGEN_46 46
+#define CK_SCMI_FLEXGEN_47 47
+#define CK_SCMI_FLEXGEN_48 48
+#define CK_SCMI_FLEXGEN_49 49
+#define CK_SCMI_FLEXGEN_50 50
+#define CK_SCMI_FLEXGEN_51 51
+#define CK_SCMI_FLEXGEN_52 52
+#define CK_SCMI_FLEXGEN_53 53
+#define CK_SCMI_FLEXGEN_54 54
+#define CK_SCMI_FLEXGEN_55 55
+#define CK_SCMI_FLEXGEN_56 56
+#define CK_SCMI_FLEXGEN_57 57
+#define CK_SCMI_FLEXGEN_58 58
+#define CK_SCMI_FLEXGEN_59 59
+#define CK_SCMI_FLEXGEN_60 60
+#define CK_SCMI_FLEXGEN_61 61
+#define CK_SCMI_FLEXGEN_62 62
+#define CK_SCMI_FLEXGEN_63 63
+#define CK_SCMI_ICN_LS_MCU 64
+#define CK_SCMI_HSE 65
+#define CK_SCMI_LSE 66
+#define CK_SCMI_HSI 67
+#define CK_SCMI_LSI 68
+#define CK_SCMI_MSI 69
+#define CK_SCMI_HSE_DIV2 70
+#define CK_SCMI_CPU1 71
+#define CK_SCMI_SYSCPU1 72
+#define CK_SCMI_PLL2 73
+#define CK_SCMI_RTC 74
+#define CK_SCMI_RTCCK 75
+#define CK_SCMI_ICN_APB1 76
+#define CK_SCMI_ICN_APB2 77
+#define CK_SCMI_ICN_APB3 78
+#define CK_SCMI_ICN_APB4 79
+#define CK_SCMI_ICN_APB5 80
+#define CK_SCMI_ICN_APBDBG 81
+#define CK_SCMI_TIMG1 82
+#define CK_SCMI_TIMG2 83
+#define CK_SCMI_BKPSRAM 84
+#define CK_SCMI_BSEC 85
+#define CK_SCMI_BUS_ETR 86
+#define CK_SCMI_FMC 87
+#define CK_SCMI_GPIOA 88
+#define CK_SCMI_GPIOB 89
+#define CK_SCMI_GPIOC 90
+#define CK_SCMI_GPIOD 91
+#define CK_SCMI_GPIOE 92
+#define CK_SCMI_GPIOF 93
+#define CK_SCMI_GPIOG 94
+#define CK_SCMI_GPIOH 95
+#define CK_SCMI_GPIOI 96
+#define CK_SCMI_GPIOZ 97
+#define CK_SCMI_HPDMA1 98
+#define CK_SCMI_HPDMA2 99
+#define CK_SCMI_HPDMA3 100
+#define CK_SCMI_IPCC1 101
+#define CK_SCMI_RETRAM 102
+#define CK_SCMI_SRAM1 103
+#define CK_SCMI_SYSRAM 104
+#define CK_SCMI_OSPI1 105
+#define CK_SCMI_TPIU 106
+#define CK_SCMI_SYSDBG 107
+#define CK_SCMI_SYSATB 108
+#define CK_SCMI_TSDBG 109
+#define CK_SCMI_BUS_STM 110
+#define CK_SCMI_KER_STM 111
+#define CK_SCMI_KER_ETR 112
+
+#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp21-clksrc.h b/include/dt-bindings/clock/stm32mp21-clksrc.h
new file mode 100644
index 0000000..560ca0a
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp21-clksrc.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+
+#define CMD_DIV 0
+#define CMD_MUX 1
+#define CMD_CLK 2
+#define CMD_FLEXGEN 3
+
+#define CMD_ADDR_BIT 0x80000000
+
+#define CMD_SHIFT 26
+#define CMD_MASK 0xFC000000
+#define CMD_DATA_MASK 0x03FFFFFF
+
+#define DIV_ID_SHIFT 8
+#define DIV_ID_MASK 0x0000FF00
+
+#define DIV_DIVN_SHIFT 0
+#define DIV_DIVN_MASK 0x000000FF
+
+#define MUX_ID_SHIFT 4
+#define MUX_ID_MASK 0x00000FF0
+
+#define MUX_SEL_SHIFT 0
+#define MUX_SEL_MASK 0x0000000F
+
+/* CLK define */
+#define CLK_ON_MASK BIT(21)
+#define CLK_ON_SHIFT 21
+
+#define CLK_ID_MASK GENMASK_32(20, 12)
+#define CLK_ID_SHIFT 12
+
+#define CLK_NO_DIV_MASK 0x0000080
+#define CLK_DIV_MASK GENMASK_32(10, 5)
+#define CLK_DIV_SHIFT 5
+
+#define CLK_NO_SEL_MASK 0x00000010
+#define CLK_SEL_MASK GENMASK_32(3, 0)
+#define CLK_SEL_SHIFT 0
+
+#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\
+ ((state) << CLK_ON_SHIFT) |\
+ ((clk_id) << CLK_ID_SHIFT) |\
+ ((div) << CLK_DIV_SHIFT) |\
+ ((sel) << CLK_SEL_SHIFT))
+
+#define CLK_OFF 0
+#define CLK_ON 1
+#define CLK_NODIV 0x00000040
+#define CLK_NOMUX 0x00000010
+
+/* Flexgen define */
+#define FLEX_ID_SHIFT 20
+#define FLEX_SEL_SHIFT 16
+#define FLEX_PDIV_SHIFT 6
+#define FLEX_FDIV_SHIFT 0
+
+#define FLEX_ID_MASK GENMASK_32(25, 20)
+#define FLEX_SEL_MASK GENMASK_32(19, 16)
+#define FLEX_PDIV_MASK GENMASK_32(15, 6)
+#define FLEX_FDIV_MASK GENMASK_32(5, 0)
+
+#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\
+ ((div_id) << DIV_ID_SHIFT |\
+ (div)))
+
+#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\
+ ((mux_id) << MUX_ID_SHIFT |\
+ (sel)))
+
+#define CLK_ADDR_SHIFT 16
+#define CLK_ADDR_MASK 0x7FFF0000
+#define CLK_ADDR_VAL_MASK 0xFFFF
+
+#define DIV_LSMCU 0
+#define DIV_APB1 1
+#define DIV_APB2 2
+#define DIV_APB3 3
+#define DIV_APB4 4
+#define DIV_APB5 5
+#define DIV_APBDBG 6
+#define DIV_RTC 7
+#define DIV_NB 8
+
+#define MUX_MUXSEL0 0
+#define MUX_MUXSEL1 1
+#define MUX_MUXSEL2 2
+#define MUX_MUXSEL3 3
+#define MUX_MUXSEL4 4
+#define MUX_MUXSEL5 5
+#define MUX_MUXSEL6 6
+#define MUX_MUXSEL7 7
+#define MUX_XBARSEL 8
+#define MUX_RTC 9
+#define MUX_MCO1 10
+#define MUX_MCO2 11
+#define MUX_ADC1 12
+#define MUX_ADC2 13
+#define MUX_USB2PHY1 14
+#define MUX_USB2PHY2 15
+#define MUX_DTS 16
+#define MUX_CPU1 17
+#define MUX_NB 18
+
+#define MUXSEL_HSI 0
+#define MUXSEL_HSE 1
+#define MUXSEL_MSI 2
+
+/* KERNEL source clocks */
+#define MUX_RTC_DISABLED 0x0
+#define MUX_RTC_LSE 0x1
+#define MUX_RTC_LSI 0x2
+#define MUX_RTC_HSE 0x3
+
+#define MUX_MCO1_FLEX61 0x0
+#define MUX_MCO1_OBSER0 0x1
+
+#define MUX_MCO2_FLEX62 0x0
+#define MUX_MCO2_OBSER1 0x1
+
+#define MUX_ADC1_FLEX46 0x0
+#define MUX_ADC1_LSMCU 0x1
+
+#define MUX_ADC2_FLEX47 0x0
+#define MUX_ADC2_LSMCU 0x1
+#define MUX_ADC2_FLEX46 0x2
+
+#define MUX_USB2PHY1_FLEX57 0x0
+#define MUX_USB2PHY1_HSE 0x1
+
+#define MUX_USB2PHY2_FLEX58 0x0
+#define MUX_USB2PHY2_HSE 0x1
+
+#define MUX_DTS_HSI 0x0
+#define MUX_DTS_HSE 0x1
+#define MUX_DTS_MSI 0x2
+
+/* PLLs source clocks */
+#define PLL_SRC_HSI 0x0
+#define PLL_SRC_HSE 0x1
+#define PLL_SRC_MSI 0x2
+#define PLL_SRC_DISABLED 0x3
+
+/* XBAR source clocks */
+#define XBAR_SRC_PLL4 0x0
+#define XBAR_SRC_PLL5 0x1
+#define XBAR_SRC_PLL6 0x2
+#define XBAR_SRC_PLL7 0x3
+#define XBAR_SRC_PLL8 0x4
+#define XBAR_SRC_HSI 0x5
+#define XBAR_SRC_HSE 0x6
+#define XBAR_SRC_MSI 0x7
+#define XBAR_SRC_HSI_KER 0x8
+#define XBAR_SRC_HSE_KER 0x9
+#define XBAR_SRC_MSI_KER 0xA
+#define XBAR_SRC_SPDIF_SYMB 0xB
+#define XBAR_SRC_I2S 0xC
+#define XBAR_SRC_LSI 0xD
+#define XBAR_SRC_LSE 0xE
+
+/*
+ * Configure a XBAR channel with its clock source
+ * channel_nb: XBAR channel number from 0 to 63
+ * channel_src: one of the 15 previous XBAR source clocks defines
+ * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
+ * can be either 1, 2, 4 or 1024
+ * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
+ * from 1 to 64
+ */
+
+#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\
+ ((ch) << FLEX_ID_SHIFT) |\
+ ((sel) << FLEX_SEL_SHIFT) |\
+ ((pdiv) << FLEX_PDIV_SHIFT) |\
+ ((fdiv) << FLEX_FDIV_SHIFT))
+
+/* Register addresses of MCO1 & MCO2 */
+#define MCO1 0x488
+#define MCO2 0x48C
+
+#define MCO_OFF 0
+#define MCO_ON 1
+#define MCO_STATUS_SHIFT 8
+
+#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\
+ ((addr) << CLK_ADDR_SHIFT) |\
+ ((status) << MCO_STATUS_SHIFT) |\
+ (sel))
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD 0
+#define SSCG_MODE_DOWN_SPREAD 1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST 0
+#define LSEDRV_MEDIUM_LOW 2
+#define LSEDRV_MEDIUM_HIGH 1
+#define LSEDRV_HIGHEST 3
+
+#endif /* _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ */
diff --git a/include/dt-bindings/reset/st,stm32mp21-rcc.h b/include/dt-bindings/reset/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..377a170
--- /dev/null
+++ b/include/dt-bindings/reset/st,stm32mp21-rcc.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
+#define _DT_BINDINGS_STM32MP21_RESET_H_
+
+/* TF-A use a binding required by driver, not aligned with Linux*/
+
+#define SYS_R 8192
+#define C1_R 8224
+#define C2_R 8288
+#define C2_HOLDBOOT_R 8608
+#define C1_HOLDBOOT_R 8609
+#define VSW_R 8672
+#define C1MS_R 8840
+#define IWDG2_KER_R 9106
+#define IWDG4_KER_R 9234
+#define DDRCP_R 9888
+#define DDRCAPB_R 9920
+#define DDRPHYCAPB_R 9952
+#define DDRCFG_R 10016
+#define DDR_R 10048
+#define OSPI1_R 10400
+#define OSPI1DLL_R 10416
+#define FMC_R 10464
+#define DBG_R 10508
+#define GPIOA_R 10592
+#define GPIOB_R 10624
+#define GPIOC_R 10656
+#define GPIOD_R 10688
+#define GPIOE_R 10720
+#define GPIOF_R 10752
+#define GPIOG_R 10784
+#define GPIOH_R 10816
+#define GPIOI_R 10848
+#define GPIOZ_R 10944
+#define HPDMA1_R 10976
+#define HPDMA2_R 11008
+#define HPDMA3_R 11040
+#define IPCC1_R 11136
+#define SSMOD_R 11392
+#define TIM1_R 14336
+#define TIM2_R 14368
+#define TIM3_R 14400
+#define TIM4_R 14432
+#define TIM5_R 14464
+#define TIM6_R 14496
+#define TIM7_R 14528
+#define TIM8_R 14560
+#define TIM10_R 14592
+#define TIM11_R 14624
+#define TIM12_R 14656
+#define TIM13_R 14688
+#define TIM14_R 14720
+#define TIM15_R 14752
+#define TIM16_R 14784
+#define TIM17_R 14816
+#define LPTIM1_R 14880
+#define LPTIM2_R 14912
+#define LPTIM3_R 14944
+#define LPTIM4_R 14976
+#define LPTIM5_R 15008
+#define SPI1_R 15040
+#define SPI2_R 15072
+#define SPI3_R 15104
+#define SPI4_R 15136
+#define SPI5_R 15168
+#define SPI6_R 15200
+#define SPDIFRX_R 15296
+#define USART1_R 15328
+#define USART2_R 15360
+#define USART3_R 15392
+#define UART4_R 15424
+#define UART5_R 15456
+#define USART6_R 15488
+#define UART7_R 15520
+#define LPUART1_R 15616
+#define I2C1_R 15648
+#define I2C2_R 15680
+#define I2C3_R 15712
+#define SAI1_R 15904
+#define SAI2_R 15936
+#define SAI3_R 15968
+#define SAI4_R 16000
+#define MDF1_R 16064
+#define ADF1_R 16096
+#define FDCAN_R 16128
+#define HDP_R 16160
+#define ADC1_R 16192
+#define ADC2_R 16224
+#define ETH1_R 16256
+#define ETH2_R 16288
+#define USBH_R 16352
+#define USB2PHY1_R 16384
+#define OTG_R 16448
+#define USB2PHY2_R 16480
+#define SDMMC1_R 16768
+#define SDMMC1DLL_R 16784
+#define SDMMC2_R 16800
+#define SDMMC2DLL_R 16816
+#define SDMMC3_R 16832
+#define SDMMC3DLL_R 16848
+#define LTDC_R 16896
+#define CSI_R 17088
+#define DCMIPP_R 17120
+#define DCMIPSSI_R 17152
+#define RNG1_R 17280
+#define RNG2_R 17312
+#define PKA_R 17344
+#define SAES_R 17376
+#define HASH1_R 17408
+#define HASH2_R 17440
+#define CRYP1_R 17472
+#define CRYP2_R 17504
+#define WWDG1_R 17696
+#define VREF_R 17760
+#define DTS_R 17792
+#define CRC_R 17824
+#define SERC_R 17856
+#define I3C1_R 17984
+#define I3C2_R 18016
+#define I3C3_R 18048
+
+#define RST_SCMI_C1_R 0
+#define RST_SCMI_C2_R 1
+#define RST_SCMI_C1_HOLDBOOT_R 2
+#define RST_SCMI_C2_HOLDBOOT_R 3
+#define RST_SCMI_FMC 4
+#define RST_SCMI_OSPI1 5
+#define RST_SCMI_OSPI1DLL 6
+
+#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index c43beb6..84107a4 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -50,22 +50,6 @@
* Numeric value expected to read from CPU's MIDR
* _resetfunc:
* Reset function for the CPU.
- * _extra1:
- * This is a placeholder for future per CPU operations. Currently,
- * some CPUs use this entry to set a test function to determine if
- * the workaround for CVE-2017-5715 needs to be applied or not.
- * _extra2:
- * This is a placeholder for future per CPU operations. Currently
- * some CPUs use this entry to set a function to disable the
- * workaround for CVE-2018-3639.
- * _extra3:
- * This is a placeholder for future per CPU operations. Currently,
- * some CPUs use this entry to set a test function to determine if
- * the workaround for CVE-2022-23960 needs to be applied or not.
- * _extra4:
- * This is a placeholder for future per CPU operations. Currently,
- * some CPUs use this entry to set a test function to determine if
- * the workaround for CVE-2024-7881 needs to be applied or not.
* _e_handler:
* This is a placeholder for future per CPU exception handlers.
* _power_down_ops:
@@ -78,7 +62,6 @@
* used to handle power down at subsequent levels
*/
.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
- _extra1:req, _extra2:req, _extra3:req, _extra4:req, \
_e_handler:req, _power_down_ops:vararg
.section .cpu_ops, "a"
.align 3
@@ -87,10 +70,6 @@
#if defined(IMAGE_AT_EL3)
.quad \_resetfunc
#endif
- .quad \_extra1
- .quad \_extra2
- .quad \_extra3
- .quad \_extra4
.quad \_e_handler
#ifdef IMAGE_BL31
/* Insert list of functions */
@@ -153,30 +132,15 @@
.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
_power_down_ops:vararg
- declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, 0, 0, \
- \_power_down_ops
+ declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, \_power_down_ops
.endm
.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
_e_handler:req, _power_down_ops:vararg
declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
- 0, 0, 0, 0, \_e_handler, \_power_down_ops
+ \_e_handler, \_power_down_ops
.endm
- .macro declare_cpu_ops_wa _name:req, _midr:req, \
- _resetfunc:req, _extra1:req, _extra2:req, \
- _extra3:req, _power_down_ops:vararg
- declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
- \_extra1, \_extra2, \_extra3, 0, 0, \_power_down_ops
- .endm
-
- .macro declare_cpu_ops_wa_4 _name:req, _midr:req, \
- _resetfunc:req, _extra1:req, _extra2:req, \
- _extra3:req, _extra4:req, _power_down_ops:vararg
- declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
- \_extra1, \_extra2, \_extra3, \_extra4, 0, \_power_down_ops
- .endm
-
/*
* This macro is used on some CPUs to detect if they are vulnerable
* to CVE-2017-5715.
@@ -188,14 +152,14 @@
* If the field equals 1, branch targets trained in one context cannot
* affect speculative execution in a different context.
*
- * If the field equals 2, it means that the system is also aware of
+ * If the field equals 2 or 3, it means that the system is also aware of
* SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
* expect users of the registers to do the right thing.
*
* Only apply mitigations if the value of this field is 0.
*/
#if ENABLE_ASSERTIONS
- cmp \_reg, #3 /* Only values 0 to 2 are expected */
+ cmp \_reg, #4 /* Only values 0 to 3 are expected */
ASM_ASSERT(lo)
#endif
@@ -240,7 +204,7 @@
* Default value is 0.
*/
.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _split_wa=0
-#if REPORT_ERRATA || ERRATA_ABI_SUPPORT
+#if INCLUDE_ERRATA_LIST
.pushsection .rodata.errata_entries
.align 3
.ifndef \_cpu\()_errata_list_start
@@ -550,7 +514,7 @@
.align \_align
\_name:
#if ENABLE_BTI
- bti jc
+ BTI jc
#endif
.endm
diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h
index 0b08919..5ba78cf 100644
--- a/include/lib/cpus/cpu_ops.h
+++ b/include/lib/cpus/cpu_ops.h
@@ -22,14 +22,6 @@
/* The number of CPU operations allowed */
#define CPU_MAX_PWR_DWN_OPS 2
-#if __aarch64__
-#define CPU_NO_EXTRA1_FUNC 0
-#define CPU_NO_EXTRA2_FUNC 0
-#define CPU_NO_EXTRA3_FUNC 0
-#define CPU_NO_EXTRA4_FUNC 0
-#endif /* __aarch64__ */
-
-
/*
* Define the sizes of the fields in the cpu_ops structure. Word size is set per
* Aarch so keep these definitions the same and each can include whatever it
@@ -41,10 +33,6 @@
#else
#define CPU_RESET_FUNC_SIZE 0
#endif /* IMAGE_AT_EL3 */
-#define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE
-#define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE
-#define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE
-#define CPU_EXTRA4_FUNC_SIZE CPU_WORD_SIZE
#define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE
/* The power down core and cluster is needed only in BL31 and BL32 */
#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
@@ -86,11 +74,7 @@
#define CPU_MIDR 0
#define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE
#if __aarch64__
-#define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
-#define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
-#define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
-#define CPU_EXTRA4_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
-#define CPU_E_HANDLER_FUNC CPU_EXTRA4_FUNC + CPU_EXTRA4_FUNC_SIZE
+#define CPU_E_HANDLER_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
#define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
#else
#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
@@ -117,10 +101,6 @@
void (*reset_func)(void);
#endif /* IMAGE_AT_EL3 */
#if __aarch64__
- void (*extra1_func)(void);
- void (*extra2_func)(void);
- void (*extra3_func)(void);
- void (*extra4_func)(void);
void (*e_handler_func)(long es);
#endif /* __aarch64__ */
#if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 1f5f5ea..bb755e0 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -27,6 +27,18 @@
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
+/* Errata ID for smc workarounds */
+#define ARCH_WORKAROUND_2 2
+#define ARCH_WORKAROUND_3 3
+
+#define INCLUDE_ERRATA_LIST ( \
+ REPORT_ERRATA | \
+ ERRATA_ABI_SUPPORT | \
+ WORKAROUND_CVE_2017_5715 | \
+ WORKAROUND_CVE_2018_3639 | \
+ WORKAROUND_CVE_2022_23960 | \
+ WORKAROUND_CVE_2024_7881)
+
#ifndef __ASSEMBLER__
#include <lib/cassert.h>
@@ -70,6 +82,8 @@
bool check_if_trbe_disable_affected_core(void);
int check_wa_cve_2024_7881(void);
bool errata_ich_vmcr_el2_applies(void);
+struct erratum_entry *find_erratum_entry(uint32_t errata_id);
+int check_erratum_applies(uint32_t cve, int errata_id);
#else
@@ -79,11 +93,10 @@
* NOTE an erratum and CVE id could clash. However, both numbers are very large
* and the probablity is minuscule. Working around this makes code very
* complicated and extremely difficult to read so it is not considered. In the
- * unlikely event that this does happen, prepending the CVE id with a 0 should
- * resolve the conflict
+ * unlikely event that this does happen, the build will fail, and unless the
+ * framework is updated to account for this one of the IDs will need to be
+ * altered to prevent the conflict.
*/
-#define ERRATUM(id) 0, id
-#define CVE(year, id) year, id
#define NO_ISB 1
#define NO_ASSERT 0
#define NO_APPLY_AT_RESET 0
@@ -96,6 +109,9 @@
#endif /* __ASSEMBLER__ */
+#define ERRATUM(id) 0, id
+#define CVE(year, id) year, id
+
/* Macro to get CPU revision code for checking errata version compatibility. */
#define CPU_REV(r, p) ((r << 4) | p)
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h
deleted file mode 100644
index 2ad56e1..0000000
--- a/include/lib/cpus/wa_cve_2017_5715.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2017_5715_H
-#define WA_CVE_2017_5715_H
-
-int check_wa_cve_2017_5715(void);
-
-#endif /* WA_CVE_2017_5715_H */
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h
deleted file mode 100644
index 5a7c9bf..0000000
--- a/include/lib/cpus/wa_cve_2018_3639.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2018_3639_H
-#define WA_CVE_2018_3639_H
-
-void *wa_cve_2018_3639_get_disable_ptr(void);
-
-#endif /* WA_CVE_2018_3639_H */
diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h
deleted file mode 100644
index 50c0f76..0000000
--- a/include/lib/cpus/wa_cve_2022_23960.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef WA_CVE_2022_23960_H
-#define WA_CVE_2022_23960_H
-
-int check_smccc_arch_wa3_applies(void);
-
-#endif /* WA_CVE_2022_23960_H */
diff --git a/include/lib/libc/string_private.h b/include/lib/libc/string_private.h
index da85fae..ab7647a 100644
--- a/include/lib/libc/string_private.h
+++ b/include/lib/libc/string_private.h
@@ -11,6 +11,7 @@
#include <stddef.h>
+void *memcpy(void *dst, const void *src, size_t len);
int memcmp(const void *s1, const void *s2, size_t len);
int strcmp(const char *s1, const char *s2);
int strncmp(const char *s1, const char *s2, size_t n);
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 098506a..68e464a 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -58,12 +58,34 @@
#define GENMASK GENMASK_32
#endif
+/*
+ * Similar to GENMASK_64 but uses a named register field to compute the mask.
+ * For a register field REG_FIELD, the macros REG_FIELD_WIDTH and
+ * REG_FIELD_SHIFT must be defined.
+ */
+#define MASK(regfield) \
+ ((~0ULL >> (64ULL - (regfield##_WIDTH))) << (regfield##_SHIFT))
+
#define HI(addr) (addr >> 32)
#define LO(addr) (addr & 0xffffffff)
#define HI_64(addr) (addr >> 64)
#define LO_64(addr) (addr & 0xffffffffffffffff)
+/**
+ * EXTRACT_FIELD - Extracts a specific bit field from a value.
+ *
+ * @reg: The input value containing the field.
+
+ * @regfield: A bitmask representing the field. For a register field REG_FIELD,
+ * the macros REG_FIELD_WIDTH and REG_FIELD_SHIFT must be defined.
+
+ * The result of this macro is the contents of the field right shifted to the
+ * least significant bit positions, with the rest being zero.
+ */
+#define EXTRACT(regfield, reg) \
+ (((reg) & MASK(regfield)) >> (regfield##_SHIFT))
+
/*
* This variant of div_round_up can be used in macro definition but should not
* be used in C code as the `div` parameter is evaluated twice.
@@ -221,17 +243,4 @@
*/
#define KHZ_TICKS_PER_SEC U(1000)
-/**
- * EXTRACT_FIELD - Extracts a specific bit field from a value.
- *
- * @val: The input value containing the field.
- * @mask: A bitmask representing the maximum value of the field
- * @shift: The starting bit position of the field.
- *
- * This macro shifts the input value (@val) to the right by @shift bits,
- * aligning the target field to the least significant bits (LSB).
- * It then applies @mask to extract only the relevant bits.
- */
-#define EXTRACT_FIELD(val, mask, shift) (((val) >> (shift)) & (mask))
-
#endif /* UTILS_DEF_H */
diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index f540fa5..a0bc1f3 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h
@@ -148,8 +148,8 @@
/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
-/* Device-nGnRE */
-#define ATTR_DEVICE MAIR_DEV_nGnRE
+/* Device-nGnRnE */
+#define ATTR_DEVICE MAIR_DEV_nGnRnE
/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
diff --git a/include/plat/arm/common/plat_acs_smc_handler.h b/include/plat/arm/common/plat_acs_smc_handler.h
new file mode 100644
index 0000000..4d337cb
--- /dev/null
+++ b/include/plat/arm/common/plat_acs_smc_handler.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef ACS_SMC_HANDLER_H
+#define ACS_SMC_HANDLER_H
+
+#include <common/runtime_svc.h>
+#include <lib/utils_def.h>
+
+/* ARM ACS SMC service call */
+#define ARM_VEN_EL3_ACS_SMC_HANDLER U(0xC7000030)
+#define is_acs_fid(smc_fid) (smc_fid == ARM_VEN_EL3_ACS_SMC_HANDLER)
+
+uintptr_t plat_arm_acs_smc_handler(unsigned int smc_fid,
+ uint64_t services,
+ uint64_t arg0,
+ uint64_t arg1,
+ uint64_t arg2,
+ void *handle);
+#endif /* ACS_SMC_HANDLER_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 4a856a7..aed85f5 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -300,7 +300,8 @@
void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size);
/* TSP utility functions */
-void arm_tsp_early_platform_setup(void);
+void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3);
/* SP_MIN utility functions */
void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
diff --git a/include/services/arm_arch_svc.h b/include/services/arm_arch_svc.h
index 699a8d7..ea7de0e 100644
--- a/include/services/arm_arch_svc.h
+++ b/include/services/arm_arch_svc.h
@@ -95,6 +95,12 @@
#define SCR_FEAT_AMUv1p1 (0)
#endif
+#if ENABLE_FEAT_TWED
+#define SCR_FEAT_TWED SCR_TWEDEn_BIT
+#else
+#define SCR_FEAT_TWED (0)
+#endif
+
#if ENABLE_FEAT_ECV
#define SCR_FEAT_ECV SCR_ECVEN_BIT
#else
@@ -119,7 +125,7 @@
#define SCR_FEAT_CSV2_2 (0)
#endif
-#if ENABLE_FEAT_RAS
+#if !RAS_TRAP_NS_ERR_REC_ACCESS
#define SCR_FEAT_RAS SCR_TERR_BIT
#else
#define SCR_FEAT_RAS (0)
@@ -182,6 +188,7 @@
SCR_FEAT_HCX | \
SCR_FEAT_LS64_ACCDATA | \
SCR_FEAT_AMUv1p1 | \
+ SCR_FEAT_TWED | \
SCR_FEAT_ECV | \
SCR_FEAT_FGT | \
SCR_FEAT_MTE2 | \
@@ -289,6 +296,7 @@
MDCR_FEAT_SPE | \
MDCR_TDOSA_BIT | \
MDCR_TDA_BIT | \
+ MDCR_EnPM2_BIT | \
MDCR_TPM_BIT | /* FEAT_PMUv3 */ \
MDCR_PLAT_FEATS)
#define MDCR_EL3_FLIPPED ( \
@@ -300,6 +308,7 @@
MDCR_PLAT_FLIPPED)
#define MDCR_EL3_IGNORED ( \
MDCR_EBWE_BIT | \
+ MDCR_EnPMS3_BIT | \
MDCR_EnPMSN_BIT | \
MDCR_SBRBE(2UL) | \
MDCR_MTPME_BIT | \
diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 86110db..56ae129 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h
@@ -246,10 +246,10 @@
#define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_SHIFT U(1)
#define DRTM_LAUNCH_FEAT_HASHING_TYPE_SHIFT U(0)
-#define DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_MASK U(0x1)
-#define DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_MASK U(0x7)
-#define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_MASK U(0x3)
-#define DRTM_LAUNCH_FEAT_HASHING_TYPE_MASK U(0x1)
+#define DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_WIDTH U(1)
+#define DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_WIDTH U(3)
+#define DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_WIDTH U(2)
+#define DRTM_LAUNCH_FEAT_HASHING_TYPE_WIDTH U(1)
#define DLME_IMG_AUTH U(0x1)
#define REG_MEM_PROTECTION_TYPE U(0x1)
diff --git a/include/services/ven_el3_svc.h b/include/services/ven_el3_svc.h
index e030b68..0336059 100644
--- a/include/services/ven_el3_svc.h
+++ b/include/services/ven_el3_svc.h
@@ -21,7 +21,7 @@
#define VEN_EL3_SVC_VERSION 0x8700ff03
#define VEN_EL3_SVC_VERSION_MAJOR 1
-#define VEN_EL3_SVC_VERSION_MINOR 0
+#define VEN_EL3_SVC_VERSION_MINOR 1
/* DEBUGFS_SMC_32 0x87000010U */
/* DEBUGFS_SMC_64 0xC7000010U */
@@ -29,4 +29,7 @@
/* PMF_SMC_GET_TIMESTAMP_32 0x87000020U */
/* PMF_SMC_GET_TIMESTAMP_64 0xC7000020U */
+/* ACS_SMC_HANDLER_32 0x87000030U */
+/* ACS_SMC_HANDLER_64 0xC7000030U */
+
#endif /* VEN_EL3_SVC_H */
diff --git a/lib/aarch64/cache_helpers.S b/lib/aarch64/cache_helpers.S
index ff9a4e6..cc46c53 100644
--- a/lib/aarch64/cache_helpers.S
+++ b/lib/aarch64/cache_helpers.S
@@ -215,7 +215,7 @@
.macro dcsw_loop _op
#if ENABLE_BTI
- bti j
+ BTI j
#endif
loop2_\_op:
lsl w7, w6, w2 // w7 = aligned max set number
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index adacc5c..553f6f9 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -65,15 +65,20 @@
ret
endfunc cortex_a57_disable_ext_debug
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a57, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
/*
* Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't
- * provide and erratum number, so assign it an obvious 1
+ * provide and erratum number, so assign it an obvious 99999
*/
-workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT
+workaround_reset_start cortex_a57, ERRATUM(99999), A57_DISABLE_NON_TEMPORAL_HINT
sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-workaround_reset_end cortex_a57, ERRATUM(1)
+workaround_reset_end cortex_a57, ERRATUM(99999)
-check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2)
+check_erratum_ls cortex_a57, ERRATUM(99999), CPU_REV(1, 2)
workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969
sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
@@ -187,11 +192,6 @@
sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
cpu_reset_func_end cortex_a57
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
-
/* ----------------------------------------------------
* The CPU Ops core power down function for Cortex-A57.
* ----------------------------------------------------
@@ -307,10 +307,7 @@
ret
endfunc cortex_a57_cpu_reg_dump
-declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \
+declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \
cortex_a57_reset_func, \
- check_erratum_cortex_a57_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a57_core_pwr_dwn, \
cortex_a57_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index fee28ee..23b27ab 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -76,14 +76,17 @@
ret
endfunc cortex_a72_disable_ext_debug
-func check_smccc_arch_workaround_3
+check_erratum_custom_start cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
-endfunc check_smccc_arch_workaround_3
+check_erratum_custom_end cortex_a72, ERRATUM(ARCH_WORKAROUND_3)
+
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a72, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
@@ -294,10 +297,7 @@
ret
endfunc cortex_a72_cpu_reg_dump
-declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
+declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
cortex_a72_reset_func, \
- check_erratum_cortex_a72_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a72_core_pwr_dwn, \
cortex_a72_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index d1fc6d4..9cc6fdb 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -33,10 +33,10 @@
ret
endfunc cortex_a73_disable_smp
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a73, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
@@ -200,10 +200,7 @@
ret
endfunc cortex_a73_cpu_reg_dump
-declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
+declare_cpu_ops cortex_a73, CORTEX_A73_MIDR, \
cortex_a73_reset_func, \
- check_erratum_cortex_a73_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a73_core_pwr_dwn, \
cortex_a73_cluster_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 13599ca..ef9c067 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -20,6 +20,11 @@
cpu_reset_prologue cortex_a75
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_3 */
+add_erratum_entry cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
+check_erratum_chosen cortex_a75, ERRATUM(ARCH_WORKAROUND_3), WORKAROUND_CVE_2022_23960
+
workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081
sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT
workaround_reset_end cortex_a75, ERRATUM(764081)
@@ -131,11 +136,6 @@
#endif
cpu_reset_func_end cortex_a75
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
-
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
@@ -170,9 +170,6 @@
ret
endfunc cortex_a75_cpu_reg_dump
-declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
+declare_cpu_ops cortex_a75, CORTEX_A75_MIDR, \
cortex_a75_reset_func, \
- check_erratum_cortex_a75_5715, \
- CPU_NO_EXTRA2_FUNC, \
- check_smccc_arch_workaround_3, \
cortex_a75_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index b8d5b4f..ca5ccf7 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -301,6 +301,11 @@
endfunc apply_cve_2018_3639_sync_wa
#endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
+/* Erratum entry and check function for SMCCC_ARCH_WORKAROUND_2*/
+add_erratum_entry cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
+check_erratum_chosen cortex_a76, ERRATUM(ARCH_WORKAROUND_2), WORKAROUND_CVE_2018_3639
+
workaround_reset_start cortex_a76, ERRATUM(798953), ERRATA_DSU_798953
errata_dsu_798953_wa_impl
workaround_reset_end cortex_a76, ERRATUM(798953)
@@ -535,9 +540,6 @@
ret
endfunc cortex_a76_cpu_reg_dump
-declare_cpu_ops_wa cortex_a76, CORTEX_A76_MIDR, \
+declare_cpu_ops cortex_a76, CORTEX_A76_MIDR, \
cortex_a76_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- cortex_a76_disable_wa_cve_2018_3639, \
- CPU_NO_EXTRA3_FUNC, \
cortex_a76_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index c4872fe..158ee0e 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -167,10 +167,6 @@
ret
endfunc cortex_x3_cpu_reg_dump
-declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \
+declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
cortex_x3_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_cortex_x3_7881, \
cortex_x3_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index fbbe925..1d0c377 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -169,10 +169,6 @@
ret
endfunc cortex_x4_cpu_reg_dump
-declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \
+declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
cortex_x4_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_cortex_x4_7881, \
cortex_x4_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 093d91d..0663b21 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S
@@ -99,10 +99,6 @@
ret
endfunc cortex_x925_cpu_reg_dump
-declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \
+declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \
cortex_x925_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_cortex_x925_7881, \
cortex_x925_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index e608422..105da5c 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -188,143 +188,3 @@
get_rev_var x0, x1
ret
endfunc cpu_get_rev_var
-
-/*
- * int check_wa_cve_2017_5715(void);
- *
- * This function returns:
- * - ERRATA_APPLIES when firmware mitigation is required.
- * - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- * - ERRATA_MISSING when firmware mitigation would be required but
- * is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
- .globl check_wa_cve_2017_5715
-func check_wa_cve_2017_5715
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA1_FUNC]
- /*
- * If the reserved function pointer is NULL, this CPU
- * is unaffected by CVE-2017-5715 so bail out.
- */
- cmp x0, #CPU_NO_EXTRA1_FUNC
- beq 1f
- br x0
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_wa_cve_2017_5715
-
-/*
- * int check_wa_cve_2024_7881(void);
- *
- * This function returns:
- * - ERRATA_APPLIES when firmware mitigation is required.
- * - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
- * - ERRATA_MISSING when firmware mitigation would be required but
- * is not compiled in.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
-.globl check_wa_cve_2024_7881
-func check_wa_cve_2024_7881
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA4_FUNC]
- /*
- * If the reserved function pointer is NULL, this CPU
- * is unaffected by CVE-2024-7881 so bail out.
- */
- cmp x0, #CPU_NO_EXTRA4_FUNC
- beq 1f
- br x0
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_wa_cve_2024_7881
-
-/*
- * void *wa_cve_2018_3639_get_disable_ptr(void);
- *
- * Returns a function pointer which is used to disable mitigation
- * for CVE-2018-3639.
- * The function pointer is only returned on cores that employ
- * dynamic mitigation. If the core uses static mitigation or is
- * unaffected by CVE-2018-3639 this function returns NULL.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
- .globl wa_cve_2018_3639_get_disable_ptr
-func wa_cve_2018_3639_get_disable_ptr
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA2_FUNC]
- ret
-endfunc wa_cve_2018_3639_get_disable_ptr
-
-/*
- * int check_smccc_arch_wa3_applies(void);
- *
- * This function checks whether SMCCC_ARCH_WORKAROUND_3 is enabled to mitigate
- * CVE-2022-23960 for this CPU. It returns:
- * - ERRATA_APPLIES when SMCCC_ARCH_WORKAROUND_3 can be invoked to mitigate
- * the CVE.
- * - ERRATA_NOT_APPLIES when SMCCC_ARCH_WORKAROUND_3 should not be invoked to
- * mitigate the CVE.
- *
- * NOTE: Must be called only after cpu_ops have been initialized
- * in per-CPU data.
- */
- .globl check_smccc_arch_wa3_applies
-func check_smccc_arch_wa3_applies
- mrs x0, tpidr_el3
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
-#if ENABLE_ASSERTIONS
- cmp x0, #0
- ASM_ASSERT(ne)
-#endif
- ldr x0, [x0, #CPU_EXTRA3_FUNC]
- /*
- * If the reserved function pointer is NULL, this CPU
- * is unaffected by CVE-2022-23960 so bail out.
- */
- cmp x0, #CPU_NO_EXTRA3_FUNC
- beq 1f
- br x0
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_smccc_arch_wa3_applies
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index 64158e7..22cd3ba 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -319,11 +319,8 @@
/* macro to declare cpu_ops for Denver SKUs */
.macro denver_cpu_ops_wa midr
- declare_cpu_ops_wa denver, \midr, \
+ declare_cpu_ops denver, \midr, \
denver_reset_func, \
- check_erratum_denver_5715, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
denver_core_pwr_dwn, \
denver_cluster_pwr_dwn
.endm
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 5868bf2..e821ecb 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -268,13 +268,6 @@
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
- /*
- * Issue Error Synchronization Barrier to synchronize SErrors before
- * exiting EL3. We're running with EAs unmasked, so any synchronized
- * errors would be taken immediately; therefore no need to inspect
- * DISR_EL1 register.
- */
- esb
exception_return
1:
ret
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index ce84942..9526b80 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -148,10 +148,6 @@
ret
endfunc neoverse_v2_cpu_reg_dump
-declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \
+declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
neoverse_v2_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_neoverse_v2_7881, \
neoverse_v2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S
index 2ead062..ca108e7 100644
--- a/lib/cpus/aarch64/neoverse_v3.S
+++ b/lib/cpus/aarch64/neoverse_v3.S
@@ -124,10 +124,6 @@
neoverse_v3_reset_func, \
neoverse_v3_core_pwr_dwn
-declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
neoverse_v3_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- CPU_NO_EXTRA2_FUNC, \
- CPU_NO_EXTRA3_FUNC, \
- check_erratum_neoverse_v3_7881, \
neoverse_v3_core_pwr_dwn
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 0530647..a1e6d60 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -6,6 +6,8 @@
/* Runtime C routines for errata workarounds and common routines */
+#include <assert.h>
+
#include <arch.h>
#include <arch_helpers.h>
#include <cortex_a75.h>
@@ -26,6 +28,31 @@
#include <neoverse_n3.h>
#include <neoverse_v3.h>
+struct erratum_entry *find_erratum_entry(uint32_t errata_id)
+{
+ struct cpu_ops *cpu_ops;
+ struct erratum_entry *entry, *end;
+
+ cpu_ops = get_cpu_ops_ptr();
+ assert(cpu_ops != NULL);
+
+ entry = cpu_ops->errata_list_start;
+ assert(entry != NULL);
+
+ end = cpu_ops->errata_list_end;
+ assert(end != NULL);
+
+ end--; /* point to the last erratum entry of the queried cpu */
+
+ while ((entry <= end)) {
+ if (entry->id == errata_id) {
+ return entry;
+ }
+ entry += 1;
+ }
+ return NULL;
+}
+
bool check_if_trbe_disable_affected_core(void)
{
switch (EXTRACT_PARTNUM(read_midr())) {
@@ -151,3 +178,21 @@
return false;
}
+
+int check_erratum_applies(uint32_t cve, int errata_id)
+{
+ struct erratum_entry *entry;
+ long rev_var;
+
+ rev_var = cpu_get_rev_var();
+
+ entry = find_erratum_entry(errata_id);
+
+ if (entry == NULL) {
+ return ERRATA_NOT_APPLIES;
+ }
+
+ assert(entry->cve == cve);
+
+ return entry->check_func(rev_var);
+}
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index ab68467..47e8699 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -31,7 +31,7 @@
/* Errata format: BL stage, CPU, errata ID, message */
#define ERRATA_FORMAT "%s: %s: CPU workaround for %s was %s\n"
-#define CVE_FORMAT "%s: %s: CPU workaround for CVE %u_%u was %s\n"
+#define CVE_FORMAT "%s: %s: CPU workaround for CVE %u_%04u was %s\n"
#define ERRATUM_FORMAT "%s: %s: CPU workaround for erratum %u was %s\n"
diff --git a/lib/el3_runtime/aarch64/context_debug.c b/lib/el3_runtime/aarch64/context_debug.c
index 1ae7f6b..1addb45 100644
--- a/lib/el3_runtime/aarch64/context_debug.c
+++ b/lib/el3_runtime/aarch64/context_debug.c
@@ -97,7 +97,6 @@
#else
size_t el1_size = 0U;
#endif /* CTX_INCLUDE_EL2_REGS */
- size_t pauth_size = 0U;
if (is_ctx_pauth_supported()) {
PRINT_SINGLE_MEM_USAGE_SEP_BLOCK();
@@ -125,12 +124,14 @@
printf("| %8luB ", el1_size);
#endif /* CTX_INCLUDE_EL2_REGS */
+#if CTX_INCLUDE_PAUTH_REGS
if (is_ctx_pauth_supported()) {
- pauth_size = sizeof(ctx->pauth_ctx);
+ size_t pauth_size = sizeof(ctx->pauth_ctx);
size_other -= pauth_size;
pauth_total += pauth_size;
printf("| %8luB ", pauth_size);
}
+#endif
printf("| %8luB | %8luB |\n", size_other, core_total);
gp_total += gp_size;
diff --git a/lib/extensions/pauth/pauth.c b/lib/extensions/pauth/pauth.c
index 2dd0d28..fbbcaa2 100644
--- a/lib/extensions/pauth/pauth.c
+++ b/lib/extensions/pauth/pauth.c
@@ -62,16 +62,25 @@
void __no_pauth pauth_enable_el3(void)
{
write_sctlr_el3(read_sctlr_el3() | SCTLR_EnIA_BIT);
+
+ if (is_feat_pauth_lr_supported()) {
+ write_sctlr2_el3(read_sctlr2_el3() | SCTLR2_EnPACM_BIT);
+ }
+
isb();
}
void __no_pauth pauth_enable_el1(void)
{
write_sctlr_el1(read_sctlr_el1() | SCTLR_EnIA_BIT);
+
+ if (is_feat_pauth_lr_supported()) {
+ write_sctlr2_el1(read_sctlr2_el1() | SCTLR2_EnPACM_BIT);
+ }
+
isb();
}
-/* Enable PAuth for EL2 */
void pauth_enable_el2(void)
{
u_register_t hcr_el2 = read_hcr_el2();
diff --git a/lib/extensions/pmuv3/aarch64/pmuv3.c b/lib/extensions/pmuv3/aarch64/pmuv3.c
index 61d1258..b47b664 100644
--- a/lib/extensions/pmuv3/aarch64/pmuv3.c
+++ b/lib/extensions/pmuv3/aarch64/pmuv3.c
@@ -78,11 +78,14 @@
* 1 | 1 | enabled | disabled only for counters 0 to
* MDCR_EL2.HPMN - 1. Enabled for the rest
*
+ * MDCR_EL3.EnPM2: Set to one so that various PMUv3p9 related system
+ * register accesses do not trap to EL3.
+ *
* MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
* accesses to all Performance Monitors registers do not trap to EL3.
*/
- mdcr_el3_val = (mdcr_el3_val | MDCR_SCCD_BIT | MDCR_MCCD_BIT) &
- ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT);
+ mdcr_el3_val |= MDCR_SCCD_BIT | MDCR_MCCD_BIT | MDCR_EnPM2_BIT;
+ mdcr_el3_val &= ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT);
mdcr_el3_val = mtpmu_disable_el3(mdcr_el3_val);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index d7df267..e499486 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -26,12 +26,12 @@
* MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses.
* When FEAT_RME is not implemented, this field is RES0.
*
- * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1
- * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented.
- * Setting this bit to 1 doesn't have any effect on it when
- * FEAT_SPEv1p2 not implemented.
+ * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Do not trap access to
+ * PMSNEVFR_EL1 or PMSDSFR_EL1 register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2
+ * or FEAT_SPE_FDS are implemented. Setting these bits to 1 doesn't have any
+ * effect on it when the features aren't implemented.
*/
- mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
+ mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT | MDCR_EnPMS3_BIT;
mdcr_el3_val &= ~(MDCR_NSPBE_BIT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
@@ -46,10 +46,11 @@
* Disable access of profiling buffer control registers from lower ELs
* in any security state. Secure state owns the buffer.
*
- * MDCR_EL3.EnPMSN (ARM v8.7): Clear the bit to trap access of PMSNEVFR_EL1
- * from EL2/EL1 to EL3.
+ * MDCR_EL3.EnPMSN (ARM v8.7) and MDCR_EL3.EnPMS3: Clear the bits to trap access
+ * of PMSNEVFR_EL1 and PMSDSFR_EL1 from EL2/EL1 to EL3.
*/
- mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT);
+ mdcr_el3_val &= ~(MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_NSPBE_BIT | MDCR_EnPMSN_BIT |
+ MDCR_EnPMS3_BIT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index f8c4a26..c9e8a04 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c
@@ -44,19 +44,19 @@
unsigned int rem;
/* num_buf is only large enough for radix >= 10 */
- if (radix < 10) {
+ if (radix < 10U) {
assert(0);
return 0;
}
do {
rem = (uint32_t)(unum % radix);
- if (rem < 0xa) {
+ if (rem < 0xaU) {
num_buf[i] = '0' + rem;
} else if (uppercase) {
- num_buf[i] = 'A' + (rem - 0xa);
+ num_buf[i] = 'A' + (rem - 0xaU);
} else {
- num_buf[i] = 'a' + (rem - 0xa);
+ num_buf[i] = 'a' + (rem - 0xaU);
}
i++;
unum /= radix;
@@ -105,7 +105,7 @@
int l_count;
long long int num;
unsigned long long int unum;
- char *str;
+ const char *str;
char padc = '\0'; /* Padding character */
int padn; /* Number of characters to pad */
int count = 0; /* Number of printed characters */
@@ -142,7 +142,7 @@
count++;
break;
case 's':
- str = va_arg(args, char *);
+ str = va_arg(args, const char *);
count += string_print(str);
break;
case 'p':
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 56bfb64..61bd08a 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2022-2025, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -58,11 +58,6 @@
armv8-5-a-feats += ${armv8-4-a-feats}
FEAT_LIST := ${armv8-5-a-feats}
-# Enable Memory tagging, Branch Target Identification for aarch64 only.
-ifeq ($(ARCH), aarch64)
- mem_tag_arch_support ?= yes
-endif #(ARCH=aarch64)
-
endif
# Enable the features which are mandatory from ARCH version 8.6 and upwards.
@@ -160,6 +155,11 @@
# direct setting. Use BRANCH_PROTECTION to enable PAUTH.
ENABLE_PAUTH ?= 0
+# FEAT_PAUTH_LR is an optional architectural feature, so this flag must be set
+# manually in addition to the BRANCH_PROTECTION flag which is used for other
+# branch protection and pointer authentication features.
+ENABLE_FEAT_PAUTH_LR ?= 0
+
# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
# must be set to 1 if the platform wants to use this feature in the Secure
# world. It is not necessary for use in the Non-secure world.
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index f438a9d..4ccca9f 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -346,11 +346,6 @@
# CTX_INCLUDE_EL2_REGS.
CTX_INCLUDE_EL2_REGS := 0
-# Enable Memory tag extension which is supported for architecture greater
-# than Armv8.5-A
-# By default it is set to "no"
-SUPPORT_STACK_MEMTAG := no
-
# Select workaround for AT speculative behaviour.
ERRATA_SPECULATIVE_AT := 0
diff --git a/package-lock.json b/package-lock.json
index 57b44de..92921f9 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,12 +1,12 @@
{
"name": "trusted-firmware-a",
- "version": "2.12.0",
+ "version": "2.13.0",
"lockfileVersion": 3,
"requires": true,
"packages": {
"": {
"name": "trusted-firmware-a",
- "version": "2.12.0",
+ "version": "2.13.0",
"license": "BSD-3-Clause",
"devDependencies": {
"@commitlint/cli": "^19.0.0",
diff --git a/package.json b/package.json
index 0908528..6061bf8 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
{
"name": "trusted-firmware-a",
- "version": "2.12.0",
+ "version": "2.13.0",
"license": "BSD-3-Clause",
"type": "module",
"private": true,
diff --git a/plat/amd/common/plat_xfer_list.c b/plat/amd/common/plat_xfer_list.c
index 7af6726..19c882b 100644
--- a/plat/amd/common/plat_xfer_list.c
+++ b/plat/amd/common/plat_xfer_list.c
@@ -45,9 +45,18 @@
continue;
case SECURE:
*bl32 = *ep;
- if (!transfer_list_set_handoff_args(tl_hdr, ep)) {
+#if defined(SPD_opteed)
+ /*
+ * Populate the args expected by opteed,
+ * arg0 - dt address,
+ * arg1 - Xfer List Convention Version,
+ * arg3 - Xfer List address
+ * remaining args are set to 0.
+ */
+ if (transfer_list_set_handoff_args(tl_hdr, bl32) == NULL) {
ERROR("Invalid transfer list\n");
}
+#endif /* SPD_opteed */
continue;
default:
ERROR("Unrecognized Image Security State %lu\n",
diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 8d9e05c..9e52f9d 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c
@@ -8,12 +8,12 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <def.h>
#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
-
-#include <def.h>
+#include <plat_clkfunc.h>
#include <plat_common.h>
#include <plat_ipi.h>
#include <plat_private.h>
@@ -123,7 +123,7 @@
uintptr_t crl_base, iou_scntrs_base, psx_base;
crl_base = CRL;
- iou_scntrs_base = IOU_SCNTRS;
+ iou_scntrs_base = IOU_SCNTRS_BASE;
psx_base = PSX_CRF;
/* Reset for system timestamp generator in FPX */
@@ -143,13 +143,11 @@
mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
IOU_SCNTRS_CONTROL_EN);
+ /* set cntfrq_el0 value so that software can discover the frequency of the system counter */
+ set_cnt_freq();
+
generic_delay_timer_init();
/* Configure IPI data */
soc_ipi_config_table_init();
}
-
-uint32_t plat_get_syscnt_freq2(void)
-{
- return cpu_clock;
-}
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 77838a9..94ace7d 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -181,7 +181,9 @@
INFO("CPU Revision = 0x%lx\n", rev_var);
INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock);
NOTICE("BL31: Executing from 0x%x\n", BL31_BASE);
+#if (defined(SPD_tspd) || defined(SPD_opteed))
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
+#endif /* SPD_tspd || SPD_opteed */
NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
}
diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
index 9bef9d0..3b42b15 100644
--- a/plat/amd/versal2/include/def.h
+++ b/plat/amd/versal2/include/def.h
@@ -126,8 +126,14 @@
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
-/* IOU SCNTRS */
-#define IOU_SCNTRS U(0xEC920000)
+#define FPD_SYSTMR_CTRL_BASE U(0xEC920000)
+
+/*
+ * Note: There is no IOU_SCNTRS in Versal Gen 2, the equivalent
+ * functionality is provided through FPD_SYSTMR_CTRL. For compatibility
+ * with existing code, maintain the same macro names.
+ */
+#define IOU_SCNTRS_BASE FPD_SYSTMR_CTRL_BASE
#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
diff --git a/plat/amd/versal2/plat_psci.c b/plat/amd/versal2/plat_psci.c
index d53d751..cded1f3 100644
--- a/plat/amd/versal2/plat_psci.c
+++ b/plat/amd/versal2/plat_psci.c
@@ -19,7 +19,6 @@
#include <plat_private.h>
#include <pm_defs.h>
-#define PM_RET_ERROR_NOFEATURE U(19)
#define ALWAYSTRUE true
#define LINEAR_MODE BIT(1)
@@ -192,7 +191,7 @@
case IOCTL_USB_SET_STATE:
break;
default:
- ret = PM_RET_ERROR_NOFEATURE;
+ ret = PM_RET_ERROR_IOCTL_NOT_SUPPORTED;
break;
}
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 283ad42..475e8ff 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -116,6 +116,7 @@
drivers/delay_timer/generic_delay_timer.c \
${GICV3_SOURCES} \
drivers/arm/pl011/aarch64/pl011_console.S \
+ plat/xilinx/common/plat_clkfunc.c \
plat/common/aarch64/crash_console_helpers.S \
plat/arm/common/arm_common.c \
plat/common/plat_gicv3.c \
diff --git a/plat/amd/versal2/pm_service/pm_client.c b/plat/amd/versal2/pm_service/pm_client.c
index 8d6b9b1..67099a6 100644
--- a/plat/amd/versal2/pm_service/pm_client.c
+++ b/plat/amd/versal2/pm_service/pm_client.c
@@ -336,6 +336,23 @@
uintptr_t val;
if (cpuid != (uint32_t) UNDEFINED_CPUID) {
+ /*
+ * Get the core index and use it to calculate offset for
+ * disabling power down and wakeup interrupts.
+ * i.e., Convert cpu-id to core_index with the following mapping:
+ * cpu-id -> core_index
+ * 0 -> 0
+ * 1 -> 1
+ * 2 -> 4
+ * 3 -> 5
+ * 4 -> 8
+ * 5 -> 9
+ * 6 -> 12
+ * 7 -> 13
+ * to match with register database.
+ */
+ uint32_t core_index = cpuid + ((cpuid / 2U) * 2U);
+
pm_client_lock_get();
/* Clear powerdown request */
@@ -346,10 +363,10 @@
isb();
/* Disabled power down interrupt */
- mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
+ mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(core_index),
APU_PCIL_CORE_X_IDS_POWER_MASK);
/* Disable wake interrupt */
- mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
+ mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(core_index),
APU_PCIL_CORE_X_IDS_WAKE_MASK);
pm_client_lock_release();
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index a11c1de..fd6cf78 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -27,7 +27,7 @@
load-address = <0x0 0x07f00000>;
max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
id = <HW_CONFIG_ID>;
- secondary-load-address = <0x0 0x82000000>;
+ secondary-load-address = <0x0 FVP_HW_CONFIG_ADDR>;
};
/*
diff --git a/plat/arm/board/fvp/fvp_bl1_measured_boot.c b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
index 7e2d9cc..d6b6863 100644
--- a/plat/arm/board/fvp/fvp_bl1_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
@@ -8,11 +8,16 @@
#include <drivers/measured_boot/event_log/event_log.h>
#include <drivers/measured_boot/metadata.h>
-#include <plat/arm/common/plat_arm.h>
#include <tools_share/zero_oid.h>
+#include <plat/arm/common/plat_arm.h>
+
/* Event Log data */
+#if TRANSFER_LIST
+static uint8_t *event_log;
+#else
static uint8_t event_log[PLAT_ARM_EVENT_LOG_MAX_SIZE];
+#endif
/* FVP table with platform specific image IDs, names and PCRs */
const event_log_metadata_t fvp_event_log_metadata[] = {
@@ -20,14 +25,23 @@
{ TB_FW_CONFIG_ID, MBOOT_TB_FW_CONFIG_STRING, PCR_0 },
{ BL2_IMAGE_ID, MBOOT_BL2_IMAGE_STRING, PCR_0 },
- { EVLOG_INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */
+ { EVLOG_INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */
};
void bl1_plat_mboot_init(void)
{
- size_t event_log_max_size = PLAT_ARM_EVENT_LOG_MAX_SIZE;
+ size_t event_log_max_size;
int rc;
+#if TRANSFER_LIST
+ event_log = transfer_list_event_log_extend(
+ secure_tl, PLAT_ARM_EVENT_LOG_MAX_SIZE,
+ &event_log_max_size);
+ assert(event_log != NULL);
+#else
+ event_log_max_size = sizeof(event_log);
+#endif
+
rc = event_log_init(event_log, event_log + event_log_max_size);
if (rc < 0) {
ERROR("Failed to initialize event log (%d).\n", rc);
@@ -43,18 +57,28 @@
void bl1_plat_mboot_finish(void)
{
- size_t event_log_cur_size;
+ size_t event_log_cur_size = event_log_get_cur_size(event_log);
- event_log_cur_size = event_log_get_cur_size(event_log);
- int rc = arm_set_tb_fw_info((uintptr_t)event_log,
- event_log_cur_size,
- PLAT_ARM_EVENT_LOG_MAX_SIZE);
- if (rc != 0) {
- /*
- * It is a fatal error because on FVP platform, BL2 software
- * assumes that a valid Event Log buffer exist and it will use
- * same Event Log buffer to append image measurements.
- */
- panic();
+#if TRANSFER_LIST
+ uint8_t *rc = transfer_list_event_log_finish(
+ secure_tl, (uintptr_t)event_log + event_log_cur_size);
+
+ if (rc != NULL) {
+ return;
}
+#else
+ int rc = arm_set_tb_fw_info((uintptr_t)event_log, event_log_cur_size,
+ PLAT_ARM_EVENT_LOG_MAX_SIZE);
+ if (rc == 0) {
+ return;
+ }
+#endif
+
+ /*
+ * Panic if we fail to set up the event log for the next stage. This is a fatal
+ * error because, on the FVP platform, BL2 software assumes that a valid
+ * Event Log buffer exists and will use the same Event Log buffer to append image
+ * measurements.
+ */
+ panic();
}
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index 28aef92..1fae0cf 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,7 +19,7 @@
#include <plat/arm/common/plat_arm.h>
#include <plat/common/common_def.h>
-#if defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)
+#if !TRANSFER_LIST && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
CASSERT(ARM_EVENT_LOG_DRAM1_SIZE >= PLAT_ARM_EVENT_LOG_MAX_SIZE, \
assert_res_eventlog_mem_insufficient);
#endif /* defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd) */
@@ -61,10 +61,17 @@
{
uint8_t *event_log_start;
uint8_t *event_log_finish;
- size_t bl1_event_log_size;
- size_t event_log_max_size;
- int rc;
+ size_t bl1_event_log_size __unused;
+ size_t event_log_max_size __unused;
+ int rc __unused;
+#if TRANSFER_LIST
+ event_log_start = transfer_list_event_log_extend(
+ secure_tl, PLAT_ARM_EVENT_LOG_MAX_SIZE, &event_log_max_size);
+ event_log_finish = event_log_start + event_log_max_size;
+
+ event_log_base = (uintptr_t)event_log_start;
+#else
rc = arm_get_tb_fw_info(&event_log_base, &bl1_event_log_size,
&event_log_max_size);
if (rc != 0) {
@@ -82,10 +89,11 @@
* BL1 and BL2 share the same Event Log buffer and that BL2 will
* append its measurements after BL1's
*/
- event_log_start = (uint8_t *)((uintptr_t)event_log_base +
- bl1_event_log_size);
- event_log_finish = (uint8_t *)((uintptr_t)event_log_base +
- event_log_max_size);
+ event_log_start =
+ (uint8_t *)((uintptr_t)event_log_base + bl1_event_log_size);
+ event_log_finish =
+ (uint8_t *)((uintptr_t)event_log_base + event_log_max_size);
+#endif
event_log_init((uint8_t *)event_log_start, event_log_finish);
}
@@ -160,7 +168,7 @@
int rc;
/* Event Log address in Non-Secure memory */
- uintptr_t ns_log_addr;
+ uintptr_t ns_log_addr __unused;
/* Event Log filled size */
size_t event_log_cur_size;
@@ -172,6 +180,15 @@
event_log_cur_size = event_log_get_cur_size((uint8_t *)event_log_base);
+#if TRANSFER_LIST
+ /*
+ * Re-size the event log for the next stage and update the size to include
+ * the entire event log (i.e., not just what this stage has added.)
+ */
+ event_log_base = (uintptr_t)transfer_list_event_log_finish(
+ secure_tl, (uintptr_t)event_log_base + event_log_cur_size);
+ event_log_cur_size = event_log_get_cur_size((uint8_t *)event_log_base);
+#else
#if defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)
/* Copy Event Log to TZC secured DRAM memory */
(void)memcpy((void *)ARM_EVENT_LOG_DRAM1_BASE,
@@ -217,6 +234,7 @@
panic();
}
#endif /* defined(SPD_tspd) || defined(SPD_spmd) */
+#endif /* TRANSFER_LIST */
event_log_dump((uint8_t *)event_log_base, event_log_cur_size);
}
diff --git a/plat/arm/board/fvp/fvp_cpu_pwr.c b/plat/arm/board/fvp/fvp_cpu_pwr.c
index f2771c2..a294534 100644
--- a/plat/arm/board/fvp/fvp_cpu_pwr.c
+++ b/plat/arm/board/fvp/fvp_cpu_pwr.c
@@ -20,8 +20,8 @@
bool check_cpupwrctrl_el1_is_available(void)
{
- /* Poupulate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
- const unsigned int midr_no_cpupwrctl[] = {
+ /* Populate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
+ static const unsigned int midr_no_cpupwrctl[] = {
BASE_AEM_MIDR,
CORTEX_A35_MIDR,
CORTEX_A53_MIDR,
diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h
index 9a51eb7..7e53a65 100644
--- a/plat/arm/board/fvp/fvp_private.h
+++ b/plat/arm/board/fvp/fvp_private.h
@@ -19,7 +19,6 @@
void fvp_interconnect_enable(void);
void fvp_interconnect_disable(void);
void fvp_timer_init(void);
-void tsp_early_platform_setup(void);
void fvp_pcpu_init(void);
void fvp_gic_driver_pre_init(void);
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 854e48a..002674c 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -93,15 +93,6 @@
#define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */
#define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U)
-/* Range of kernel DTB load address */
-#define FVP_DTB_DRAM_MAP_START ULL(0x82000000)
-#define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */
-
-#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
- FVP_DTB_DRAM_MAP_START, \
- FVP_DTB_DRAM_MAP_SIZE, \
- MT_MEMORY | MT_RO | MT_NS)
-
/*
* On the FVP platform when using the EL3 SPMC implementation allocate the
* datastore for tracking shared memory descriptors in the TZC DRAM section
@@ -206,7 +197,7 @@
# define PLAT_ARM_MMAP_ENTRIES 12
# define MAX_XLAT_TABLES 6
# else
-# define PLAT_ARM_MMAP_ENTRIES 11
+# define PLAT_ARM_MMAP_ENTRIES 12
# define MAX_XLAT_TABLES 5
# endif /* (IMAGE_BL2 && ENABLE_RME) */
#else
@@ -227,7 +218,7 @@
*/
#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \
FVP_TRUSTED_SRAM_SIZE == 512
-#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000)
+#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xD000)
#else
#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
#endif
@@ -509,12 +500,19 @@
/*
* Maximum size of Event Log buffer used in Measured Boot Event Log driver
+ * TODO: calculate maximum EventLog size using the calculation:
+ * Maximum size of Event Log * Number of images
*/
-#if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
-/* Account for additional measurements of secure partitions and SPM. */
-#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800)
+#if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed)))
+/*
+ * Account for additional measurements of secure partitions and SPM.
+ * Also, account for OP-TEE running with maximum number of SPs.
+ */
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800)
+#elif defined(IMAGE_BL1) && TRANSFER_LIST
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x200)
#else
-#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400)
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400)
#endif
/*
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index beb6d5d..26ea58d 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -292,7 +292,7 @@
plat/arm/board/fvp/fvp_ide_keymgmt.c
endif
-ifeq (${ENABLE_FEAT_RNG_TRAP},1)
+ifneq (${ENABLE_FEAT_RNG_TRAP},0)
BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c
endif
@@ -359,6 +359,10 @@
$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
HW_CONFIG := ${FVP_HW_CONFIG}
+# Allow hw_config's secondary-load-address in the DT to be changed
+FVP_HW_CONFIG_ADDR ?= 0x82000000
+DTC_CPPFLAGS += -DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR)
+
# Set default initrd base 128MiB offset of the default kernel address in FVP
INITRD_BASE ?= 0x90000000
diff --git a/plat/arm/board/fvp/tsp/fvp_tsp_setup.c b/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
index 3c8a963..53a84c6 100644
--- a/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
+++ b/plat/arm/board/fvp/tsp/fvp_tsp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,9 +8,10 @@
#include "../fvp_private.h"
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
- arm_tsp_early_platform_setup();
+ arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3);
/* Initialize the platform config for future decision making */
fvp_config_setup();
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 0216000..76bae38 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -258,11 +258,7 @@
#define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)
-#if TARGET_PLATFORM == 2
-#define PLAT_ARM_NSTIMER_FRAME_ID U(0)
-#else
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
-#endif
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
@@ -276,10 +272,7 @@
#define PLAT_ARM_NSRAM_SIZE 0x00008000 /* 64KB */
#endif /* TARGET_FLAVOUR_FPGA */
-#if TARGET_PLATFORM <= 2
-#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
-#elif TARGET_PLATFORM >= 3
+#if TARGET_PLATFORM >= 3
#if TC_FPGA_FS_IMG_IN_RAM
/* 10GB reserved for system+userdata+vendor images */
@@ -348,28 +341,19 @@
CSS_SCMI_PAYLOAD_SIZE_MAX)
#define PLAT_ARM_CLUSTER_COUNT U(1)
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2
-#define PLAT_MAX_CPUS_PER_CLUSTER U(14)
-#else /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM == 2 */
#define PLAT_MAX_PE_PER_CPU U(1)
#define PLATFORM_CORE_COUNT (PLAT_MAX_CPUS_PER_CLUSTER * PLAT_ARM_CLUSTER_COUNT)
/* Message Handling Unit (MHU) base addresses */
-#if TARGET_PLATFORM <= 2
- #define PLAT_CSS_MHU_BASE UL(0x45400000)
-#elif TARGET_PLATFORM >= 3
+#if TARGET_PLATFORM >= 3
#define PLAT_CSS_MHU_BASE UL(0x46000000)
#endif /* TARGET_PLATFORM >= 3 */
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
/* AP<->RSS MHUs */
-#if TARGET_PLATFORM <= 2
-#define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000)
-#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000)
-#elif TARGET_PLATFORM == 3
+#if TARGET_PLATFORM == 3
#define PLAT_RSE_AP_SND_MHU_BASE UL(0x49000000)
#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x49100000)
#elif TARGET_PLATFORM == 4
@@ -403,36 +387,6 @@
*/
#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x30000
-#if TARGET_PLATFORM <= 2
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x25000000)
-#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT 4
-
-#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
-
-#define TZC_NSAID_DEFAULT U(0)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
-
-/*
- * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to
- * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as
- * secure. The second and third regions gives non secure access to rest of DRAM.
- */
-#define TC_TZC_REGIONS_DEF \
- {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
- TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \
- ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
-#endif
-
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
@@ -468,13 +422,11 @@
#undef ARM_CONSOLE_BAUDRATE
#define ARM_CONSOLE_BAUDRATE 38400
-#if TARGET_PLATFORM <= 2
-#define TC_UARTCLK 5000000
-#elif TARGET_PLATFORM == 3
+#if TARGET_PLATFORM == 3
#define TC_UARTCLK 3750000
#elif TARGET_PLATFORM == 4
#define TC_UARTCLK 4000000
-#endif /* TARGET_PLATFORM <=2 */
+#endif /* TARGET_PLATFORM == 3 */
#if TARGET_FLAVOUR_FVP
diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
index cc2f760..9a8172a 100644
--- a/plat/arm/board/tc/include/tc_helpers.S
+++ b/plat/arm/board/tc/include/tc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -74,10 +74,6 @@
ret
endfunc enable_dsu_pmu_el1_access
-func TC_HANDLER(2)
- ret
-endfunc TC_HANDLER(2)
-
func TC_HANDLER(3)
mov x9, lr
bl mark_extllc_presence
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index bbccce6..b29f0d6 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -67,15 +67,10 @@
endif
endif
-ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
+ifneq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0)
$(error Platform ${PLAT}$(TARGET_PLATFORM) is no longer available.)
endif
-ifneq ($(shell expr $(TARGET_PLATFORM) = 2), 0)
- $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
- Some of the features might not work as expected)
-endif
-
ifeq ($(shell expr $(TARGET_PLATFORM) \<= 4), 0)
$(error TARGET_PLATFORM must be less than or equal to 4)
endif
@@ -109,35 +104,13 @@
# Save DSU PMU registers on cluster off and restore them on cluster on
PRESERVE_DSU_PMU_REGS := 1
-# Specify MHU type based on platform
-ifneq ($(filter ${TARGET_PLATFORM}, 2),)
- PLAT_MHU := MHUv2
-else
- PLAT_MHU := MHUv3
-endif
+PLAT_MHU := MHUv3
TC_BASE = plat/arm/board/tc
PLAT_INCLUDES += -I${TC_BASE}/include/ \
-I${TC_BASE}/fdts/
-# CPU libraries for TARGET_PLATFORM=1
-ifeq (${TARGET_PLATFORM}, 1)
-TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \
- lib/cpus/aarch64/cortex_a715.S \
- lib/cpus/aarch64/cortex_x3.S
-endif
-
-# CPU libraries for TARGET_PLATFORM=2
-ifeq (${TARGET_PLATFORM}, 2)
-ERRATA_A520_2938996 := 1
-ERRATA_X4_2726228 := 1
-
-TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \
- lib/cpus/aarch64/cortex_a720.S \
- lib/cpus/aarch64/cortex_x4.S
-endif
-
# CPU libraries for TARGET_PLATFORM=3
ifeq (${TARGET_PLATFORM}, 3)
ERRATA_A520_2938996 := 1
@@ -183,10 +156,6 @@
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c
-ifeq ($(shell test $(TARGET_PLATFORM) -le 2; echo $$?),0)
-BL2_SOURCES += plat/arm/common/arm_tzc400.c
-endif
-
BL31_SOURCES += ${INTERCONNECT_SOURCES} \
${TC_CPU_SOURCES} \
${TC_BASE}/tc_bl31_setup.c \
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index a358390..7f2014b 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -54,23 +54,13 @@
}
#endif /* PLATFORM_TEST_TFM_TESTSUITE */
-#if TARGET_PLATFORM <= 2
static scmi_channel_plat_info_t tc_scmi_plat_info = {
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
- .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
- .db_preserve_mask = 0xfffffffe,
- .db_modify_mask = 0x1,
- .ring_doorbell = &mhuv2_ring_doorbell,
-};
-#elif TARGET_PLATFORM >= 3
-static scmi_channel_plat_info_t tc_scmi_plat_info = {
- .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
.db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
.db_preserve_mask = 0xfffffffe,
.db_modify_mask = 0x1,
.ring_doorbell = &mhu_ring_doorbell,
};
-#endif
/* the bottom 3 AMU group 1 counters */
#define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2))
diff --git a/plat/arm/board/tc/tc_security.c b/plat/arm/board/tc/tc_security.c
index 7c7a1a1..804a35b 100644
--- a/plat/arm/board/tc/tc_security.c
+++ b/plat/arm/board/tc/tc_security.c
@@ -7,21 +7,8 @@
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
-#if (TARGET_PLATFORM <= 2)
-static const arm_tzc_regions_info_t tzc_regions[] = {
- TC_TZC_REGIONS_DEF,
- {}
-};
-#endif
-
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
-#if (TARGET_PLATFORM <= 2)
- unsigned int i;
- for (i = 0U; i < TZC400_COUNT; i++) {
- arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
- }
-#endif
}
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index bd3946c..522017f 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -320,6 +320,13 @@
void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node)
{
entry_point_info_t *ep __unused;
+
+ /*
+ * Information might have been added to the TL before this (i.e. event log)
+ * make sure the checksum is up to date.
+ */
+ transfer_list_update_checksum(secure_tl);
+
ep = transfer_list_set_handoff_args(secure_tl,
&next_param_node->ep_info);
assert(ep != NULL);
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 82f96ba..f196269 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -133,7 +133,12 @@
}
#endif
else {
+#if TRANSFER_LIST && !RESET_TO_BL31
+ next_image_info = transfer_list_set_handoff_args(
+ secure_tl, &bl32_image_ep_info);
+#else
next_image_info = &bl32_image_ep_info;
+#endif
}
/*
@@ -394,6 +399,16 @@
te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
transfer_list_entry_data(te));
assert(te != NULL);
+
+ te = transfer_list_find(secure_tl, TL_TAG_TPM_EVLOG);
+ if (te != NULL) {
+ te = transfer_list_add(ns_tl, TL_TAG_TPM_EVLOG, te->data_size,
+ transfer_list_entry_data(te));
+ if (te == NULL) {
+ ERROR("Failed to load event log in Non-Secure transfer list\n");
+ panic();
+ }
+ }
#endif /* TRANSFER_LIST && !RESET_TO_BL31 */
#if RESET_TO_BL31
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index d3c2a96..53fe806 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -79,6 +79,15 @@
$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
$(eval $(call add_define,ARM_BL31_IN_DRAM))
+# Macro to enable ACS SMC handler
+PLAT_ARM_ACS_SMC_HANDLER := 0
+ifeq (${ENABLE_ACS_SMC}, 1)
+PLAT_ARM_ACS_SMC_HANDLER := 1
+endif
+
+# Build macro necessary for branching to ACS tests
+$(eval $(call add_define,PLAT_ARM_ACS_SMC_HANDLER))
+
# As per CCA security model, all root firmware must execute from on-chip secure
# memory. This means we must not run BL31 from TZC-protected DRAM.
ifeq (${ARM_BL31_IN_DRAM},1)
@@ -305,6 +314,11 @@
plat/arm/common/arm_topology.c \
plat/common/plat_psci_common.c
+ifeq (${PLAT_ARM_ACS_SMC_HANDLER},1)
+BL31_SOURCES += plat/arm/common/plat_acs_smc_handler.c \
+ ${VENDOR_EL3_SRCS}
+endif
+
ifeq (${TRANSFER_LIST}, 1)
include lib/transfer_list/transfer_list.mk
TRANSFER_LIST_SOURCES += plat/arm/common/arm_transfer_list.c
@@ -388,8 +402,9 @@
ifneq (${TRUSTED_BOARD_BOOT},0)
# Include common TBB sources
- AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/img_parser_mod.c
+ AUTH_MK := drivers/auth/auth.mk
+ $(info Including ${AUTH_MK})
+ include ${AUTH_MK}
# Include the selected chain of trust sources.
ifeq (${COT},tbbr)
@@ -456,6 +471,9 @@
ifeq (${MEASURED_BOOT},1)
BL1_SOURCES += ${EVENT_LOG_SOURCES}
BL2_SOURCES += ${EVENT_LOG_SOURCES}
+ ifeq (${SPD_tspd},1)
+ BL32_SOURCES += ${EVENT_LOG_SOURCES}
+ endif
endif
ifeq (${DRTM_SUPPORT},1)
@@ -463,12 +481,22 @@
endif
endif
-ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT} ${DRTM_SUPPORT}),)
- CRYPTO_SOURCES := drivers/auth/crypto_mod.c \
- lib/fconf/fconf_tbbr_getter.c
+ifneq ($(filter 1,${MEASURED_BOOT} ${DRTM_SUPPORT}),)
+ifeq (${TRUSTED_BOARD_BOOT},0)
+ CRYPTO_SOURCES := drivers/auth/crypto_mod.c
BL1_SOURCES += ${CRYPTO_SOURCES}
BL2_SOURCES += ${CRYPTO_SOURCES}
+endif
+endif
+
+ifeq (${DRTM_SUPPORT},1)
BL31_SOURCES += drivers/auth/crypto_mod.c
+endif
+
+ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT} ${DRTM_SUPPORT}),)
+ FCONF_TBB_SOURCES := lib/fconf/fconf_tbbr_getter.c
+ BL1_SOURCES += ${FCONF_TBB_SOURCES}
+ BL2_SOURCES += ${FCONF_TBB_SOURCES}
# We expect to locate the *.mk files under the directories specified below
CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
diff --git a/plat/arm/common/plat_acs_smc_handler.c b/plat/arm/common/plat_acs_smc_handler.c
new file mode 100644
index 0000000..6f96874
--- /dev/null
+++ b/plat/arm/common/plat_acs_smc_handler.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdint.h>
+#include <plat/arm/common/plat_acs_smc_handler.h>
+
+/*
+ * Placeholder function for handling ACS SMC calls.
+ * return 0 till the handling is done.
+ */
+uintptr_t plat_arm_acs_smc_handler(unsigned int smc_fid, uint64_t services,
+ uint64_t arg0, uint64_t arg1, uint64_t arg2, void *handle)
+{
+ WARN("Unimplemented ACS Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+}
diff --git a/plat/arm/common/tsp/arm_tsp.mk b/plat/arm/common/tsp/arm_tsp.mk
index 4ad77c6..d7592df 100644
--- a/plat/arm/common/tsp/arm_tsp.mk
+++ b/plat/arm/common/tsp/arm_tsp.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,3 +8,10 @@
BL32_SOURCES += plat/arm/common/arm_topology.c \
plat/arm/common/tsp/arm_tsp_setup.c \
plat/common/aarch64/platform_mp_stack.S
+
+ifeq (${TRANSFER_LIST},1)
+BL32_SOURCES += $(TRANSFER_LIST_SOURCES)
+ifeq (${MEASURED_BOOT},1)
+BL32_SOURCES += $(EVENT_LOG_SOURCES)
+endif
+endif
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index 4f45579..d018dee 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -13,6 +13,9 @@
#include <common/debug.h>
#include <drivers/arm/pl011.h>
#include <drivers/console.h>
+#if TRANSFER_LIST && MEASURED_BOOT
+#include <drivers/measured_boot/event_log/event_log.h>
+#endif
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
@@ -26,13 +29,32 @@
BL32_END - BL32_BASE, \
MT_MEMORY | MT_RW | MT_SECURE)
+#define MAP_FW_HANDOFF MAP_REGION_FLAT( \
+ PLAT_ARM_EL3_FW_HANDOFF_BASE, \
+ PLAT_ARM_FW_HANDOFF_SIZE, \
+ MT_MEMORY | MT_RO | MT_SECURE)
+
+struct transfer_list_header *secure_tl __unused;
+
/*******************************************************************************
* Initialize the UART
******************************************************************************/
static console_t arm_tsp_runtime_console;
-void arm_tsp_early_platform_setup(void)
+void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
+#if TRANSFER_LIST
+ secure_tl = (struct transfer_list_header *)arg3;
+ assert(secure_tl != NULL);
+
+ if (transfer_list_check_header(secure_tl) == TL_OPS_NON) {
+ ERROR("Invalid transfer list received");
+ transfer_list_dump(secure_tl);
+ panic();
+ }
+#endif
+
/*
* Initialize a different console than already in use to display
* messages from TSP
@@ -41,16 +63,18 @@
PLAT_ARM_TSP_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE,
&arm_tsp_runtime_console);
- if (rc == 0)
+ if (rc == 0) {
panic();
+ }
console_set_scope(&arm_tsp_runtime_console,
CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
}
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
- arm_tsp_early_platform_setup();
+ arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3);
}
/*******************************************************************************
@@ -58,6 +82,8 @@
******************************************************************************/
void tsp_platform_setup(void)
{
+ struct transfer_list_entry *te __unused;
+
/*
* On GICv2 the driver must be initialised before calling the plat_ic_*
* functions as they need the data structures. Higher versions don't.
@@ -65,6 +91,17 @@
#if USE_GIC_DRIVER == 2
gic_init(plat_my_core_pos());
#endif
+
+#if TRANSFER_LIST && MEASURED_BOOT
+ te = transfer_list_find(secure_tl, TL_TAG_TPM_EVLOG);
+ assert(te != NULL);
+
+ /*
+ * Note the actual log is offset 4-bytes from the start of entry data, the
+ * first bytes are reserved.
+ */
+ event_log_dump(transfer_list_entry_data(te) + U(4), te->data_size - U(4));
+#endif
}
/*******************************************************************************
@@ -81,6 +118,9 @@
const mmap_region_t bl_regions[] = {
MAP_BL_TSP_TOTAL,
ARM_MAP_BL_RO,
+#if TRANSFER_LIST
+ MAP_FW_HANDOFF,
+#endif
{0}
};
diff --git a/plat/brcm/board/common/board_common.mk b/plat/brcm/board/common/board_common.mk
index 24a27ed..ef11e39 100644
--- a/plat/brcm/board/common/board_common.mk
+++ b/plat/brcm/board/common/board_common.mk
@@ -225,10 +225,11 @@
KEY_ALG := rsa_1_5
# Include common TBB sources
-AUTH_SOURCES += drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c \
drivers/auth/tbbr/tbbr_cot_bl2.c
BL2_SOURCES += ${AUTH_SOURCES}
diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index b67d3ff..0b919e5 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -127,10 +127,11 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
BL1_SOURCES += ${AUTH_SOURCES} \
plat/common/tbbr/plat_tbbr.c \
diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index c278d8e..a4be841 100644
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -120,10 +120,11 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
BL1_SOURCES += ${AUTH_SOURCES} \
plat/common/tbbr/plat_tbbr.c \
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index a7e8fe8..7d201c2 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -56,10 +56,11 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
BL2_SOURCES += ${AUTH_SOURCES} \
plat/common/tbbr/plat_tbbr.c \
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index e54256c..d2e812d 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -112,10 +112,11 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c \
drivers/auth/tbbr/tbbr_cot_bl2.c
BL2_SOURCES += ${AUTH_SOURCES} \
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 98b99d1..7d42391 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -109,10 +109,11 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c \
drivers/auth/tbbr/tbbr_cot_bl2.c
BL2_SOURCES += ${AUTH_SOURCES} \
@@ -149,6 +150,7 @@
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+ERRATA_A53_1530924 := 1
IMX_DRAM_RETENTION ?= 1
$(eval $(call assert_boolean,IMX_DRAM_RETENTION))
diff --git a/plat/imx/imx93/trdc_config.h b/plat/imx/imx93/trdc_config.h
index c623a19..478bbcd 100644
--- a/plat/imx/imx93/trdc_config.h
+++ b/plat/imx/imx93/trdc_config.h
@@ -40,6 +40,7 @@
{ 1, 2, 1, MBC_BLK_ALL, 2, true }, /* MBC1 CM33 system TCM for M33 DID2 */
{ 0, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS1 for A55 DID3 */
+ { 0, 3, 0, 79, 0, true }, /* MBC0 AIPS1 BLK_CTRL_S_AONMIX for A55 DID3 */
{ 0, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC0 Sentinel_SOC_In for A55 DID3 */
{ 0, 3, 2, MBC_BLK_ALL, 0, false }, /* MBC0 GPIO1 for A55 DID3 */
{ 1, 3, 0, MBC_BLK_ALL, 1, false }, /* MBC1 CM33 code TCM for A55 DID3 */
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index a3c3545..dabe865 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -67,6 +67,11 @@
mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
+
+ /* Enable TF-A BL31 logs when running from non-secure world also. */
+ console_set_scope(&console,
+ (CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
+
/*
* Check params passed from BL31 should not be NULL,
*/
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 9cf1e11..66e0ea5 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -217,9 +217,11 @@
NOTICE("SOCFPGA: CPU ID = %x\n", cpuid);
INFO("SOCFPGA: Invalidate Data cache\n");
invalidate_dcache_all();
-
/* Invalidate for NS EL2 and EL1 */
invalidate_cache_low_el();
+
+ NOTICE("SOCFPGA: Setting CLUSTERECTRL_EL1\n");
+ setup_clusterectlr_el1();
}
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
@@ -303,6 +305,22 @@
mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu);
}
+void setup_clusterectlr_el1(void)
+{
+ uint64_t value = 0;
+
+ /* Read CLUSTERECTLR_EL1 */
+ asm volatile("mrs %0, S3_0_C15_C3_4" : "=r"(value));
+
+ /* Disable broadcasting atomics */
+ value |= 0x80; /* set bit 7 */
+ /* Disable sending data with clean evicts */
+ value &= 0xFFFFBFFF; /* Mask out bit 14 */
+
+ /* Write CLUSTERECTLR_EL1 */
+ asm volatile("msr S3_0_C15_C3_4, %0" :: "r"(value));
+}
+
void bl31_plat_runtime_setup(void)
{
/* Dummy override function. */
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 8c86ab1..f4b53e8 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -160,6 +160,11 @@
#define SOCFPGA_ECC_QSPI_ECC_STARTACC 0x7C
#define SOCFPGA_ECC_QSPI_ECC_WDCTRL 0x80
+/* IOSSM mailbox address */
+#define IOSSM_CMD_PARAM 0x18400438
+#define IOSSM_CMD_TRIG_OP 0x1840043C
+#define IOSSM_CMD_RESP_STATUS 0x1840045C
+
#define DMA0_STREAM_CTRL_REG 0x10D1217C
#define DMA1_STREAM_CTRL_REG 0x10D12180
#define SDM_STREAM_CTRL_REG 0x10D12184
diff --git a/plat/intel/soc/agilex5/soc/agilex5_ddr.c b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
index 0d60324..acf7528 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_ddr.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
@@ -297,7 +297,7 @@
bool full_mem_init = false;
phys_size_t hw_ddr_size;
phys_size_t config_ddr_size;
- struct io96b_info io96b_ctrl;
+ struct io96b_info io96b_ctrl = {0};
enum reset_type reset_t = get_reset_type(mmio_read_32(SOCFPGA_SYSMGR(
BOOT_SCRATCH_COLD_3)));
bool is_dualport = hoff_ptr->ddr_config & BIT(0);
diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h
index f92678f..21d9b66 100644
--- a/plat/intel/soc/common/include/socfpga_fcs.h
+++ b/plat/intel/soc/common/include/socfpga_fcs.h
@@ -76,6 +76,10 @@
#define FCS_MAX_DATA_SIZE 0x20000000 /* 512 MB */
#define FCS_MIN_DATA_SIZE 0x8 /* 8 Bytes */
+#define FCS_AES_DATA_SIZE_CHECK(x) (((x >= FCS_AES_MIN_DATA_SIZE) && \
+ (x <= FCS_AES_MAX_DATA_SIZE)) ? \
+ true : false)
+
#define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U
#define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U
#define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U
@@ -362,7 +366,7 @@
uint32_t session_id, uint32_t context_id,
uint64_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t dst_size,
- uint32_t aad_size, uint8_t is_finalised,
+ uint32_t padding_size, uint8_t is_finalised,
uint32_t *send_id, uint64_t smmu_src_addr,
uint64_t smmu_dst_addr);
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index f965b7d..4da318b 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -309,7 +309,7 @@
((client_id << MBOX_CLIENT_ID_SHIFT) | \
(job_id << MBOX_JOB_ID_SHIFT) | \
(args_len << MBOX_CMD_LEN_SHIFT) | \
- (indirect << MBOX_CMD_LEN_SHIFT) | \
+ (indirect << MBOX_INDIRECT_SHIFT) | \
cmd)
#define FLAG_SDM_RESPONSE_IS_VALID BIT(0)
@@ -362,7 +362,7 @@
/* SDM client callback template */
typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd,
- uint32_t *ret_args);
+ uint64_t *ret_args);
/* SDM command data structure */
typedef struct sdm_command {
@@ -394,7 +394,7 @@
sdm_command_callback cb, uint32_t *cb_args,
uint32_t cb_args_len);
-int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint32_t *ret_args,
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint64_t *ret_args,
uint32_t *ret_args_size);
int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index fbe18c3..782b2b5 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -65,4 +65,6 @@
void plat_secondary_cpus_bl31_entry(void);
+void setup_clusterectlr_el1(void);
+
#endif /* SOCFPGA_PRIVATE_H */
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 7f96adb..9e06397 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -153,6 +153,9 @@
/* ATF build version */
#define INTEL_SIP_SMC_ATF_BUILD_VER 0xC200009B
+/* IO96B ECC Error Injection */
+#define INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR 0xC200009C
+
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
@@ -163,6 +166,8 @@
#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
SYSMGR_ECC_DDR0_MASK |\
SYSMGR_ECC_DDR1_MASK)
+#define IOSSM_ECC_ERR_INJ_DELAY_USECS (40U)
+#define IOSSM_CMD_STATUS_RESP_READY BIT(0)
/* Non-mailbox SMC Call */
#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
@@ -255,6 +260,12 @@
#define SMC_RET_ARGS_FOUR (4)
#define SMC_RET_ARGS_FIVE (5)
#define SMC_RET_ARGS_SIX (6)
+#define SMC_RET_ARGS_SEVEN (7)
+#define SMC_RET_ARGS_EIGHT (8)
+#define SMC_RET_ARGS_NINE (9)
+#define SMC_RET_ARGS_TEN (10)
+
+#define MBOX_GEN_CMD_MAX_WORDS (0x1000)
/*
* SiP SVC Version3 SMC Functions IDs
@@ -278,6 +289,14 @@
#define ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP (0x420000E8)
#define ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT (0x420000E9)
+/* RSU related commands */
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT (0x420000EA)
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS (0x420000EB)
+#define ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY (0x420000EC)
+
+/* V3 Generic mailbox command. */
+#define ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD (0x420000EE)
+
/* FCS crypto service VAB/SDOS commands */
#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER (0x4200012C)
#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT (0x4200012D)
@@ -344,6 +363,8 @@
#define GET_CLIENT_ID(x) (((x) & 0xF0) >> 4)
#define GET_JOB_ID(x) ((x) & 0x0F)
+#define GET_ADDR64(high, low) (((uint64_t)(high) \
+ << 32) | (low))
#endif /* SIP_SVC_V3 */
#endif /* SOCFPGA_SIP_SVC_H */
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index b9c7b59..507a9e9 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -25,7 +25,7 @@
static fcs_crypto_service_data fcs_ecdsa_get_pubkey_param;
static fcs_crypto_service_data fcs_ecdh_request_param;
-uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -42,7 +42,7 @@
return ret_args_len;
}
-uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -57,7 +57,7 @@
return ret_args_len;
}
-uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -74,7 +74,7 @@
return ret_args_len;
}
-uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -92,7 +92,7 @@
return ret_args_len;
}
-uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -107,7 +107,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -124,7 +124,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -144,7 +144,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -162,7 +162,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -180,7 +180,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -198,7 +198,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -215,7 +215,7 @@
return ret_args_len;
}
-uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -233,7 +233,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -251,7 +251,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -268,7 +268,7 @@
return ret_args_len;
}
-uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -304,6 +304,17 @@
}
}
+/* As of now used on only Agilex5 platform. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+static bool is_16_bytes_aligned(uint32_t data)
+{
+ if ((data % (MBOX_WORD_BYTE * 4U)) != 0U)
+ return false;
+ else
+ return true;
+}
+#endif
+
static bool is_32_bytes_aligned(uint32_t data)
{
if ((data % (8U * MBOX_WORD_BYTE)) != 0U) {
@@ -2708,7 +2719,7 @@
uint32_t session_id, uint32_t context_id,
uint64_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t dst_size,
- uint32_t aad_size, uint8_t is_finalised,
+ uint32_t padding_size, uint8_t is_finalised,
uint32_t *send_id, uint64_t smmu_src_addr,
uint64_t smmu_dst_addr)
{
@@ -2719,30 +2730,55 @@
uint32_t fcs_aes_crypt_payload[FCS_AES_CMD_MAX_WORD_SIZE];
uint32_t src_addr_sdm = (uint32_t)src_addr;
uint32_t dst_addr_sdm = (uint32_t)dst_addr;
+ bool is_src_size_aligned;
+ bool is_dst_size_aligned;
+ bool is_src_size_valid;
+ bool is_dst_size_valid;
if (fcs_aes_init_payload.session_id != session_id ||
fcs_aes_init_payload.context_id != context_id) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
+
+ /* Default source and destination size align check, 32 bytes alignment. */
+ is_src_size_aligned = is_32_bytes_aligned(src_size);
+ is_dst_size_aligned = is_32_bytes_aligned(dst_size);
+ is_src_size_valid = FCS_AES_DATA_SIZE_CHECK(src_size);
+ is_dst_size_valid = FCS_AES_DATA_SIZE_CHECK(dst_size);
+
+ /*
+ * Get the requested block mode.
+ * On the Agilex5 platform with GCM and GCM-GHASH modes, the source and destination size
+ * should be in multiples of 16 bytes. For other platforms and other modes, it should be
+ * in multiples of 32 bytes.
+ */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ uint32_t block_mode = fcs_aes_init_payload.crypto_param[0] & FCS_CRYPTO_BLOCK_MODE_MASK;
+
+ if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+ (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+ is_src_size_aligned = is_16_bytes_aligned(src_size);
+ is_dst_size_aligned = is_16_bytes_aligned(dst_size);
+ /* The size validity here is, should be 0 or multiples of 16 bytes. */
+ is_src_size_valid = is_16_bytes_aligned(src_size);
+ is_dst_size_valid = is_16_bytes_aligned(dst_size);
+ }
+#endif
if ((!is_8_bytes_aligned(src_addr)) ||
- (!is_32_bytes_aligned(src_size)) ||
+ (!is_src_size_aligned) ||
(!is_address_in_ddr_range(src_addr, src_size))) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
if ((!is_8_bytes_aligned(dst_addr)) ||
- (!is_32_bytes_aligned(dst_size)) ||
+ (!is_dst_size_aligned) ||
(!is_address_in_ddr_range(dst_addr, dst_size))) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- if ((dst_size > FCS_AES_MAX_DATA_SIZE ||
- dst_size < FCS_AES_MIN_DATA_SIZE) ||
- (src_size > FCS_AES_MAX_DATA_SIZE ||
- src_size < FCS_AES_MIN_DATA_SIZE)) {
+ if (!is_src_size_valid || !is_dst_size_valid)
return INTEL_SIP_SMC_STATUS_REJECTED;
- }
/* Prepare crypto header*/
flag = 0;
@@ -2802,11 +2838,14 @@
fcs_aes_crypt_payload[i] = dst_size;
i++;
- /* Additional Authenticated Data size */
- if (aad_size > 0) {
- fcs_aes_crypt_payload[i] = aad_size;
+ /* Padding data size, only on Agilex5 with GCM and GCM-GHASH modes. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+ (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+ fcs_aes_crypt_payload[i] = padding_size;
i++;
}
+#endif
status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE) ||
(smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE)) ?
@@ -2828,7 +2867,7 @@
sizeof(fcs_aes_init_payload));
}
- if (status < 0U) {
+ if (status < 0) {
return INTEL_SIP_SMC_STATUS_ERROR;
}
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 3b3b479..bf1b7fb 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1442,7 +1442,7 @@
}
int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id,
- uint32_t *ret_args, uint32_t *ret_args_len)
+ uint64_t *ret_args, uint32_t *ret_args_len)
{
sdm_command_t *cmd_desc = NULL;
sdm_response_t *resp_desc = NULL;
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f4a3ea0..ff19e23 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -9,6 +9,7 @@
#include <assert.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <tools_share/uuid.h>
@@ -799,10 +800,26 @@
}
return INTEL_SIP_SMC_STATUS_OK;
}
+
+static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command)
+{
+ volatile uint64_t atf_ddr_buffer;
+ volatile uint64_t val;
+
+ mmio_write_32(IOSSM_CMD_PARAM, *syndrome);
+ mmio_write_32(IOSSM_CMD_TRIG_OP, command);
+ udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS);
+ atf_ddr_buffer = 0xCAFEBABEFEEDFACE; /* Write data */
+ memcpy_s((void *)&val, sizeof(val),
+ (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer));
+
+ /* Clear response_ready BIT0 of status_register before sending next command. */
+ mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY);
+}
#endif
#if SIP_SVC_V3
-uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -816,7 +833,7 @@
return ret_args_len;
}
-uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -831,7 +848,7 @@
return ret_args_len;
}
-uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -848,7 +865,7 @@
return ret_args_len;
}
-uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
uint8_t ret_args_len = 0U;
sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -866,35 +883,201 @@
return ret_args_len;
}
+uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ uint32_t retry_counter = ~0U;
+ uint32_t failure_source = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ /* Get the failure source and current image retry counter value from the response. */
+ failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK;
+ retry_counter = resp->resp_data[8];
+
+ if ((retry_counter != ~0U) && (failure_source == 0U))
+ resp->resp_data[5] |= RSU_VERSION_ACMF;
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ /* Current CMF */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]);
+ /* Last Failing CMF Address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]);
+ /* Config State */
+ ret_args[ret_args_len++] = resp->resp_data[4];
+ /* Version */
+ ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]);
+ /* Failure Source */
+ ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16);
+ /* Error location */
+ ret_args[ret_args_len++] = resp->resp_data[6];
+ /* Error details */
+ ret_args[ret_args_len++] = resp->resp_data[7];
+ /* Current image retry counter */
+ ret_args[ret_args_len++] = resp->resp_data[8];
+
+ return ret_args_len;
+}
+
-static uintptr_t smc_ret(void *handle, uint32_t *ret_args, uint32_t ret_args_len)
+uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ /* Sub Partition Table (SPT) 0 address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]);
+ /* Sub Partition Table (SPT) 1 address */
+ ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]);
+
+ return ret_args_len;
+}
+
+static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len)
+{
+
switch (ret_args_len) {
case SMC_RET_ARGS_ONE:
+ VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]);
SMC_RET1(handle, ret_args[0]);
break;
case SMC_RET_ARGS_TWO:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]);
SMC_RET2(handle, ret_args[0], ret_args[1]);
break;
case SMC_RET_ARGS_THREE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2]);
SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]);
break;
case SMC_RET_ARGS_FOUR:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
break;
case SMC_RET_ARGS_FIVE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
break;
+ case SMC_RET_ARGS_SIX:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5]);
+ SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5]);
+ break;
+
+ case SMC_RET_ARGS_SEVEN:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+ "x6 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6]);
+ SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6]);
+ break;
+
+ case SMC_RET_ARGS_EIGHT:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7]);
+ SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7]);
+ break;
+
+ case SMC_RET_ARGS_NINE:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx, x8 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8]);
+ SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+ 0, 0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+
+ case SMC_RET_ARGS_TEN:
+ VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+ "x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n",
+ __func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3],
+ ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+ ret_args[9], ret_args[10]);
+ SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+ ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9],
+ 0, 0, 0, 0, 0, 0, 0, 0);
+ break;
+
default:
+ VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ",
+ __func__, ret_args_len);
SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
break;
}
}
+static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd)
+{
+ /* Check if the command is allowed to be executed in generic mbox format */
+ bool is_cmd_allowed = false;
+
+ switch (cmd) {
+ case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
+ case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
+ case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
+ case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION:
+ /* These commands are not supported in the generic mailbox format. */
+ break;
+
+ default:
+ is_cmd_allowed = true;
+ break;
+ } /* switch */
+
+ return is_cmd_allowed;
+}
+
/*
* This function is responsible for handling all SiP SVC V3 calls from the
* non-secure world.
@@ -929,8 +1112,8 @@
switch (smc_fid) {
case ALTERA_SIP_SMC_ASYNC_RESP_POLL:
{
- uint32_t ret_args[8] = {0};
- uint32_t ret_args_len;
+ uint64_t ret_args[16] = {0};
+ uint32_t ret_args_len = 0;
status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
GET_JOB_ID(x1),
@@ -1177,6 +1360,111 @@
SMC_RET1(handle, status);
}
+ case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_GET_SUBPARTITION_TABLE,
+ NULL,
+ 0,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_rsu_spt,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_RSU_STATUS,
+ NULL,
+ 0,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_rsu_status,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY:
+ {
+ uint32_t notify_code = (uint32_t)x2;
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_HPS_STAGE_NOTIFY,
+ ¬ify_code,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD:
+ {
+ /* Filter the required commands here. */
+ if (!is_gen_mbox_cmd_allowed(smc_fid)) {
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ /* Collect all the args passed in, and send the mailbox command. */
+ uint32_t mbox_cmd = (uint32_t)x2;
+ uint32_t *cmd_payload_addr = NULL;
+ uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE;
+ uint32_t *resp_payload_addr = NULL;
+ uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE;
+
+ if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) ||
+ (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) {
+ ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ /* Make sure we have valid command payload length and buffer */
+ if (cmd_payload_len != 0U) {
+ cmd_payload_addr = (uint32_t *)x3;
+ if (cmd_payload_addr == NULL) {
+ ERROR("MBOX: 0x%x: Command payload address is NULL\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+ }
+
+ /* Make sure we have valid response payload length and buffer */
+ if (resp_payload_len != 0U) {
+ resp_payload_addr = (uint32_t *)x5;
+ if (resp_payload_addr == NULL) {
+ ERROR("MBOX: 0x%x: Response payload address is NULL\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+ }
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ mbox_cmd,
+ (uint32_t *)cmd_payload_addr,
+ cmd_payload_len,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)resp_payload_addr,
+ resp_payload_len);
+
+ SMC_RET1(handle, status);
+ }
+
case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
{
uint32_t session_id = (uint32_t)x2;
@@ -2194,6 +2482,12 @@
SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
VERSION_MINOR, VERSION_PATCH);
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR:
+ intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2);
+ SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
+#endif
+
default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index bdad8b5..81b3551 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -125,7 +125,7 @@
$(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \
$(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c \
$(MARVELL_DRV_BASE)/ddr_phy_access.c \
- drivers/rambus/trng_ip_76.c
+ $(MARVELL_DRV_BASE)/trng.c
ifeq (${MSS_SUPPORT}, 1)
MARVELL_DRV += $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c
diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c
index c4c5c0e..55d316f 100644
--- a/plat/marvell/armada/common/mrvl_sip_svc.c
+++ b/plat/marvell/armada/common/mrvl_sip_svc.c
@@ -9,7 +9,7 @@
#include <common/runtime_svc.h>
#include <drivers/marvell/cache_llc.h>
#include <drivers/marvell/mochi/ap_setup.h>
-#include <drivers/rambus/trng_ip_76.h>
+#include <drivers/marvell/trng.h>
#include <lib/smccc.h>
#include <marvell_plat_priv.h>
@@ -164,12 +164,12 @@
ret = mvebu_ddr_phy_read(x1, (uint16_t *)&read);
SMC_RET2(handle, ret, read);
case MV_SIP_RNG_64:
- if ((x1 % 2 + 1) > sizeof(read)/4) {
- ERROR("%s: Maximum %ld random bytes per SMC call\n",
- __func__, sizeof(read));
+ if (x1 > 1) {
SMC_RET1(handle, SMC_UNK);
}
- ret = eip76_rng_get_random((uint8_t *)&read, 4 * (x1 % 2 + 1));
+
+ ret = mv_trng_get_random32((uint32_t *)&read,
+ ((uint8_t)x1 + 1));
SMC_RET2(handle, ret, read);
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk
index 75cc80a..d2a8fd3 100644
--- a/plat/mediatek/build_helpers/options.mk
+++ b/plat/mediatek/build_helpers/options.mk
@@ -1,27 +1,32 @@
#
-# Copyright (c) 2022-2023, MediaTek Inc. All rights reserved.
+# Copyright (c) 2022-2025, MediaTek Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# call add_defined_option to evaluate MTK defined value
-$(eval $(call add_defined_option,MTK_SIP_KERNEL_BOOT_ENABLE))
-$(eval $(call add_defined_option,PLAT_EXTRA_RODATA_INCLUDES))
-$(eval $(call add_defined_option,MTK_EXTRA_LINKERFILE))
-$(eval $(call add_defined_option,MTK_BL31_AS_BL2))
-$(eval $(call add_defined_option,MTK_BL33_IS_64BIT))
-$(eval $(call add_defined_option,PLAT_XLAT_TABLES_DYNAMIC))
-$(eval $(call add_defined_option,MTK_ADAPTED))
-$(eval $(call add_defined_option,MTK_PUBEVENT_ENABLE))
-$(eval $(call add_defined_option,MTK_SOC))
-$(eval $(call add_defined_option,UART_CLOCK))
-$(eval $(call add_defined_option,UART_BAUDRATE))
-$(eval $(call add_defined_option,CONFIG_MTK_MCUSYS))
-$(eval $(call add_defined_option,CONFIG_MTK_PM_SUPPORT))
-$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_SUPPORT))
-$(eval $(call add_defined_option,CONFIG_MTK_SMP_EN))
-$(eval $(call add_defined_option,CONFIG_MTK_CPU_SUSPEND_EN))
-$(eval $(call add_defined_option,CONFIG_MTK_PM_ARCH))
-$(eval $(call add_defined_option,CONFIG_MTK_CPU_PM_ARCH))
-$(eval $(call add_defined_option,CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND))
-$(eval $(call add_defined_option,CONFIG_MTK_MTCMOS))
+DEFINED_OPTIONS := \
+ CONFIG_MTK_CPU_PM_ARCH \
+ CONFIG_MTK_CPU_PM_SUPPORT \
+ CONFIG_MTK_CPU_SUSPEND_EN \
+ CONFIG_MTK_DISABLE_CACHE_AS_RAM \
+ CONFIG_MTK_MCUSYS \
+ CONFIG_MTK_MTCMOS \
+ CONFIG_MTK_PM_ARCH \
+ CONFIG_MTK_PM_SUPPORT \
+ CONFIG_MTK_SMMU_SID \
+ CONFIG_MTK_SMP_EN \
+ CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND \
+ MTK_ADAPTED \
+ MTK_BL31_AS_BL2 \
+ MTK_BL33_IS_64BIT \
+ MTK_EXTRA_LINKERFILE \
+ MTK_PUBEVENT_ENABLE \
+ MTK_SIP_KERNEL_BOOT_ENABLE \
+ MTK_SOC \
+ PLAT_EXTRA_RODATA_INCLUDES \
+ PLAT_XLAT_TABLES_DYNAMIC \
+ UART_BAUDRATE \
+ UART_CLOCK
+
+$(foreach opt, $(DEFINED_OPTIONS),$(eval $(call add_defined_option,$(opt))))
diff --git a/plat/mediatek/common/cache_ops.c b/plat/mediatek/common/cache_ops.c
new file mode 100644
index 0000000..df43667
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <lib/mmio.h>
+
+#include <cache_ops.h>
+#include <mcucfg.h>
+
+#define L3_SHARE_EN 9
+#define L3_SHARE_PRE_EN 8
+
+void disable_cache_as_ram(void)
+{
+ unsigned long v;
+
+ mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_EN);
+ dsb();
+
+ __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+ v |= (0xf << 4);
+ __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+ dsb();
+
+ do {
+ __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+ } while (((v >> 0x4) & 0xf) != 0xf);
+
+ mmio_clrbits_32(MP0_CLUSTER_CFG0, 1 << L3_SHARE_PRE_EN);
+ dsb();
+}
diff --git a/plat/mediatek/common/cache_ops.h b/plat/mediatek/common/cache_ops.h
new file mode 100644
index 0000000..aeec6be
--- /dev/null
+++ b/plat/mediatek/common/cache_ops.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _CACHES_OPS_H_
+#define _CACHES_OPS_H_
+
+void disable_cache_as_ram(void);
+
+#endif /* _CACHES_OPS_H_ */
diff --git a/plat/mediatek/common/mtk_bl31_lib.c b/plat/mediatek/common/mtk_bl31_lib.c
new file mode 100644
index 0000000..3428471
--- /dev/null
+++ b/plat/mediatek/common/mtk_bl31_lib.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+int mtk_bl31_map_to_sip_error(enum mtk_bl31_status status)
+{
+ switch (status) {
+ case MTK_BL31_STATUS_SUCCESS:
+ return MTK_SIP_E_SUCCESS;
+ case MTK_BL31_STATUS_INVALID_PARAM:
+ return MTK_SIP_E_INVALID_PARAM;
+ case MTK_BL31_STATUS_NOT_SUPPORTED:
+ return MTK_SIP_E_NOT_SUPPORTED;
+ case MTK_BL31_STATUS_INVALID_RANGE:
+ return MTK_SIP_E_INVALID_RANGE;
+ case MTK_BL31_STATUS_PERMISSION_DENY:
+ return MTK_SIP_E_PERMISSION_DENY;
+ case MTK_BL31_STATUS_LOCK_FAIL:
+ return MTK_SIP_E_LOCK_FAIL;
+ default:
+ ERROR("%s: unknown status: %d\n", __func__, status);
+ }
+
+ return MTK_SIP_E_NOT_SUPPORTED;
+}
+
+int mtk_bl31_mmap_add_dynamic_region(unsigned long long base_pa, size_t size,
+ enum mtk_bl31_memory_type type)
+{
+ unsigned int attr;
+
+ switch (type) {
+ case MTK_BL31_DEV_RW_SEC:
+ attr = MT_DEVICE | MT_RW | MT_SECURE;
+ break;
+ default:
+ attr = 0;
+ ERROR("%s: unknown memory type %d\n", __func__, type);
+ break;
+ }
+
+ return mmap_add_dynamic_region(base_pa, base_pa, size, attr);
+}
+
+int mtk_bl31_mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
+{
+ return mmap_remove_dynamic_region(base_va, size);
+}
diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c
index 0d264b9..a6d1e73 100644
--- a/plat/mediatek/common/mtk_bl31_setup.c
+++ b/plat/mediatek/common/mtk_bl31_setup.c
@@ -24,6 +24,9 @@
#endif
/* MTK headers */
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+#include <cache_ops.h>
+#endif
#if MTK_SIP_KERNEL_BOOT_ENABLE
#include <cold_boot.h>
#endif
@@ -101,6 +104,9 @@
u_register_t hw_config, u_register_t plat_params_from_bl2)
{
+#if CONFIG_MTK_DISABLE_CACHE_AS_RAM
+ disable_cache_as_ram();
+#endif
#if COREBOOT
static console_t console;
diff --git a/plat/mediatek/common/rules.mk b/plat/mediatek/common/rules.mk
index 6acc731..66ea8b7 100644
--- a/plat/mediatek/common/rules.mk
+++ b/plat/mediatek/common/rules.mk
@@ -8,7 +8,8 @@
MODULE := mtk_common
-LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_bl31_setup.c
+LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_bl31_lib.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mtk_bl31_setup.c
LOCAL_SRCS-y += ${LOCAL_DIR}/mtk_smc_handlers.c
LOCAL_SRCS-$(MTK_SIP_KERNEL_BOOT_ENABLE) += ${LOCAL_DIR}/cold_boot.c
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
index 632af52..70168d1 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.c
@@ -22,7 +22,15 @@
uint32_t count = 0;
while ((mmio_read_32(reg) & mask) != expect) {
- if (count > retry_times) {
+ /*
+ * If retry_times == HW_SEM_NO_WAIT, it is just for checking if the hardware
+ * semaphore can be locked or not. The purpose is for SMMU to check NPU power
+ * status. Hence, just returning -EBUSY is okay. There is no need to show any
+ * ERROR message here.
+ */
+ if (retry_times == HW_SEM_NO_WAIT) {
+ return -EBUSY;
+ } else if (count > retry_times) {
ERROR("%s: timed out, reg = %x, mask = %x, expect = %x\n",
__func__, reg, mask, expect);
return -EBUSY;
@@ -116,14 +124,14 @@
{
return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
- APU_HW_SEM_SYS_APMCU, HW_SEM_GET, 0, 0);
+ APU_HW_SEM_SYS_APMCU, HW_SEM_GET, HW_SEM_NO_WAIT, 0);
}
int rv_iommu_hw_sem_unlock(void)
{
return apu_hw_sema_ctl_per_mbox(APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_CTRL,
APU_MBOX(APU_HW_SEM_SYS_APMCU) + APU_MBOX_SEMA1_STA,
- APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, 0, 0);
+ APU_HW_SEM_SYS_APMCU, HW_SEM_PUT, HW_SEM_NO_WAIT, 0);
}
int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout,
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
index b5a48e2..17f5500 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_rv_pwr_ctrl.h
@@ -27,6 +27,7 @@
uint8_t bypass);
#define HW_SEM_TIMEOUT (300) /* 300 us */
+#define HW_SEM_NO_WAIT (0) /* no wait */
/* APU MBOX */
#define MBOX_WKUP_CFG (0x80)
diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
index a0d21c6..6edf9c6 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
@@ -6,14 +6,11 @@
#define ENABLE_SMPU_PROTECT (1)
-#if ENABLE_SMPU_PROTECT
-#include "emi.h"
-#endif
-
#include <common/debug.h>
#include <lib/mmio.h>
#include <apusys_security_ctrl_plat.h>
+#include <mtk_bl31_interface.h>
#define APUSYS_SEC_FW_EMI_REGION (23)
@@ -71,9 +68,10 @@
int apusys_plat_setup_sec_mem(void)
{
#if ENABLE_SMPU_PROTECT
- return sip_emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
- (APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >> EMI_MPU_ALIGN_BITS,
- APUSYS_SEC_FW_EMI_REGION);
+ return emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
+ (APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >>
+ EMI_MPU_ALIGN_BITS,
+ APUSYS_SEC_FW_EMI_REGION);
#else
INFO("%s: Bypass SMPU protection setup.\n", __func__);
return 0;
diff --git a/plat/mediatek/drivers/apusys/mt8196/rules.mk b/plat/mediatek/drivers/apusys/mt8196/rules.mk
index aeb6d3d..67243da 100644
--- a/plat/mediatek/drivers/apusys/mt8196/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8196/rules.mk
@@ -8,10 +8,6 @@
MODULE := apusys_${MTK_SOC}
-ifeq (${CONFIG_MTK_APUSYS_EMI_SUPPORT}, y)
-PLAT_INCLUDES += -I${MTK_PLAT}/drivers/emi/common
-endif
-
LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_ammu.c
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_devapc.c
LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c
diff --git a/plat/mediatek/drivers/apusys/rules.mk b/plat/mediatek/drivers/apusys/rules.mk
index 24cc79c..f487c11 100644
--- a/plat/mediatek/drivers/apusys/rules.mk
+++ b/plat/mediatek/drivers/apusys/rules.mk
@@ -13,7 +13,6 @@
PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_CE_SUPPORT))
-$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_EMI_SUPPORT))
$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_LOGTOP_SUPPORT))
$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT))
$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT))
diff --git a/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c b/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
index 563e6b5..a1c903e 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
+++ b/plat/mediatek/drivers/cpu_pm/cpcv5_4/mt_lp_irqremain.c
@@ -7,12 +7,11 @@
#include <stdint.h>
#include <stdio.h>
-#include <drivers/cirq.h>
-
#include <platform_def.h>
#include <lib/pm/mtk_pm.h>
#include <lpm_v2/mt_lp_rm.h>
+#include <mt_cirq.h>
#include "mt_cpu_pm.h"
#include "mt_lp_irqremain.h"
diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c
new file mode 100644
index 0000000..eb4436c
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/pm/mtk_pm.h>
+#include <mtk_bl31_interface.h>
+
+static void *cpu_qos_handle_cluster_on_event_cb(const void *arg)
+{
+ return cpu_qos_handle_cluster_on_event(arg);
+}
+
+MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(cpu_qos_handle_cluster_on_event_cb);
diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c
new file mode 100644
index 0000000..f3540bd
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+void cpu_qos_change_dcc(uint32_t on, uint32_t is_auto)
+{
+}
+
+void *cpu_qos_handle_cluster_on_event(const void *arg)
+{
+ return (void *)arg;
+}
diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk b/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk
new file mode 100644
index 0000000..fa12496
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := cpu_qos_$(MTK_SOC)
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/mtk_cpuqos.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/mtk_cpuqos_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/cpu_qos/rules.mk b/plat/mediatek/drivers/cpu_qos/rules.mk
new file mode 100644
index 0000000..c67a136
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/rules.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+SUB_RULES := $(LOCAL_DIR)/$(MTK_SOC)
+
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES)))
diff --git a/plat/mediatek/drivers/emi/common/emi.h b/plat/mediatek/drivers/emi/common/emi.h
deleted file mode 100644
index eb2a0d3..0000000
--- a/plat/mediatek/drivers/emi/common/emi.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2025, Mediatek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef EMI_H
-#define EMI_H
-
-#include <stdint.h>
-
-#define EMI_MPU_ALIGN_BITS 12
-
-uint64_t sip_emi_mpu_set_protection(u_register_t start, u_register_t end, u_register_t region);
-
-#endif /* EMI_H */
diff --git a/plat/mediatek/drivers/emi/emi_ctrl.c b/plat/mediatek/drivers/emi/emi_ctrl.c
new file mode 100644
index 0000000..00ac7df
--- /dev/null
+++ b/plat/mediatek/drivers/emi/emi_ctrl.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+#define NO_PROTECTION 0
+#define SEC_RW 1
+#define SEC_RW_NSEC_R 2
+#define SEC_RW_NSEC_W 3
+#define SEC_R_NSEC_R 4
+#define FORBIDDEN 5
+#define SEC_R_NSEC_RW 6
+
+#define EMIMPU_SET 0
+#define EMIMPU_CLEAR 1
+#define EMIMPU_READ 2
+#define EMIMPU_SLVERR 3
+#define EMIDBG_DUMP 4
+#define EMIDBG_MSG 5
+#define AID_TABLE_SET 6
+#define EMIMPU_CLEAR_MD 7
+#define KP_SET 8
+#define KP_CLEAR 9
+
+#define EMIMPU_READ_SA 0
+#define EMIMPU_READ_EA 1
+#define EMIMPU_READ_APC 2
+#define EMIMPU_READ_ENABLE 3
+#define EMIMPU_READ_AID 4
+#define EMIMPU_CHECK_NS_CPU 5
+#define EMIMPU_CHECK_REGION_INFO 6
+#define EMIMPU_PAGE_BASE_REGION 7
+#define SLBMPU_CLEAR 8
+#define EMIMPU_CHECK_HP_MOD 9
+#define EMI_CLE 10
+#define SLC_PARITY_SELECT 11
+#define SLC_PARITY_CLEAR 12
+
+static uint64_t emi_mpu_read_by_type(unsigned int reg_type, unsigned int region,
+ unsigned int aid_shift, struct smccc_res *smccc_ret)
+{
+ switch (reg_type) {
+ case EMIMPU_READ_SA:
+ return emi_mpu_read_addr(region, 0x0);
+ case EMIMPU_READ_EA:
+ return emi_mpu_read_addr(region, 0x8);
+ case EMIMPU_READ_ENABLE:
+ return emi_mpu_read_enable(region);
+ case EMIMPU_READ_AID:
+ return emi_mpu_read_aid(region, aid_shift);
+ case EMIMPU_CHECK_REGION_INFO:
+ return emi_mpu_check_region_info(region, &smccc_ret->a1, &smccc_ret->a2);
+ case EMIMPU_CHECK_NS_CPU:
+ return emi_mpu_check_ns_cpu();
+ case EMIMPU_PAGE_BASE_REGION:
+ return emi_mpu_page_base_region();
+ case EMIMPU_CHECK_HP_MOD:
+ return emi_mpu_smc_hp_mod_check();
+ default:
+ return 0;
+ }
+}
+
+static u_register_t sip_emidbg_control(u_register_t op_id,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *handle,
+ struct smccc_res *smccc_ret)
+{
+ enum mtk_bl31_status ret;
+
+ switch (op_id) {
+ case EMIDBG_DUMP:
+ return MTK_SIP_E_SUCCESS;
+ case EMIDBG_MSG:
+ return MTK_SIP_E_SUCCESS;
+#ifdef MTK_EMI_MPU_DEBUG
+ case EMIMPU_READ:
+ ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3,
+ (unsigned int)x4, smccc_ret);
+ break;
+#endif
+ case EMIMPU_CLEAR_MD:
+ ret = emi_clear_md_violation();
+ break;
+ case KP_CLEAR:
+ ret = emi_kp_clear_violation((unsigned int)x2);
+ break;
+#ifdef CONFIG_MTK_SLB_MPU_CLEAR
+ case SLBMPU_CLEAR:
+ ret = slb_clear_violation((unsigned int)x2);
+ break;
+#endif
+#ifdef CONFIG_MTK_EMI_CLEAR
+ case EMI_CLEAR:
+ ret = emi_clear_violation((unsigned int)x2, (unsigned int)x3);
+ break;
+#endif
+#ifdef CONFIG_MTK_SLC_PARITY
+ case SLC_PARITY_SELECT:
+ ret = slc_parity_select((unsigned int)x2, (unsigned int)x3);
+ break;
+ case SLC_PARITY_CLEAR:
+ ret = slc_parity_clear((unsigned int)x2);
+ break;
+#endif
+ default:
+ return MTK_SIP_E_NOT_SUPPORTED;
+ }
+
+ return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_EMIDBG_CONTROL, sip_emidbg_control);
+
+static u_register_t sip_emimpu_control(u_register_t op_id,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *handle,
+ struct smccc_res *smccc_ret)
+{
+ enum mtk_bl31_status ret;
+
+ switch (op_id) {
+ case EMIMPU_SET:
+ ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4);
+ break;
+ case AID_TABLE_SET:
+ ret = emi_mpu_set_aid((unsigned int)x2, (unsigned int)x3);
+ break;
+ case EMIMPU_READ:
+ ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3,
+ (unsigned int)x4, smccc_ret);
+ break;
+ case KP_SET:
+ ret = emi_kp_set_protection((size_t)x2, (size_t)x3, (unsigned int)x4);
+ break;
+ case KP_CLEAR:
+ ret = emi_kp_clear_violation((unsigned int)x2);
+ break;
+ default:
+ return MTK_SIP_E_NOT_SUPPORTED;
+ }
+
+ return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_BL_EMIMPU_CONTROL, sip_emimpu_control);
+
+static u_register_t sip_tee_emimpu_control(u_register_t op_id,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *handle,
+ struct smccc_res *smccc_ret)
+{
+ enum mtk_bl31_status ret;
+
+ switch (op_id) {
+ case EMIMPU_SET:
+ ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4);
+ break;
+ case EMIMPU_CLEAR:
+ ret = emi_clear_protection((unsigned int)x2);
+ break;
+ default:
+ return MTK_SIP_E_NOT_SUPPORTED;
+ }
+
+ return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_TEE_EMI_MPU_CONTROL, sip_tee_emimpu_control);
+
+int emi_mpu_init(void)
+{
+ INFO("[%s] emi mpu initialization\n", __func__);
+
+ emi_protection_init();
+
+ return 0;
+}
+MTK_PLAT_SETUP_0_INIT(emi_mpu_init);
diff --git a/plat/mediatek/drivers/emi/emi_stub.c b/plat/mediatek/drivers/emi/emi_stub.c
index 3682bf7..abe559a 100644
--- a/plat/mediatek/drivers/emi/emi_stub.c
+++ b/plat/mediatek/drivers/emi/emi_stub.c
@@ -3,13 +3,95 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <common/debug.h>
-#include "common/emi.h"
-#include <mtk_sip_svc.h>
+#include <mtk_bl31_interface.h>
-uint64_t sip_emi_mpu_set_protection(u_register_t start, u_register_t end,
- u_register_t region)
+uint64_t emi_mpu_read_addr(unsigned int region, unsigned int offset)
+{
+ return 0;
+}
+
+uint64_t emi_mpu_read_enable(unsigned int region)
+{
+ return 0;
+}
+
+uint64_t emi_mpu_read_aid(unsigned int region, unsigned int aid_shift)
+{
+ return 0;
+}
+
+uint64_t emi_mpu_check_ns_cpu(void)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_kp_set_protection(size_t start, size_t end, unsigned int region)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_kp_clear_violation(unsigned int emiid)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_protection(unsigned int region)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_md_violation(void)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+uint64_t emi_mpu_check_region_info(unsigned int region, uint64_t *sa, uint64_t *ea)
+{
+ return 0;
+}
+
+uint64_t emi_mpu_page_base_region(void)
+{
+ return 0;
+}
+
+uint64_t emi_mpu_smc_hp_mod_check(void)
+{
+ return 0;
+}
+
+enum mtk_bl31_status slb_clear_violation(unsigned int id)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_violation(unsigned int id, unsigned int type)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status slc_parity_select(unsigned int id, unsigned int port)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status slc_parity_clear(unsigned int id)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_mpu_set_aid(unsigned int region, unsigned int num)
+{
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+void emi_protection_init(void)
+{
+}
+
+enum mtk_bl31_status emi_mpu_set_protection(uint32_t start, uint32_t end,
+ unsigned int region)
{
- return MTK_SIP_E_NOT_SUPPORTED;
+ return MTK_BL31_STATUS_NOT_SUPPORTED;
}
diff --git a/plat/mediatek/drivers/emi/rules.mk b/plat/mediatek/drivers/emi/rules.mk
index 9f462bb..ffe1817 100644
--- a/plat/mediatek/drivers/emi/rules.mk
+++ b/plat/mediatek/drivers/emi/rules.mk
@@ -8,8 +8,9 @@
MODULE := emi
+LOCAL_SRCS-y := $(LOCAL_DIR)/emi_ctrl.c
ifeq ($(MTKLIB_PATH),)
-LOCAL_SRCS-y := $(LOCAL_DIR)/emi_stub.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/emi_stub.c
endif
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c
new file mode 100644
index 0000000..50fd2e7
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_iommu_priv.h>
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+/* mm iommu */
+#define SMI_L0_ID (0)
+#define SMI_L1_ID (1)
+#define SMI_L2_ID (2)
+#define SMI_L4_ID (3)
+#define SMI_L7_ID (4)
+#define SMI_L9_ID (5)
+#define SMI_L11_ID (6)
+#define SMI_L13_ID (7)
+#define SMI_L14_ID (8)
+#define SMI_L16_ID (9)
+#define SMI_L17_ID (10)
+#define SMI_L19_ID (11)
+#define SMI_L20_ID (12)
+
+/* infra iommu */
+#define PERICFG_AO_IOMMU_0 (0x90)
+#define PERICFG_AO_IOMMU_1 (0x94)
+#define MMU_DEV_PCIE_0 (0)
+#define IFR_CFG_GROUP_NUM (1)
+
+static struct mtk_smi_larb_config mt8189_larb_cfg[] = {
+ [SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 8, 0),
+ [SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 8, 0),
+ [SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 11, 0),
+ [SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 12, 0),
+ [SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 18, 0),
+ [SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 29, 0),
+ [SMI_L11_ID] = LARB_CFG_ENTRY(SMI_LARB_11_BASE, 29, 0),
+ [SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 15, 0),
+ [SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 10, 0),
+ [SMI_L16_ID] = LARB_CFG_ENTRY(SMI_LARB_16_BASE, 17, 0),
+ [SMI_L17_ID] = LARB_CFG_ENTRY(SMI_LARB_17_BASE, 17, 0),
+ [SMI_L19_ID] = LARB_CFG_ENTRY(SMI_LARB_19_BASE, 4, 0),
+ [SMI_L20_ID] = LARB_CFG_ENTRY(SMI_LARB_20_BASE, 6, 0),
+};
+
+static uint32_t mt8189_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = {
+ PERICFG_AO_BASE,
+};
+static uint32_t mt8189_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = {
+ PERICFG_AO_IOMMU_1,
+};
+static struct mtk_ifr_mst_config mt8189_ifr_mst_cfg[] = {
+ [MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 0),
+};
+
+struct mtk_smi_larb_config *g_larb_cfg = &mt8189_larb_cfg[0];
+const unsigned int g_larb_num = ARRAY_SIZE(mt8189_larb_cfg);
+
+static struct mtk_secure_iommu_config mt8189_secure_iommu_config[] = {
+ SEC_IOMMU_CFG_ENTRY(MM_IOMMU_BASE),
+};
+
+struct mtk_secure_iommu_config *g_sec_iommu_cfg = &mt8189_secure_iommu_config[0];
+const unsigned int g_sec_iommu_num = ARRAY_SIZE(mt8189_secure_iommu_config);
+
+struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8189_ifr_mst_cfg[0];
+const unsigned int g_ifr_mst_num = ARRAY_SIZE(mt8189_ifr_mst_cfg);
+
+uint32_t *g_ifr_mst_cfg_base = &mt8189_ifr_mst_cfg_base[0];
+uint32_t *g_ifr_mst_cfg_offs = &mt8189_ifr_mst_cfg_offs[0];
+
+/**
+ * Protect infra iommu enable setting registers as secure access.
+ * This is removed in MT8189, just return here.
+ */
+void mtk_infra_iommu_enable_protect(void)
+{
+}
diff --git a/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h
new file mode 100644
index 0000000..935036f
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IOMMU_PLAT_H
+#define IOMMU_PLAT_H
+
+/* mm iommu */
+#define ATF_MTK_SMI_LARB_CFG_SUPPORT
+
+/* mm iommu, sec bank dump */
+#define ATF_MTK_IOMMU_CFG_SUPPORT
+
+/* infra iommu */
+#define ATF_MTK_INFRA_MASTER_CFG_SUPPORT
+
+#endif /* IOMMU_PLAT_H */
diff --git a/plat/mediatek/drivers/mminfra/mminfra_common.h b/plat/mediatek/drivers/mminfra/mminfra_common.h
new file mode 100644
index 0000000..93820c7
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mminfra_common.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMINFRA_COMMON_H
+#define MMINFRA_COMMON_H
+
+#define mminfra_info(fmt, args...) INFO("[mminfra] %s: "fmt"\n", __func__, ##args)
+#define mminfra_err(fmt, args...) ERROR("[mminfra] %s: "fmt"\n", __func__, ##args)
+
+#endif
diff --git a/plat/mediatek/drivers/mminfra/mminfra_stub.c b/plat/mediatek/drivers/mminfra/mminfra_stub.c
deleted file mode 100644
index dc37280..0000000
--- a/plat/mediatek/drivers/mminfra/mminfra_stub.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2025, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <drivers/mminfra_public.h>
-
-int mminfra_get_if_in_use(void)
-{
- return 0;
-}
-
-int mminfra_put(void)
-{
- return 0;
-}
diff --git a/plat/mediatek/drivers/mminfra/mt8196/mminfra.c b/plat/mediatek/drivers/mminfra/mt8196/mminfra.c
new file mode 100644
index 0000000..1086c75
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mt8196/mminfra.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <drivers/mminfra_public.h>
+#include <mminfra.h>
+#include <mtk_mmap_pool.h>
+
+static const mmap_region_t mminfra_plat_mmap[] MTK_MMAP_SECTION = {
+ MAP_REGION_FLAT(MMINFRA_HW_VOTER_BASE, PAGE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ {0}
+};
+DECLARE_MTK_MMAP_REGIONS(mminfra_plat_mmap);
+
+static struct mtk_mminfra_pwr_ctrl mminfra_pwr_ctrl = {
+ .hw_voter = {
+ .base = MMINFRA_HW_VOTER_BASE,
+ .set_ofs = 0x104,
+ .clr_ofs = 0x108,
+ .en_ofs = 0x100,
+ .en_shift = 0x1,
+ .done_bits = VLP_AO_RSVD6,
+ },
+ .hw_sema = {
+ .base = SPM_BASE,
+ .offset = SPM_SEMAPHORE_M1,
+ .offset_all = {
+ SPM_SEMAPHORE_M0,
+ SPM_SEMAPHORE_M1,
+ SPM_SEMAPHORE_M2,
+ SPM_SEMAPHORE_M3,
+ SPM_SEMAPHORE_M4,
+ SPM_SEMAPHORE_M5,
+ SPM_SEMAPHORE_M6,
+ SPM_SEMAPHORE_M7,
+ },
+ .set_val = SPM_SEMA_MMINFRA,
+ },
+ .active = true,
+ .ref_cnt = 0,
+};
+
+static int spm_semaphore_get(uint32_t base, uint32_t set_val)
+{
+ int cnt = SEMA_RETRY_CNT;
+ uint32_t val;
+
+ val = mmio_read_32(base);
+ if ((val & set_val) == set_val) {
+ mminfra_err("hw_sem was already got, base:0x%x=0x%x, set_val:0x%x\n",
+ base, val, set_val);
+ return -1;
+ }
+
+ while (cnt > 0) {
+ mmio_write_32(base, set_val);
+ udelay(10);
+ if ((mmio_read_32(base) & set_val) == set_val)
+ return 0;
+ cnt--;
+ }
+
+ mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val);
+ return -1;
+}
+
+static int spm_semaphore_release(uint32_t base, uint32_t set_val)
+{
+ int cnt = SEMA_RETRY_CNT;
+ uint32_t val;
+
+ val = mmio_read_32(base);
+ if ((val & set_val) != set_val) {
+ mminfra_err("hw_sem was already released, base:0x%x=0x%x, set_val:0x%x\n",
+ base, val, set_val);
+ return -1;
+ }
+ do {
+ mmio_write_32(base, set_val);
+ udelay(10);
+ if (cnt-- < 0) {
+ if ((mmio_read_32(base) & set_val) != set_val)
+ return 0;
+ mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val);
+ return -1;
+ }
+ } while ((mmio_read_32(base) & set_val) == set_val);
+
+ return 0;
+}
+
+static int mminfra_hw_sema_ctrl(struct mminfra_hw_sema *hw_sema, bool is_get)
+{
+ int i, ret;
+
+ if (!hw_sema)
+ return 0;
+
+ if (is_get)
+ ret = spm_semaphore_get(hw_sema->base + hw_sema->offset, hw_sema->set_val);
+ else
+ ret = spm_semaphore_release(hw_sema->base + hw_sema->offset, hw_sema->set_val);
+
+ if (ret)
+ for (i = 0; i < SPM_SEMA_MMINFRA_NR; i++)
+ mminfra_err("0x%x=0x%x\n", hw_sema->base + hw_sema->offset_all[i],
+ mmio_read_32(hw_sema->base + hw_sema->offset_all[i]));
+
+ return ret;
+}
+
+static bool is_mminfra_ready(struct mminfra_hw_voter *hw_voter)
+{
+ if (!hw_voter)
+ return false;
+
+ return !!(mmio_read_32(hw_voter->done_bits) & MMINFRA_DONE);
+}
+
+static int mminfra_hwv_power_ctrl(struct mminfra_hw_voter *hw_voter, bool is_on)
+{
+ uint32_t vote_ofs, vote_mask, vote_ack;
+ uint32_t val = 0, cnt;
+
+ vote_mask = BIT(hw_voter->en_shift);
+ vote_ofs = is_on ? hw_voter->set_ofs : hw_voter->clr_ofs;
+ vote_ack = is_on ? vote_mask : 0x0;
+
+ /* Vote on off */
+ cnt = 0;
+ do {
+ mmio_write_32(hw_voter->base + vote_ofs, vote_mask);
+ udelay(MTK_POLL_HWV_VOTE_US);
+ val = mmio_read_32(hw_voter->base + hw_voter->en_ofs);
+ if ((val & vote_mask) == vote_ack)
+ break;
+
+ if (cnt > MTK_POLL_HWV_VOTE_CNT) {
+ mminfra_err("vote mminfra timeout, is_on:%d, 0x%x=0x%x\n",
+ is_on, hw_voter->base + hw_voter->en_ofs, val);
+ return -1;
+ }
+ cnt++;
+ } while (1);
+
+ if (!is_on)
+ return 0;
+
+ /* Confirm done bits */
+ cnt = 0;
+ while (cnt < MTK_POLL_DONE_RETRY) {
+ if (is_mminfra_ready(hw_voter))
+ return 0;
+ udelay(MTK_POLL_DONE_DELAY_US);
+ cnt++;
+ }
+
+ mminfra_err("polling mminfra done timeout, 0x%x=0x%x\n",
+ hw_voter->done_bits, val);
+ return -1;
+}
+
+int mminfra_get_if_in_use(void)
+{
+ int ret, is_on = MMINFRA_RET_POWER_OFF;
+
+ if (!mminfra_pwr_ctrl.active) {
+ mminfra_err("not ready\n");
+ return MMINFRA_RET_POWER_OFF;
+ }
+
+ spin_lock(&mminfra_pwr_ctrl.lock);
+ if (mminfra_pwr_ctrl.ref_cnt > 0) {
+ mminfra_pwr_ctrl.ref_cnt++;
+ is_on = MMINFRA_RET_POWER_ON;
+ spin_unlock(&mminfra_pwr_ctrl.lock);
+ return is_on;
+ }
+
+ ret = mminfra_hw_sema_ctrl(&mminfra_pwr_ctrl.hw_sema, true);
+ if (ret)
+ goto err;
+
+ /* Check if mminfra is in use */
+ if (is_mminfra_ready(&mminfra_pwr_ctrl.hw_voter)) {
+ ret = mminfra_hwv_power_ctrl(&mminfra_pwr_ctrl.hw_voter, true);
+ if (ret) {
+ mminfra_err("vote for mminfra fail, ret=%d\n", ret);
+ goto err;
+ }
+ mminfra_pwr_ctrl.ref_cnt++;
+ is_on = MMINFRA_RET_POWER_ON;
+ } else {
+ is_on = MMINFRA_RET_POWER_OFF;
+ }
+
+ ret = mminfra_hw_sema_ctrl(&mminfra_pwr_ctrl.hw_sema, false);
+ if (ret)
+ goto err;
+ ret = is_on; /* Return power is on or off. */
+err:
+ spin_unlock(&mminfra_pwr_ctrl.lock);
+ return ret;
+}
+
+int mminfra_put(void)
+{
+ if (!mminfra_pwr_ctrl.active) {
+ mminfra_err("not ready\n");
+ return 0;
+ }
+
+ spin_lock(&mminfra_pwr_ctrl.lock);
+ mminfra_pwr_ctrl.ref_cnt--;
+ if (mminfra_pwr_ctrl.ref_cnt > 0)
+ goto out;
+
+ mminfra_hwv_power_ctrl(&mminfra_pwr_ctrl.hw_voter, false);
+out:
+ spin_unlock(&mminfra_pwr_ctrl.lock);
+ return 0;
+}
diff --git a/plat/mediatek/drivers/mminfra/mt8196/mminfra.h b/plat/mediatek/drivers/mminfra/mt8196/mminfra.h
new file mode 100644
index 0000000..fcee08c
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mt8196/mminfra.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMINFRA_H
+#define MMINFRA_H
+
+#include <lib/spinlock.h>
+
+#include "../mminfra_common.h"
+#include <platform_def.h>
+
+#define VLP_AO_RSVD6 (MTK_VLP_TRACER_MON_BASE + 0x918)
+#define MMINFRA_DONE (1U << 0)
+
+#define SPM_SEMA_MMINFRA (1U << 5)
+#define SPM_SEMA_MMINFRA_NR (8)
+
+#define SEMA_RETRY_CNT (500)
+
+#define SPM_SEMAPHORE_M0 (0x69C)
+#define SPM_SEMAPHORE_M1 (0x6A0)
+#define SPM_SEMAPHORE_M2 (0x6A4)
+#define SPM_SEMAPHORE_M3 (0x6A8)
+#define SPM_SEMAPHORE_M4 (0x6AC)
+#define SPM_SEMAPHORE_M5 (0x6B0)
+#define SPM_SEMAPHORE_M6 (0x6B4)
+#define SPM_SEMAPHORE_M7 (0x6B8)
+
+#define MMINFRA_HW_VOTER_BASE (0x31A80000)
+#define MTK_POLL_HWV_VOTE_US (2)
+#define MTK_POLL_HWV_VOTE_CNT (2500)
+#define MTK_POLL_DONE_DELAY_US (1)
+#define MTK_POLL_DONE_RETRY (3000)
+
+struct mminfra_hw_sema {
+ uint32_t base;
+ uint32_t offset;
+ uint32_t offset_all[SPM_SEMA_MMINFRA_NR];
+ uint32_t set_val;
+};
+
+struct mminfra_hw_voter {
+ uint32_t base;
+ uint32_t set_ofs;
+ uint32_t clr_ofs;
+ uint32_t en_ofs;
+ uint32_t en_shift;
+ uint32_t done_bits;
+};
+
+struct mtk_mminfra_pwr_ctrl {
+ spinlock_t lock;
+ struct mminfra_hw_voter hw_voter;
+ struct mminfra_hw_sema hw_sema;
+ uint32_t ref_cnt;
+ bool active;
+};
+
+#endif
diff --git a/plat/mediatek/drivers/mminfra/rules.mk b/plat/mediatek/drivers/mminfra/rules.mk
index f3a6822..cd5d607 100644
--- a/plat/mediatek/drivers/mminfra/rules.mk
+++ b/plat/mediatek/drivers/mminfra/rules.mk
@@ -8,10 +8,9 @@
MODULE := mminfra
-PLAT_INCLUDES += -I${MTK_PLAT}/include/drivers/
+PLAT_INCLUDES += -I$(MTK_PLAT)/include/drivers/
+PLAT_INCLUDES += -I$(MTK_PLAT)/drivers/mminfra/$(MTK_SOC)
-ifeq ($(MTKLIB_PATH),)
-LOCAL_SRCS-y := ${LOCAL_DIR}/mminfra_stub.c
-endif
+LOCAL_SRCS-y := $(LOCAL_DIR)/$(MTK_SOC)/mminfra.c
$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/slbc/mt8196/rules.mk b/plat/mediatek/drivers/slbc/mt8196/rules.mk
new file mode 100644
index 0000000..eabddfa
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/mt8196/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := slbc_$(MTK_SOC)
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/slbc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/slbc/mt8196/slbc.c b/plat/mediatek/drivers/slbc/mt8196/slbc.c
new file mode 100644
index 0000000..5f7b1e1
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/mt8196/slbc.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+#define MODULE_TAG "[SLBC]"
+
+enum {
+ MTK_SLBC_KERNEL_OP_CPU_DCC = 0,
+};
+
+static u_register_t slbc_kernel_handler(u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4,
+ void *handle,
+ struct smccc_res *smccc_ret)
+{
+ uint32_t request_ops = (uint32_t)x1;
+ u_register_t ret = 0;
+
+ switch (request_ops) {
+ case MTK_SLBC_KERNEL_OP_CPU_DCC:
+ cpu_qos_change_dcc(x2, x3);
+ break;
+ default:
+ ERROR("%s: %s, unknown request_ops = %x\n", MODULE_TAG, __func__, request_ops);
+ ret = EIO;
+ break;
+ }
+
+ VERBOSE("%s: %s, request_ops = %x, ret = %lu\n", MODULE_TAG, __func__, request_ops, ret);
+ return ret;
+}
+
+/* Register SiP SMC service */
+DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_SLBC_CONTROL, slbc_kernel_handler);
diff --git a/plat/mediatek/drivers/slbc/rules.mk b/plat/mediatek/drivers/slbc/rules.mk
new file mode 100644
index 0000000..93fd1b8
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/rules.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := slbc
+
+LOCAL_SOC_DIR := $(LOCAL_DIR)/$(MTK_SOC)
+PLATFORM_DIR_EXIST := $(shell test -f $(LOCAL_SOC_DIR)/rules.mk && echo yes)
+
+ifeq ($(PLATFORM_DIR_EXIST), yes)
+SUB_RULES-y := $(LOCAL_SOC_DIR)
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
+endif
diff --git a/plat/mediatek/drivers/smmu/smmu.c b/plat/mediatek/drivers/smmu/smmu.c
index 4d31071..a3d83ec 100644
--- a/plat/mediatek/drivers/smmu/smmu.c
+++ b/plat/mediatek/drivers/smmu/smmu.c
@@ -255,9 +255,6 @@
break;
}
- if (ret)
- ERROR(TAG "%s, smmu_%u cmd:%u fail:%u\n", __func__, smmu_id, cmd_id, ret);
-
return ret;
}
/* Register MTK SMMU service */
diff --git a/plat/mediatek/drivers/smmu_sid/rules.mk b/plat/mediatek/drivers/smmu_sid/rules.mk
new file mode 100644
index 0000000..9c6dfc8
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/rules.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := smmu_sid
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/smmu_sid.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/smmu_sid_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/smmu_sid/smmu_sid.c b/plat/mediatek/drivers/smmu_sid/smmu_sid.c
new file mode 100644
index 0000000..2d852b6
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/smmu_sid.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_bl31_interface.h>
+
+static int mtk_smmu_sid_init(void)
+{
+ return smmu_sid_init();
+}
+
+MTK_PLAT_SETUP_0_INIT(mtk_smmu_sid_init);
diff --git a/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c b/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c
new file mode 100644
index 0000000..2ed162c
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+int smmu_sid_init(void)
+{
+ return 0;
+}
diff --git a/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c b/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c
new file mode 100644
index 0000000..2db07bf
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/pmic/pmic_set_lowpower.h>
+#if defined(CONFIG_MTK_MTCMOS)
+#include <mtcmos.h>
+#endif
+#include <mtk_bl31_interface.h>
+
+static void ufs_vsx_lpm(bool lpm, uint64_t ufs_version)
+{
+ if (lpm) {
+ /* MT6363 VS2 voter LOW byte BIT6 vote reduce VS2 voltage */
+ PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_CLR);
+
+ /* VS2 buck can enter LPM */
+ PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_LP);
+ } else {
+ /* MT6363 VS2 voter LOW byte BIT6 vote raise VS2 voltage */
+ PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_SET);
+
+ /* VS2 buck can not enter LPM */
+ PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_ONLV);
+ }
+}
+
+void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version)
+{
+ if (vcc_on)
+ ufs_vsx_lpm(false, ufs_version);
+ else
+ ufs_vsx_lpm(true, ufs_version);
+}
+
+int ufs_spm_mtcmos_power(bool on)
+{
+#if defined(CONFIG_MTK_MTCMOS)
+ return spm_mtcmos_ctrl_ufs0(on ? STA_POWER_ON : STA_POWER_DOWN);
+#else
+ return 0;
+#endif
+}
+
+int ufs_phy_spm_mtcmos_power(bool on)
+{
+#if defined(CONFIG_MTK_MTCMOS)
+ return spm_mtcmos_ctrl_ufs0_phy(on ? STA_POWER_ON : STA_POWER_DOWN);
+#else
+ return 0;
+#endif
+}
diff --git a/plat/mediatek/drivers/ufs/rules.mk b/plat/mediatek/drivers/ufs/rules.mk
new file mode 100644
index 0000000..13d3f53
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/rules.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := ufs
+
+PLAT_INCLUDES += -I$(LOCAL_DIR)
+PLAT_INCLUDES += -I$(MTK_PLAT)/include/drivers/
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/ufs_ctrl.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/$(MTK_SOC)/ufs_ctrl_soc.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/ufs_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/ufs/ufs_ctrl.c b/plat/mediatek/drivers/ufs/ufs_ctrl.c
new file mode 100644
index 0000000..14d0616
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/ufs_ctrl.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+/* MTK header */
+#include <drivers/pmic/pmic_swap_api.h>
+#include <lpm_v2/mt_lp_api.h>
+#include <lpm_v2/mt_lp_rq.h>
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+/* UFS generic control flags */
+#define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
+#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
+#define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
+#define UFS_MTK_SIP_REF_CLK_NOTIFICATION BIT(3)
+#define UFS_MTK_SIP_SRAM_PWR_CTRL BIT(5)
+#define UFS_MTK_SIP_GET_VCC_INFO BIT(6)
+#define UFS_MTK_SIP_DEVICE_PWR_CTRL BIT(7)
+#define UFS_MTK_SIP_MPHY_CTRL BIT(8)
+#define UFS_MTK_SIP_MTCMOS_CTRL BIT(9)
+
+enum {
+ VCC_NONE = 0,
+ VCC_1,
+ VCC_2,
+};
+
+static void ufs_get_vcc_info(struct smccc_res *smccc_ret)
+{
+ if (smccc_ret == NULL)
+ return;
+
+ if (is_second_pmic_pp_swap())
+ smccc_ret->a1 = VCC_2;
+ else
+ smccc_ret->a1 = VCC_1;
+}
+
+/* SPM resource control */
+#define RSC_MEM (MT_LP_RQ_DRAM | MT_LP_RQ_EMI)
+#define RSC_PMIC MT_LP_RQ_PMIC
+
+static int ufs_rsc_ctrl(unsigned int rsc, bool hold)
+{
+ static struct mt_lp_resource_user ufs_res_user;
+ int ret = -1;
+
+ if (!ufs_res_user.uid) {
+ ret = mt_lp_resource_user_register("UFS", &ufs_res_user);
+
+ if (ret) {
+ WARN("%s: register lp resource failed\n", __func__);
+ return ret;
+ }
+ }
+
+ if (hold)
+ ret = ufs_res_user.request(&ufs_res_user, rsc);
+ else
+ ret = ufs_res_user.release(&ufs_res_user);
+
+ VERBOSE("%s: rsc=%d, hold=%d\n", __func__, rsc, hold);
+
+ if (ret)
+ WARN("%s: RSC_%d %s failed\n", __func__, rsc, hold ? "request" : "release");
+
+ return ret;
+}
+
+int ufs_rsc_ctrl_mem(bool hold)
+{
+ return ufs_rsc_ctrl(RSC_MEM, hold);
+}
+
+int ufs_rcs_ctrl_pmic(bool hold)
+{
+ return ufs_rsc_ctrl(RSC_PMIC, hold);
+}
+
+/* UFS clock status */
+static uint32_t ufs_clk_sta = UFS_REF_CLK_ON;
+
+bool ufs_is_clk_status_off(void)
+{
+ return ufs_clk_sta == UFS_REF_CLK_OFF;
+}
+
+void ufs_set_clk_status(bool on)
+{
+ if (on)
+ ufs_clk_sta = UFS_REF_CLK_ON;
+ else
+ ufs_clk_sta = UFS_REF_CLK_OFF;
+}
+
+static u_register_t ufs_knl_ctrl(u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *handle,
+ struct smccc_res *smccc_ret)
+{
+ uint64_t ret = 0;
+
+ switch (x1) {
+ case UFS_MTK_SIP_VA09_PWR_CTRL:
+ ufs_mphy_va09_cg_ctrl(!!x2);
+ break;
+ case UFS_MTK_SIP_DEVICE_RESET:
+ ufs_device_reset_ctrl(!!x2);
+ break;
+ case UFS_MTK_SIP_CRYPTO_CTRL:
+ ufs_crypto_hie_init();
+ break;
+ case UFS_MTK_SIP_REF_CLK_NOTIFICATION:
+ ufs_ref_clk_status(x2, x3);
+ break;
+ case UFS_MTK_SIP_SRAM_PWR_CTRL:
+ ufs_sram_pwr_ctrl(x2);
+ break;
+ case UFS_MTK_SIP_GET_VCC_INFO:
+ ufs_get_vcc_info(smccc_ret);
+ break;
+ case UFS_MTK_SIP_DEVICE_PWR_CTRL:
+ ufs_device_pwr_ctrl(x2, x3);
+ break;
+ case UFS_MTK_SIP_MPHY_CTRL:
+ ufs_mphy_ctrl(x2);
+ break;
+ case UFS_MTK_SIP_MTCMOS_CTRL:
+#if defined(CONFIG_MTK_MTCMOS)
+ ufs_mtcmos_ctrl(!!x2);
+#endif
+ break;
+ default:
+ ret = -1;
+ WARN("[UFS] invalid argument 0x%lx from kernel\n", x1);
+ break;
+ }
+
+ return ret;
+}
+
+static u_register_t ufs_bl_ctrl(u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *handle,
+ struct smccc_res *smccc_ret)
+{
+ uint64_t ret = 0;
+
+ switch (x1) {
+ case UFS_MTK_SIP_DEVICE_RESET:
+ ufs_device_reset_ctrl(x2);
+ break;
+ default:
+ ret = -1;
+ WARN("[UFS] invalid argument 0x%lx from bootloader\n", x1);
+ break;
+ }
+
+ return ret;
+}
+
+DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_UFS_CONTROL, ufs_knl_ctrl);
+DECLARE_SMC_HANDLER(MTK_SIP_BL_UFS_CONTROL, ufs_bl_ctrl);
diff --git a/plat/mediatek/drivers/ufs/ufs_stub.c b/plat/mediatek/drivers/ufs/ufs_stub.c
new file mode 100644
index 0000000..c03f27e
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/ufs_stub.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+void ufs_mphy_va09_cg_ctrl(bool enable) {}
+void ufs_device_reset_ctrl(bool rst_n) {}
+void ufs_crypto_hie_init(void) {}
+void ufs_ref_clk_status(uint32_t on, enum ufs_notify_change_status stage) {}
+void ufs_sram_pwr_ctrl(bool on) {}
+void ufs_device_pwr_ctrl(bool vcc_on, uint64_t ufs_version) {}
+void ufs_mphy_ctrl(enum ufs_mtk_mphy_op op) {}
+void ufs_mtcmos_ctrl(bool on) {}
diff --git a/plat/mediatek/include/mtk_bl31_interface.h b/plat/mediatek/include/mtk_bl31_interface.h
new file mode 100644
index 0000000..208276c
--- /dev/null
+++ b/plat/mediatek/include/mtk_bl31_interface.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_BL31_INTERFACE_H__
+#define __MTK_BL31_INTERFACE_H__
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+enum mtk_bl31_status {
+ MTK_BL31_STATUS_SUCCESS = 0,
+ MTK_BL31_STATUS_INVALID_PARAM = -1,
+ MTK_BL31_STATUS_NOT_SUPPORTED = -2,
+ MTK_BL31_STATUS_INVALID_RANGE = -3,
+ MTK_BL31_STATUS_PERMISSION_DENY = -4,
+ MTK_BL31_STATUS_LOCK_FAIL = -5,
+};
+
+int mtk_bl31_map_to_sip_error(enum mtk_bl31_status status);
+
+enum mtk_bl31_memory_type {
+ MTK_BL31_DEV_RW_SEC = 0,
+};
+
+int mtk_bl31_mmap_add_dynamic_region(unsigned long long base_pa, size_t size,
+ enum mtk_bl31_memory_type attr);
+int mtk_bl31_mmap_remove_dynamic_region(uintptr_t base_va, size_t size);
+
+/* UFS definitions */
+enum ufs_mtk_mphy_op {
+ UFS_MPHY_BACKUP = 0,
+ UFS_MPHY_RESTORE,
+};
+
+enum ufs_notify_change_status {
+ PRE_CHANGE,
+ POST_CHANGE,
+};
+
+/* UFS interfaces */
+void ufs_mphy_va09_cg_ctrl(bool enable);
+void ufs_device_reset_ctrl(bool rst_n);
+void ufs_crypto_hie_init(void);
+void ufs_ref_clk_status(uint32_t on, enum ufs_notify_change_status stage);
+void ufs_sram_pwr_ctrl(bool on);
+void ufs_device_pwr_ctrl(bool vcc_on, uint64_t ufs_version);
+void ufs_mphy_ctrl(enum ufs_mtk_mphy_op op);
+void ufs_mtcmos_ctrl(bool on);
+
+/* UFS functions implemented in the public ATF repo */
+int ufs_rsc_ctrl_mem(bool hold);
+int ufs_rsc_ctrl_pmic(bool hold);
+void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version);
+int ufs_spm_mtcmos_power(bool on);
+int ufs_phy_spm_mtcmos_power(bool on);
+bool ufs_is_clk_status_off(void);
+void ufs_set_clk_status(bool on);
+
+/* EMI interfaces */
+uint64_t emi_mpu_read_addr(unsigned int region, unsigned int offset);
+uint64_t emi_mpu_read_enable(unsigned int region);
+uint64_t emi_mpu_read_aid(unsigned int region, unsigned int aid_shift);
+uint64_t emi_mpu_check_ns_cpu(void);
+enum mtk_bl31_status emi_mpu_set_protection(uint32_t start, uint32_t end,
+ unsigned int region);
+enum mtk_bl31_status emi_kp_set_protection(size_t start, size_t end, unsigned int region);
+enum mtk_bl31_status emi_kp_clear_violation(unsigned int emiid);
+enum mtk_bl31_status emi_clear_protection(unsigned int region);
+enum mtk_bl31_status emi_clear_md_violation(void);
+uint64_t emi_mpu_check_region_info(unsigned int region, uint64_t *sa, uint64_t *ea);
+uint64_t emi_mpu_page_base_region(void);
+uint64_t emi_mpu_smc_hp_mod_check(void);
+enum mtk_bl31_status slb_clear_violation(unsigned int id);
+enum mtk_bl31_status emi_clear_violation(unsigned int id, unsigned int type);
+enum mtk_bl31_status slc_parity_select(unsigned int id, unsigned int port);
+enum mtk_bl31_status slc_parity_clear(unsigned int id);
+enum mtk_bl31_status emi_mpu_set_aid(unsigned int region, unsigned int num);
+void emi_protection_init(void);
+
+/* CPU QoS interfaces */
+void cpu_qos_change_dcc(uint32_t on, uint32_t is_auto);
+void *cpu_qos_handle_cluster_on_event(const void *arg);
+
+/* SMMU sid interfaces */
+int smmu_sid_init(void);
+
+#endif /* __MTK_BL31_INTERFACE_H__ */
diff --git a/plat/mediatek/mt8189/include/platform_def.h b/plat/mediatek/mt8189/include/platform_def.h
index 66bec16..067ebcc 100644
--- a/plat/mediatek/mt8189/include/platform_def.h
+++ b/plat/mediatek/mt8189/include/platform_def.h
@@ -45,6 +45,44 @@
#define UART_BAUDRATE (115200)
/*******************************************************************************
+ * Infra IOMMU related constants
+ ******************************************************************************/
+#define PERICFG_AO_BASE (IO_PHYS + 0x01036000)
+#define PERICFG_AO_REG_SIZE (0x1000)
+
+/*******************************************************************************
+ * CIRQ related constants
+ ******************************************************************************/
+#define SYS_CIRQ_BASE (IO_PHYS + 204000)
+#define MD_WDT_IRQ_BIT_ID (519)
+#define CIRQ_REG_NUM (19)
+#define CIRQ_SPI_START (128)
+#define CIRQ_IRQ_NUM (598)
+
+/*******************************************************************************
+ * MM IOMMU & SMI related constants
+ ******************************************************************************/
+#define SMI_LARB_0_BASE (IO_PHYS + 0x0401c000)
+#define SMI_LARB_1_BASE (IO_PHYS + 0x0401d000)
+#define SMI_LARB_2_BASE (IO_PHYS + 0x0f002000)
+#define SMI_LARB_4_BASE (IO_PHYS + 0x0602e000)
+#define SMI_LARB_7_BASE (IO_PHYS + 0x07010000)
+#define SMI_LARB_9_BASE (IO_PHYS + 0x0502e000)
+#define SMI_LARB_11_BASE (IO_PHYS + 0x0582e000)
+#define SMI_LARB_13_BASE (IO_PHYS + 0x0a001000)
+#define SMI_LARB_14_BASE (IO_PHYS + 0x0a002000)
+#define SMI_LARB_16_BASE (IO_PHYS + 0x0a00f000)
+#define SMI_LARB_17_BASE (IO_PHYS + 0x0a010000)
+#define SMI_LARB_19_BASE (IO_PHYS + 0x0b10f000)
+#define SMI_LARB_20_BASE (IO_PHYS + 0x0b00f000)
+#define SMI_LARB_REG_RNG_SIZE (0x1000)
+
+#define MM_IOMMU_BASE (IO_PHYS + 0x0e802000 + 0x4000)
+#define APU_IOMMU_BASE (IO_PHYS + 0x09010000)
+
+#define IOMMU_REG_RNG_SIZE (0x5000)
+
+/*******************************************************************************
* System counter frequency related constants
******************************************************************************/
#define SYS_COUNTER_FREQ_IN_HZ (13000000)
@@ -81,6 +119,18 @@
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE (MT_GIC_BASE)
+#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 300
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+
+/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
diff --git a/plat/mediatek/mt8189/plat_config.mk b/plat/mediatek/mt8189/plat_config.mk
index 6b4064a..f06555b 100644
--- a/plat/mediatek/mt8189/plat_config.mk
+++ b/plat/mediatek/mt8189/plat_config.mk
@@ -21,6 +21,7 @@
#
MCUSYS_VERSION := v1
PLAT_EXTRA_RODATA_INCLUDES := 1
+CONFIG_MTK_DISABLE_CACHE_AS_RAM := $(COREBOOT)
# Configs for A78 and A55
CTX_INCLUDE_AARCH32_REGS := 0
diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
index 31a5ed5..c0c0427 100644
--- a/plat/mediatek/mt8189/platform.mk
+++ b/plat/mediatek/mt8189/platform.mk
@@ -27,6 +27,9 @@
MODULES-y += $(MTK_PLAT)/lib/mtk_init
MODULES-y += $(MTK_PLAT)/lib/pm
MODULES-y += $(MTK_PLAT)/topology
+MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/gic600
+MODULES-y += $(MTK_PLAT)/drivers/iommu
MODULES-y += $(MTK_PLAT)/drivers/mcusys
MODULES-y += $(MTK_PLAT)/drivers/timer
@@ -50,6 +53,10 @@
$(MTK_PLAT)/$(MTK_SOC)/drivers/gpio/mtgpio.c \
$(MTK_PLAT)/$(MTK_SOC)/plat_mmap.c
+ifeq (${CONFIG_MTK_DISABLE_CACHE_AS_RAM}, 1)
+BL31_SOURCES += ${MTK_PLAT}/common/cache_ops.c
+endif
+
include plat/mediatek/build_helpers/mtk_build_helpers_epilogue.mk
include lib/coreboot/coreboot.mk
diff --git a/plat/mediatek/mt8196/include/platform_def.h b/plat/mediatek/mt8196/include/platform_def.h
index 363c8cc..fb5212a 100644
--- a/plat/mediatek/mt8196/include/platform_def.h
+++ b/plat/mediatek/mt8196/include/platform_def.h
@@ -230,6 +230,7 @@
#define SUB_EMI_APB_BASE (IO_PHYS + 0x00529000)
#define SUB_INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00525000)
#define SUB_INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00504000)
+#define EMI_MPU_ALIGN_BITS 12
/*******************************************************************************
* System counter frequency related constants
@@ -341,4 +342,10 @@
#define SSPM_CFGREG_BASE (IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET)
#define SSPM_CFGREG_SIZE (0x1000)
+/*******************************************************************************
+ * MMinfra related constants
+ ******************************************************************************/
+#define MTK_VLP_TRACER_MON_BASE (IO_PHYS + 0x0c000000)
+#define MTK_VLP_TRACER_MON_REG_SIZE (0x1000)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index 84a25e9..e0dd87e 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk
@@ -27,7 +27,6 @@
CONFIG_ARCH_ARM_V9 := y
CONFIG_MTK_APUSYS_CE_SUPPORT := y
-CONFIG_MTK_APUSYS_EMI_SUPPORT := y
CONFIG_MTK_APUSYS_LOGTOP_SUPPORT := y
CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT := y
CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT := y
@@ -50,6 +49,7 @@
CPU_PWR_TOPOLOGY := group_4_3_1
CPU_PM_CORE_ARCH64_ONLY := y
CPU_PM_DOMAIN_CORE_ONLY := n
+CPU_PM_IRQ_REMAIN_ENABLE := y
CPU_PM_SUSPEND_NOTIFY := y
CONFIG_MTK_SPM_SUPPORT := y
CONFIG_MTK_SPM_COMMON_SUPPORT := y
@@ -60,6 +60,7 @@
CONFIG_MTK_PMIC_LOWPOWER := y
CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
CONFIG_MTK_PMIC_SPT_SUPPORT := n
+CONFIG_MTK_SMMU_SID := y
CONFIG_MTK_SPMI := y
PMIC_CHIP := mt6363
diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk
index 172a074..e98ec4b 100644
--- a/plat/mediatek/mt8196/platform.mk
+++ b/plat/mediatek/mt8196/platform.mk
@@ -45,19 +45,23 @@
MODULES-y += $(MTK_PLAT)/lib/system_reset
MODULES-y += $(MTK_PLAT)/drivers/apusys
MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/cpu_qos
MODULES-y += $(MTK_PLAT)/drivers/dp
MODULES-y += $(MTK_PLAT)/drivers/emi
MODULES-y += $(MTK_PLAT)/drivers/gicv3
MODULES-y += $(MTK_PLAT)/drivers/mcusys
MODULES-y += $(MTK_PLAT)/drivers/mminfra
+MODULES-y += $(MTK_PLAT)/drivers/slbc
MODULES-y += $(MTK_PLAT)/drivers/smmu
MODULES-y += $(MTK_PLAT)/drivers/spm
MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-y += $(MTK_PLAT)/drivers/ufs
MODULES-y += $(MTK_PLAT)/drivers/vcp
MODULES-y += $(MTK_PLAT)/helpers
MODULES-y += $(MTK_PLAT)/topology
MODULES-$(CONFIG_MTK_CPU_PM_SUPPORT) += $(MTK_PLAT)/drivers/cpu_pm
MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SMMU_SID) += $(MTK_PLAT)/drivers/smmu_sid
MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
MODULES-$(CONFIG_MTK_MTCMOS) += $(MTK_PLAT)/drivers/mtcmos
diff --git a/plat/mediatek/topology/armv9/topology.c b/plat/mediatek/topology/armv9/topology.c
deleted file mode 100644
index d6ecc83..0000000
--- a/plat/mediatek/topology/armv9/topology.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2024, Mediatek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <lib/psci/psci.h>
-#include <platform_def.h>
-
-#pragma weak plat_get_power_domain_tree_desc
-
-static const unsigned char mtk_power_domain_tree_desc[] = {
- /* Number of root nodes */
- PLATFORM_SYSTEM_COUNT,
- /* Number of children for the root node */
- PLATFORM_CLUSTER_COUNT,
- /* Number of children for the first cluster node */
- PLATFORM_CLUSTER0_CORE_COUNT
-};
-
-/*******************************************************************************
- * This function returns the default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return mtk_power_domain_tree_desc;
-}
diff --git a/plat/nuvoton/npcm845x/platform.mk b/plat/nuvoton/npcm845x/platform.mk
index a69336a..df1809d 100644
--- a/plat/nuvoton/npcm845x/platform.mk
+++ b/plat/nuvoton/npcm845x/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
#
# Copyright (c) 2017-2023 Nuvoton Ltd.
#
@@ -330,10 +330,11 @@
ifneq (${TRUSTED_BOARD_BOOT},0)
# Include common TBB sources
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- lib/fconf/fconf_tbbr_getter.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+AUTH_SOURCES += lib/fconf/fconf_tbbr_getter.c
# Include the selected chain of trust sources.
ifeq (${COT},tbbr)
diff --git a/plat/nxp/common/tbbr/tbbr.mk b/plat/nxp/common/tbbr/tbbr.mk
index 0233398..f07d7af 100644
--- a/plat/nxp/common/tbbr/tbbr.mk
+++ b/plat/nxp/common/tbbr/tbbr.mk
@@ -146,9 +146,11 @@
PLAT_INCLUDES += -Iinclude/common/tbbr
# Generic files for authentication framework
-TBBR_SOURCES += drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+TBBR_SOURCES += ${AUTH_SOURCES} \
plat/common/tbbr/plat_tbbr.c \
${PLAT_TBBR_SOURCES}
diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
index 7121900..a7dda0d 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_helpers.S
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
@@ -113,14 +113,12 @@
/* void platform_mem_init(void); */
func platform_mem_init
mov x10, x30
- mov x0, #BL31_BASE
- mov x1, #(BL31_LIMIT & 0xFFFFU)
- movk x1, #(BL31_LIMIT >> 16), lsl #16
+ mov_imm x0, BL31_BASE
+ mov_imm x1, BL31_LIMIT
sub x1, x1, x0
bl zeromem
- mov x0, #BL33_BASE
- mov x1, #(BL33_LIMIT & 0xFFFFU)
- movk x1, #(BL33_LIMIT >> 16), lsl #16
+ mov_imm x0, BL33_BASE
+ mov_imm x1, BL33_LIMIT
sub x1, x1, x0
bl zeromem
mov x30, x10
diff --git a/plat/qemu/common/qemu_spm.c b/plat/qemu/common/qemu_spm.c
index abedbe4..873b97b 100644
--- a/plat/qemu/common/qemu_spm.c
+++ b/plat/qemu/common/qemu_spm.c
@@ -129,7 +129,9 @@
{
uintptr_t ns_buf_base;
- dt_add_ns_buf_node(&ns_buf_base);
+ if (dt_add_ns_buf_node(&ns_buf_base) != 0) {
+ panic();
+ }
plat_qemu_secure_partition_mmap[0].base_pa = ns_buf_base;
plat_qemu_secure_partition_mmap[0].base_va = ns_buf_base;
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index bd75abc..acd8e0f 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -45,9 +45,11 @@
ifneq (${TRUSTED_BOARD_BOOT},0)
- AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c
+ AUTH_MK := drivers/auth/auth.mk
+ $(info Including ${AUTH_MK})
+ include ${AUTH_MK}
+
+ AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
BL1_SOURCES += ${AUTH_SOURCES} \
bl1/tbbr/tbbr_img_desc.c \
@@ -100,12 +102,16 @@
endif
-ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),)
- CRYPTO_SOURCES := drivers/auth/crypto_mod.c
+ifeq (${MEASURED_BOOT},1)
+ifeq (${TRUSTED_BOARD_BOOT},0)
+ CRYPTO_SOURCES := drivers/auth/crypto_mod.c
- BL1_SOURCES += ${CRYPTO_SOURCES}
- BL2_SOURCES += ${CRYPTO_SOURCES}
+ BL1_SOURCES += ${CRYPTO_SOURCES}
+ BL2_SOURCES += ${CRYPTO_SOURCES}
+endif
+endif
+ifneq ($(filter 1,${MEASURED_BOOT} ${TRUSTED_BOARD_BOOT}),)
# We expect to locate the *.mk files under the directories specified below
#
include drivers/auth/mbedtls/mbedtls_crypto.mk
diff --git a/plat/qemu/qemu/qemu_measured_boot.c b/plat/qemu/qemu/qemu_measured_boot.c
index 4736f9d..8f88984 100644
--- a/plat/qemu/qemu/qemu_measured_boot.c
+++ b/plat/qemu/qemu/qemu_measured_boot.c
@@ -83,13 +83,17 @@
ERROR("%s(): Unable to update %s_FW_CONFIG\n",
__func__, "NT");
/*
- * It is a fatal error because on QEMU secure world software
+ * It is a non-fatal error because on QEMU secure world software
* assumes that a valid event log exists and will use it to
- * record the measurements into the fTPM or sw-tpm.
+ * record the measurements into the fTPM or sw-tpm, but the boot
+ * can also happen without TPM on the platform. It's up to
+ * higher layer in boot sequence to decide if this is fatal or
+ * not, e.g. by not providing access to TPM encrypted storage.
* Note: In QEMU platform, OP-TEE uses nt_fw_config to get the
* secure Event Log buffer address.
*/
- panic();
+ WARN("Ignoring TPM errors, continuing without\n");
+ return;
}
/* Copy Event Log to Non-secure memory */
diff --git a/plat/qti/common/src/aarch64/qti_kryo4_gold.S b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
index 49b7cf0..61eb755 100644
--- a/plat/qti/common/src/aarch64/qti_kryo4_gold.S
+++ b/plat/qti/common/src/aarch64/qti_kryo4_gold.S
@@ -59,9 +59,7 @@
ret
endfunc qti_kryo4_gold_cpu_reg_dump
-declare_cpu_ops_wa qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
+declare_cpu_ops qti_kryo4_gold, QTI_KRYO4_GOLD_MIDR, \
qti_kryo4_gold_reset_func, \
- CPU_NO_EXTRA1_FUNC, \
- cortex_a76_disable_wa_cve_2018_3639, \
cortex_a76_core_pwr_dwn, \
qti_kryo4_gold_cluster_pwr_dwn
diff --git a/plat/qti/msm8916/tsp/msm8916_tsp_setup.c b/plat/qti/msm8916/tsp/msm8916_tsp_setup.c
index 218af57..88d3c93 100644
--- a/plat/qti/msm8916/tsp/msm8916_tsp_setup.c
+++ b/plat/qti/msm8916/tsp/msm8916_tsp_setup.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2023, Stephan Gerhold <stephan@gerhold.net>
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,7 +11,8 @@
#include "../msm8916_setup.h"
#include <platform_def.h>
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
msm8916_early_platform_setup();
}
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index 5297177..b60482e 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -220,10 +220,11 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
- AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
- drivers/auth/tbbr/tbbr_cot_common.c
+ AUTH_MK := drivers/auth/auth.mk
+ $(info Including ${AUTH_MK})
+ include ${AUTH_MK}
+
+ AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
BL1_SOURCES += ${AUTH_SOURCES} \
bl1/tbbr/tbbr_img_desc.c \
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index 7a5a03c..12f92eb 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -63,9 +63,11 @@
ifeq (${TRUSTED_BOARD_BOOT},1)
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-BL2_SOURCES += drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
+
+BL2_SOURCES += ${AUTH_SOURCES} \
drivers/auth/tbbr/tbbr_cot_common.c \
drivers/auth/tbbr/tbbr_cot_bl2.c \
plat/common/tbbr/plat_tbbr.c \
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 21d95cf..850bd75 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -88,10 +88,11 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
-BL2_SOURCES += drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c \
+BL2_SOURCES += ${AUTH_SOURCES} \
drivers/auth/tbbr/tbbr_cot_common.c \
drivers/auth/tbbr/tbbr_cot_bl2.c \
plat/common/tbbr/plat_tbbr.c \
diff --git a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
index 4bbb259..31583b5 100644
--- a/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
+++ b/plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,8 @@
static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN;
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
uniphier_soc = uniphier_get_soc_id();
if (uniphier_soc == UNIPHIER_SOC_UNKNOWN)
diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index eec6247..56a8814 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk
@@ -180,9 +180,9 @@
endif
ifeq (${TRUSTED_BOARD_BOOT},1)
-AUTH_SOURCES := drivers/auth/auth_mod.c \
- drivers/auth/crypto_mod.c \
- drivers/auth/img_parser_mod.c
+AUTH_MK := drivers/auth/auth.mk
+$(info Including ${AUTH_MK})
+include ${AUTH_MK}
ifeq (${GENERATE_COT},1)
TFW_NVCTR_VAL := 0
diff --git a/plat/st/common/stm32mp_crypto_lib.c b/plat/st/common/stm32mp_crypto_lib.c
index 7223022..6c70b50 100644
--- a/plat/st/common/stm32mp_crypto_lib.c
+++ b/plat/st/common/stm32mp_crypto_lib.c
@@ -661,7 +661,8 @@
crypto_verify_hash,
NULL,
crypto_auth_decrypt,
- crypto_convert_pk);
+ crypto_convert_pk,
+ NULL);
#else /* No decryption support */
REGISTER_CRYPTO_LIB("stm32_crypto_lib",
@@ -670,5 +671,6 @@
crypto_verify_hash,
NULL,
NULL,
- crypto_convert_pk);
+ crypto_convert_pk,
+ NULL);
#endif
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index e700823..0e0586b 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -17,6 +17,8 @@
# Default Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
+TF_CFLAGS += -DSTM32MP1X
+
STM32MP13 ?= 0
STM32MP15 ?= 0
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 621b784..1d49fe7 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -34,97 +34,46 @@
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
+ const char *reason_str = "Unidentified";
- if (rstsr == 0U) {
- WARN("Reset reason unknown\n");
- return;
+#if !STM32MP21
+ if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
+ INFO("CA35 processor core 1 reset\n");
}
-
- INFO("Reset reason (0x%x):\n", rstsr);
+#endif /* !STM32MP21 */
if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
- INFO("System exits from Standby for CA35\n");
- return;
+ reason_str = "System exits from Standby for CA35";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
+ reason_str = "D1 domain exits from DStandby";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_VCPURSTF) != 0U) {
+ reason_str = "System reset from VCPU monitor";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
+ reason_str = "CA35 reset by CM33 (C1RST)";
+ } else {
+ reason_str = "Unidentified";
}
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
- INFO("D1 domain exits from DStandby\n");
- return;
+ } else {
+ if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
+ reason_str = "Power-on reset (por_rstn)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
+ reason_str = "Brownout reset (bor_rstn)";
+ } else if ((rstsr & (RCC_C1BOOTRSTSSETR_SYSC2RSTF |
+ RCC_C1BOOTRSTSSETR_SYSC1RSTF)) != 0U) {
+ reason_str = "System reset (SYSRST)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
+ reason_str = "Clock failure on HSE";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF) != 0U) {
+ reason_str = "IWDG system reset (iwdgX_out_rst)";
+ } else if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
+ reason_str = "Pin reset from NRST";
+ } else {
+ reason_str = "Unidentified";
}
}
- if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
- INFO(" Power-on Reset (rst_por)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
- INFO(" Brownout Reset (rst_bor)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
- INFO(" System reset (SYSRST) by M33\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
- INFO(" System reset (SYSRST) by A35\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
- INFO(" Clock failure on HSE\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
- INFO(" IWDG1 system reset (rst_iwdg1)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
- INFO(" IWDG2 system reset (rst_iwdg2)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
- INFO(" IWDG3 system reset (rst_iwdg3)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
- INFO(" IWDG4 system reset (rst_iwdg4)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
- INFO(" IWDG5 system reset (rst_iwdg5)\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
- INFO(" A35 processor core 1 reset\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
- INFO(" Pad Reset from NRST\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
- INFO(" Reset due to a failure of VDD_CORE\n");
- return;
- }
-
- if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
- INFO(" A35 processor reset\n");
- return;
- }
-
- ERROR(" Unidentified reset reason\n");
+ INFO("Reset reason: %s (0x%x)\n", reason_str, rstsr);
}
void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
@@ -164,11 +113,19 @@
* The protection is enable at each reset by hardware
* and must be disabled by software.
*/
+#if STM32MP21
+ mmio_setbits_32(pwr_base + PWR_BDCR, PWR_BDCR_DBP);
+
+ while ((mmio_read_32(pwr_base + PWR_BDCR) & PWR_BDCR_DBP) == 0U) {
+ ;
+ }
+#else /* STM32MP21 */
mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
;
}
+#endif /* STM32MP21 */
/* Reset backup domain on cold boot cases */
if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 06298a4..c20435b 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -30,11 +30,36 @@
# Default Device tree
DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
+TF_CFLAGS += -DSTM32MP2X
+
+STM32MP21 ?= 0
+STM32MP23 ?= 0
+STM32MP25 ?= 0
+
+ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
+STM32MP21 := 1
+endif
+ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
+STM32MP23 := 1
+endif
+ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
STM32MP25 := 1
+endif
+ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
+$(warning STM32MP21=$(STM32MP21))
+$(warning STM32MP23=$(STM32MP23))
+$(warning STM32MP25=$(STM32MP25))
+$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
+$(error Cannot enable more than one STM32MP2x flag)
+endif
-# STM32 image header version v2.2
+# STM32 image header version v2.2 or v2.3 for STM32MP21
STM32_HEADER_VERSION_MAJOR := 2
+ifeq ($(STM32MP21),1)
+STM32_HEADER_VERSION_MINOR := 3
+else
STM32_HEADER_VERSION_MINOR := 2
+endif
# Set load address for serial boot devices
DWL_BUFFER_BASE ?= 0x87000000
@@ -110,6 +135,8 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
+ STM32MP23 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))
@@ -133,6 +160,8 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
+ STM32MP23 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 1b8c4f5..27fc5f9 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -10,16 +10,31 @@
#include <common/tbbr/tbbr_img_def.h>
#ifndef __ASSEMBLER__
#include <drivers/st/bsec.h>
-#endif
-#include <drivers/st/stm32mp25_rcc.h>
-#ifndef __ASSEMBLER__
#include <drivers/st/stm32mp2_clk.h>
#endif
+#if STM32MP21
+#include <drivers/st/stm32mp21_pwr.h>
+#include <drivers/st/stm32mp21_rcc.h>
+#else /* STM32MP21 */
#include <drivers/st/stm32mp2_pwr.h>
+#include <drivers/st/stm32mp25_rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP21
+#include <dt-bindings/clock/st,stm32mp21-rcc.h>
+#include <dt-bindings/clock/stm32mp21-clksrc.h>
+#include <dt-bindings/reset/st,stm32mp21-rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP23
#include <dt-bindings/clock/stm32mp25-clks.h>
#include <dt-bindings/clock/stm32mp25-clksrc.h>
-#include <dt-bindings/gpio/stm32-gpio.h>
#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP23 */
+#if STM32MP25
+#include <dt-bindings/clock/stm32mp25-clks.h>
+#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP25 */
+#include <dt-bindings/gpio/stm32-gpio.h>
#ifndef __ASSEMBLER__
#include <boot_api.h>
@@ -386,7 +401,7 @@
#define DDRPHYC_BASE U(0x48C00000)
/*******************************************************************************
- * Miscellaneous STM32MP1 peripherals base address
+ * Miscellaneous STM32MP2 peripherals base address
******************************************************************************/
#define BSEC_BASE U(0x44000000)
#define DBGMCU_BASE U(0x4A010000)
@@ -422,7 +437,11 @@
#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
#define DT_DDR_COMPAT "st,stm32mp2-ddr"
#define DT_PWR_COMPAT "st,stm32mp25-pwr"
+#if STM32MP21
+#define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc"
+#else
#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
+#endif
#define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
#define DT_UART_COMPAT "st,stm32h7-uart"
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index df49f48..c679344 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -226,14 +226,6 @@
wfi();
}
-static int k3_validate_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- /* TODO: perform the proper validation */
-
- return PSCI_E_SUCCESS;
-}
-
static void k3_pwr_domain_suspend_to_mode(const psci_power_state_t *target_state, uint8_t mode)
{
unsigned int core, proc_id;
@@ -294,7 +286,6 @@
.get_sys_suspend_power_state = k3_get_sys_suspend_power_state,
.system_off = k3_system_off,
.system_reset = k3_system_reset,
- .validate_power_state = k3_validate_power_state,
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
diff --git a/plat/xilinx/zynqmp/custom_sip_svc.c b/plat/xilinx/common/custom_sip_svc.c
similarity index 90%
rename from plat/xilinx/zynqmp/custom_sip_svc.c
rename to plat/xilinx/common/custom_sip_svc.c
index c39e4be..2cefb78 100644
--- a/plat/xilinx/zynqmp/custom_sip_svc.c
+++ b/plat/xilinx/common/custom_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/include/custom_svc.h b/plat/xilinx/common/include/custom_svc.h
similarity index 71%
rename from plat/xilinx/zynqmp/include/custom_svc.h
rename to plat/xilinx/common/include/custom_svc.h
index 242f3eb..2884b69 100644
--- a/plat/xilinx/zynqmp/include/custom_svc.h
+++ b/plat/xilinx/common/include/custom_svc.h
@@ -1,13 +1,13 @@
/*
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef CUSTOM_SVC_H
#define CUSTOM_SVC_H
-#define ZYNQMP_SIP_SVC_CUSTOM U(0x82002000)
-#define ZYNQMP_SIP_SVC64_CUSTOM U(0xC2002000)
+#define SOC_SIP_SVC_CUSTOM U(0x82002000)
+#define SOC_SIP_SVC64_CUSTOM U(0xC2002000)
uint64_t custom_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
uint64_t x3, uint64_t x4, void *cookie,
diff --git a/plat/xilinx/common/include/ipi.h b/plat/xilinx/common/include/ipi.h
index 71c06c3..c628496 100644
--- a/plat/xilinx/common/include/ipi.h
+++ b/plat/xilinx/common/include/ipi.h
@@ -38,9 +38,9 @@
/* structure to maintain IPI configuration information */
struct ipi_config {
- unsigned int ipi_bit_mask;
- unsigned int ipi_reg_base;
- unsigned char secure_only;
+ uint32_t ipi_bit_mask;
+ uint32_t ipi_reg_base;
+ uint8_t secure_only;
};
/*********************************************************************
@@ -52,7 +52,7 @@
uint32_t total_ipi);
/* Validate IPI mailbox access */
-int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure);
+int32_t ipi_mb_validate(uint32_t local, uint32_t remote, uint32_t is_secure);
/* Open the IPI mailbox */
void ipi_mb_open(uint32_t local, uint32_t remote);
diff --git a/plat/xilinx/common/include/pm_api_sys.h b/plat/xilinx/common/include/pm_api_sys.h
index 2e4b342..fc55cc3 100644
--- a/plat/xilinx/common/include/pm_api_sys.h
+++ b/plat/xilinx/common/include/pm_api_sys.h
@@ -24,7 +24,7 @@
enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1,
uint32_t x2, uint32_t x3, uint32_t x4,
- uint32_t x5, uint64_t *result);
+ uint32_t x5, uint32_t *result);
enum pm_ret_status pm_self_suspend(uint32_t nid,
uint32_t latency,
uint32_t state,
@@ -41,20 +41,10 @@
enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag,
uint32_t ack);
void pm_client_set_wakeup_sources(uint32_t node_id);
-enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
- uint32_t value, uint32_t flag);
-enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
- uint32_t *value, uint32_t flag);
-enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode,
- uint32_t flag);
-enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode,
- uint32_t flag);
enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack,
uint32_t flag);
enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype,
uint32_t flag);
-enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2,
- uint32_t arg3, uint32_t *data, uint32_t flag);
uint32_t pm_get_shutdown_scope(void);
enum pm_ret_status pm_feature_check(uint32_t api_id, uint32_t *ret_payload,
uint32_t flag);
@@ -70,7 +60,8 @@
* Assigning of argument values into array elements.
*/
#define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) { \
- pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | ((mid) << 8U) | ((flag) << 24U)); \
+ pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | \
+ ((uint32_t)(mid) << 8U) | ((uint32_t)(flag) << 24U)); \
}
#define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \
diff --git a/plat/xilinx/common/include/pm_common.h b/plat/xilinx/common/include/pm_common.h
index 68d1db2..5e53ec6 100644
--- a/plat/xilinx/common/include/pm_common.h
+++ b/plat/xilinx/common/include/pm_common.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,9 +29,9 @@
#define RET_PAYLOAD_ARG_CNT 6U
#define PAYLOAD_ARG_SIZE 4U /* size in bytes */
-#define TZ_VERSION_MAJOR 1
-#define TZ_VERSION_MINOR 0
-#define TZ_VERSION ((TZ_VERSION_MAJOR << 16) | \
+#define TZ_VERSION_MAJOR 1U
+#define TZ_VERSION_MINOR 0U
+#define TZ_VERSION (((uint32_t)TZ_VERSION_MAJOR << 16U) | \
TZ_VERSION_MINOR)
/**
diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index 9920611..3901555 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,7 +22,6 @@
#define PM_STATE_SUSPEND_TO_RAM 0xFU
#define MAX_LATENCY (~0U)
-#define MAX_QOS 100U
/* Processor core device IDs */
#define APU_DEVID(IDX) NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \
@@ -202,28 +201,6 @@
ABORT_REASON_UNKNOWN,
};
-enum pm_opchar_type {
- PM_OPCHAR_TYPE_POWER = 1,
- PM_OPCHAR_TYPE_TEMP,
- PM_OPCHAR_TYPE_LATENCY,
-};
-
-/*
- * Subsystem IDs
- */
-typedef enum {
- XPM_SUBSYSID_PMC,
- XPM_SUBSYSID_PSM,
- XPM_SUBSYSID_APU,
- XPM_SUBSYSID_RPU0_LOCK,
- XPM_SUBSYSID_RPU0_0,
- XPM_SUBSYSID_RPU0_1,
- XPM_SUBSYSID_DDR0,
- XPM_SUBSYSID_ME,
- XPM_SUBSYSID_PL,
- XPM_SUBSYSID_MAX,
-} XPm_SubsystemId;
-
/* TODO: move pm_ret_status from device specific location to common location */
/**
* enum pm_ret_status - enum represents the return status codes for a PM
@@ -231,7 +208,7 @@
* @PM_RET_SUCCESS: success.
* @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated).
* @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated).
- * @PM_RET_ERROR_NOFEATURE: feature is not available.
+ * @PM_RET_ERROR_IOCTL_NOT_SUPPORTED: IOCTL is not supported.
* @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication.
* @PM_RET_ERROR_NOT_ENABLED: feature is not enabled.
* @PM_RET_ERROR_INTERNAL: internal error.
@@ -246,21 +223,21 @@
* supported.
*/
enum pm_ret_status {
- PM_RET_SUCCESS,
- PM_RET_ERROR_ARGS = 1,
- PM_RET_ERROR_NOTSUPPORTED = 4,
- PM_RET_ERROR_NOFEATURE = 19,
- PM_RET_ERROR_INVALID_CRC = 301,
- PM_RET_ERROR_NOT_ENABLED = 29,
- PM_RET_ERROR_INTERNAL = 2000,
- PM_RET_ERROR_CONFLICT = 2001,
- PM_RET_ERROR_ACCESS = 2002,
- PM_RET_ERROR_INVALID_NODE = 2003,
- PM_RET_ERROR_DOUBLE_REQ = 2004,
- PM_RET_ERROR_ABORT_SUSPEND = 2005,
- PM_RET_ERROR_TIMEOUT = 2006,
- PM_RET_ERROR_NODE_USED = 2007,
- PM_RET_ERROR_NO_FEATURE = 2008
+ PM_RET_SUCCESS = 0U,
+ PM_RET_ERROR_ARGS = 1U,
+ PM_RET_ERROR_NOTSUPPORTED = 4U,
+ PM_RET_ERROR_IOCTL_NOT_SUPPORTED = 19U,
+ PM_RET_ERROR_NOT_ENABLED = 29U,
+ PM_RET_ERROR_INVALID_CRC = 301U,
+ PM_RET_ERROR_INTERNAL = 2000U,
+ PM_RET_ERROR_CONFLICT = 2001U,
+ PM_RET_ERROR_ACCESS = 2002U,
+ PM_RET_ERROR_INVALID_NODE = 2003U,
+ PM_RET_ERROR_DOUBLE_REQ = 2004U,
+ PM_RET_ERROR_ABORT_SUSPEND = 2005U,
+ PM_RET_ERROR_TIMEOUT = 2006U,
+ PM_RET_ERROR_NODE_USED = 2007U,
+ PM_RET_ERROR_NO_FEATURE = 2008U
};
/*
diff --git a/plat/xilinx/common/include/pm_node.h b/plat/xilinx/common/include/pm_node.h
index 3ee55c2..0efebdf 100644
--- a/plat/xilinx/common/include/pm_node.h
+++ b/plat/xilinx/common/include/pm_node.h
@@ -22,10 +22,6 @@
#define NODE_SUBCLASS_MASK_BITS GENMASK_32(5, 0)
#define NODE_TYPE_MASK_BITS GENMASK_32(5, 0)
#define NODE_INDEX_MASK_BITS GENMASK_32(13, 0)
-#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
-#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
-#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
-#define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
@@ -33,12 +29,6 @@
(((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
(((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
-#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
-#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \
- NODE_SUBCLASS_SHIFT)
-#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
-#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
-
/*********************************************************************
* Enum definitions
********************************************************************/
diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
index 18ae096..8dc6da0 100644
--- a/plat/xilinx/common/ipi.c
+++ b/plat/xilinx/common/ipi.c
@@ -67,12 +67,12 @@
* Return: - 1 if within range, 0 if not.
*
*/
-static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
+static inline uint32_t is_ipi_mb_within_range(uint32_t local, uint32_t remote)
{
- int ret = 1;
+ uint32_t ret = 1U;
if ((remote >= ipi_total) || (local >= ipi_total)) {
- ret = 0;
+ ret = 0U;
}
return ret;
@@ -87,11 +87,11 @@
* Return: 0 success, negative value for errors.
*
*/
-int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
+int32_t ipi_mb_validate(uint32_t local, uint32_t remote, uint32_t is_secure)
{
- int ret = 0;
+ int32_t ret = 0;
- if (is_ipi_mb_within_range(local, remote) == 0) {
+ if (is_ipi_mb_within_range(local, remote) == 0U) {
ret = -EINVAL;
} else if (IPI_IS_SECURE(local) && (is_secure == 0U)) {
ret = -EPERM;
diff --git a/plat/xilinx/common/pm_service/pm_api_sys.c b/plat/xilinx/common/pm_service/pm_api_sys.c
index 679f935..efb9286 100644
--- a/plat/xilinx/common/pm_service/pm_api_sys.c
+++ b/plat/xilinx/common/pm_service/pm_api_sys.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -109,7 +109,7 @@
*/
enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1,
uint32_t x2, uint32_t x3, uint32_t x4,
- uint32_t x5, uint64_t *result)
+ uint32_t x5, uint32_t *result)
{
uint32_t payload[PAYLOAD_ARG_CNT] = {0};
uint32_t module_id;
@@ -122,7 +122,7 @@
}
PM_PACK_PAYLOAD6(payload, module_id, flag, x0, x1, x2, x3, x4, x5);
- return pm_ipi_send_sync(primary_proc, payload, (uint32_t *)result, RET_PAYLOAD_ARG_CNT);
+ return pm_ipi_send_sync(primary_proc, payload, result, RET_PAYLOAD_ARG_CNT);
}
/**
@@ -163,8 +163,7 @@
/* Send request to the PLM */
PM_PACK_PAYLOAD6(payload, LIBPM_MODULE_ID, flag, PM_SELF_SUSPEND,
- proc->node_id, latency, state, address,
- (address >> 32));
+ nid, latency, state, address, (address >> 32));
ret = pm_ipi_send_sync(proc, payload, NULL, 0);
exit_label:
@@ -280,6 +279,13 @@
{
enum pm_ret_status ret = PM_RET_SUCCESS;
+ /*
+ * Typecasting to void to intentionally retain the variable and avoid
+ * MISRA violation for unused parameters. This may be used in the
+ * future if callbacks to a secure target are required.
+ */
+ (void)flag;
+
/* Return if interrupt is not from PMU */
if (pm_ipi_irq_status(primary_proc) != 0U) {
@@ -403,6 +409,7 @@
break;
default:
ret = PM_RET_ERROR_NO_FEATURE;
+ break;
}
return ret;
@@ -433,33 +440,31 @@
case PM_GET_TRUSTZONE_VERSION:
ret_payload[0] = PM_API_VERSION_2;
ret = PM_RET_SUCCESS;
- goto exit_label;
+ break;
case TF_A_PM_REGISTER_SGI:
ret_payload[0] = PM_API_BASE_VERSION;
ret = PM_RET_SUCCESS;
- goto exit_label;
- default:
break;
- }
+ default:
+ module_id = (api_id & MODULE_ID_MASK) >> 8U;
- module_id = (api_id & MODULE_ID_MASK) >> 8U;
+ /*
+ * feature check should be done only for LIBPM module
+ * If module_id is 0, then we consider it LIBPM module as default id
+ */
+ if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
+ ret = PM_RET_SUCCESS;
+ break;
+ }
- /*
- * feature check should be done only for LIBPM module
- * If module_id is 0, then we consider it LIBPM module as default id
- */
- if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
- ret = PM_RET_SUCCESS;
- goto exit_label;
- }
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
+ PM_FEATURE_CHECK, api_id);
+ ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, RET_PAYLOAD_ARG_CNT);
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
- PM_FEATURE_CHECK, api_id);
- ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, RET_PAYLOAD_ARG_CNT);
+ break;
+ }
-exit_label:
return ret;
-
}
/**
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index 610acc7..38c36e5 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -27,7 +27,7 @@
* power down. Therefore, there is no doubt to use the spin_lock here.
*/
#if !HW_ASSISTED_COHERENCY
-DEFINE_BAKERY_LOCK(pm_secure_lock);
+static DEFINE_BAKERY_LOCK(pm_secure_lock);
static inline void pm_ipi_lock_get(void)
{
bakery_lock_get(&pm_secure_lock);
@@ -222,8 +222,8 @@
enum pm_ret_status pm_ipi_buff_read_callb(uint32_t *value, size_t count)
{
size_t i;
- size_t local_count = count;
#if IPI_CRC_CHECK
+ size_t local_count = count;
uint32_t crc;
#endif
uintptr_t buffer_base = IPI_BUFFER_REMOTE_BASE +
@@ -231,14 +231,14 @@
IPI_BUFFER_REQ_OFFSET;
enum pm_ret_status ret = PM_RET_SUCCESS;
- if (local_count > (uint32_t)IPI_BUFFER_MAX_WORDS) {
- local_count = IPI_BUFFER_MAX_WORDS;
- }
-
for (i = 0; i < count; i++) {
value[i] = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
}
#if IPI_CRC_CHECK
+ if (local_count > (uint32_t)IPI_BUFFER_MAX_WORDS) {
+ local_count = IPI_BUFFER_MAX_WORDS;
+ }
+
crc = mmio_read_32(buffer_base + (PAYLOAD_CRC_POS * PAYLOAD_ARG_SIZE));
if (crc != calculate_crc((uint32_t *)buffer_base, IPI_W0_TO_W6_SIZE)) {
NOTICE("ERROR in CRC response payload value:0x%x\n", crc);
@@ -312,7 +312,7 @@
}
#if IPI_CRC_CHECK
-uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t bufsize)
+uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize)
{
uint32_t crcinit = CRC_INIT_VALUE;
uint32_t order = CRC_ORDER;
@@ -320,20 +320,22 @@
uint32_t i, j, c, bit, datain, crcmask, crchighbit;
uint32_t crc = crcinit;
- crcmask = ((uint32_t)((1U << (order - 1U)) - 1U) << 1U) | 1U;
- crchighbit = (uint32_t)(1U << (order - 1U));
+ crcmask = ((((uint32_t)1U << (order - 1U)) - 1U) << 1U) | 1U;
+ crchighbit = ((uint32_t)1U << (order - 1U));
- for (i = 0U; i < bufsize; i++) {
+ for (i = 0U; i < buffersize; i++) {
datain = mmio_read_8((unsigned long)payload + i);
c = datain;
j = 0x80U;
while (j != 0U) {
bit = crc & crchighbit;
crc <<= 1U;
- if (0U != (c & j))
+ if (0U != (c & j)) {
bit ^= crchighbit;
- if (bit != 0U)
+ }
+ if (bit != 0U) {
crc ^= polynom;
+ }
j >>= 1U;
}
crc &= crcmask;
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index bc8e251..77ebb62 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -29,7 +29,6 @@
#define MODE 0x80000000U
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
#define INVALID_SGI 0xFFU
#define PM_INIT_SUSPEND_CB (30U)
#define PM_NOTIFY_CB (32U)
@@ -182,9 +181,11 @@
}
}
notify_os();
- } else if (payload[2] == EVENT_CPU_PWRDWN) {
- request_cpu_pwrdwn();
- (void)psci_cpu_off();
+ } else {
+ if (payload[2] == EVENT_CPU_PWRDWN) {
+ request_cpu_pwrdwn();
+ (void)psci_cpu_off();
+ }
}
break;
case (uint32_t)PM_RET_ERROR_INVALID_CRC:
@@ -301,7 +302,7 @@
* until their use case in linux driver changes.
*
*/
-static uintptr_t eemi_for_compatibility(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_for_compatibility(uint32_t api_id, const uint32_t *pm_arg,
void *handle, uint32_t security_flag)
{
enum pm_ret_status ret;
@@ -346,7 +347,7 @@
* Return: If EEMI API found then, uintptr_t type address, else 0.
*
*/
-static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, const uint32_t *pm_arg,
void *handle, uint32_t security_flag)
{
enum pm_ret_status ret;
@@ -394,7 +395,7 @@
* Return: If TF-A specific API found then, uintptr_t type address, else 0
*
*/
-static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t TF_A_specific_handler(uint32_t api_id, const uint32_t *pm_arg,
void *handle, uint32_t security_flag)
{
switch (api_id) {
@@ -461,15 +462,14 @@
* Return: If EEMI API found then, uintptr_t type address, else 0
*
*/
-static uintptr_t eemi_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_handler(uint32_t api_id, const uint32_t *pm_arg,
void *handle, uint32_t security_flag)
{
enum pm_ret_status ret;
uint32_t buf[RET_PAYLOAD_ARG_CNT] = {0};
ret = pm_handle_eemi_call(security_flag, api_id, pm_arg[0], pm_arg[1],
- pm_arg[2], pm_arg[3], pm_arg[4],
- (uint64_t *)buf);
+ pm_arg[2], pm_arg[3], pm_arg[4], buf);
/*
* Two IOCTLs, to get clock name and pinctrl name of pm_query_data API
* receives 5 words of respoonse from firmware. Currently linux driver can
diff --git a/plat/xilinx/common/tsp/tsp_plat_setup.c b/plat/xilinx/common/tsp/tsp_plat_setup.c
index 21c29c3..5df4b6e 100644
--- a/plat/xilinx/common/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/common/tsp/tsp_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, Advanced Micro Devices. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -17,7 +17,8 @@
/*******************************************************************************
* Initialize the UART
******************************************************************************/
-void tsp_early_platform_setup(void)
+void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
/*
* Register a different console than already in use to display
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index befe36c..70b0fa6 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -18,8 +18,9 @@
#include <plat/common/platform.h>
#include <plat_arm.h>
#include <plat_console.h>
-#include <plat_clkfunc.h>
+#include <custom_svc.h>
+#include <plat_clkfunc.h>
#include <plat_fdt.h>
#include <plat_private.h>
#include <plat_startup.h>
@@ -143,6 +144,8 @@
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
+
+ custom_early_setup();
}
static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
@@ -220,6 +223,8 @@
if (rc != 0) {
panic();
}
+
+ custom_runtime_setup();
}
/*
@@ -248,6 +253,8 @@
{0}
};
+ custom_mmap_add();
+
setup_page_tables(bl_regions, plat_get_mmap());
enable_mmu(0);
}
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index a3886a4..d8b334a 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -17,7 +17,9 @@
******************************************************************************/
/* Size of cacheable stacks */
+#ifndef PLATFORM_STACK_SIZE
#define PLATFORM_STACK_SIZE U(0x440)
+#endif
#define PLATFORM_CORE_COUNT U(2)
#define PLAT_MAX_PWR_LVL U(1)
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 032339f..1c365b4 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -136,6 +136,13 @@
static void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
+ /*
+ * Typecasting to void to intentionally retain the variable and avoid
+ * MISRA violation for unused parameters. This may be used in the
+ * future if specific action is required based on CPU power state.
+ */
+ (void)target_state;
+
/* Enable the gic cpu interface */
plat_versal_gic_pcpu_init();
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 8be4be6..83d2d6f 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -144,3 +144,9 @@
CORTEX_A72_H_INC := 1
$(eval $(call add_define, CORTEX_A72_H_INC))
endif
+
+ifdef CUSTOM_PKG_PATH
+include $(CUSTOM_PKG_PATH)/custom_pkg.mk
+else
+BL31_SOURCES += plat/xilinx/common/custom_sip_svc.c
+endif
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index de2cac8..77e3fb0 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,7 +28,7 @@
#define UNDEFINED_CPUID (~0U)
-DEFINE_BAKERY_LOCK(pm_client_secure_lock);
+static DEFINE_BAKERY_LOCK(pm_client_secure_lock);
static const struct pm_ipi apu_ipi = {
.local_ipi_id = IPI_LOCAL_ID,
diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index bb3f728..5e7ce9e 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c
@@ -13,6 +13,7 @@
#include <common/runtime_svc.h>
#include <tools_share/uuid.h>
+#include <custom_svc.h>
#include "ipi_mailbox_svc.h"
#include "pm_svc_main.h"
@@ -105,6 +106,11 @@
case VERSAL_SIP_SVC_VERSION:
SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
+ case SOC_SIP_SVC_CUSTOM:
+ case SOC_SIP_SVC64_CUSTOM:
+ return custom_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+
default:
WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
SMC_RET1(handle, SMC_UNK);
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index d131a92..2308a75 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -203,14 +203,28 @@
return ret;
}
+#if SDEI_SUPPORT
+static int rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
+ void *handle, void *cookie)
+#else
static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
void *handle, void *cookie)
+#endif
{
uint32_t intr_id;
uint32_t i;
interrupt_type_handler_t handler = NULL;
+#if SDEI_SUPPORT
+ /* when SDEI_SUPPORT is enabled, ehf_el3_interrupt_handler
+ * reads the interrupt id prior to calling the
+ * rdo_el3_interrupt_handler and passes that id to the
+ * handler.
+ */
+ intr_id = id;
+#else
intr_id = plat_ic_get_pending_interrupt_id();
+#endif
for (i = 0; i < MAX_INTR_EL3; i++) {
if (intr_id == type_el3_interrupt_table[i].id) {
@@ -236,6 +250,7 @@
void bl31_plat_runtime_setup(void)
{
+#if !SDEI_SUPPORT
uint64_t flags = 0;
int32_t rc;
@@ -245,6 +260,9 @@
if (rc != 0) {
panic();
}
+#else
+ ehf_register_priority_handler(PLAT_IPI_PRI, rdo_el3_interrupt_handler);
+#endif
}
/*
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index ae49450..461fda8 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#define PLATFORM_DEF_H
#include <arch.h>
+#include <drivers/arm/gic_common.h>
#include <plat_common.h>
#include "versal_net_def.h"
@@ -119,6 +120,24 @@
#define PLAT_ARM_GICD_BASE U(0xE2000000)
#define PLAT_ARM_GICR_BASE U(0xE2060000)
+/* interrupt priorities when SDEI is enabled:
+ * RAS in future is planned to have highest priority (lower value 0x10)
+ * followed by IPI and SDEI exceptions in a step of 0x10.
+ */
+
+#if SDEI_SUPPORT
+#define VERSAL_NET_SDEI_SGI_PRIVATE U(8)
+#define PLAT_SDEI_CRITICAL_PRI 0x30
+#define PLAT_SDEI_NORMAL_PRI 0x40
+#define PLAT_PRI_BITS U(3)
+#define PLAT_IPI_PRI 0x20
+
+#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_IPI_PRI)
+
+#define VERSAL_NET_SDEI_SH_EVENT_0 U(200)
+#define VERSAL_NET_SDEI_PRV_EV U(201)
+#endif
+
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
@@ -127,6 +146,19 @@
#define PLAT_VERSAL_NET_IPI_IRQ 89
#define PLAT_VERSAL_IPI_IRQ PLAT_VERSAL_NET_IPI_IRQ
+#if SDEI_SUPPORT
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, PLAT_IPI_PRI, grp, \
+ GIC_INTR_CFG_LEVEL)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, PLAT_IPI_PRI, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, PLAT_IPI_PRI, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(VERSAL_NET_SDEI_SGI_PRIVATE, PLAT_SDEI_NORMAL_PRI, grp, \
+ GIC_INTR_CFG_EDGE)
+#else
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(VERSAL_NET_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
@@ -136,6 +168,7 @@
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE)
+#endif
#define IRQ_MAX 200U
diff --git a/plat/xilinx/versal_net/plat_psci.c b/plat/xilinx/versal_net/plat_psci.c
index fcb32b9..399500d 100644
--- a/plat/xilinx/versal_net/plat_psci.c
+++ b/plat/xilinx/versal_net/plat_psci.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,8 +19,6 @@
#include <plat_private.h>
#include <pm_defs.h>
-#define PM_RET_ERROR_NOFEATURE U(19)
-
static uintptr_t versal_net_sec_entry;
static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
@@ -175,7 +173,7 @@
mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1);
return 0;
}
- return PM_RET_ERROR_NOFEATURE;
+ return PM_RET_ERROR_IOCTL_NOT_SUPPORTED;
}
static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index eda3e36..5e8f2b4 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -145,3 +145,10 @@
${LIBFDT_SRCS} \
${PLAT_PATH}/sip_svc_setup.c \
${XLAT_TABLES_LIB_SRCS}
+
+SDEI_SUPPORT := 0
+EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
+ifeq (${SDEI_SUPPORT},1)
+BL31_SOURCES += plat/common/aarch64/plat_ehf.c \
+ plat/xilinx/versal_net/versal_net_sdei.c
+endif
diff --git a/plat/xilinx/versal_net/versal_net_sdei.c b/plat/xilinx/versal_net/versal_net_sdei.c
new file mode 100644
index 0000000..e42c066
--- /dev/null
+++ b/plat/xilinx/versal_net/versal_net_sdei.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <bl31/ehf.h>
+#include <common/debug.h>
+#include <plat/common/platform.h>
+#include <services/sdei.h>
+
+#include <platform_def.h>
+
+int arm_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ int ret;
+ uintptr_t base = BL31_BASE;
+ uintptr_t limit = BL31_LIMIT;
+
+ ret = ((entrypoint < base) || (entrypoint > limit)) ? 0 : -1;
+ return ret;
+}
+
+/* Private event mappings */
+static sdei_ev_map_t versal_net_sdei_private[] = {
+ SDEI_DEFINE_EVENT_0(VERSAL_NET_SDEI_SGI_PRIVATE),
+ SDEI_PRIVATE_EVENT(VERSAL_NET_SDEI_PRV_EV, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
+};
+
+/* Shared event mappings */
+static sdei_ev_map_t versal_net_sdei_shared[] = {
+ SDEI_SHARED_EVENT(VERSAL_NET_SDEI_SH_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
+};
+
+void plat_sdei_setup(void)
+{
+ INFO("SDEI platform setup\n");
+}
+
+/* Export ARM SDEI events */
+REGISTER_SDEI_MAP(versal_net_sdei_private, versal_net_sdei_shared);
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 27e5427..d2cb220 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -162,7 +162,7 @@
ifdef CUSTOM_PKG_PATH
include $(CUSTOM_PKG_PATH)/custom_pkg.mk
else
-BL31_SOURCES += plat/xilinx/zynqmp/custom_sip_svc.c
+BL31_SOURCES += plat/xilinx/common/custom_sip_svc.c
endif
ifneq (${RESET_TO_BL31},1)
diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index 1baefb3..6d94422 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c
@@ -105,8 +105,8 @@
case ZYNQMP_SIP_SVC_VERSION:
SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
- case ZYNQMP_SIP_SVC_CUSTOM:
- case ZYNQMP_SIP_SVC64_CUSTOM:
+ case SOC_SIP_SVC_CUSTOM:
+ case SOC_SIP_SVC64_CUSTOM:
return custom_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
diff --git a/pyproject.toml b/pyproject.toml
index 88c4753..0c39f49 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
[tool.poetry]
name = "trusted-firmware-a"
-version = "2.12.0"
+version = "2.13.0"
description = "Trusted Firmware-A (TF-A) Python dependencies."
authors = ["Arm Ltd."]
license = "BSD-3-Clause"
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 46333af..6051de8 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -7,9 +7,6 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <lib/cpus/errata.h>
-#include <lib/cpus/wa_cve_2017_5715.h>
-#include <lib/cpus/wa_cve_2018_3639.h>
-#include <lib/cpus/wa_cve_2022_23960.h>
#include <lib/smccc.h>
#include <services/arm_arch_svc.h>
#include <smccc_helpers.h>
@@ -35,8 +32,11 @@
/* Workaround checks are currently only implemented for aarch64 */
#if WORKAROUND_CVE_2017_5715
case SMCCC_ARCH_WORKAROUND_1:
- if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
+ if (check_erratum_applies(CVE(2017, 5715))
+ == ERRATA_NOT_APPLIES) {
return 1;
+ }
+
return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
#endif
@@ -66,8 +66,10 @@
* or permanently mitigated, report the latter as not
* needing dynamic mitigation.
*/
- if (wa_cve_2018_3639_get_disable_ptr() == NULL)
+ if (check_erratum_applies(ERRATUM(ARCH_WORKAROUND_2))
+ == ERRATA_NOT_APPLIES)
return 1;
+
/*
* If we get here, this CPU requires dynamic mitigation
* so report it as such.
@@ -87,10 +89,13 @@
* CVE-2017-5715 since this SMC can be used instead of
* SMCCC_ARCH_WORKAROUND_1.
*/
- if ((check_smccc_arch_wa3_applies() == ERRATA_NOT_APPLIES) &&
- (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)) {
+ if ((check_erratum_applies(ERRATUM(ARCH_WORKAROUND_3))
+ == ERRATA_NOT_APPLIES) &&
+ (check_erratum_applies(CVE(2017, 5715))
+ == ERRATA_NOT_APPLIES)) {
return 1;
}
+
return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
#endif
@@ -101,7 +106,7 @@
#if WORKAROUND_CVE_2024_7881
case SMCCC_ARCH_WORKAROUND_4:
- if (check_wa_cve_2024_7881() != ERRATA_APPLIES) {
+ if (check_erratum_applies(CVE(2024, 7881)) != ERRATA_APPLIES) {
return SMC_ARCH_CALL_NOT_SUPPORTED;
}
return 0;
diff --git a/services/el3/ven_el3_svc.c b/services/el3/ven_el3_svc.c
index 32a3dc2..431bfbf 100644
--- a/services/el3/ven_el3_svc.c
+++ b/services/el3/ven_el3_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,9 @@
#include <common/runtime_svc.h>
#include <lib/debugfs.h>
#include <lib/pmf/pmf.h>
+#if PLAT_ARM_ACS_SMC_HANDLER
+#include <plat/arm/common/plat_acs_smc_handler.h>
+#endif /* PLAT_ARM_ACS_SMC_HANDLER */
#include <services/ven_el3_svc.h>
#include <tools_share/uuid.h>
@@ -71,6 +74,15 @@
#endif /* ENABLE_PMF */
+#if PLAT_ARM_ACS_SMC_HANDLER
+ /*
+ * Dispatch ACS calls to ACS SMC handler and return its return value
+ */
+ if (is_acs_fid(smc_fid)) {
+ return plat_arm_acs_smc_handler(smc_fid, x1, x2, x3, x4, handle);
+ }
+#endif /* PLAT_ARM_ACS_SMC_HANDLER */
+
switch (smc_fid) {
case VEN_EL3_SVC_UID:
/* Return UID to the caller */
diff --git a/services/std_svc/drtm/drtm_main.c b/services/std_svc/drtm/drtm_main.c
index 8f71571..b7a03f3 100644
--- a/services/std_svc/drtm/drtm_main.c
+++ b/services/std_svc/drtm/drtm_main.c
@@ -329,10 +329,8 @@
* Ensure that if DLME Authorities Schema (Bits [2:1]) is set, then
* DLME image authentication (Bit[6]) must also be set
*/
- if ((EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_MASK,
- DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA_SHIFT) == DLME_AUTH_SCHEMA) &&
- (EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_MASK,
- DRTM_LAUNCH_FEAT_DLME_IMG_AUTH_SHIFT) != DLME_IMG_AUTH)) {
+ if ((EXTRACT(DRTM_LAUNCH_FEAT_PCR_USAGE_SCHEMA, val) == DLME_AUTH_SCHEMA) &&
+ (EXTRACT(DRTM_LAUNCH_FEAT_DLME_IMG_AUTH, val) != DLME_IMG_AUTH)) {
return INVALID_PARAMETERS;
}
@@ -340,8 +338,7 @@
* Check if Bits [5:3] (Memory protection type) matches with platform's
* memory protection type
*/
- if (EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_MASK,
- DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE_SHIFT) !=
+ if (EXTRACT(DRTM_LAUNCH_FEAT_MEM_PROTECTION_TYPE, val) !=
__builtin_ctz(plat_dma_prot_feat->dma_protection_support)) {
return INVALID_PARAMETERS;
}
@@ -350,8 +347,7 @@
* Check if Bits [0] (Type of hashing) matches with platform's
* supported hash type.
*/
- if (EXTRACT_FIELD(val, DRTM_LAUNCH_FEAT_HASHING_TYPE_MASK,
- DRTM_LAUNCH_FEAT_HASHING_TYPE_SHIFT) !=
+ if (EXTRACT(DRTM_LAUNCH_FEAT_HASHING_TYPE, val) !=
plat_tpm_feat->tpm_based_hash_support) {
return INVALID_PARAMETERS;
}
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index d688431..d685eef 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -48,5 +48,5 @@
struct em_cpu cpu_errata_list[MAX_PLAT_CPU_ERRATA_ENTRIES];
};
-int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag);
+int32_t verify_errata_implemented(uint32_t errata_id);
#endif /* ERRATA_CPUSPEC_H */
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index a945637..74a1586 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -166,50 +166,33 @@
#endif
/* Function to check if the errata exists for the specific CPU and rxpx */
-int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag)
+int32_t verify_errata_implemented(uint32_t errata_id)
{
- int32_t ret_val;
- struct cpu_ops *cpu_ops;
- struct erratum_entry *entry, *end;
+ struct erratum_entry *entry;
long rev_var;
- ret_val = EM_UNKNOWN_ERRATUM;
rev_var = cpu_get_rev_var();
#if ERRATA_NON_ARM_INTERCONNECT
- ret_val = non_arm_interconnect_errata(errata_id, rev_var);
+ int32_t ret_val = non_arm_interconnect_errata(errata_id, rev_var);
if (ret_val != EM_UNKNOWN_ERRATUM) {
return ret_val;
}
#endif
+ entry = find_erratum_entry(errata_id);
+ if (entry == NULL)
+ return EM_UNKNOWN_ERRATUM;
- cpu_ops = get_cpu_ops_ptr();
- assert(cpu_ops != NULL);
-
- entry = cpu_ops->errata_list_start;
- assert(entry != NULL);
-
- end = cpu_ops->errata_list_end;
- assert(end != NULL);
-
- end--; /* point to the last erratum entry of the queried cpu */
-
- while ((entry <= end) && (ret_val == EM_UNKNOWN_ERRATUM)) {
- if (entry->id == errata_id) {
- if (entry->check_func(rev_var)) {
- if (entry->chosen & WA_ENABLED_MASK)
- if (entry->chosen & SPLIT_WA_MASK)
- return EM_AFFECTED;
- else
- return EM_HIGHER_EL_MITIGATION;
- else
- return EM_AFFECTED;
- }
- return EM_NOT_AFFECTED;
- }
- entry += 1;
+ if (entry->check_func(rev_var)) {
+ if (entry->chosen & WA_ENABLED_MASK)
+ if (entry->chosen & SPLIT_WA_MASK)
+ return EM_AFFECTED;
+ else
+ return EM_HIGHER_EL_MITIGATION;
+ else
+ return EM_AFFECTED;
}
- return ret_val;
+ return EM_NOT_AFFECTED;
}
/* Predicate indicating that a function id is part of EM_ABI */
@@ -271,7 +254,7 @@
if (((uint32_t)x2 != 0) && (validate_spsr_mode())) {
SMC_RET1(handle, EM_INVALID_PARAMETERS);
}
- ret_id = verify_errata_implemented((uint32_t)x1, (uint32_t)x2);
+ ret_id = verify_errata_implemented((uint32_t)x1);
SMC_RET1(handle, ret_id);
break; /* unreachable */
default:
diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c
index e0c7971..cc8f557 100644
--- a/services/std_svc/sdei/sdei_event.c
+++ b/services/std_svc/sdei/sdei_event.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,14 +19,14 @@
* Both shared and private maps are stored in single-dimensional array. Private
* event entries are kept for each PE forming a 2D array.
*/
-sdei_entry_t *get_event_entry(sdei_ev_map_t *map)
+sdei_entry_t *get_event_entry(const sdei_ev_map_t *map)
{
const sdei_mapping_t *mapping;
sdei_entry_t *cpu_priv_base;
unsigned int base_idx;
long int idx;
- if (is_event_private(map)) {
+ if ((map->map_flags & BIT_32(SDEI_MAPF_PRIVATE_SHIFT_)) != 0U) {
/*
* For a private map, find the index of the mapping in the
* array.
@@ -52,6 +52,39 @@
}
/*
+ * Retrieve the SDEI entry for the given mapping and target PE.
+ *
+ * on success : Returns a pointer to the SDEI entry
+ *
+ * On error, returns NULL
+ *
+ * Both shared and private maps are stored in single-dimensional array. Private
+ * event entries are kept for each PE forming a 2D array.
+ */
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe)
+{
+ sdei_entry_t *cpu_priv_base;
+ unsigned int base_idx;
+ long int idx;
+
+ /*
+ * For a private map, find the index of the mapping in the
+ * array.
+ */
+ idx = mapsub;
+
+ /* Base of private mappings for this CPU */
+ base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
+ base_idx *= nm;
+ cpu_priv_base = &sdei_private_event_table[base_idx];
+ /*
+ * Return the address of the entry at the same index in the
+ * per-CPU event entry.
+ */
+ return &cpu_priv_base[idx];
+}
+
+/*
* Find event mapping for a given interrupt number: On success, returns pointer
* to the event mapping. On error, returns NULL.
*/
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index c58adba..4854b2e 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,7 +29,8 @@
#define MAX_EVENT_NESTING 2U
/* Per-CPU SDEI state access macro */
-#define sdei_get_this_pe_state() (&cpu_state[plat_my_core_pos()])
+#define sdei_get_this_pe_state() (&cpu_state[plat_my_core_pos()])
+#define sdei_get_target_pe_state(_pe) (&cpu_state[plat_core_pos_by_mpidr(_pe)])
/* Structure to store information about an outstanding dispatch */
typedef struct sdei_dispatch_context {
@@ -58,6 +59,13 @@
/* SDEI states for all cores in the system */
static sdei_cpu_state_t cpu_state[PLATFORM_CORE_COUNT];
+bool sdei_is_target_pe_masked(uint64_t target_pe)
+{
+ const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
+
+ return state->pe_masked;
+}
+
int64_t sdei_pe_mask(void)
{
int64_t ret = 0;
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index 01cc131..bbc9f73 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -910,25 +910,54 @@
/* Send a signal to another SDEI client PE */
static int sdei_signal(int ev_num, uint64_t target_pe)
{
+ unsigned int i;
sdei_ev_map_t *map;
+ sdei_ev_map_t *map_priv;
+ sdei_entry_t *se;
/* Only event 0 can be signalled */
- if (ev_num != SDEI_EVENT_0)
+ if (ev_num != SDEI_EVENT_0) {
return SDEI_EINVAL;
+ }
/* Find mapping for event 0 */
map = find_event_map(SDEI_EVENT_0);
- if (map == NULL)
+ if (map == NULL) {
return SDEI_EINVAL;
+ }
/* The event must be signalable */
- if (!is_event_signalable(map))
+ if (!is_event_signalable(map)) {
return SDEI_EINVAL;
+ }
/* Validate target */
- if (!is_valid_mpidr(target_pe))
+ if (!is_valid_mpidr(target_pe)) {
+ return SDEI_EINVAL;
+ }
+
+ /* The event must be unmasked */
+ if (sdei_is_target_pe_masked(target_pe)) {
return SDEI_EINVAL;
+ }
+ /* The event must be registered and enabled */
+ if (is_event_private(map)) {
+ map_priv = SDEI_PRIVATE_MAPPING()->map;
+ for (i = 0; i < SDEI_PRIVATE_MAPPING()->num_maps; i++) {
+ if (map_priv->ev_num == SDEI_EVENT_0) {
+ se = get_event_entry_target_pe((long int) i,
+ (unsigned int) SDEI_PRIVATE_MAPPING()->num_maps, target_pe);
+ if (!(GET_EV_STATE((se), REGISTERED))) {
+ return SDEI_EINVAL;
+ }
+ if (!(GET_EV_STATE((se), ENABLED))) {
+ return SDEI_EINVAL;
+ }
+ }
+ map_priv++;
+ }
+ }
/* Raise SGI. Platform will validate target_pe */
plat_ic_raise_el3_sgi((int) map->intr, (u_register_t) target_pe);
diff --git a/services/std_svc/sdei/sdei_private.h b/services/std_svc/sdei/sdei_private.h
index 44a7301..d48db46 100644
--- a/services/std_svc/sdei/sdei_private.h
+++ b/services/std_svc/sdei/sdei_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -232,13 +232,15 @@
sdei_ev_map_t *find_event_map_by_intr(unsigned int intr_num, bool shared);
sdei_ev_map_t *find_event_map(int ev_num);
-sdei_entry_t *get_event_entry(sdei_ev_map_t *map);
+sdei_entry_t *get_event_entry(const sdei_ev_map_t *map);
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe);
int64_t sdei_event_context(void *handle, unsigned int param);
int sdei_event_complete(bool resume, uint64_t pc);
-void sdei_pe_unmask(void);
+bool sdei_is_target_pe_masked(uint64_t target_pe);
int64_t sdei_pe_mask(void);
+void sdei_pe_unmask(void);
int sdei_intr_handler(uint32_t intr_raw, uint32_t flags, void *handle,
void *cookie);
diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index 9975ea3..81e9fb8 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json
@@ -1,6 +1,6 @@
{
"name": "conventional-changelog-tf-a",
- "version": "2.12.0",
+ "version": "2.13.0",
"license": "BSD-3-Clause",
"private": true,
"main": "index.js",