| commit | 0cba8cffbecead9ac6a8363fc24b17c18fb326ca | [log] [tgz] |
|---|---|---|
| author | Guo Yi <yguo@cavium.com> | Wed Feb 17 00:56:48 2021 +0000 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Tue Apr 20 12:59:54 2021 +0200 |
| tree | 0eb19d353e0bf2664cbb6b1a8ebfd0ffbb1af114 | |
| parent | 2309961fa23dd9eb5369e1a019ad94278eb4de53 [diff] |
plat: marvell: armada: a8k: Fix LD selector mask Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by: Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
diff --git a/plat/marvell/armada/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c index 4114327..59a3a3a 100644 --- a/plat/marvell/armada/a8k/common/plat_ble_setup.c +++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c
@@ -383,7 +383,7 @@ /* Set access to LD0 */ reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); - reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_OFFS; + reg_val &= ~EFUSE_SRV_CTRL_LD_SEL_USER_MASK; mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); /* Obtain the value of LD0[125:63] */