FVP: apply new naming conventions to memory regions
Secure ROM at address 0x0000_0000 is defined as FVP_TRUSTED_ROM
Secure RAM at address 0x0400_0000 is defined as FVP_TRUSTED_SRAM
Secure RAM at address 0x0600_0000 is defined as FVP_TRUSTED_DRAM
BLn_BASE and BLn_LIMIT definitions have been updated and are based on
these new memory regions.
The available memory for each bootloader in the linker script is
defined by BLn_BASE and BLn_LIMIT, instead of the complete memory
region.
TZROM_BASE/SIZE and TZRAM_BASE/SIZE are no longer required as part of
the platform porting.
FVP common definitions are defined in fvp_def.h while platform_def.h
contains exclusively (with a few exceptions) the definitions that are
mandatory in the porting guide. Therefore, platform_def.h now includes
fvp_def.h instead of the other way around.
Porting guide has been updated to reflect these changes.
Change-Id: I39a6088eb611fc4a347db0db4b8f1f0417dbab05
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S
index 967ba32..0ca4a63 100644
--- a/bl1/bl1.ld.S
+++ b/bl1/bl1.ld.S
@@ -35,8 +35,8 @@
ENTRY(bl1_entrypoint)
MEMORY {
- ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
- RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
+ ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT
+ RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT
}
SECTIONS
diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S
index e348d4f..1665f5d 100644
--- a/bl2/bl2.ld.S
+++ b/bl2/bl2.ld.S
@@ -35,7 +35,7 @@
ENTRY(bl2_entrypoint)
MEMORY {
- RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
+ RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT
}
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 34a349f..83ef7e7 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -36,7 +36,7 @@
MEMORY {
- RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
+ RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT
}
diff --git a/docs/porting-guide.md b/docs/porting-guide.md
index db2bad8..eb3b86d 100644
--- a/docs/porting-guide.md
+++ b/docs/porting-guide.md
@@ -150,31 +150,6 @@
Defines the total number of nodes in the affinity heirarchy at all affinity
levels used by the platform.
-* **#define : TZROM_BASE**
-
- Defines the base address of secure ROM on the platform, where the BL1 binary
- is loaded. This constant is used by the linker scripts to ensure that the
- BL1 image fits into the available memory.
-
-* **#define : TZROM_SIZE**
-
- Defines the size of secure ROM on the platform. This constant is used by the
- linker scripts to ensure that the BL1 image fits into the available memory.
-
-* **#define : TZRAM_BASE**
-
- Defines the base address of the secure RAM on platform, where the data
- section of the BL1 binary is loaded. The BL2 and BL3-1 images are also
- loaded in this secure RAM region. This constant is used by the linker
- scripts to ensure that the BL1 data section and BL2/BL3-1 binary images fit
- into the available memory.
-
-* **#define : TZRAM_SIZE**
-
- Defines the size of the secure RAM on the platform. This constant is used by
- the linker scripts to ensure that the BL1 data section and BL2/BL3-1 binary
- images fit into the available memory.
-
* **#define : BL1_RO_BASE**
Defines the base address in secure ROM where BL1 originally lives. Must be
diff --git a/docs/user-guide.md b/docs/user-guide.md
index ef5de71..4af9c28 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -314,11 +314,11 @@
On FVP, the TSP binary runs from Trusted SRAM by default. It is also possible
to run it from Trusted DRAM. This is controlled by the build configuration
-`TSP_RAM_LOCATION`:
+`FVP_TSP_RAM_LOCATION`:
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
BL33=<path-to>/<bl33_image> \
- make PLAT=fvp SPD=tspd TSP_RAM_LOCATION=tdram all fip
+ make PLAT=fvp SPD=tspd FVP_TSP_RAM_LOCATION=tdram all fip
### Checking source code style
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index d22fd55..b8f32a1 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -56,9 +56,9 @@
* configure_mmu_elx() will give the available subset of that,
*/
const mmap_region_t fvp_mmap[] = {
- { TZROM_BASE, TZROM_BASE, TZROM_SIZE,
+ { FVP_TRUSTED_ROM_BASE, FVP_TRUSTED_ROM_BASE, FVP_TRUSTED_ROM_SIZE,
MT_MEMORY | MT_RO | MT_SECURE },
- { TZDRAM_BASE, TZDRAM_BASE, TZDRAM_SIZE,
+ { FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_SIZE,
MT_MEMORY | MT_RW | MT_SECURE },
{ FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE,
MT_MEMORY | MT_RO | MT_SECURE },
diff --git a/plat/fvp/aarch64/fvp_helpers.S b/plat/fvp/aarch64/fvp_helpers.S
index 4011306..4eecd4c 100644
--- a/plat/fvp/aarch64/fvp_helpers.S
+++ b/plat/fvp/aarch64/fvp_helpers.S
@@ -34,7 +34,7 @@
#include <gic_v2.h>
#include <pl011.h>
#include "../drivers/pwrc/fvp_pwrc.h"
-#include "../fvp_def.h"
+#include "platform_def.h"
.globl platform_get_entrypoint
.globl plat_secondary_cold_boot_setup
@@ -140,7 +140,7 @@
* its safe to read it here with SO attributes
* ---------------------------------------------
*/
- ldr x10, =TZDRAM_BASE + MBOX_OFF
+ ldr x10, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
bl platform_get_core_pos
lsl x0, x0, #CACHE_WRITEBACK_SHIFT
ldr x0, [x10, x0]
@@ -163,7 +163,7 @@
* -----------------------------------------------------
*/
func platform_mem_init
- ldr x0, =TZDRAM_BASE + MBOX_OFF
+ ldr x0, =FVP_TRUSTED_DRAM_BASE + MBOX_OFF
mov w1, #PLATFORM_CORE_COUNT
loop:
str xzr, [x0], #CACHE_WRITEBACK_GRANULE
diff --git a/plat/fvp/bl1_fvp_setup.c b/plat/fvp/bl1_fvp_setup.c
index b146fdb..ddb81df 100644
--- a/plat/fvp/bl1_fvp_setup.c
+++ b/plat/fvp/bl1_fvp_setup.c
@@ -76,12 +76,12 @@
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Allow BL1 to see the whole Trusted RAM */
- bl1_tzram_layout.total_base = TZRAM_BASE;
- bl1_tzram_layout.total_size = TZRAM_SIZE;
+ bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
+ bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
/* Calculate how much RAM BL1 is using and how much remains free */
- bl1_tzram_layout.free_base = TZRAM_BASE;
- bl1_tzram_layout.free_size = TZRAM_SIZE;
+ bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
+ bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
reserve_mem(&bl1_tzram_layout.free_base,
&bl1_tzram_layout.free_size,
BL1_RAM_BASE,
@@ -117,8 +117,8 @@
fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
bl1_tzram_layout.total_size,
- TZROM_BASE,
- TZROM_BASE + TZROM_SIZE,
+ BL1_RO_BASE,
+ BL1_RO_LIMIT,
BL1_COHERENT_RAM_BASE,
BL1_COHERENT_RAM_LIMIT);
}
diff --git a/plat/fvp/bl2_fvp_setup.c b/plat/fvp/bl2_fvp_setup.c
index c0ad340..b200b37 100644
--- a/plat/fvp/bl2_fvp_setup.c
+++ b/plat/fvp/bl2_fvp_setup.c
@@ -97,7 +97,7 @@
{
bl2_to_bl31_params_mem_t *bl31_params_mem;
-#if TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
+#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
/*
* Ensure that the secure DRAM memory used for passing BL31 arguments
* does not overlap with the BL32_BASE.
diff --git a/plat/fvp/fvp_def.h b/plat/fvp/fvp_def.h
index a757b4d..c54537f 100644
--- a/plat/fvp/fvp_def.h
+++ b/plat/fvp/fvp_def.h
@@ -1,4 +1,4 @@
-#/*
+/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -31,19 +31,29 @@
#ifndef __FVP_DEF_H__
#define __FVP_DEF_H__
-#include <platform_def.h> /* for TZROM_SIZE */
-
-
/* Firmware Image Package */
#define FIP_IMAGE_NAME "fip.bin"
#define FVP_PRIMARY_CPU 0x0
+/* Memory location options for Shared data and TSP in FVP */
+#define FVP_IN_TRUSTED_SRAM 0
+#define FVP_IN_TRUSTED_DRAM 1
+
/*******************************************************************************
* FVP memory map related constants
******************************************************************************/
+#define FVP_TRUSTED_ROM_BASE 0x00000000
+#define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
+
+#define FVP_TRUSTED_SRAM_BASE 0x04000000
+#define FVP_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
+
+#define FVP_TRUSTED_DRAM_BASE 0x06000000
+#define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
+
#define FLASH0_BASE 0x08000000
-#define FLASH0_SIZE TZROM_SIZE
+#define FLASH0_SIZE 0x04000000
#define FLASH1_BASE 0x0c000000
#define FLASH1_SIZE 0x04000000
@@ -67,7 +77,7 @@
#define MBOX_OFF 0x1000
/* Base address where parameters to BL31 are stored */
-#define PARAMS_BASE TZDRAM_BASE
+#define PARAMS_BASE FVP_TRUSTED_DRAM_BASE
#define DRAM1_BASE 0x80000000ull
#define DRAM1_SIZE 0x80000000ull
@@ -229,5 +239,4 @@
#define FVP_NSAID_HDLCD0 2
#define FVP_NSAID_CLCD 7
-
#endif /* __FVP_DEF_H__ */
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index 22e53e1..775e558 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -103,7 +103,7 @@
} while (psysr & PSYSR_AFF_L0);
linear_id = platform_get_core_pos(mpidr);
- fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
+ fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE + MBOX_OFF);
fvp_mboxes[linear_id].value = sec_entrypoint;
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
@@ -240,7 +240,8 @@
/* Program the jump address for the target cpu */
linear_id = platform_get_core_pos(mpidr);
- fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
+ fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE +
+ MBOX_OFF);
fvp_mboxes[linear_id].value = sec_entrypoint;
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
sizeof(unsigned long));
@@ -329,7 +330,8 @@
fvp_pwrc_clr_wen(mpidr);
/* Zero the jump address in the mailbox for this cpu */
- fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
+ fvp_mboxes = (mailbox_t *) (FVP_TRUSTED_DRAM_BASE +
+ MBOX_OFF);
linear_id = platform_get_core_pos(mpidr);
fvp_mboxes[linear_id].value = 0;
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h
index 70f84bb..3b94c42 100644
--- a/plat/fvp/include/platform_def.h
+++ b/plat/fvp/include/platform_def.h
@@ -32,6 +32,7 @@
#define __PLATFORM_DEF_H__
#include <arch.h>
+#include <../fvp_def.h>
/*******************************************************************************
@@ -74,31 +75,22 @@
#define MAX_IO_HANDLES 4
/*******************************************************************************
- * Platform memory map related constants
- ******************************************************************************/
-#define TZROM_BASE 0x00000000
-#define TZROM_SIZE 0x04000000
-
-#define TZRAM_BASE 0x04000000
-#define TZRAM_SIZE 0x40000
-
-/* Location of trusted dram on the base fvp */
-#define TZDRAM_BASE 0x06000000
-#define TZDRAM_SIZE 0x02000000
-
-/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
-#define BL1_RO_BASE TZROM_BASE
-#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
+#define BL1_RO_BASE FVP_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \
+ + FVP_TRUSTED_ROM_SIZE)
/*
* Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
* the current BL1 RW debug size plus a little space for growth.
*/
-#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000)
-#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE)
+#define BL1_RW_BASE (FVP_TRUSTED_SRAM_BASE + \
+ FVP_TRUSTED_SRAM_SIZE - \
+ 0x6000)
+#define BL1_RW_LIMIT (FVP_TRUSTED_SRAM_BASE + \
+ FVP_TRUSTED_SRAM_SIZE)
/*******************************************************************************
* BL2 specific defines.
@@ -117,9 +109,12 @@
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
-#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000)
+#define BL31_BASE (FVP_TRUSTED_SRAM_BASE + \
+ FVP_TRUSTED_SRAM_SIZE - \
+ 0x1D000)
#define BL31_PROGBITS_LIMIT BL1_RW_BASE
-#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
+#define BL31_LIMIT (FVP_TRUSTED_SRAM_BASE + \
+ FVP_TRUSTED_SRAM_SIZE)
/*******************************************************************************
* BL32 specific defines.
@@ -127,22 +122,19 @@
/*
* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
*/
-#define TSP_IN_TZRAM 0
-#define TSP_IN_TZDRAM 1
-
-#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
-# define TSP_SEC_MEM_BASE TZRAM_BASE
-# define TSP_SEC_MEM_SIZE TZRAM_SIZE
-# define BL32_BASE TZRAM_BASE
+#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM
+# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
+# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
+# define BL32_BASE FVP_TRUSTED_SRAM_BASE
# define BL32_PROGBITS_LIMIT BL2_BASE
# define BL32_LIMIT BL31_BASE
-#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
-# define TSP_SEC_MEM_BASE TZDRAM_BASE
-# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
-# define BL32_BASE (TZDRAM_BASE + 0x2000)
-# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
+#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
+# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
+# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
+# define BL32_BASE (FVP_TRUSTED_DRAM_BASE + 0x2000)
+# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
#else
-# error "Unsupported TSP_RAM_LOCATION_ID value"
+# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
#endif
/*******************************************************************************
diff --git a/plat/fvp/platform.mk b/plat/fvp/platform.mk
index f6275b7..945a300 100644
--- a/plat/fvp/platform.mk
+++ b/plat/fvp/platform.mk
@@ -30,18 +30,17 @@
# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
# Trusted SRAM is the default.
-TSP_RAM_LOCATION := tsram
-
-ifeq (${TSP_RAM_LOCATION}, tsram)
- TSP_RAM_LOCATION_ID := TSP_IN_TZRAM
-else ifeq (${TSP_RAM_LOCATION}, tdram)
- TSP_RAM_LOCATION_ID := TSP_IN_TZDRAM
+FVP_TSP_RAM_LOCATION := tsram
+ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
+ FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_SRAM
+else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
+ FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_DRAM
else
- $(error "Unsupported TSP_RAM_LOCATION value")
+ $(error "Unsupported FVP_TSP_RAM_LOCATION value")
endif
-# Process TSP_RAM_LOCATION_ID flag
-$(eval $(call add_define,TSP_RAM_LOCATION_ID))
+# Process flags
+$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
PLAT_INCLUDES := -Iplat/fvp/include/