commit 0c2a2caa8ba9a9672a719dfccc3bf0568467b00d
author Pranav Madhu <pranav.madhu@arm.com> Mon Aug 01 13:57:52 2022 +0530
committer Pranav Madhu <pranav.madhu@arm.com> Thu Sep 15 18:09:56 2022 +0530
tree fd9915356eac4cfd6de36db1a723815de8886796
parent 434c0b71c6995d6ab42068df86494a7c995f74d2

fix(gicv3): update the affinity mask to 8 bit

The GIC ICC_SGI0R_EL1 register's affinity fields are 8bit wide for GIC
v3 and v4. Fix the SGIR_AFF_MASK variable accordingly.

Change-Id: I09f3fdd006708b40162776620f82abcfc6c3f782
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

include/drivers/arm/gicv3.h

diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index 8371dd5..860ea7a 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -315,7 +315,7 @@
 #define SGIR_IRM_SHIFT			40
 #define SGIR_IRM_MASK			ULL(0x1)
 #define SGIR_AFF3_SHIFT			48
-#define SGIR_AFF_MASK			ULL(0xf)
+#define SGIR_AFF_MASK			ULL(0xff)
 
 #define SGIR_IRM_TO_AFF			U(0)