diff --git a/.gitignore b/.gitignore
index b4359c1..562f812 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,6 +11,10 @@
 
 # Ignore build products from tools
 tools/**/*.o
+tools/renesas/rcar_layout_create/*.bin
+tools/renesas/rcar_layout_create/*.srec
+tools/renesas/rcar_layout_create/*.map
+tools/renesas/rcar_layout_create/*.elf
 tools/fiptool/fiptool
 tools/fiptool/fiptool.exe
 tools/cert_create/src/*.o
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 66cb3f3..81e7ba3 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -188,8 +188,15 @@
         __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
         . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
         __BAKERY_LOCK_END__ = .;
+
+	/*
+	 * If BL31 doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__
+	 * will be zero. For this reason, the only two valid values for
+	 * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value
+	 * PLAT_PERCPU_BAKERY_LOCK_SIZE.
+	 */
 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
-    ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
+    ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE),
         "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
 #endif
 #endif
diff --git a/docs/plat/rcar-gen3.rst b/docs/plat/rcar-gen3.rst
new file mode 100644
index 0000000..84e0e67
--- /dev/null
+++ b/docs/plat/rcar-gen3.rst
@@ -0,0 +1,269 @@
+Description
+===========
+
+"R-Car" is the nickname for Renesas' system-on-chip (SoC) family for
+car information systems designed for the next-generation of automotive
+computing for the age of autonomous vehicles.
+
+The scalable R-Car hardware platform and flexible software platform
+cover the full product range, from the premium class to the entry
+level. Plug-ins are available for multiple open-source software tools.
+
+
+Renesas R-Car Gen3 evaluation boards:
+-------------------------------------
+
++------------+-----------------+-----------------------------+
+|            |     Standard    |   Low Cost Boards (LCB)     |
++============+=================+=============================+
+| R-Car H3   | - Salvator-X    | - R-Car Starter Kit Premier |
+|            | - Salvator-XS   |                             |
++------------+-----------------+-----------------------------+
+| R-Car M3-W | - Salvator-X    |                             |
+|            | - Salvator-XS   | - R-Car Starter Kit Pro     |
++------------+-----------------+-----------------------------+
+| R-Car M3-N | - Salvator-X    |                             |
+|            | - Salvator-XS   |                             |
++------------+-----------------+-----------------------------+
+| R-Car V3M  | - Eagle         | - Starter Kit               |
++------------+-----------------+-----------------------------+
+| R-Car V3H  | - Condor        | - Starter Kit               |
++------------+-----------------+-----------------------------+
+| R-Car D3   | - Draak         |                             |
++------------+-----------------+-----------------------------+
+
+`boards info <https://elinux.org/R-Car>`__
+
+The current TF-A port has been tested on the R-Car H3 Salvator-X
+Soc_id r8a7795 revision ES1.1 (uses a Secure Payload Dispatcher)
+
+
+::
+
+    ARM CA57 (ARMv8) 1.5 GHz quad core, with NEON/VFPv4, L1$ I/D
+    48K/32K, L2$ 2MB
+    ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K,
+    L2$ 512K
+    Memory controller for LPDDR4-3200 4GB in 2 channels, each 64-bit wide
+    Two- and three-dimensional graphics engines,
+    Video processing units,
+    3 channels Display Output,
+    6 channels Video Input,
+    SD card host interface,
+    USB3.0 and USB2.0 interfaces,
+    CAN interfaces
+    Ethernet AVB
+    PCI Express Interfaces
+    Memories
+        INTERNAL 384KB SYSTEM RAM
+        DDR 4 GB LPDDR4
+        HYPERFLASH 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S)
+        QSPI FLASH 16MB QSPI (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI
+        MODULE
+        EMMC 32 GB EMMC (HS400 240 MBYTES/S)
+        MICROSD-CARD SLOT (SDR104 100 MBYTES/S)
+
+
+Overview
+--------
+On the rcar-gen3 the BOOTROM starts the cpu at EL3; for this port BL2
+will therefore be entered at this exception level (the Renesas' ATF
+reference tree [1] resets into EL1 before entering BL2 - see its
+bl2.ld.S)
+
+BL2 initializes DDR (and on some platforms i2c to interface to the
+PMIC) before determining the boot reason (cold or warm).
+
+During suspend all CPUs are switched off and the DDR is put in backup
+mode (some kind of self-refresh mode). This means that BL2 is always
+entered in a cold boot scenario.
+
+Once BL2 boots, it determines the boot reason, writes it to shared
+memory (BOOT_KIND_BASE) together with the BL31 parameters
+(PARAMS_BASE) and jumps to BL31.
+
+To all effects, BL31 is as if it is being entered in reset mode since
+it still needs to initialize the rest of the cores; this is the reason
+behind using direct shared memory access to  BOOT_KIND_BASE _and_
+PARAMS_BASE instead of using registers to get to those locations (see
+el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
+case).
+
+Depending on the boot reason BL31 initializes the rest of the cores:
+in case of suspend, it uses a MBOX memory region to recover the
+program counters.
+
+[1] https://github.com/renesas-rcar/arm-trusted-firmware
+
+
+How to build
+============
+
+The TF-A build options depend on the target board so you will have to
+refer to those specific instructions. What follows is customized to
+the H3 SiP Salvator-X development system used in this port.
+
+Build Tested:
+-------------
+RCAR_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
+MBEDTLS_DIR=$mbedtls_src
+
+$ MBEDTLS_DIR=$mbedtls_src_tree make clean bl2 bl31 rcar_layout_tool \
+PLAT=rcar ${RCAR_OPT} SPD=opteed
+
+System Tested:
+--------------------
+* mbed_tls:
+  git@github.com:ARMmbed/mbedtls.git [devel]
+
+  commit 552754a6ee82bab25d1bdf28c8261a4518e65e4d
+  Merge: 68dbc94 f34a4c1
+  Author: Simon Butcher <simon.butcher@arm.com>
+  Date:   Thu Aug 30 00:57:28 2018 +0100
+
+* optee_os:
+  https://github.com/BayLibre/optee_os
+
+  Until it gets merged into OP-TEE, the port requires Renesas'
+  Trusted   Environment with a modification to support power
+  management.
+  commit 80105192cba9e704ebe8df7ab84095edc2922f84
+
+  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
+  Date:   Thu Aug 30 16:49:49 2018 +0200
+  plat-rcar: cpu-suspend: handle the power level
+  Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
+
+* u-boot:
+  The port has beent tested using mainline uboot.
+
+  commit 4cdeda511f8037015b568396e6dcc3d8fb41e8c0
+  Author: Fabio Estevam <festevam@gmail.com>
+  Date:   Tue Sep 4 10:23:12 2018 -0300
+
+* linux:
+  The port has beent tested using mainline kernel.
+
+  commit 7876320f88802b22d4e2daf7eb027dd14175a0f8
+  Author: Linus Torvalds <torvalds@linux-foundation.org>
+  Date:   Sun Sep 16 11:52:37 2018 -0700
+  Linux 4.19-rc4
+
+TF-A Build Procedure
+--------------------
+
+-  Fetch all the above 4 repositories.
+
+-  Prepare the AARCH64 toolchain.
+
+-  Build u-boot using r8a7795_salvator-x_defconfig.
+   Result: u-boot-elf.srec
+
+.. code:: bash
+
+       make CROSS_COMPILE=aarch64-linux-gnu-
+	  r8a7795_salvator-x_defconfig
+
+       make CROSS_COMPILE=aarch64-linux-gnu-
+
+-  Build atf
+   Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec
+
+.. code:: bash
+
+       RCAR_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
+
+       MBEDTLS_DIR=$mbedtls_src_tree make clean bl2 bl31 rcar \
+       PLAT=rcar ${RCAR_OPT} SPD=opteed
+
+-  Build optee-os
+   Result: tee.srec
+
+.. code:: bash
+
+       make -j8 PLATFORM="rcar" CFG_ARM64_core=y
+
+Install Procedure
+-----------------
+
+- Boot the board in Mini-monitor mode and enable access to the
+  Hyperflash.
+
+
+- Use the XSL2 Mini-monitor utility to accept all the SREC ascii
+  transfers over serial.
+
+
+Boot trace
+==========
+
+Notice that BL31 traces are not accessible via the console and that in
+order to verbose the BL2 output you will have to compile TF-A with
+LOG_LEVEL=50 and DEBUG=1
+
+::
+
+   Initial Program Loader(CA57) Rev.1.0.22
+   NOTICE:  BL2: PRR is R-Car H3 Ver.1.1
+   NOTICE:  BL2: Board is Salvator-X Rev.1.0
+   NOTICE:  BL2: Boot device is HyperFlash(80MHz)
+   NOTICE:  BL2: LCM state is CM
+   NOTICE:  AVS setting succeeded. DVFS_SetVID=0x53
+   NOTICE:  BL2: DDR1600(rev.0.33)NOTICE:  [COLD_BOOT]NOTICE:  ..0
+   NOTICE:  BL2: DRAM Split is 4ch
+   NOTICE:  BL2: QoS is default setting(rev.0.37)
+   NOTICE:  BL2: Lossy Decomp areas
+   NOTICE:       Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
+   NOTICE:       Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
+   NOTICE:       Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
+   NOTICE:  BL2: v2.0(release):v2.0-rc0-32-gbcda69a
+   NOTICE:  BL2: Built : 16:41:23, Oct  2 2018
+   NOTICE:  BL2: Normal boot
+   INFO:    BL2: Doing platform setup
+   INFO:    BL2: Loading image id 3
+   NOTICE:  BL2: dst=0xe6322000 src=0x8180000 len=512(0x200)
+   NOTICE:  BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)
+   WARNING: r-car ignoring the BL31 size from certificate,using
+   RCAR_TRUSTED_SRAM_SIZE instead
+   INFO:    Loading image id=3 at address 0x44000000
+   NOTICE:  rcar_file_len: len: 0x0003e000
+   NOTICE:  BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000)
+   INFO:    Image id=3 loaded: 0x44000000 - 0x4403e000
+   INFO:    BL2: Loading image id 4
+   INFO:    Loading image id=4 at address 0x44100000
+   NOTICE:  rcar_file_len: len: 0x00100000
+   NOTICE:  BL2: dst=0x44100000 src=0x8200000 len=1048576(0x100000)
+   INFO:    Image id=4 loaded: 0x44100000 - 0x44200000
+   INFO:    BL2: Loading image id 5
+   INFO:    Loading image id=5 at address 0x50000000
+   NOTICE:  rcar_file_len: len: 0x00100000
+   NOTICE:  BL2: dst=0x50000000 src=0x8640000 len=1048576(0x100000)
+   INFO:    Image id=5 loaded: 0x50000000 - 0x50100000
+   NOTICE:  BL2: Booting BL31
+   INFO:    Entry point address = 0x44000000
+   INFO:    SPSR = 0x3cd
+   VERBOSE: Argument #0 = 0xe6325578
+   VERBOSE: Argument #1 = 0x0
+   VERBOSE: Argument #2 = 0x0
+   VERBOSE: Argument #3 = 0x0
+   VERBOSE: Argument #4 = 0x0
+   VERBOSE: Argument #5 = 0x0
+   VERBOSE: Argument #6 = 0x0
+   VERBOSE: Argument #7 = 0x0
+
+
+   U-Boot 2018.09-rc3-00028-g3711616 (Sep 27 2018 - 18:50:24 +0200)
+
+   CPU: Renesas Electronics R8A7795 rev 1.1
+   Model: Renesas Salvator-X board based on r8a7795 ES2.0+
+   DRAM:  3.5 GiB
+   Flash: 64 MiB
+   MMC:   sd@ee100000: 0, sd@ee140000: 1, sd@ee160000: 2
+   Loading Environment from MMC... OK
+   In:    serial@e6e88000
+   Out:   serial@e6e88000
+   Err:   serial@e6e88000
+   Net:   eth0: ethernet@e6800000
+   Hit any key to stop autoboot:  0
+   =>
+
diff --git a/drivers/renesas/rcar/auth/auth_mod.c b/drivers/renesas/rcar/auth/auth_mod.c
new file mode 100644
index 0000000..04ed279
--- /dev/null
+++ b/drivers/renesas/rcar/auth/auth_mod.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights
+ * reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <mmio.h>
+#include <platform.h>
+#include <platform_def.h>
+#include <stddef.h>
+
+#include "rom_api.h"
+
+typedef int32_t(*secure_boot_api_f) (uint32_t a, uint32_t b, void *c);
+extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr);
+
+#define	RCAR_IMAGE_ID_MAX	(10)
+#define	RCAR_CERT_MAGIC_NUM	(0xE291F358U)
+#define RCAR_BOOT_KEY_CERT	(0xE6300C00U)
+#define RCAR_BOOT_KEY_CERT_NEW	(0xE6300F00U)
+#define	RST_BASE		(0xE6160000U)
+#define	RST_MODEMR		(RST_BASE + 0x0060U)
+#define	MFISSOFTMDR		(0xE6260600U)
+#define	MODEMR_MD5_MASK		(0x00000020U)
+#define	MODEMR_MD5_SHIFT	(5U)
+#define	SOFTMD_BOOTMODE_MASK	(0x00000001U)
+#define	SOFTMD_NORMALBOOT	(0x1U)
+
+static secure_boot_api_f secure_boot_api;
+
+int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id)
+{
+	return 1;
+}
+
+int auth_mod_verify_img(unsigned int img_id, void *ptr, unsigned int len)
+{
+	int32_t ret = 0, index = 0;
+	uint32_t cert_addr = 0U;
+	static const struct img_to_cert_t {
+		uint32_t id;
+		int32_t cert;
+		const char *name;
+	} image[RCAR_IMAGE_ID_MAX] = {
+		{ BL31_IMAGE_ID, SOC_FW_CONTENT_CERT_ID, "BL31" },
+		{ BL32_IMAGE_ID, TRUSTED_OS_FW_CONTENT_CERT_ID, "BL32" },
+		{ BL33_IMAGE_ID, NON_TRUSTED_FW_CONTENT_CERT_ID, "BL33" },
+		{ BL332_IMAGE_ID, BL332_CERT_ID, "BL332" },
+		{ BL333_IMAGE_ID, BL333_CERT_ID, "BL333" },
+		{ BL334_IMAGE_ID, BL334_CERT_ID, "BL334" },
+		{ BL335_IMAGE_ID, BL335_CERT_ID, "BL335" },
+		{ BL336_IMAGE_ID, BL336_CERT_ID, "BL336" },
+		{ BL337_IMAGE_ID, BL337_CERT_ID, "BL337" },
+		{ BL338_IMAGE_ID, BL338_CERT_ID, "BL338" },
+	};
+
+#if IMAGE_BL2
+	switch (img_id) {
+	case TRUSTED_KEY_CERT_ID:
+	case SOC_FW_KEY_CERT_ID:
+	case TRUSTED_OS_FW_KEY_CERT_ID:
+	case NON_TRUSTED_FW_KEY_CERT_ID:
+	case BL332_KEY_CERT_ID:
+	case BL333_KEY_CERT_ID:
+	case BL334_KEY_CERT_ID:
+	case BL335_KEY_CERT_ID:
+	case BL336_KEY_CERT_ID:
+	case BL337_KEY_CERT_ID:
+	case BL338_KEY_CERT_ID:
+	case SOC_FW_CONTENT_CERT_ID:
+	case TRUSTED_OS_FW_CONTENT_CERT_ID:
+	case NON_TRUSTED_FW_CONTENT_CERT_ID:
+	case BL332_CERT_ID:
+	case BL333_CERT_ID:
+	case BL334_CERT_ID:
+	case BL335_CERT_ID:
+	case BL336_CERT_ID:
+	case BL337_CERT_ID:
+	case BL338_CERT_ID:
+		return ret;
+	case BL31_IMAGE_ID:
+	case BL32_IMAGE_ID:
+	case BL33_IMAGE_ID:
+	case BL332_IMAGE_ID:
+	case BL333_IMAGE_ID:
+	case BL334_IMAGE_ID:
+	case BL335_IMAGE_ID:
+	case BL336_IMAGE_ID:
+	case BL337_IMAGE_ID:
+	case BL338_IMAGE_ID:
+		goto verify_image;
+	default:
+		return -1;
+	}
+
+verify_image:
+	for (index = 0; index < RCAR_IMAGE_ID_MAX; index++) {
+		if (img_id != image[index].id)
+			continue;
+
+		ret = rcar_get_certificate(image[index].cert, &cert_addr);
+		break;
+	}
+
+	if (ret || (index == RCAR_IMAGE_ID_MAX)) {
+		ERROR("Verification Failed for image id = %d\n", img_id);
+		return ret;
+	}
+#if RCAR_BL2_DCACHE == 1
+	/* clean and disable */
+	write_sctlr_el1(read_sctlr_el1() & ~SCTLR_C_BIT);
+	dcsw_op_all(DCCISW);
+#endif
+	ret = (mmio_read_32(RCAR_BOOT_KEY_CERT_NEW) == RCAR_CERT_MAGIC_NUM) ?
+	    secure_boot_api(RCAR_BOOT_KEY_CERT_NEW, cert_addr, NULL) :
+	    secure_boot_api(RCAR_BOOT_KEY_CERT, cert_addr, NULL);
+	if (ret)
+		ERROR("Verification Failed 0x%x, %s\n", ret, image[index].name);
+
+#if RCAR_BL2_DCACHE == 1
+	/* enable */
+	write_sctlr_el1(read_sctlr_el1() | SCTLR_C_BIT);
+#endif
+
+#endif
+	return ret;
+}
+
+static int32_t normal_boot_verify(uint32_t a, uint32_t b, void *c)
+{
+	return 0;
+}
+
+void auth_mod_init(void)
+{
+#if RCAR_SECURE_BOOT
+	uint32_t soft_md = mmio_read_32(MFISSOFTMDR) & SOFTMD_BOOTMODE_MASK;
+	uint32_t md = mmio_read_32(RST_MODEMR) & MODEMR_MD5_MASK;
+	uint32_t lcs, ret;
+
+	secure_boot_api = (secure_boot_api_f) &rcar_rom_secure_boot_api;
+
+	ret = rcar_rom_get_lcs(&lcs);
+	if (ret) {
+		ERROR("BL2: Failed to get the LCS. (%d)\n", ret);
+		panic();
+	}
+
+	switch (lcs) {
+	case LCS_SE:
+		if (soft_md == SOFTMD_NORMALBOOT)
+			secure_boot_api = &normal_boot_verify;
+		break;
+	case LCS_SD:
+		secure_boot_api = &normal_boot_verify;
+		break;
+	default:
+		if (md >> MODEMR_MD5_SHIFT)
+			secure_boot_api = &normal_boot_verify;
+	}
+
+	NOTICE("BL2: %s boot\n",
+	       secure_boot_api == &normal_boot_verify ? "Normal" : "Secure");
+#else
+	NOTICE("BL2: Normal boot\n");
+	secure_boot_api = &normal_boot_verify;
+#endif
+}
diff --git a/drivers/renesas/rcar/avs/avs_driver.c b/drivers/renesas/rcar/avs/avs_driver.c
new file mode 100644
index 0000000..80a7c91
--- /dev/null
+++ b/drivers/renesas/rcar/avs/avs_driver.c
@@ -0,0 +1,623 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <debug.h>
+#include <utils_def.h>
+#include "cpg_registers.h"
+#include "avs_driver.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+
+#if (AVS_SETTING_ENABLE == 1)
+#if PMIC_ROHM_BD9571
+/* Read PMIC register for debug. 1:enable / 0:disable */
+#define AVS_READ_PMIC_REG_ENABLE	0
+/* The re-try number of times of the AVS setting. */
+#define AVS_RETRY_NUM			(1U)
+#endif /* PMIC_ROHM_BD9571 */
+
+/* Base address of Adaptive Voltage Scaling module registers*/
+#define	AVS_BASE			(0xE60A0000U)
+/* Adaptive Dynamic Voltage ADJust Parameter2 registers */
+#define	ADVADJP2			(AVS_BASE + 0x013CU)
+
+/* Mask VOLCOND bit in ADVADJP2 registers */
+#define	ADVADJP2_VOLCOND_MASK		(0x000001FFU)	/* VOLCOND[8:0] */
+
+#if PMIC_ROHM_BD9571
+/* I2C for DVFS bit in CPG registers for module standby and software reset*/
+#define CPG_SYS_DVFS_BIT		(0x04000000U)
+#endif /* PMIC_ROHM_BD9571 */
+/* ADVFS Module bit in CPG registers for module standby and software reset*/
+#define CPG_SYS_ADVFS_BIT		(0x02000000U)
+
+#if PMIC_ROHM_BD9571
+/* Base address of IICDVFS registers*/
+#define	IIC_DVFS_BASE			(0xE60B0000U)
+/* IIC bus data register */
+#define	IIC_ICDR			(IIC_DVFS_BASE + 0x0000U)
+/* IIC bus control register */
+#define	IIC_ICCR			(IIC_DVFS_BASE + 0x0004U)
+/* IIC bus status register */
+#define	IIC_ICSR			(IIC_DVFS_BASE + 0x0008U)
+/* IIC interrupt control register */
+#define	IIC_ICIC			(IIC_DVFS_BASE + 0x000CU)
+/* IIC clock control register low */
+#define	IIC_ICCL			(IIC_DVFS_BASE + 0x0010U)
+/* IIC clock control register high */
+#define	IIC_ICCH			(IIC_DVFS_BASE + 0x0014U)
+
+/* Bit in ICSR register */
+#define ICSR_BUSY			(0x10U)
+#define ICSR_AL				(0x08U)
+#define ICSR_TACK			(0x04U)
+#define ICSR_WAIT			(0x02U)
+#define ICSR_DTE			(0x01U)
+
+/* Bit in ICIC register */
+#define ICIC_TACKE			(0x04U)
+#define ICIC_WAITE			(0x02U)
+#define ICIC_DTEE			(0x01U)
+
+/* I2C bus interface enable */
+#define ICCR_ENABLE			(0x80U)
+/* Start condition */
+#define ICCR_START			(0x94U)
+/* Stop condition */
+#define ICCR_STOP			(0x90U)
+/* Restart condition with change to receive mode change */
+#define ICCR_START_RECV			(0x81U)
+/* Stop condition for receive mode */
+#define ICCR_STOP_RECV			(0xC0U)
+
+/* Low-level period of SCL */
+#define	ICCL_FREQ_8p33M			(0x07U)	/* for CP Phy 8.3333MHz */
+#define	ICCL_FREQ_10M			(0x09U)	/* for CP Phy 10MHz */
+#define	ICCL_FREQ_12p5M			(0x0BU)	/* for CP Phy 12.5MHz */
+#define	ICCL_FREQ_16p66M		(0x0EU)	/* for CP Phy 16.6666MHz */
+/* High-level period of SCL */
+#define	ICCH_FREQ_8p33M			(0x01U)	/* for CP Phy 8.3333MHz */
+#define	ICCH_FREQ_10M			(0x02U)	/* for CP Phy 10MHz */
+#define	ICCH_FREQ_12p5M			(0x03U)	/* for CP Phy 12.5MHz */
+#define	ICCH_FREQ_16p66M		(0x05U)	/* for CP Phy 16.6666MHz */
+
+/* PMIC */
+#define	PMIC_W_SLAVE_ADDRESS		(0x60U)	/* ROHM BD9571 slave address + (W) */
+#define	PMIC_R_SLAVE_ADDRESS		(0x61U)	/* ROHM BD9571 slave address + (R) */
+#define	PMIC_DVFS_SETVID		(0x54U)	/* ROHM BD9571 DVFS SetVID register */
+#endif /* PMIC_ROHM_BD9571  */
+
+/* Individual information */
+#define EFUSE_AVS0			(0U)
+#define EFUSE_AVS_NUM			ARRAY_SIZE(init_vol_tbl)
+
+typedef struct {
+	uint32_t avs;		/* AVS code */
+	uint8_t vol;		/* Voltage */
+} initial_voltage_t;
+
+static const initial_voltage_t init_vol_tbl[] = {
+	/*      AVS code,       RHOM BD9571 DVFS SetVID register */
+	{0x00U, 0x53U},		/* AVS0, 0.83V */
+	{0x01U, 0x52U},		/* AVS1, 0.82V */
+	{0x02U, 0x51U},		/* AVS2, 0.81V */
+	{0x04U, 0x50U},		/* AVS3, 0.80V */
+	{0x08U, 0x4FU},		/* AVS4, 0.79V */
+	{0x10U, 0x4EU},		/* AVS5, 0.78V */
+	{0x20U, 0x4DU},		/* AVS6, 0.77V */
+	{0x40U, 0x4CU}		/* AVS7, 0.76V */
+};
+
+#if PMIC_ROHM_BD9571
+/* Kind of AVS settings status */
+typedef enum {
+	avs_status_none = 0,
+	avs_status_init,
+	avs_status_start_condition,
+	avs_status_set_slave_addr,
+	avs_status_write_reg_addr,
+	avs_status_write_reg_data,
+	avs_status_stop_condition,
+	avs_status_end,
+	avs_status_complete,
+	avs_status_al_start,
+	avs_status_al_transfer,
+	avs_status_nack,
+	avs_status_error_stop,
+	ave_status_error_end
+} avs_status_t;
+
+/* Kind of AVS error */
+typedef enum {
+	avs_error_none = 0,
+	avs_error_al,
+	avs_error_nack
+} avs_error_t;
+
+static avs_status_t avs_status;
+static uint32_t avs_retry;
+#endif /* PMIC_ROHM_BD9571  */
+static uint32_t efuse_avs = EFUSE_AVS0;
+
+#if PMIC_ROHM_BD9571
+/* prototype */
+static avs_error_t avs_check_error(void);
+static void avs_set_iic_clock(void);
+#if AVS_READ_PMIC_REG_ENABLE == 1
+static uint8_t avs_read_pmic_reg(uint8_t addr);
+static void avs_poll(uint8_t bit_pos, uint8_t val);
+#endif
+#endif /* PMIC_ROHM_BD9571 */
+#endif /* (AVS_SETTING_ENABLE==1) */
+
+/*
+ * Initialize to enable the AVS setting.
+ */
+void rcar_avs_init(void)
+{
+#if (AVS_SETTING_ENABLE == 1)
+	uint32_t val;
+
+#if PMIC_ROHM_BD9571
+	/* Initialize AVS status */
+	avs_status = avs_status_init;
+#endif /* PMIC_ROHM_BD9571 */
+
+	/* Enable clock supply to ADVFS. */
+	mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, CPG_SYS_ADVFS_BIT);
+
+	/* Read AVS code (Initial values are derived from eFuse) */
+	val = mmio_read_32(ADVADJP2) & ADVADJP2_VOLCOND_MASK;
+
+	for (efuse_avs = 0U; efuse_avs < EFUSE_AVS_NUM; efuse_avs++) {
+		if (val == init_vol_tbl[efuse_avs].avs)
+			break;
+	}
+
+	if (efuse_avs >= EFUSE_AVS_NUM)
+		efuse_avs = EFUSE_AVS0;	/* Not applicable */
+#if PMIC_ROHM_BD9571
+	/* Enable clock supply to DVFS. */
+	mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, CPG_SYS_DVFS_BIT);
+
+	/* Disable I2C module and All internal registers initialized. */
+	mmio_write_8(IIC_ICCR, 0x00U);
+	while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) {
+		/* Disable I2C module and All internal registers initialized. */
+		mmio_write_8(IIC_ICCR, 0x00U);
+	}
+
+	/* Set next status */
+	avs_status = avs_status_start_condition;
+
+#endif /* PMIC_ROHM_BD9571 */
+#endif /* (AVS_SETTING_ENABLE==1) */
+}
+
+/*
+ * Set the value of register corresponding to the voltage
+ * by transfer of I2C to PIMC.
+ */
+void rcar_avs_setting(void)
+{
+#if (AVS_SETTING_ENABLE == 1)
+#if PMIC_ROHM_BD9571
+	avs_error_t err;
+
+	switch (avs_status) {
+	case avs_status_start_condition:
+		/* Set ICCR.ICE=1 to activate the I2C module. */
+		mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE);
+		/* Set frequency of 400kHz */
+		avs_set_iic_clock();
+		/* Set ICIC.TACKE=1, ICIC.WAITE=1, ICIC.DTEE=1 to */
+		/* enable interrupt control.                      */
+		mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC)
+			     | ICIC_TACKE | ICIC_WAITE | ICIC_DTEE);
+		/* Write H'94 in ICCR to issue start condition */
+		mmio_write_8(IIC_ICCR, ICCR_START);
+		/* Set next status */
+		avs_status = avs_status_set_slave_addr;
+		break;
+	case avs_status_set_slave_addr:
+		/* Check error. */
+		err = avs_check_error();
+		if (err == avs_error_al) {
+			/* Recovery sequence of just after start. */
+			avs_status = avs_status_al_start;
+		} else if (err == avs_error_nack) {
+			/* Recovery sequence of detected NACK */
+			avs_status = avs_status_nack;
+		} else {
+			/* Was data transmission enabled ? */
+			if ((mmio_read_8(IIC_ICSR) & ICSR_DTE) == ICSR_DTE) {
+				/* Clear ICIC.DTEE to disable a DTE interrupt */
+				mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC)
+					     & (uint8_t) (~ICIC_DTEE));
+				/* Send PMIC slave address + (W) */
+				mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS);
+				/* Set next status */
+				avs_status = avs_status_write_reg_addr;
+			}
+		}
+		break;
+	case avs_status_write_reg_addr:
+		/* Check error. */
+		err = avs_check_error();
+		if (err == avs_error_al) {
+			/* Recovery sequence of during data transfer. */
+			avs_status = avs_status_al_transfer;
+		} else if (err == avs_error_nack) {
+			/* Recovery sequence of detected NACK */
+			avs_status = avs_status_nack;
+		} else {
+			/* If wait state after data transmission. */
+			if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
+				/* Write PMIC DVFS_SetVID address */
+				mmio_write_8(IIC_ICDR, PMIC_DVFS_SETVID);
+				/* Clear ICSR.WAIT to exit from wait state. */
+				mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
+					     & (uint8_t) (~ICSR_WAIT));
+				/* Set next status */
+				avs_status = avs_status_write_reg_data;
+			}
+		}
+		break;
+	case avs_status_write_reg_data:
+		/* Check error. */
+		err = avs_check_error();
+		if (err == avs_error_al) {
+			/* Recovery sequence of during data transfer. */
+			avs_status = avs_status_al_transfer;
+		} else if (err == avs_error_nack) {
+			/* Recovery sequence of detected NACK */
+			avs_status = avs_status_nack;
+		} else {
+			/* If wait state after data transmission. */
+			if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
+				/* Dose efuse_avs exceed the number of */
+				/* the tables? */
+				if (efuse_avs >= EFUSE_AVS_NUM) {
+					ERROR("AVS number of eFuse is out "
+					      "of a range. number=%u\n",
+					      efuse_avs);
+					/* Infinite loop */
+					panic();
+				}
+				/* Write PMIC DVFS_SetVID value */
+				mmio_write_8(IIC_ICDR,
+					     init_vol_tbl[efuse_avs].vol);
+				/* Clear ICSR.WAIT to exit from wait state. */
+				mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
+					     & (uint8_t) (~ICSR_WAIT));
+				/* Set next status */
+				avs_status = avs_status_stop_condition;
+			}
+		}
+		break;
+	case avs_status_stop_condition:
+		err = avs_check_error();
+		if (err == avs_error_al) {
+			/* Recovery sequence of during data transfer. */
+			avs_status = avs_status_al_transfer;
+		} else if (err == avs_error_nack) {
+			/* Recovery sequence of detected NACK */
+			avs_status = avs_status_nack;
+		} else {
+			/* If wait state after data transmission. */
+			if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
+				/* Write H'90 in ICCR to issue stop condition */
+				mmio_write_8(IIC_ICCR, ICCR_STOP);
+				/* Clear ICSR.WAIT to exit from wait state. */
+				mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
+					     & (uint8_t) (~ICSR_WAIT));
+				/* Set next status */
+				avs_status = avs_status_end;
+			}
+		}
+		break;
+	case avs_status_end:
+		/* Is this module not busy?. */
+		if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) {
+			/* Set ICCR=H'00 to disable the I2C module. */
+			mmio_write_8(IIC_ICCR, 0x00U);
+			/* Set next status */
+			avs_status = avs_status_complete;
+		}
+		break;
+	case avs_status_al_start:
+		/* Clear ICSR.AL bit */
+		mmio_write_8(IIC_ICSR, (mmio_read_8(IIC_ICSR)
+					& (uint8_t) (~ICSR_AL)));
+		/* Transmit a clock pulse */
+		mmio_write_8(IIC_ICDR, init_vol_tbl[EFUSE_AVS0].vol);
+		/* Set next status */
+		avs_status = avs_status_error_stop;
+		break;
+	case avs_status_al_transfer:
+		/* Clear ICSR.AL bit */
+		mmio_write_8(IIC_ICSR, (mmio_read_8(IIC_ICSR)
+					& (uint8_t) (~ICSR_AL)));
+		/* Set next status */
+		avs_status = avs_status_error_stop;
+		break;
+	case avs_status_nack:
+		/* Write H'90 in ICCR to issue stop condition */
+		mmio_write_8(IIC_ICCR, ICCR_STOP);
+		/* Disable a WAIT and DTEE interrupt. */
+		mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC)
+			     & (uint8_t) (~(ICIC_WAITE | ICIC_DTEE)));
+		/* Clear ICSR.TACK bit */
+		mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
+			     & (uint8_t) (~ICSR_TACK));
+		/* Set next status */
+		avs_status = ave_status_error_end;
+		break;
+	case avs_status_error_stop:
+		/* If wait state after data transmission. */
+		if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {
+			/* Write H'90 in ICCR to issue stop condition */
+			mmio_write_8(IIC_ICCR, ICCR_STOP);
+			/* Clear ICSR.WAIT to exit from wait state. */
+			mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)
+				     & (uint8_t) (~ICSR_WAIT));
+			/* Set next status */
+			avs_status = ave_status_error_end;
+		}
+		break;
+	case ave_status_error_end:
+		/* Is this module not busy?. */
+		if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) {
+			/* Set ICCR=H'00 to disable the I2C module. */
+			mmio_write_8(IIC_ICCR, 0x00U);
+			/* Increment the re-try number of times. */
+			avs_retry++;
+			/* Set start a re-try to status. */
+			avs_status = avs_status_start_condition;
+		}
+		break;
+	case avs_status_complete:
+		/* After "avs_status" became the "avs_status_complete", */
+		/* "avs_setting()" function may be called. */
+		break;
+	default:
+		/* This case is not possible. */
+		ERROR("AVS setting is in invalid status. status=%u\n",
+		      avs_status);
+		/* Infinite loop */
+		panic();
+		break;
+	}
+#endif /* PMIC_ROHM_BD9571 */
+#endif /* (AVS_SETTING_ENABLE==1) */
+}
+
+/*
+ * Finish the AVS setting.
+ */
+void rcar_avs_end(void)
+{
+#if (AVS_SETTING_ENABLE == 1)
+	uint32_t mstp;
+
+#if PMIC_ROHM_BD9571
+	/* While status is not completion, be repeated. */
+	while (avs_status != avs_status_complete)
+		rcar_avs_setting();
+
+	NOTICE("AVS setting succeeded. DVFS_SetVID=0x%x\n",
+	       init_vol_tbl[efuse_avs].vol);
+
+#if AVS_READ_PMIC_REG_ENABLE == 1
+	{
+		uint8_t addr = PMIC_DVFS_SETVID;
+		uint8_t value = avs_read_pmic_reg(addr);
+		NOTICE("Read PMIC register. address=0x%x value=0x%x \n",
+		       addr, value);
+	}
+#endif
+
+	/* Bit of the module which wants to disable clock supply. */
+	mstp = CPG_SYS_DVFS_BIT;
+	/* Disables the supply of clock signal to a module. */
+	cpg_write(CPG_SMSTPCR9, mmio_read_32(CPG_SMSTPCR9) | mstp);
+#endif /* PMIC_ROHM_BD9571 */
+
+	/* Bit of the module which wants to disable clock supply. */
+	mstp = CPG_SYS_ADVFS_BIT;
+	/* Disables the supply of clock signal to a module. */
+	cpg_write(CPG_SMSTPCR9, mmio_read_32(CPG_SMSTPCR9) | mstp);
+
+#endif /* (AVS_SETTING_ENABLE==1) */
+}
+
+#if (AVS_SETTING_ENABLE == 1)
+#if PMIC_ROHM_BD9571
+/*
+ * Check error and judge re-try.
+ */
+static avs_error_t avs_check_error(void)
+{
+	avs_error_t ret;
+
+	if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) {
+		NOTICE("Loss of arbitration is detected. "
+		       "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+		/* Check of retry number of times */
+		if (avs_retry >= AVS_RETRY_NUM) {
+			ERROR("AVS setting failed in retry. max=%u\n",
+			      AVS_RETRY_NUM);
+			/* Infinite loop */
+			panic();
+		}
+		/* Set the error detected to error status. */
+		ret = avs_error_al;
+	} else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) {
+		NOTICE("Non-acknowledge is detected. "
+		       "AVS status=%d Retry=%u\n", avs_status, avs_retry);
+		/* Check of retry number of times */
+		if (avs_retry >= AVS_RETRY_NUM) {
+			ERROR("AVS setting failed in retry. max=%u\n",
+			      AVS_RETRY_NUM);
+			/* Infinite loop */
+			panic();
+		}
+		/* Set the error detected to error status. */
+		ret = avs_error_nack;
+	} else {
+		/* Not error. */
+		ret = avs_error_none;
+	}
+	return ret;
+}
+
+/*
+ * Set I2C for DVFS clock.
+ */
+static void avs_set_iic_clock(void)
+{
+	uint32_t md_pin;
+
+	/* Read Mode pin register. */
+	md_pin = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
+	/* Set the module clock (CP phy) for the IIC-DVFS. */
+	/* CP phy is EXTAL / 2.                            */
+	switch (md_pin) {
+	case MD14_MD13_TYPE_0:	/* EXTAL = 16.6666MHz */
+		mmio_write_8(IIC_ICCL, ICCL_FREQ_8p33M);
+		mmio_write_8(IIC_ICCH, ICCH_FREQ_8p33M);
+		break;
+	case MD14_MD13_TYPE_1:	/* EXTAL = 20MHz */
+		mmio_write_8(IIC_ICCL, ICCL_FREQ_10M);
+		mmio_write_8(IIC_ICCH, ICCH_FREQ_10M);
+		break;
+	case MD14_MD13_TYPE_2:	/* EXTAL = 25MHz (H3/M3) */
+		mmio_write_8(IIC_ICCL, ICCL_FREQ_12p5M);
+		mmio_write_8(IIC_ICCH, ICCH_FREQ_12p5M);
+		break;
+	case MD14_MD13_TYPE_3:	/* EXTAL = 33.3333MHz */
+		mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M);
+		mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M);
+		break;
+	default:		/* This case is not possible. */
+		/* CP Phy frequency is to be set for the 16.66MHz */
+		mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M);
+		mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M);
+		break;
+	}
+}
+
+#if AVS_READ_PMIC_REG_ENABLE == 1
+/*
+ * Read the value of the register of PMIC.
+ */
+static uint8_t avs_read_pmic_reg(uint8_t addr)
+{
+	uint8_t reg;
+
+	/* Set ICCR.ICE=1 to activate the I2C module. */
+	mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE);
+
+	/* Set frequency of 400kHz */
+	avs_set_iic_clock();
+
+	/* Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission    */
+	/* interrupt and wait interrupt.                                */
+	mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE);
+
+	/* Write H'94 in ICCR to issue start condition */
+	mmio_write_8(IIC_ICCR, ICCR_START);
+
+	/* Wait for a until ICSR.DTE becomes 1. */
+	avs_poll(ICSR_DTE, 1U);
+
+	/* Clear ICIC.DTEE to disable a DTE interrupt. */
+	mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t) (~ICIC_DTEE));
+	/* Send slave address of PMIC */
+	mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS);
+
+	/* Wait for a until ICSR.WAIT becomes 1. */
+	avs_poll(ICSR_WAIT, 1U);
+
+	/* write PMIC address */
+	mmio_write_8(IIC_ICDR, addr);
+	/* Clear ICSR.WAIT to exit from WAIT status. */
+	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
+
+	/* Wait for a until ICSR.WAIT becomes 1. */
+	avs_poll(ICSR_WAIT, 1U);
+
+	/* Write H'94 in ICCR to issue restart condition */
+	mmio_write_8(IIC_ICCR, ICCR_START);
+	/* Clear ICSR.WAIT to exit from WAIT status. */
+	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
+	/* Set ICIC.DTEE=1 to enable data transmission interrupt. */
+	mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE);
+
+	/* Wait for a until ICSR.DTE becomes 1. */
+	avs_poll(ICSR_DTE, 1U);
+
+	/* Clear ICIC.DTEE to disable a DTE interrupt. */
+	mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t) (~ICIC_DTEE));
+	/* Send slave address of PMIC */
+	mmio_write_8(IIC_ICDR, PMIC_R_SLAVE_ADDRESS);
+
+	/* Wait for a until ICSR.WAIT becomes 1. */
+	avs_poll(ICSR_WAIT, 1U);
+
+	/* Write H'81 to ICCR to issue the repeated START condition     */
+	/* for changing the transmission mode to the receive mode.      */
+	mmio_write_8(IIC_ICCR, ICCR_START_RECV);
+	/* Clear ICSR.WAIT to exit from WAIT status. */
+	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
+
+	/* Wait for a until ICSR.WAIT becomes 1. */
+	avs_poll(ICSR_WAIT, 1U);
+
+	/* Set ICCR to H'C0 for the STOP condition */
+	mmio_write_8(IIC_ICCR, ICCR_STOP_RECV);
+	/* Clear ICSR.WAIT to exit from WAIT status. */
+	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));
+	/* Set ICIC.DTEE=1 to enable data transmission interrupt. */
+	mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE);
+
+	/* Wait for a until ICSR.DTE becomes 1. */
+	avs_poll(ICSR_DTE, 1U);
+
+	/* Receive DVFS SetVID register */
+	/* Clear ICIC.DTEE to disable a DTE interrupt. */
+	mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t) (~ICIC_DTEE));
+	/* Receive DVFS SetVID register */
+	reg = mmio_read_8(IIC_ICDR);
+
+	/* Wait until ICSR.BUSY is cleared. */
+	avs_poll(ICSR_BUSY, 0U);
+
+	/* Set ICCR=H'00 to disable the I2C module. */
+	mmio_write_8(IIC_ICCR, 0x00U);
+
+	return reg;
+}
+
+/*
+ * Wait processing by the polling.
+ */
+static void avs_poll(uint8_t bit_pos, uint8_t val)
+{
+	uint8_t bit_val = 0U;
+
+	if (val != 0U)
+		bit_val = bit_pos;
+
+	while (1) {
+		if ((mmio_read_8(IIC_ICSR) & bit_pos) == bit_val)
+			break;
+	}
+}
+#endif /* AVS_READ_PMIC_REG_ENABLE */
+#endif /* PMIC_ROHM_BD9571 */
+#endif /* (AVS_SETTING_ENABLE==1) */
diff --git a/drivers/renesas/rcar/avs/avs_driver.h b/drivers/renesas/rcar/avs/avs_driver.h
new file mode 100644
index 0000000..e868928
--- /dev/null
+++ b/drivers/renesas/rcar/avs/avs_driver.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights
+ * reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AVS_DRIVER_H__
+#define AVS_DRIVER_H__
+
+/* AVS Setting. 1:enable / 0:disable */
+#ifndef AVS_SETTING_ENABLE
+#define AVS_SETTING_ENABLE	1
+#endif /* AVS_SETTING_ENABLE */
+
+void rcar_avs_init(void);
+void rcar_avs_setting(void);
+void rcar_avs_end(void);
+
+#endif /* AVS_DRIVER_H__ */
diff --git a/drivers/renesas/rcar/board/board.c b/drivers/renesas/rcar/board/board.c
new file mode 100644
index 0000000..147a0b0
--- /dev/null
+++ b/drivers/renesas/rcar/board/board.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
+ * reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <iic_dvfs.h>
+#include "board.h"
+#include "utils_def.h"
+
+#ifndef BOARD_DEFAULT
+#if (RCAR_LSI == RCAR_E3)
+#define BOARD_DEFAULT		(BOARD_EBISU << BOARD_CODE_SHIFT)
+#else
+#define BOARD_DEFAULT		(BOARD_SALVATOR_X << BOARD_CODE_SHIFT)
+#endif
+#endif
+
+#define BOARD_CODE_MASK		(0xF8)
+#define BOARD_REV_MASK		(0x07)
+#define BOARD_CODE_SHIFT	(0x03)
+#define BOARD_ID_UNKNOWN	(0xFF)
+
+#define SXS_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define SX_ID	{ 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define SKP_ID	{ 0x10U, 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define SK_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define EB4_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define EB_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define KK_ID	{ 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+
+const char *g_board_tbl[] = {
+	[BOARD_STARTER_KIT_PRE] = "Starter Kit Premier",
+	[BOARD_STARTER_KIT] = "Starter Kit",
+	[BOARD_SALVATOR_XS] = "Salvator-XS",
+	[BOARD_SALVATOR_X] = "Salvator-X",
+	[BOARD_EBISU_4D] = "Ebisu-4D",
+	[BOARD_KRIEK] = "Kriek",
+	[BOARD_EBISU] = "Ebisu",
+	[BOARD_UNKNOWN] = "unknown"
+};
+
+int32_t rcar_get_board_type(uint32_t *type, uint32_t *rev)
+{
+	int32_t ret = 0;
+	const uint8_t board_tbl[][8] = {
+		[BOARD_STARTER_KIT_PRE] = SKP_ID,
+		[BOARD_SALVATOR_XS] = SXS_ID,
+		[BOARD_STARTER_KIT] = SK_ID,
+		[BOARD_SALVATOR_X] = SX_ID,
+		[BOARD_EBISU_4D] = EB4_ID,
+		[BOARD_EBISU] = EB_ID,
+		[BOARD_KRIEK] = KK_ID,
+	};
+	static uint8_t board_id = BOARD_ID_UNKNOWN;
+
+	if (board_id != BOARD_ID_UNKNOWN)
+		goto get_type;
+
+#if PMIC_ROHM_BD9571
+	/* Board ID detection from EEPROM */
+	ret = rcar_iic_dvfs_receive(EEPROM, BOARD_ID, &board_id);
+	if (ret) {
+		board_id = BOARD_ID_UNKNOWN;
+		goto get_type;
+	}
+
+	if (board_id == BOARD_ID_UNKNOWN)
+		board_id = BOARD_DEFAULT;
+#else
+	board_id = BOARD_DEFAULT;
+#endif
+
+get_type:
+	*type = ((uint32_t) board_id & BOARD_CODE_MASK) >> BOARD_CODE_SHIFT;
+
+	if (*type >= ARRAY_SIZE(board_tbl)) {
+		/* no revision information, set Rev0.0. */
+		*rev = 0;
+		return ret;
+	}
+
+	*rev = board_tbl[*type][(uint8_t) (board_id & BOARD_REV_MASK)];
+
+	return ret;
+}
diff --git a/drivers/renesas/rcar/board/board.h b/drivers/renesas/rcar/board/board.h
new file mode 100644
index 0000000..15d80b9
--- /dev/null
+++ b/drivers/renesas/rcar/board/board.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
+ * reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#define BOARD_SALVATOR_X		(0x00)
+#define BOARD_KRIEK			(0x01)
+#define BOARD_STARTER_KIT		(0x02)
+#define BOARD_SALVATOR_XS		(0x04)
+#define BOARD_EBISU			(0x08)
+#define BOARD_STARTER_KIT_PRE		(0x0B)
+#define BOARD_EBISU_4D			(0x0DU)
+#define BOARD_UNKNOWN			(BOARD_EBISU_4D + 1U)
+
+#define BOARD_REV_UNKNOWN		(0xFF)
+
+extern const char *g_board_tbl[];
+
+/************************************************************************
+ * Revisions are expressed in 8 bits.
+ *  The upper 4 bits are major version.
+ *  The lower 4 bits are minor version.
+ ************************************************************************/
+#define GET_BOARD_MAJOR(a)	((uint32_t)(a) >> 0x4)
+#define GET_BOARD_MINOR(a)	((uint32_t)(a) &  0xF)
+#define GET_BOARD_NAME(a)	(g_board_tbl[(a)])
+
+int32_t rcar_get_board_type(uint32_t *type, uint32_t *rev);
+
+#endif
diff --git a/drivers/renesas/rcar/common.c b/drivers/renesas/rcar/common.c
new file mode 100644
index 0000000..e82e8b5
--- /dev/null
+++ b/drivers/renesas/rcar/common.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include "rcar_private.h"
+
+void
+#if IMAGE_BL31
+    __attribute__ ((section(".system_ram")))
+#endif
+    cpg_write(uintptr_t regadr, uint32_t regval)
+{
+	uint32_t value = (regval);
+	mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
+	mmio_write_32(regadr, value);
+}
+
+void
+#if IMAGE_BL31
+    __attribute__ ((section(".system_ram")))
+#endif
+    mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
+{
+	uint32_t reg;
+	reg = mmio_read_32(mstpcr);
+	reg &= ~target_bit;
+	cpg_write(mstpcr, reg);
+	while ((mmio_read_32(mstpsr) & target_bit) != 0U) {
+	}
+}
diff --git a/drivers/renesas/rcar/console/rcar_console.S b/drivers/renesas/rcar/console/rcar_console.S
new file mode 100644
index 0000000..e3c7363
--- /dev/null
+++ b/drivers/renesas/rcar/console/rcar_console.S
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+	.globl	console_init
+	.globl	console_putc
+	.globl	console_uninit
+	.globl	console_core_init
+	.globl	console_core_putc
+	.globl	console_core_getc
+	.globl	console_flush
+
+	.extern	rcar_log_init
+	.extern	rcar_set_log_data
+
+	/* -----------------------------------------------
+	 * int console_core_init(unsigned long base_addr,
+	 * unsigned int uart_clk, unsigned int baud_rate)
+	 * Function to initialize the log area. This
+	 * function will be accessed by console_init and
+	 * crash reporting.
+	 * Return 1 on SUCCESS, 0 on error
+	 * In: x0 - Not used
+	 *     w1 - Not used
+	 *     w2 - Not used
+	 * -----------------------------------------------
+	 */
+func console_core_init
+	b	rcar_log_init
+endfunc console_core_init
+func  console_init
+	b	console_core_init
+endfunc console_init
+
+	/* --------------------------------------------------------
+	 * int console_core_putc(int c, unsigned long base_addr)
+	 * Function to output a character over the log area.
+	 * Return 1 on SUCCESS, 0 on error
+	 * In : w0 - Not used
+	 *      x1 - Not used
+	 * --------------------------------------------------------
+	 */
+func console_core_putc
+	b	rcar_set_log_data
+endfunc console_core_putc
+func console_putc
+	b	console_core_putc
+endfunc console_putc
+
+	/* ---------------------------------------------
+	 * int console_core_getc(unsigned long base_addr)
+	 * Function to get a character from the console.
+	 * It returns the character grabbed on success
+	 * or -1 on error.
+	 * In : x0 - console base address
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_core_getc
+	ret
+endfunc console_core_getc
+
+	/* -----------------------------------------------
+	 * void console_uninit(void)
+	 * Function to finish the use of console driver.
+	 * -----------------------------------------------
+	 */
+func console_uninit
+	ret
+endfunc console_uninit
+
+	/* ---------------------------------------------
+	 * int console_flush(void)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output. It returns 0
+	 * upon successful completion, otherwise it
+	 * returns -1.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_flush
+	mov	w0, #0
+	ret
+endfunc console_flush
diff --git a/drivers/renesas/rcar/console/rcar_printf.c b/drivers/renesas/rcar/console/rcar_printf.c
new file mode 100644
index 0000000..9321b58
--- /dev/null
+++ b/drivers/renesas/rcar/console/rcar_printf.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <stdarg.h>
+#include <stdint.h>
+
+#include	<arch_helpers.h>
+#include	<platform_def.h>
+#include	<bakery_lock.h>
+#include	"rcar_def.h"
+#include	"rcar_private.h"
+#include	"rcar_printf.h"
+
+#define INDEX_TIMER_COUNT	(4U)
+
+extern RCAR_INSTANTIATE_LOCK typedef struct log_head {
+	uint8_t head[4];
+	uint32_t index;
+	uint32_t size;
+	uint8_t res[4];
+} loghead_t;
+
+typedef struct log_map {
+	loghead_t header;
+	uint8_t log_data[RCAR_BL31_LOG_MAX];
+	uint8_t res_data[RCAR_LOG_RES_SIZE];
+} logmap_t;
+
+int32_t rcar_set_log_data(int32_t c)
+{
+	logmap_t *t_log;
+
+	t_log = (logmap_t *) RCAR_BL31_LOG_BASE;
+
+	rcar_lock_get();
+
+	/*
+	 * If index is broken, then index and size initialize
+	 */
+	if (t_log->header.index >= (uint32_t) RCAR_BL31_LOG_MAX) {
+		t_log->header.index = 0U;
+		t_log->header.size = 0U;
+	}
+	/*
+	 * data store to log area then index and size renewal
+	 */
+	t_log->log_data[t_log->header.index] = (uint8_t) c;
+	t_log->header.index++;
+	if (t_log->header.size < t_log->header.index) {
+		t_log->header.size = t_log->header.index;
+	}
+	if (t_log->header.index >= (uint32_t) RCAR_BL31_LOG_MAX) {
+		t_log->header.index = 0U;
+	}
+
+	rcar_lock_release();
+
+	return 1;
+}
+
+int32_t rcar_log_init(void)
+{
+
+	static const uint8_t const_header[] = "TLOG";
+	logmap_t *t_log;
+	int16_t init_flag = 0;
+
+	t_log = (logmap_t *) RCAR_BL31_LOG_BASE;
+	if (memcmp
+	    ((const void *)t_log->header.head, (const void *)const_header,
+	     sizeof(t_log->header.head)) != 0) {
+		/*
+		 * Log header is not "TLOG", then log area initialize
+		 */
+		init_flag = 1;
+	}
+	if (t_log->header.index >= (uint32_t) RCAR_BL31_LOG_MAX) {
+		/*
+		 * index is broken, then log area initialize
+		 */
+		init_flag = 1;
+	}
+	if (init_flag == 1) {
+		(void)memset((void *)t_log->log_data, 0,
+			     (size_t) RCAR_BL31_LOG_MAX);
+		(void)memcpy((void *)t_log->header.head,
+			     (const void *)const_header,
+			     sizeof(t_log->header.head));
+		t_log->header.index = 0U;
+		t_log->header.size = 0U;
+#ifndef IMAGE_BL2
+		rcar_stack_generic_timer[INDEX_TIMER_COUNT] = 0U;
+#endif
+	}
+	rcar_lock_init();
+
+	return 1;
+}
diff --git a/drivers/renesas/rcar/console/rcar_printf.h b/drivers/renesas/rcar/console/rcar_printf.h
new file mode 100644
index 0000000..dd7a61b
--- /dev/null
+++ b/drivers/renesas/rcar/console/rcar_printf.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	RCAR_PRINTF_H__
+#define	RCAR_PRINTF_H__
+
+#include <string.h>
+
+int32_t rcar_set_log_data(int32_t c);
+int32_t rcar_log_init(void);
+
+#if IMAGE_BL31
+extern uint64_t rcar_stack_generic_timer[5];
+#endif
+
+#endif
diff --git a/drivers/renesas/rcar/cpld/ulcb_cpld.c b/drivers/renesas/rcar/cpld/ulcb_cpld.c
new file mode 100644
index 0000000..92e438a
--- /dev/null
+++ b/drivers/renesas/rcar/cpld/ulcb_cpld.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+
+#define SCLK			8	/* GP_6_8 */
+#define SSTBZ			3	/* GP_2_3 */
+#define MOSI			7	/* GP_6_7 */
+
+#define CPLD_ADDR_RESET		0x80	/* RW */
+
+/* LSI Multiplexed Pin Setting Mask Register */
+#define PFC_PMMR		0xE6060000
+
+/* General output registers */
+#define GPIO_OUTDT2		0xE6052008
+#define GPIO_OUTDT6		0xE6055408
+
+/* General input/output switching registers */
+#define GPIO_INOUTSEL2		0xE6052004
+#define GPIO_INOUTSEL6		0xE6055404
+
+/* GPIO/perihperal function select */
+#define PFC_GPSR2		0xE6060108
+#define PFC_GPSR6		0xE6060118
+
+static void gpio_set_value(uint32_t addr, uint8_t gpio, uint32_t val)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(addr);
+	if (val)
+		reg |= (1 << gpio);
+	else
+		reg &= ~(1 << gpio);
+	mmio_write_32(addr, reg);
+}
+
+static void gpio_direction_output(uint32_t addr, uint8_t gpio)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(addr);
+	reg |= (1 << gpio);
+	mmio_write_32(addr, reg);
+}
+
+static void gpio_pfc(uint32_t addr, uint8_t gpio)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(addr);
+	reg &= ~(1 << gpio);
+	mmio_write_32(PFC_PMMR, ~reg);
+	mmio_write_32(addr, reg);
+}
+
+static void cpld_write(uint8_t addr, uint32_t data)
+{
+	int i;
+
+	for (i = 0; i < 32; i++) {
+		/* MSB first */
+		gpio_set_value(GPIO_OUTDT6, MOSI, data & (1 << 31));
+		gpio_set_value(GPIO_OUTDT6, SCLK, 1);
+		data <<= 1;
+		gpio_set_value(GPIO_OUTDT6, SCLK, 0);
+	}
+
+	for (i = 0; i < 8; i++) {
+		/* MSB first */
+		gpio_set_value(GPIO_OUTDT6, MOSI, addr & 0x80);
+		gpio_set_value(GPIO_OUTDT6, SCLK, 1);
+		addr <<= 1;
+		gpio_set_value(GPIO_OUTDT6, SCLK, 0);
+	}
+
+	/* WRITE */
+	gpio_set_value(GPIO_OUTDT6, MOSI, 1);
+	gpio_set_value(GPIO_OUTDT2, SSTBZ, 0);
+	gpio_set_value(GPIO_OUTDT6, SCLK, 1);
+	gpio_set_value(GPIO_OUTDT6, SCLK, 0);
+	gpio_set_value(GPIO_OUTDT2, SSTBZ, 1);
+}
+
+static void cpld_init(void)
+{
+	gpio_pfc(PFC_GPSR6, SCLK);
+	gpio_pfc(PFC_GPSR2, SSTBZ);
+	gpio_pfc(PFC_GPSR6, MOSI);
+
+	gpio_set_value(GPIO_OUTDT6, SCLK, 0);
+	gpio_set_value(GPIO_OUTDT2, SSTBZ, 1);
+	gpio_set_value(GPIO_OUTDT6, MOSI, 0);
+
+	gpio_direction_output(GPIO_INOUTSEL6, SCLK);
+	gpio_direction_output(GPIO_INOUTSEL2, SSTBZ);
+	gpio_direction_output(GPIO_INOUTSEL6, MOSI);
+}
+
+void rcar_cpld_reset_cpu(void)
+{
+	cpld_init();
+
+	cpld_write(CPLD_ADDR_RESET, 1);
+}
diff --git a/drivers/renesas/rcar/delay/micro_delay.S b/drivers/renesas/rcar/delay/micro_delay.S
new file mode 100644
index 0000000..978973c
--- /dev/null
+++ b/drivers/renesas/rcar/delay/micro_delay.S
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include "micro_delay.h"
+
+#define CPG_BASE		(0xE6150000)
+#define CPG_SMSTPCR1		(0x0134)
+#define CPG_CPGWPR		(0x0900)
+
+/* Module bit for TMU ch3-5 */
+#define MSTPCR1_TMU1		(1 << 24)
+
+#define TMU3_BASE		(0xE6FC0000)
+#define TMU_TSTR		(0x0004)
+#define TMU_TCOR		(0x0008)
+#define TMU_TCNT		(0x000C)
+#define TMU_TCR		(0x0010)
+/* Start bit for TMU ch3 */
+#define TSTR1_TMU3		(1 << 0)
+
+#define MIDR_CA57		(0x0D07 << MIDR_PN_SHIFT)
+#define MIDR_CA53		(0x0D03 << MIDR_PN_SHIFT)
+
+	.globl	rcar_micro_delay
+#if (TMU3_MEASUREMENT == 1)
+	.globl	tmu3_init
+	.globl	tmu3_start
+	.globl	tmu3_stop
+	.globl	tcnt3_snapshot
+#endif
+	/* Aligned with the cache line */
+	.align	6
+
+func rcar_micro_delay
+	cbz	x0, micro_delay_e
+	mrs	x1, midr_el1
+	and	x1, x1, #MIDR_PN_MASK << MIDR_PN_SHIFT
+	mov	w2, #MIDR_CA53
+	cmp	w1, w2
+	b.eq	micro_delay_ca53
+	b	micro_delay_ca57
+micro_delay_e:
+	ret
+endfunc rcar_micro_delay
+
+func micro_delay_ca57
+ca57_loop_1:
+	mov	x1, #185
+ca57_loop_2:
+	subs	x1, x1, #1
+	b.ne	ca57_loop_2
+	subs	x0, x0, #1
+	b.ne	ca57_loop_1
+	ret
+endfunc micro_delay_ca57
+
+func micro_delay_ca53
+ca53_loop_1:
+	mov	x1, #134
+ca53_loop_2:
+	subs	x1, x1, #1
+	b.ne	ca53_loop_2
+	subs	x0, x0, #1
+	b.ne	ca53_loop_1
+	ret
+endfunc micro_delay_ca53
+
+#if (TMU3_MEASUREMENT == 1)
+func tmu3_init
+	ldr	x2, =CPG_BASE
+	ldr	w0, [x2, #CPG_SMSTPCR1]
+	ldr	w1, [x2, #CPG_MSTPSR1]
+	ldr	w2, #MSTPCR1_TMU1
+	bl	mstpcr_write
+	ret
+endfunc tmu3_init
+
+func tmu3_start
+	ldr	x0, =TMU3_BASE
+	mov	w1, #0xFFFFFFFF
+	str	w1, [x0, TMU_TCNT]
+
+	ldr	x0, =TMU3_BASE
+	ldrb	w1, [x0, TMU_TSTR]
+	orr	w1, w1, #TSTR1_TMU3
+	strb	w1, [x0, TMU_TSTR]
+	ret
+endfunc tmu3_start
+
+func tcnt3_snapshot
+	ldr	x0, =TMU3_BASE
+	ldr	w0, [x0, TMU_TCNT]
+	ret
+endfunc tcnt3_snapshot
+
+
+func tmu3_stop
+	ldr	x0, =TMU3_BASE
+	ldrb	w1, [x0, TMU_TSTR]
+	and	w1, w1, #~TSTR1_TMU3
+	strb	w1, [x0, TMU_TSTR]
+	ret
+endfunc tmu3_stop
+#endif
diff --git a/drivers/renesas/rcar/delay/micro_delay.h b/drivers/renesas/rcar/delay/micro_delay.h
new file mode 100644
index 0000000..f598394
--- /dev/null
+++ b/drivers/renesas/rcar/delay/micro_delay.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MICRO_DELAY_H__
+#define MICRO_DELAY_H__
+
+#define TMU3_MEASUREMENT	(0)
+
+#ifndef __ASSEMBLY__
+#include "stdint.h"
+void rcar_micro_delay(uint32_t count_us);
+
+#if (TMU3_MEASUREMENT == 1)
+void tmu3_start(void);
+void tmu3_init(void);
+void tmu3_stop(void);
+
+uint32_t tcnt3_snapshot(void);
+#endif
+
+#endif
+
+#endif
diff --git a/drivers/renesas/rcar/dma/dma_driver.c b/drivers/renesas/rcar/dma/dma_driver.c
new file mode 100644
index 0000000..d4fa65d
--- /dev/null
+++ b/drivers/renesas/rcar/dma/dma_driver.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <arch_helpers.h>
+#include <string.h>
+#include <mmio.h>
+#include "rcar_def.h"
+#include "cpg_registers.h"
+#include "debug.h"
+#include "rcar_private.h"
+
+/* DMA CHANNEL setting (0/16/32) */
+#define	DMA_CH		0
+
+#if (DMA_CH == 0)
+#define SYS_DMAC_BIT	((uint32_t)1U << 19U)
+#define DMA_BASE	(0xE6700000U)
+#elif (DMA_CH == 16)
+#define SYS_DMAC_BIT	((uint32_t)1U << 18U)
+#define DMA_BASE	(0xE7300000U)
+#elif (DMA_CH == 32)
+#define SYS_DMAC_BIT	((uint32_t)1U << 17U)
+#define DMA_BASE	(0xE7320000U)
+#else
+#define SYS_DMAC_BIT	((uint32_t)1U << 19U)
+#define DMA_BASE	(0xE6700000U)
+#endif
+
+/* DMA operation */
+#define DMA_DMAOR	(DMA_BASE + 0x0060U)
+/* DMA secure control */
+#define	DMA_DMASEC	(DMA_BASE + 0x0030U)
+/* DMA channel clear */
+#define DMA_DMACHCLR	(DMA_BASE + 0x0080U)
+/* DMA source address */
+#define DMA_DMASAR	(DMA_BASE + 0x8000U)
+/* DMA destination address */
+#define DMA_DMADAR	(DMA_BASE + 0x8004U)
+/* DMA transfer count */
+#define DMA_DMATCR	(DMA_BASE + 0x8008U)
+/* DMA channel control */
+#define DMA_DMACHCR	(DMA_BASE + 0x800CU)
+/* DMA fixed destination address */
+#define DMA_DMAFIXDAR	(DMA_BASE + 0x8014U)
+
+#define	DMA_USE_CHANNEL		(0x00000001U)
+#define	DMAOR_INITIAL		(0x0301U)
+#define	DMACHCLR_CH_ALL		(0x0000FFFFU)
+#define	DMAFIXDAR_32BIT_SHIFT	(32U)
+#define	DMAFIXDAR_DAR_MASK	(0x000000FFU)
+#define	DMADAR_BOUNDARY_ADDR	(0x100000000ULL)
+#define	DMATCR_CNT_SHIFT	(6U)
+#define	DMATCR_MAX		(0x00FFFFFFU)
+#define	DMACHCR_TRN_MODE	(0x00105409U)
+#define	DMACHCR_DE_BIT		(0x00000001U)
+#define	DMACHCR_TE_BIT		(0x00000002U)
+#define	DMACHCR_CHE_BIT		(0x80000000U)
+
+#define	DMA_SIZE_UNIT		FLASH_TRANS_SIZE_UNIT
+#define	DMA_FRACTION_MASK	(0xFFU)
+#define DMA_DST_LIMIT		(0x10000000000ULL)
+
+/* transfer length limit */
+#define DMA_LENGTH_LIMIT	((DMATCR_MAX * (1U << DMATCR_CNT_SHIFT)) \
+				& ~DMA_FRACTION_MASK)
+
+static void dma_enable(void)
+{
+	mstpcr_write(CPG_SMSTPCR2, CPG_MSTPSR2, SYS_DMAC_BIT);
+}
+
+static void dma_setup(void)
+{
+	mmio_write_16(DMA_DMAOR, 0);
+	mmio_write_32(DMA_DMACHCLR, DMACHCLR_CH_ALL);
+}
+
+static void dma_start(uintptr_t dst, uint32_t src, uint32_t len)
+{
+	mmio_write_16(DMA_DMAOR, DMAOR_INITIAL);
+	mmio_write_32(DMA_DMAFIXDAR, (dst >> DMAFIXDAR_32BIT_SHIFT) &
+		      DMAFIXDAR_DAR_MASK);
+	mmio_write_32(DMA_DMADAR, dst & UINT32_MAX);
+	mmio_write_32(DMA_DMASAR, src);
+	mmio_write_32(DMA_DMATCR, len >> DMATCR_CNT_SHIFT);
+	mmio_write_32(DMA_DMASEC, DMA_USE_CHANNEL);
+	mmio_write_32(DMA_DMACHCR, DMACHCR_TRN_MODE);
+}
+
+static void dma_end(void)
+{
+	while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_TE_BIT) == 0) {
+		if ((mmio_read_32(DMA_DMACHCR) & DMACHCR_CHE_BIT) != 0U) {
+			ERROR("BL2: DMA - Channel Address Error\n");
+			panic();
+			break;
+		}
+	}
+	/* DMA transfer Disable */
+	mmio_clrbits_32(DMA_DMACHCR, DMACHCR_DE_BIT);
+	while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_DE_BIT) != 0)
+		;
+
+	mmio_write_32(DMA_DMASEC, 0);
+	mmio_write_16(DMA_DMAOR, 0);
+	mmio_write_32(DMA_DMACHCLR, DMA_USE_CHANNEL);
+}
+
+void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len)
+{
+	uint32_t dma_len = len;
+
+	if (len & DMA_FRACTION_MASK)
+		dma_len = (len + DMA_SIZE_UNIT) & ~DMA_FRACTION_MASK;
+
+	if (!dma_len || dma_len > DMA_LENGTH_LIMIT) {
+		ERROR("BL2: DMA - size invalid, length (0x%x)\n", dma_len);
+		panic();
+	}
+
+	if (src & DMA_FRACTION_MASK) {
+		ERROR("BL2: DMA - source address invalid (0x%x), "
+			"length (0x%x)\n", src, dma_len);
+		panic();
+	}
+
+	if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR	||
+	    (dst + dma_len > DMA_DST_LIMIT)			||
+	    (dst & DMA_FRACTION_MASK)) {
+		ERROR("BL2: DMA - destination address invalid (0x%lx), "
+		      "length (0x%x)\n", dst, dma_len);
+		panic();
+	}
+
+	dma_start(dst, src, dma_len);
+	dma_end();
+}
+
+void rcar_dma_init(void)
+{
+	dma_enable();
+	dma_setup();
+}
diff --git a/drivers/renesas/rcar/emmc/emmc_cmd.c b/drivers/renesas/rcar/emmc/emmc_cmd.c
new file mode 100644
index 0000000..0f39349
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_cmd.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+#include "micro_delay.h"
+
+static void emmc_little_to_big(uint8_t *p, uint32_t value)
+{
+	if (p == NULL)
+		return;
+
+	p[0] = (uint8_t) (value >> 24);
+	p[1] = (uint8_t) (value >> 16);
+	p[2] = (uint8_t) (value >> 8);
+	p[3] = (uint8_t) value;
+}
+
+static void emmc_softreset(void)
+{
+	int32_t loop = 10000;
+	int32_t retry = 1000;
+
+	/* flag clear */
+	mmc_drv_obj.during_cmd_processing = FALSE;
+	mmc_drv_obj.during_transfer = FALSE;
+	mmc_drv_obj.during_dma_transfer = FALSE;
+	mmc_drv_obj.state_machine_blocking = FALSE;
+	mmc_drv_obj.force_terminate = FALSE;
+	mmc_drv_obj.dma_error_flag = FALSE;
+
+	/* during operation ? */
+	if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0)
+		goto reset;
+
+	/* wait CMDSEQ = 0 */
+	while (loop > 0) {
+		if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0)
+			break;	/* ready */
+
+		loop--;
+		if ((loop == 0) && (retry > 0)) {
+			rcar_micro_delay(1000U);	/* wait 1ms */
+			loop = 10000;
+			retry--;
+		}
+	}
+
+reset:
+	/* reset */
+	SETR_32(SOFT_RST, (GETR_32(SOFT_RST) & (~SOFT_RST_SDRST)));
+	SETR_32(SOFT_RST, (GETR_32(SOFT_RST) | SOFT_RST_SDRST));
+
+	/* initialize */
+	SETR_32(SD_INFO1, 0x00000000U);
+	SETR_32(SD_INFO2, SD_INFO2_CLEAR);
+	SETR_32(SD_INFO1_MASK, 0x00000000U);	/* all interrupt disable */
+	SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);	/* all interrupt disable */
+
+}
+
+static void emmc_read_response(uint32_t *response)
+{
+	uint8_t *p;
+
+	if (response == NULL)
+		return;
+
+	/* read response */
+	if (mmc_drv_obj.response_length != EMMC_MAX_RESPONSE_LENGTH) {
+		*response = GETR_32(SD_RSP10);	/* [39:8] */
+		return;
+	}
+
+	/* CSD or CID */
+	p = (uint8_t *) (response);
+	emmc_little_to_big(p, ((GETR_32(SD_RSP76) << 8)
+			| (GETR_32(SD_RSP54) >> 24)));	/* [127:96]     */
+	emmc_little_to_big(p + 4, ((GETR_32(SD_RSP54) << 8)
+			| (GETR_32(SD_RSP32) >> 24)));	/* [95:64]      */
+	emmc_little_to_big(p + 8, ((GETR_32(SD_RSP32) << 8)
+			| (GETR_32(SD_RSP10) >> 24)));	/* [63:32]      */
+	emmc_little_to_big(p + 12, (GETR_32(SD_RSP10) << 8));
+}
+
+static EMMC_ERROR_CODE emmc_response_check(uint32_t *response,
+					   uint32_t error_mask)
+{
+
+	HAL_MEMCARD_RESPONSE_TYPE response_type =
+	    (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
+					 cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+
+	if (response == NULL)
+		return EMMC_ERR_PARAM;
+
+	if (response_type == HAL_MEMCARD_RESPONSE_NONE)
+		return EMMC_SUCCESS;
+
+
+	if (response_type <= HAL_MEMCARD_RESPONSE_R1b) {
+		/* R1 or R1b */
+		mmc_drv_obj.current_state =
+		    (EMMC_R1_STATE) ((*response & EMMC_R1_STATE_MASK) >>
+				     EMMC_R1_STATE_SHIFT);
+		if ((*response & error_mask) != 0) {
+			if ((0x80 & *response) != 0) {
+				ERROR("BL2: emmc SWITCH_ERROR\n");
+			}
+			return EMMC_ERR_CARD_STATUS_BIT;
+		}
+		return EMMC_SUCCESS;;
+	}
+
+	if (response_type == HAL_MEMCARD_RESPONSE_R4) {
+		if ((*response & EMMC_R4_STATUS) != 0)
+			return EMMC_ERR_CARD_STATUS_BIT;
+	}
+
+	return EMMC_SUCCESS;
+}
+
+static void emmc_WaitCmd2Cmd_8Cycle(void)
+{
+	uint32_t dataL, wait = 0;
+
+	dataL = GETR_32(SD_CLK_CTRL);
+	dataL &= 0x000000FF;
+
+	switch (dataL) {
+	case 0xFF:
+	case 0x00:
+	case 0x01:
+	case 0x02:
+	case 0x04:
+	case 0x08:
+	case 0x10:
+	case 0x20:
+		wait = 10U;
+		break;
+	case 0x40:
+		wait = 20U;
+		break;
+	case 0x80:
+		wait = 30U;
+		break;
+	}
+
+	rcar_micro_delay(wait);
+}
+
+static void cmdErrSdInfo2Log(void)
+{
+	ERROR("BL2: emmc ERR SD_INFO2 = 0x%x\n", mmc_drv_obj.error_info.info2);
+}
+
+static void emmc_data_transfer_dma(void)
+{
+	mmc_drv_obj.during_dma_transfer = TRUE;
+	mmc_drv_obj.dma_error_flag = FALSE;
+
+	SETR_32(SD_INFO1_MASK, 0x00000000U);
+	SETR_32(SD_INFO2_MASK, (SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
+
+	/* DMAC setting */
+	if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) {
+		/* transfer complete interrupt enable */
+		SETR_32(DM_CM_INFO1_MASK,
+			(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE));
+		SETR_32(DM_CM_INFO2_MASK,
+			(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE));
+		/* BUFF --> FIFO */
+		SETR_32(DM_CM_DTRAN_MODE, (DM_CM_DTRAN_MODE_CH0 |
+					   DM_CM_DTRAN_MODE_BIT_WIDTH));
+	} else {
+		/* transfer complete interrupt enable */
+		SETR_32(DM_CM_INFO1_MASK,
+			(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE));
+		SETR_32(DM_CM_INFO2_MASK,
+			(DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE));
+		/* FIFO --> BUFF */
+		SETR_32(DM_CM_DTRAN_MODE, (DM_CM_DTRAN_MODE_CH1
+					   | DM_CM_DTRAN_MODE_BIT_WIDTH));
+	}
+	SETR_32(DM_DTRAN_ADDR, (((uintptr_t) mmc_drv_obj.buff_address_virtual &
+				 DM_DTRAN_ADDR_WRITE_MASK)));
+
+	SETR_32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START);
+}
+
+EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response)
+{
+	EMMC_ERROR_CODE rtn_code = EMMC_SUCCESS;
+	HAL_MEMCARD_RESPONSE_TYPE response_type;
+	HAL_MEMCARD_COMMAND_TYPE cmd_type;
+	EMMC_INT_STATE state;
+	uint32_t err_not_care_flag = FALSE;
+
+	/* parameter check */
+	if (response == NULL) {
+		emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_PARAM);
+		return EMMC_ERR_PARAM;
+	}
+
+	/* state check */
+	if (mmc_drv_obj.clock_enable != TRUE) {
+		emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	if (mmc_drv_obj.state_machine_blocking == TRUE) {
+		emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR);
+		return EMMC_ERR;
+	}
+
+	state = ESTATE_BEGIN;
+	response_type =
+	    (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
+					 cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+	cmd_type =
+	    (HAL_MEMCARD_COMMAND_TYPE) (mmc_drv_obj.cmd_info.
+					cmd & HAL_MEMCARD_COMMAND_TYPE_MASK);
+
+	/* state machine */
+	while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) {
+		/* The interrupt factor flag is observed. */
+		emmc_interrupt();
+
+		/* wait interrupt */
+		if (mmc_drv_obj.state_machine_blocking == TRUE)
+			continue;
+
+		switch (state) {
+		case ESTATE_BEGIN:
+			/* Busy check */
+			if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0) {
+				emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD,
+						      EMMC_ERR_CARD_BUSY);
+				return EMMC_ERR_CARD_BUSY;
+			}
+
+			/* clear register */
+			SETR_32(SD_INFO1, 0x00000000U);
+			SETR_32(SD_INFO2, SD_INFO2_CLEAR);
+			SETR_32(SD_INFO1_MASK, SD_INFO1_INFO0);
+			SETR_32(SD_INFO2_MASK,
+				(SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
+
+			state = ESTATE_ISSUE_CMD;
+			/* through */
+
+		case ESTATE_ISSUE_CMD:
+			/* ARG */
+			SETR_32(SD_ARG, mmc_drv_obj.cmd_info.arg);
+			/* issue cmd */
+			SETR_32(SD_CMD, mmc_drv_obj.cmd_info.hw);
+			/* Set driver flag */
+			mmc_drv_obj.during_cmd_processing = TRUE;
+			mmc_drv_obj.state_machine_blocking = TRUE;
+
+			if (response_type == HAL_MEMCARD_RESPONSE_NONE) {
+				state = ESTATE_NON_RESP_CMD;
+			} else {
+				state = ESTATE_RCV_RESP;
+			}
+
+			break;
+
+		case ESTATE_NON_RESP_CMD:
+			/* interrupt disable */
+			SETR_32(SD_INFO1_MASK, 0x00000000U);
+			SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
+
+			/* check interrupt */
+			if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
+				/* error interrupt */
+				cmdErrSdInfo2Log();
+				rtn_code = EMMC_ERR_INFO2;
+				state = ESTATE_ERROR;
+			} else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) ==
+				   0) {
+				/* not receive expected interrupt */
+				rtn_code = EMMC_ERR_RESPONSE;
+				state = ESTATE_ERROR;
+			} else {
+				emmc_WaitCmd2Cmd_8Cycle();
+				state = ESTATE_END;
+			}
+			break;
+
+		case ESTATE_RCV_RESP:
+			/* interrupt disable */
+			SETR_32(SD_INFO1_MASK, 0x00000000U);
+			SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
+
+			/* check interrupt */
+			if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
+				if ((mmc_drv_obj.get_partition_access_flag ==
+				     TRUE)
+				    && ((mmc_drv_obj.int_event2 & SD_INFO2_ERR6)
+					!= 0U)) {
+					err_not_care_flag = TRUE;
+					rtn_code = EMMC_ERR_CMD_TIMEOUT;
+				} else {
+					/* error interrupt */
+					cmdErrSdInfo2Log();
+					rtn_code = EMMC_ERR_INFO2;
+				}
+				state = ESTATE_ERROR;
+				break;
+			} else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) ==
+				   0) {
+				/* not receive expected interrupt */
+				rtn_code = EMMC_ERR_RESPONSE;
+				state = ESTATE_ERROR;
+				break;
+			}
+
+			/* read response */
+			emmc_read_response(response);
+
+			/* check response */
+			rtn_code = emmc_response_check(response, error_mask);
+			if (rtn_code != EMMC_SUCCESS) {
+				state = ESTATE_ERROR;
+				break;
+			}
+
+			if (response_type == HAL_MEMCARD_RESPONSE_R1b) {
+				/* R1b */
+				SETR_32(SD_INFO2_MASK,
+					(SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
+				state = ESTATE_RCV_RESPONSE_BUSY;
+			} else {
+				state = ESTATE_CHECK_RESPONSE_COMPLETE;
+			}
+			break;
+
+		case ESTATE_RCV_RESPONSE_BUSY:
+			/* check interrupt */
+			if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
+				/* error interrupt */
+				cmdErrSdInfo2Log();
+				rtn_code = EMMC_ERR_INFO2;
+				state = ESTATE_ERROR;
+				break;
+			}
+			/* DAT0 not Busy */
+			if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0) {
+				state = ESTATE_CHECK_RESPONSE_COMPLETE;
+				break;
+			}
+			break;
+
+		case ESTATE_CHECK_RESPONSE_COMPLETE:
+			if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) {
+				state = ESTATE_DATA_TRANSFER;
+			} else {
+				emmc_WaitCmd2Cmd_8Cycle();
+				state = ESTATE_END;
+			}
+			break;
+
+		case ESTATE_DATA_TRANSFER:
+			/* ADTC command  */
+			mmc_drv_obj.during_transfer = TRUE;
+			mmc_drv_obj.state_machine_blocking = TRUE;
+
+			if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
+				/* DMA */
+				emmc_data_transfer_dma();
+			} else {
+				/* PIO */
+				/* interrupt enable (FIFO read/write enable) */
+				if (mmc_drv_obj.cmd_info.dir ==
+				    HAL_MEMCARD_WRITE) {
+					SETR_32(SD_INFO2_MASK,
+						(SD_INFO2_BWE | SD_INFO2_ALL_ERR
+						 | SD_INFO2_CLEAR));
+				} else {
+					SETR_32(SD_INFO2_MASK,
+						(SD_INFO2_BRE | SD_INFO2_ALL_ERR
+						 | SD_INFO2_CLEAR));
+				}
+			}
+			state = ESTATE_DATA_TRANSFER_COMPLETE;
+			break;
+
+		case ESTATE_DATA_TRANSFER_COMPLETE:
+			/* check interrupt */
+			if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) {
+				/* error interrupt */
+				cmdErrSdInfo2Log();
+				rtn_code = EMMC_ERR_INFO2;
+				state = ESTATE_TRANSFER_ERROR;
+				break;
+			}
+
+			/* DMAC error ? */
+			if (mmc_drv_obj.dma_error_flag == TRUE) {
+				/* Error occurred in DMAC driver. */
+				rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER;
+				state = ESTATE_TRANSFER_ERROR;
+			} else if (mmc_drv_obj.during_dma_transfer == TRUE) {
+				/* DMAC not finished. unknown error */
+				rtn_code = EMMC_ERR;
+				state = ESTATE_TRANSFER_ERROR;
+			} else {
+				SETR_32(SD_INFO1_MASK, SD_INFO1_INFO2);
+				SETR_32(SD_INFO2_MASK,
+					(SD_INFO2_ALL_ERR | SD_INFO2_CLEAR));
+
+				mmc_drv_obj.state_machine_blocking = TRUE;
+
+				state = ESTATE_ACCESS_END;
+			}
+			break;
+
+		case ESTATE_ACCESS_END:
+
+			/* clear flag */
+			if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
+				SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);	/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+				SETR_32(SD_STOP, 0x00000000U);
+				mmc_drv_obj.during_dma_transfer = FALSE;
+			}
+
+			SETR_32(SD_INFO1_MASK, 0x00000000U);
+			SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
+			SETR_32(SD_INFO1, 0x00000000U);
+			SETR_32(SD_INFO2, SD_INFO2_CLEAR);
+
+			if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0) {
+				emmc_WaitCmd2Cmd_8Cycle();
+				state = ESTATE_END;
+			} else {
+				state = ESTATE_ERROR;
+			}
+			break;
+
+		case ESTATE_TRANSFER_ERROR:
+			/* The error occurred in the Data transfer.  */
+			if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
+				SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);	/* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+				SETR_32(SD_STOP, 0x00000000U);
+				mmc_drv_obj.during_dma_transfer = FALSE;
+			}
+			/* through */
+
+		case ESTATE_ERROR:
+			if (err_not_care_flag == TRUE) {
+				mmc_drv_obj.during_cmd_processing = FALSE;
+			} else {
+				emmc_softreset();
+				emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD,
+						      rtn_code);
+			}
+			return rtn_code;
+
+		default:
+			state = ESTATE_END;
+			break;
+		}		/* switch (state) */
+	}			/*  while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
+
+	/* force terminate */
+	if (mmc_drv_obj.force_terminate == TRUE) {
+		/* timeout timer is expired. Or, PIO data transfer error. */
+		/* Timeout occurred in the DMA transfer. */
+		if (mmc_drv_obj.during_dma_transfer == TRUE) {
+			mmc_drv_obj.during_dma_transfer = FALSE;
+		}
+		ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n");
+		emmc_softreset();
+
+		return EMMC_ERR_FORCE_TERMINATE;	/* error information has already been written. */
+	}
+
+	/* success */
+	mmc_drv_obj.during_cmd_processing = FALSE;
+	mmc_drv_obj.during_transfer = FALSE;
+
+	return EMMC_SUCCESS;
+}
diff --git a/drivers/renesas/rcar/emmc/emmc_config.h b/drivers/renesas/rcar/emmc/emmc_config.h
new file mode 100644
index 0000000..16dcea1
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_config.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file  emmc_config.h
+ * @brief Configuration file
+ *
+ */
+
+#ifndef __EMMC_CONFIG_H__
+#define __EMMC_CONFIG_H__
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+/** @brief MMC driver config
+ */
+#define EMMC_RCA                1UL	/* RCA  */
+#define EMMC_RW_DATA_TIMEOUT    0x40UL	/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17)  */
+#define EMMC_RETRY_COUNT        0	/* how many times to try after fail. Don't change. */
+#define EMMC_CMD_MAX            60UL	/* Don't change. */
+
+/** @brief etc
+ */
+#define LOADIMAGE_FLAGS_DMA_ENABLE              0x00000001UL
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+#endif /* #ifndef __EMMC_CONFIG_H__ */
+/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_def.h b/drivers/renesas/rcar/emmc/emmc_def.h
new file mode 100644
index 0000000..2944515
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_def.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file  emmc_def.h
+ * @brief eMMC boot is expecting this header file
+ *
+ */
+
+#ifndef __EMMC_DEF_H__
+#define __EMMC_DEF_H__
+
+#include "emmc_std.h"
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+#define EMMC_POWER_ON		(1U)
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+extern st_mmc_base mmc_drv_obj;
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/** @brief for assembler program
+ */
+uint32_t _rom_emmc_finalize(void);
+
+/** @brief eMMC driver API
+ */
+EMMC_ERROR_CODE rcar_emmc_init(void);
+EMMC_ERROR_CODE emmc_terminate(void);
+EMMC_ERROR_CODE rcar_emmc_memcard_power(uint8_t mode);
+EMMC_ERROR_CODE rcar_emmc_mount(void);
+EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq);
+EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg);
+EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id);
+EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual,
+				 uint32_t sector_number, uint32_t count,
+				 uint32_t feature_flags);
+EMMC_ERROR_CODE emmc_write_sector(uint32_t *buff_address_virtual,
+				  uint32_t sector_number, uint32_t count,
+				  uint32_t feature_flags);
+EMMC_ERROR_CODE emmc_erase_sector(uint32_t *start_address,
+				  uint32_t *end_address);
+uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom);
+
+/** @brief interrupt service
+ */
+uint32_t emmc_interrupt(void);
+
+/** @brief DMA
+ */
+
+/** @brief send command API
+ */
+EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response);
+void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg);
+void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg,
+			 uint32_t *buff_address_virtual, uint32_t len,
+			 HAL_MEMCARD_OPERATION dir,
+			 HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode);
+EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg);
+
+/** @brief for error information
+ */
+void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code);
+void emmc_write_error_info_func_no(uint16_t func_no);
+
+/* ********************************* CODE ********************************** */
+
+#endif /* #define __EMMC_DEF_H__ */
+/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_hal.h b/drivers/renesas/rcar/emmc/emmc_hal.h
new file mode 100644
index 0000000..633446c
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_hal.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file  emmc_hal.h
+ * @brief emmc boot driver is expecting this header file
+ *
+ */
+
+#ifndef __EMMC_HAL_H__
+#define __EMMC_HAL_H__
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+#include <stdint.h>
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+/** @brief memory card error/status types
+ */
+#define HAL_MEMCARD_OUT_OF_RANGE            0x80000000L
+#define HAL_MEMCARD_ADDRESS_ERROR           0x40000000L
+#define HAL_MEMCARD_BLOCK_LEN_ERROR         0x20000000L
+#define HAL_MEMCARD_ERASE_SEQ_ERROR         0x10000000L
+#define HAL_MEMCARD_ERASE_PARAM             0x08000000L
+#define HAL_MEMCARD_WP_VIOLATION            0x04000000L
+#define HAL_MEMCARD_CARD_IS_LOCKED          0x02000000L
+#define HAL_MEMCARD_LOCK_UNLOCK_FAILED      0x01000000L
+#define HAL_MEMCARD_COM_CRC_ERROR           0x00800000L
+#define HAL_MEMCARD_ILEGAL_COMMAND          0x00400000L
+#define HAL_MEMCARD_CARD_ECC_FAILED         0x00200000L
+#define HAL_MEMCARD_CC_ERROR                0x00100000L
+#define HAL_MEMCARD_ERROR                   0x00080000L
+#define HAL_MEMCARD_UNDERRUN                0x00040000L
+#define HAL_MEMCARD_OVERRUN                 0x00020000L
+#define HAL_MEMCARD_CIDCSD_OVERWRITE        0x00010000L
+#define HAL_MEMCARD_WP_ERASE_SKIP           0x00008000L
+#define HAL_MEMCARD_CARD_ECC_DISABLED       0x00004000L
+#define HAL_MEMCARD_ERASE_RESET             0x00002000L
+#define HAL_MEMCARD_CARD_STATE              0x00001E00L
+#define HAL_MEMCARD_CARD_READY_FOR_DATA     0x00000100L
+#define HAL_MEMCARD_APP_CMD                 0x00000020L
+#define HAL_MEMCARD_SWITCH_ERROR            0x00000080L
+#define HAL_MEMCARD_AKE_SEQ_ERROR           0x00000008L
+#define HAL_MEMCARD_NO_ERRORS               0x00000000L
+
+/** @brief Memory card response types
+ */
+#define HAL_MEMCARD_COMMAND_INDEX_MASK      0x0003f
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/** @brief Type of the return value.
+ */
+typedef enum {
+	HAL_MEMCARD_FAIL = 0U,
+	HAL_MEMCARD_OK = 1U,
+	HAL_MEMCARD_DMA_ALLOC_FAIL = 2U,     /**< DMA channel allocation failed */
+	HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U,  /**< DMA transfer failed */
+	HAL_MEMCARD_CARD_STATUS_ERROR = 4U,  /**< A non-masked error bit was set in the card status */
+	HAL_MEMCARD_CMD_TIMEOUT = 5U,	     /**< Command timeout occurred */
+	HAL_MEMCARD_DATA_TIMEOUT = 6U,	     /**< Data timeout occurred */
+	HAL_MEMCARD_CMD_CRC_ERROR = 7U,	     /**< Command CRC error occurred */
+	HAL_MEMCARD_DATA_CRC_ERROR = 8U	     /**< Data CRC error occurred */
+} HAL_MEMCARD_RETURN;
+
+/** @brief memory access operation
+ */
+typedef enum {
+	HAL_MEMCARD_READ = 0U,	 /**< read */
+	HAL_MEMCARD_WRITE = 1U	 /**< write */
+} HAL_MEMCARD_OPERATION;
+
+/** @brief Type of data width on memorycard bus
+ */
+typedef enum {
+	HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
+	HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
+	HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
+} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
+
+/** @brief Presence of the memory card
+ */
+typedef enum {
+	HAL_MEMCARD_CARD_IS_IN = 0U,
+	HAL_MEMCARD_CARD_IS_OUT = 1U
+} HAL_MEMCARD_PRESENCE_STATUS;	/* presence status of the memory card */
+
+/** @brief mode of data transfer
+ */
+typedef enum {
+	HAL_MEMCARD_DMA = 0U,
+	HAL_MEMCARD_NOT_DMA = 1U
+} HAL_MEMCARD_DATA_TRANSFER_MODE;
+
+/** @brief Memory card response types.
+ */
+typedef enum hal_memcard_response_type {
+	HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
+	HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
+	HAL_MEMCARD_RESPONSE_R1b = 0x00200U,
+	HAL_MEMCARD_RESPONSE_R2 = 0x00300U,
+	HAL_MEMCARD_RESPONSE_R3 = 0x00400U,
+	HAL_MEMCARD_RESPONSE_R4 = 0x00500U,
+	HAL_MEMCARD_RESPONSE_R5 = 0x00600U,
+	HAL_MEMCARD_RESPONSE_R6 = 0x00700U,
+	HAL_MEMCARD_RESPONSE_R7 = 0x00800U,
+	HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
+} HAL_MEMCARD_RESPONSE_TYPE;
+
+/** @brief Memory card command types.
+ */
+typedef enum hal_memcard_command_type {
+	HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
+	HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
+	HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U,
+	HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U,
+	HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U,
+	HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
+} HAL_MEMCARD_COMMAND_TYPE;
+
+/** @brief Type of memory card
+ */
+typedef enum hal_memcard_command_card_type {
+	HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
+	HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
+	HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U,
+	HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
+} HAL_MEMCARD_COMMAND_CARD_TYPE;
+
+/** @brief Memory card application command.
+ */
+typedef enum hal_memcard_command_app_norm {
+	HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
+	HAL_MEMCARD_COMMAND_APP = 0x20000U,
+	HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
+} HAL_MEMCARD_COMMAND_APP_NORM;
+
+/** @brief Memory card command codes.
+ */
+typedef enum {
+/* class 0 and class 1 */
+	CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD0 */
+	CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD1 */
+	CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD2 */
+	CMD2_ALL_SEND_CID_SD =
+	    2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD3 */
+	CMD3_SEND_RELATIVE_ADDR =
+	    3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD4 */
+	CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD5 */
+	CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD6 */
+	CMD6_SWITCH_FUNC =
+	    6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	ACMD6_SET_BUS_WIDTH =
+	    6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD7 */
+	CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD7(from Disconnected State to Programming State) */
+	CMD7_DESELECT_CARD =
+	    7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
+	CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD8 */
+	CMD8_SEND_IF_COND =
+	    8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+	CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD9 */
+	CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD10 */
+	CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD11 */
+	CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD12 */
+	CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD12(R1b : write case) */
+	CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD13 */
+	ACMD13_SD_STATUS =
+	    13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD14 */
+	CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD15 */
+
+/* class 2 */
+	CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD16 */
+	CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD17 */
+	CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD18 */
+	CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD19 */
+
+/* class 3 */
+	CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD20 */
+	CMD21 = 21,		/* CMD21 */
+	CMD22 = 22,		/* CMD22 */
+	ACMD22_SEND_NUM_WR_BLOCKS =
+	    22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+
+/* class 4 */
+	CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD23 */
+	ACMD23_SET_WR_BLK_ERASE_COUNT =
+	    23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	CMD24_WRITE_BLOCK = 24 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD24 */
+	CMD25_WRITE_MULTIPLE_BLOCK = 25 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD25 */
+	CMD26_PROGRAM_CID = 26 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD26 */
+	CMD27_PROGRAM_CSD = 27 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD27 */
+
+/* class 6 */
+	CMD28_SET_WRITE_PROT = 28 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD28 */
+	CMD29_CLR_WRITE_PROT = 29 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD29 */
+	CMD30_SEND_WRITE_PROT = 30 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD30 */
+	CMD30_SEND_WRITE_PROT_TYPE = 31 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD31 */
+
+/* class 5 */
+	CMD32_ERASE_WR_BLK_START = 32 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD32 */
+	CMD33_ERASE_WR_BLK_END = 33 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD33 */
+	CMD34 = 34,		/* CMD34 */
+	CMD35_ERASE_GROUP_START = 35 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD35 */
+	CMD36_ERASE_GROUP_END = 36 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD36 */
+	CMD37 = 37,		/* CMD37 */
+	CMD38_ERASE = 38 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD38 */
+
+/* class 9 */
+	CMD39_FASTIO = 39 | HAL_MEMCARD_RESPONSE_R4 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD39 */
+	CMD40_GO_IRQSTATE = 40 | HAL_MEMCARD_RESPONSE_R5 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD40 */
+	CMD41 = 41,		/* CMD41 */
+	ACMD41_SD_SEND_OP_COND =
+	    41 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+
+/* class 7 */
+	CMD42_LOCK_UNLOCK = 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD42 */
+	ACMD42_SET_CLR_CARD_DETECT =
+	    42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	CMD43 = 43,		/* CMD43 */
+	CMD44 = 44,		/* CMD44 */
+	CMD45 = 45,		/* CMD45 */
+	CMD46 = 46,		/* CMD46 */
+	CMD47 = 47,		/* CMD47 */
+	CMD48 = 48,		/* CMD48 */
+	CMD49 = 49,		/* CMD49 */
+	CMD50 = 50,		/* CMD50 */
+	CMD51 = 51,		/* CMD51 */
+	ACMD51_SEND_SCR =
+	    51 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+	    HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+	CMD52 = 52,		/* CMD52 */
+	CMD53 = 53,		/* CMD53 */
+	CMD54 = 54,		/* CMD54 */
+
+/* class 8 */
+	CMD55_APP_CMD = 55 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD55 */
+	CMD56_GEN_CMD = 56 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,	/* CMD56 */
+	CMD57 = 57,		/* CMD57 */
+	CMD58 = 58,		/* CMD58 */
+	CMD59 = 59,		/* CMD59 */
+	CMD60 = 60,		/* CMD60 */
+	CMD61 = 61,		/* CMD61 */
+	CMD62 = 62,		/* CMD62 */
+	CMD63 = 63		/* CMD63 */
+} HAL_MEMCARD_COMMAND;
+
+/** @brief Configuration structure from HAL layer.
+ *
+ * If some field is not available it should be filled with 0xFF.
+ * The API version is 32-bit unsigned integer telling the version of the API. The integer is divided to four sections which each can be treated as a 8-bit unsigned number:
+ * Bits 31-24 make the most significant part of the version number. This number starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This number changes only, if the API itself changes so much that it is not compatible anymore with older releases.
+ * Bits 23-16 API minor version number. For example API version 2.1 would be 0x0201xxxx.
+ * Bits 15-8 are the number of the year when release is done. The 0 is year 2000, 1 is year 2001 and so on
+ * Bits 7- are the week number when release is done. First full week of the year is 1
+ *
+ * @note Example: let's assume that release 2.1 is done on week 10 year 2008 the version will get the value 0x0201080A
+ */
+typedef struct {
+    /**
+    * Version of the chipset API implementation
+    *
+    * bits [31:24] API specification major version number.<br>
+    * bits [23:16] API specification minor version number.<br>
+    * bits [15:8] API implemention year. (2000 = 0, 2001 = 1, ...)<br>
+    * bits [7:0] API implemention week.<br>
+    * Example: API specification version 4.0, implementation w46 2008 => 0x0400082E
+    */
+	uint32_t api_version;
+
+    /** maximum block count which can be transferred at once */
+	uint32_t max_block_count;
+
+    /** maximum clock frequence in Hz supported by HW */
+	uint32_t max_clock_freq;
+
+    /** maximum data bus width supported by HW */
+	uint16_t max_data_width;
+
+    /** Is high-speed mode supported by HW (yes=1, no=0) */
+	uint8_t hs_mode_supported;
+
+    /** Is memory card removable (yes=1, no=0) */
+	uint8_t card_removable;
+
+} HAL_MEMCARD_HW_CONF;
+
+/** @brief Configuration structure to HAL layer.
+ */
+typedef struct {
+    /** how many times to try after fail, for instance sending command */
+	uint32_t retries_after_fail;
+} HAL_MEMCARD_INIT_CONF;
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+#endif /* __EMMC_HAL_H__ */
+
+/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_init.c b/drivers/renesas/rcar/emmc/emmc_init.c
new file mode 100644
index 0000000..386fb1e
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_init.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <mmio.h>
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+#include "rcar_private.h"
+
+st_mmc_base mmc_drv_obj;
+
+EMMC_ERROR_CODE rcar_emmc_memcard_power(uint8_t mode)
+{
+
+	if (mode == TRUE) {
+		/* power on (Vcc&Vccq is always power on) */
+		mmc_drv_obj.card_power_enable = TRUE;
+	} else {
+		/* power off (Vcc&Vccq is always power on) */
+		mmc_drv_obj.card_power_enable = FALSE;
+		mmc_drv_obj.mount = FALSE;
+		mmc_drv_obj.selected = FALSE;
+	}
+
+	return EMMC_SUCCESS;
+}
+static __inline void emmc_set_retry_count(uint32_t retry)
+{
+	mmc_drv_obj.retries_after_fail = retry;
+}
+
+static __inline void emmc_set_data_timeout(uint32_t data_timeout)
+{
+	mmc_drv_obj.data_timeout = data_timeout;
+}
+
+static void emmc_memset(uint8_t *buff, uint8_t data, uint32_t cnt)
+{
+	if (buff == NULL) {
+		return;
+	}
+
+	while (cnt > 0) {
+		*buff++ = data;
+		cnt--;
+	}
+}
+
+static void emmc_driver_config(void)
+{
+	emmc_set_retry_count(EMMC_RETRY_COUNT);
+	emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT);
+}
+
+static void emmc_drv_init(void)
+{
+	emmc_memset((uint8_t *) (&mmc_drv_obj), 0, sizeof(st_mmc_base));
+	mmc_drv_obj.card_present = HAL_MEMCARD_CARD_IS_IN;
+	mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT;
+	mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
+}
+
+static EMMC_ERROR_CODE emmc_dev_finalize(void)
+{
+	EMMC_ERROR_CODE result;
+	uint32_t dataL;
+
+	/* MMC power off
+	 * the power supply of eMMC device is always turning on.
+	 * RST_n : Hi --> Low level.
+	 */
+	result = rcar_emmc_memcard_power(FALSE);
+
+	/* host controller reset */
+	SETR_32(SD_INFO1, 0x00000000U);		/* all interrupt clear */
+	SETR_32(SD_INFO2, SD_INFO2_CLEAR);	/* all interrupt clear */
+	SETR_32(SD_INFO1_MASK, 0x00000000U);	/* all interrupt disable */
+	SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);	/* all interrupt disable */
+	SETR_32(SD_CLK_CTRL, 0x00000000U);	/* MMC clock stop */
+
+	dataL = mmio_read_32(CPG_SMSTPCR3);
+	if ((dataL & CPG_MSTP_MMC) == 0U) {
+		dataL |= (CPG_MSTP_MMC);
+		mmio_write_32(CPG_CPGWPR, (~dataL));
+		mmio_write_32(CPG_SMSTPCR3, dataL);
+	}
+
+	return result;
+}
+
+static EMMC_ERROR_CODE emmc_dev_init(void)
+{
+	/* Enable clock supply to eMMC. */
+	mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
+
+	/* Set SD clock */
+	mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0)));	/* SD phy 200MHz */
+
+	/* Stop SDnH clock & SDn=200MHz */
+	mmio_write_32(CPG_SDxCKCR, (BIT9 | BIT0));
+
+	/* MMCIF initialize */
+	SETR_32(SD_INFO1, 0x00000000U);		/* all interrupt clear */
+	SETR_32(SD_INFO2, SD_INFO2_CLEAR);	/* all interrupt clear */
+	SETR_32(SD_INFO1_MASK, 0x00000000U);	/* all interrupt disable */
+	SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);	/* all interrupt disable */
+
+	SETR_32(HOST_MODE, 0x00000000U);	/* SD_BUF access width = 64-bit */
+	SETR_32(SD_OPTION, 0x0000C0EEU);	/* Bus width = 1bit, timeout=MAX */
+	SETR_32(SD_CLK_CTRL, 0x00000000U);	/* Automatic Control=Disable, Clock Output=Disable */
+
+	return EMMC_SUCCESS;
+}
+
+static EMMC_ERROR_CODE emmc_reset_controller(void)
+{
+	EMMC_ERROR_CODE retult;
+
+	/* initialize mmc driver */
+	emmc_drv_init();
+
+	/* initialize H/W */
+	retult = emmc_dev_init();
+	if (EMMC_SUCCESS != retult) {
+		return retult;
+	}
+
+	mmc_drv_obj.initialize = TRUE;
+
+	return retult;
+
+}
+
+EMMC_ERROR_CODE emmc_terminate(void)
+{
+	EMMC_ERROR_CODE result;
+
+	result = emmc_dev_finalize();
+
+	emmc_memset((uint8_t *) (&mmc_drv_obj), 0, sizeof(st_mmc_base));
+
+	return result;
+}
+
+EMMC_ERROR_CODE rcar_emmc_init(void)
+{
+	EMMC_ERROR_CODE retult;
+
+	retult = emmc_reset_controller();
+	if (EMMC_SUCCESS != retult) {
+		return retult;
+	}
+
+	emmc_driver_config();
+
+	return EMMC_SUCCESS;
+}
diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/rcar/emmc/emmc_interrupt.c
new file mode 100644
index 0000000..3077db4
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_interrupt.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
+ * reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#include "emmc_config.h"
+#include "emmc_def.h"
+#include "emmc_hal.h"
+#include "emmc_registers.h"
+#include "emmc_std.h"
+#include "rcar_def.h"
+
+#include <mmio.h>
+#include <stddef.h>
+
+static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual);
+
+uint32_t emmc_interrupt(void)
+{
+	EMMC_ERROR_CODE result;
+	uint32_t prr_data;
+	uint32_t cut_ver;
+	uint32_t end_bit;
+
+	prr_data = mmio_read_32((uintptr_t) RCAR_PRR);
+	cut_ver = prr_data & RCAR_CUT_MASK;
+	if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_H3) {
+		if (cut_ver == RCAR_CUT_VER10) {
+			end_bit = BIT17;
+		} else if (cut_ver == RCAR_CUT_VER11) {
+			end_bit = BIT17;
+		} else {
+			end_bit = BIT20;
+		}
+	} else if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_M3) {
+		if (cut_ver == RCAR_CUT_VER10) {
+			end_bit = BIT17;
+		} else {
+			end_bit = BIT20;
+		}
+	} else {
+		end_bit = BIT20;
+	}
+
+	/* SD_INFO */
+	mmc_drv_obj.error_info.info1 = GETR_32(SD_INFO1);
+	mmc_drv_obj.error_info.info2 = GETR_32(SD_INFO2);
+
+	/* SD_INFO EVENT */
+	mmc_drv_obj.int_event1 =
+	    mmc_drv_obj.error_info.info1 & GETR_32(SD_INFO1_MASK);
+	mmc_drv_obj.int_event2 =
+	    mmc_drv_obj.error_info.info2 & GETR_32(SD_INFO2_MASK);
+
+	/* ERR_STS */
+	mmc_drv_obj.error_info.status1 = GETR_32(SD_ERR_STS1);
+	mmc_drv_obj.error_info.status2 = GETR_32(SD_ERR_STS2);
+
+	/* DM_CM_INFO */
+	mmc_drv_obj.error_info.dm_info1 = GETR_32(DM_CM_INFO1);
+	mmc_drv_obj.error_info.dm_info2 = GETR_32(DM_CM_INFO2);
+
+	/* DM_CM_INFO EVENT */
+	mmc_drv_obj.dm_event1 =
+	    mmc_drv_obj.error_info.dm_info1 & GETR_32(DM_CM_INFO1_MASK);
+	mmc_drv_obj.dm_event2 =
+	    mmc_drv_obj.error_info.dm_info2 & GETR_32(DM_CM_INFO2_MASK);
+
+	/* ERR SD_INFO2 */
+	if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0) {
+		SETR_32(SD_INFO1_MASK, 0x00000000U);	/* interrupt disable */
+		SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);	/* interrupt disable */
+		SETR_32(SD_INFO1, 0x00000000U);	/* interrupt clear */
+		SETR_32(SD_INFO2, SD_INFO2_CLEAR);	/* interrupt clear */
+		mmc_drv_obj.state_machine_blocking = FALSE;
+	}
+
+	/* PIO Transfer */
+	/* BWE/BRE */
+	else if (((SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2)) {
+		/* BWE */
+		if (SD_INFO2_BWE & mmc_drv_obj.int_event2) {
+			SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
+		}
+		/* BRE */
+		else {
+			SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
+		}
+
+		result = emmc_trans_sector(mmc_drv_obj.buff_address_virtual);
+		mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH;
+		mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH;
+
+		if (result != EMMC_SUCCESS) {
+			/* data transfer error */
+			emmc_write_error_info(EMMC_FUNCNO_NONE, result);
+
+			/* Panic */
+			SETR_32(SD_INFO1_MASK, 0x00000000U);
+			SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR);
+			SETR_32(SD_INFO1, 0x00000000U);
+			/* interrupt clear */
+			SETR_32(SD_INFO2, SD_INFO2_CLEAR);
+			mmc_drv_obj.force_terminate = TRUE;
+		} else {
+			mmc_drv_obj.during_transfer = FALSE;
+		}
+		mmc_drv_obj.state_machine_blocking = FALSE;
+	}
+
+	/* DMA_TRANSFER */
+	/* DM_CM_INFO1: DMA-ch0 transfer complete or error occurred */
+	else if ((BIT16 & mmc_drv_obj.dm_event1) != 0) {
+		SETR_32(DM_CM_INFO1, 0x00000000U);
+		SETR_32(DM_CM_INFO2, 0x00000000U);
+		/* interrupt clear */
+		SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
+		/* DM_CM_INFO2:  DMA-ch0 error occured */
+		if ((BIT16 & mmc_drv_obj.dm_event2) != 0) {
+			mmc_drv_obj.dma_error_flag = TRUE;
+		} else {
+			mmc_drv_obj.during_dma_transfer = FALSE;
+			mmc_drv_obj.during_transfer = FALSE;
+		}
+		/* wait next interrupt */
+		mmc_drv_obj.state_machine_blocking = FALSE;
+	}
+	/* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
+	else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) {
+		SETR_32(DM_CM_INFO1, 0x00000000U);
+		SETR_32(DM_CM_INFO2, 0x00000000U);
+		/* interrupt clear */
+		SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
+		/* DM_CM_INFO2: DMA-ch1 error occured */
+		if ((BIT17 & mmc_drv_obj.dm_event2) != 0) {
+			mmc_drv_obj.dma_error_flag = TRUE;
+		} else {
+			mmc_drv_obj.during_dma_transfer = FALSE;
+			mmc_drv_obj.during_transfer = FALSE;
+		}
+		/* wait next interrupt */
+		mmc_drv_obj.state_machine_blocking = FALSE;
+	}
+
+	/* Response end  */
+	else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0) {
+		/* interrupt clear */
+		SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO0));
+		mmc_drv_obj.state_machine_blocking = FALSE;
+	}
+	/* Access end  */
+	else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0) {
+		/* interrupt clear */
+		SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO2));
+		mmc_drv_obj.state_machine_blocking = FALSE;
+	} else {
+		/* nothing to do. */
+	}
+
+	return (uint32_t) 0;
+}
+
+static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual)
+{
+	uint32_t length, i;
+	uint64_t *bufPtrLL;
+
+	if (buff_address_virtual == NULL) {
+		return EMMC_ERR_PARAM;
+	}
+
+	if ((mmc_drv_obj.during_transfer != TRUE)
+	    || (mmc_drv_obj.remain_size == 0)) {
+		return EMMC_ERR_STATE;
+	}
+
+	bufPtrLL = (uint64_t *) buff_address_virtual;
+	length = mmc_drv_obj.remain_size;
+
+	/* data transefer */
+	for (i = 0; i < (length >> 3); i++) {
+		/* Write */
+		if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) {
+			SETR_64(SD_BUF0, *bufPtrLL);	/* buffer --> FIFO */
+		}
+		/* Read */
+		else {
+			/* Checks when the read data reaches SD_SIZE. */
+			/* The BRE bit is cleared at emmc_interrupt function. */
+			if (((i %
+			      (uint32_t) (EMMC_BLOCK_LENGTH >>
+					  EMMC_BUF_SIZE_SHIFT)) == 0U)
+			    && (i != 0U)) {
+				/* BRE check */
+				while (((GETR_32(SD_INFO2)) & SD_INFO2_BRE) ==
+				       0U) {
+					/* ERROR check */
+					if (((GETR_32(SD_INFO2)) &
+					     SD_INFO2_ALL_ERR) != 0U) {
+						return EMMC_ERR_TRANSFER;
+					}
+				}
+				/* BRE clear */
+				SETR_32(SD_INFO2,
+					(uint32_t) (GETR_32(SD_INFO2) &
+						    ~SD_INFO2_BRE));
+			}
+			*bufPtrLL = GETR_64(SD_BUF0);	/* FIFO --> buffer */
+		}
+		bufPtrLL++;
+	}
+
+	return EMMC_SUCCESS;
+}
diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/rcar/emmc/emmc_mount.c
new file mode 100644
index 0000000..9a7d2ca
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_mount.c
@@ -0,0 +1,680 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <mmio.h>
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+#include "micro_delay.h"
+#include "rcar_def.h"
+
+static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode);
+static EMMC_ERROR_CODE emmc_card_init(void);
+static EMMC_ERROR_CODE emmc_high_speed(void);
+static EMMC_ERROR_CODE emmc_bus_width(uint32_t width);
+static uint32_t emmc_set_timeout_register_value(uint32_t freq);
+static void set_sd_clk(uint32_t clkDiv);
+static uint32_t emmc_calc_tran_speed(uint32_t *freq);
+static void emmc_get_partition_access(void);
+static void emmc_set_bootpartition(void);
+
+static void emmc_set_bootpartition(void)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	if (reg == RCAR_PRODUCT_M3_CUT10) {
+		mmc_drv_obj.boot_partition_en =
+		    (EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] &
+					  EMMC_BOOT_PARTITION_EN_MASK) >>
+					 EMMC_BOOT_PARTITION_EN_SHIFT);
+	} else if ((reg == RCAR_PRODUCT_H3_CUT20)
+		   || (reg == RCAR_PRODUCT_M3_CUT11)) {
+		mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access;
+	} else {
+		if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) !=
+		    0U) {
+			mmc_drv_obj.boot_partition_en = PARTITION_ID_BOOT_2;
+		} else {
+			mmc_drv_obj.boot_partition_en = PARTITION_ID_BOOT_1;
+		}
+	}
+}
+
+static EMMC_ERROR_CODE emmc_card_init(void)
+{
+	int32_t retry;
+	uint32_t freq = MMC_400KHZ;	/* 390KHz */
+	EMMC_ERROR_CODE result;
+	uint32_t resultCalc;
+
+	/* state check */
+	if ((mmc_drv_obj.initialize != TRUE)
+	    || (mmc_drv_obj.card_power_enable != TRUE)
+	    || ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)
+	    ) {
+		emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	/* clock on (force change) */
+	mmc_drv_obj.current_freq = 0;
+	mmc_drv_obj.max_freq = MMC_20MHZ;
+	result = emmc_set_request_mmc_clock(&freq);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return EMMC_ERR;
+	}
+
+	rcar_micro_delay(1000U);	/* wait 1ms */
+
+	/* Get current access partition */
+	emmc_get_partition_access();
+
+	/* CMD0, arg=0x00000000 */
+	result = emmc_send_idle_cmd(0x00000000);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return result;
+	}
+
+	rcar_micro_delay(200U);	/* wait 74clock 390kHz(189.74us) */
+
+	/* CMD1 */
+	emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE);
+	for (retry = 300; retry > 0; retry--) {
+		result =
+		    emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+		if (result != EMMC_SUCCESS) {
+			emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+			return result;
+		}
+
+		if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0) {
+			break;	/* card is ready. exit loop */
+		}
+		rcar_micro_delay(1000U);	/* wait 1ms */
+	}
+
+	if (retry == 0) {
+		emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_TIMEOUT);
+		return EMMC_ERR_TIMEOUT;
+	}
+
+	switch (mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) {
+	case EMMC_OCR_ACCESS_MODE_SECT:
+		mmc_drv_obj.access_mode = TRUE;	/* sector mode */
+		break;
+	default:
+		/* unknown value */
+		emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR);
+		return EMMC_ERR;
+	}
+
+	/* CMD2 */
+	emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000);
+	mmc_drv_obj.response = (uint32_t *) (&mmc_drv_obj.cid_data[0]);	/* use CID special buffer */
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return result;
+	}
+
+	/* CMD3 */
+	emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return result;
+	}
+
+	/* CMD9 (CSD) */
+	emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16);
+	mmc_drv_obj.response = (uint32_t *) (&mmc_drv_obj.csd_data[0]);	/* use CSD special buffer */
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return result;
+	}
+
+	/* card version check */
+	if (EMMC_CSD_SPEC_VARS() < 4) {
+		emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
+				      EMMC_ERR_ILLEGAL_CARD);
+		return EMMC_ERR_ILLEGAL_CARD;
+	}
+
+	/* CMD7 (select card) */
+	emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return result;
+	}
+
+	mmc_drv_obj.selected = TRUE;
+
+	/* card speed check */
+	resultCalc = emmc_calc_tran_speed(&freq);	/* Card spec is calculated from TRAN_SPEED(CSD).  */
+	if (resultCalc == 0) {
+		emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
+				      EMMC_ERR_ILLEGAL_CARD);
+		return EMMC_ERR_ILLEGAL_CARD;
+	}
+	mmc_drv_obj.max_freq = freq;	/* max frequency (card spec) */
+
+	result = emmc_set_request_mmc_clock(&freq);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return EMMC_ERR;
+	}
+
+	/* set read/write timeout */
+	mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq);
+	SETR_32(SD_OPTION,
+		((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) |
+		 mmc_drv_obj.data_timeout));
+
+	/* SET_BLOCKLEN(512byte) */
+	/* CMD16 */
+	emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return result;
+	}
+
+	/* Transfer Data Length */
+	SETR_32(SD_SIZE, EMMC_BLOCK_LENGTH);
+
+	/* CMD8 (EXT_CSD) */
+	emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000,
+			    (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
+			    EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ,
+			    HAL_MEMCARD_NOT_DMA);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		/* CMD12 is not send.
+		 * If BUS initialization is failed, user must be execute Bus initialization again.
+		 * Bus initialization is start CMD0(soft reset command).
+		 */
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		return result;
+	}
+
+	/* Set boot partition */
+	emmc_set_bootpartition();
+
+	return EMMC_SUCCESS;
+}
+
+static EMMC_ERROR_CODE emmc_high_speed(void)
+{
+	uint32_t freq;	      /**< High speed mode clock frequency */
+	EMMC_ERROR_CODE result;
+	uint8_t cardType;
+
+	/* state check */
+	if (mmc_drv_obj.selected != TRUE) {
+		emmc_write_error_info(EMMC_FUNCNO_HIGH_SPEED, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	/* max frequency */
+	cardType = (uint8_t) mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE];
+	if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0)
+		freq = MMC_52MHZ;
+	else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0)
+		freq = MMC_26MHZ;
+	else
+		freq = MMC_20MHZ;
+
+	/* Hi-Speed-mode selction */
+	if ((MMC_52MHZ == freq) || (MMC_26MHZ == freq)) {
+		/* CMD6 */
+		emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING);
+		result =
+		    emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+		if (result != EMMC_SUCCESS) {
+			emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
+			return result;
+		}
+
+		mmc_drv_obj.hs_timing = TIMING_HIGH_SPEED;	/* High-Speed */
+	}
+
+	/* set mmc clock */
+	mmc_drv_obj.max_freq = freq;
+	result = emmc_set_request_mmc_clock(&freq);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
+		return EMMC_ERR;
+	}
+
+	/* set read/write timeout */
+	mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq);
+	SETR_32(SD_OPTION,
+		((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) |
+		 mmc_drv_obj.data_timeout));
+
+	/* CMD13 */
+	emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16);
+	result =
+	    emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
+		return result;
+	}
+
+	return EMMC_SUCCESS;
+}
+
+static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode)
+{
+	uint32_t value;
+
+	/* busy check */
+	if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) {
+		emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK,
+				      EMMC_ERR_CARD_BUSY);
+		return EMMC_ERR;
+	}
+
+	if (mode == TRUE) {
+		/* clock ON */
+		value =
+		    ((GETR_32(SD_CLK_CTRL) | MMC_SD_CLK_START) &
+		     SD_CLK_WRITE_MASK);
+		SETR_32(SD_CLK_CTRL, value);	/* on  */
+		mmc_drv_obj.clock_enable = TRUE;
+	} else {
+		/* clock OFF */
+		value =
+		    ((GETR_32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) &
+		     SD_CLK_WRITE_MASK);
+		SETR_32(SD_CLK_CTRL, value);	/* off */
+		mmc_drv_obj.clock_enable = FALSE;
+	}
+
+	return EMMC_SUCCESS;
+}
+
+static EMMC_ERROR_CODE emmc_bus_width(uint32_t width)
+{
+	EMMC_ERROR_CODE result = EMMC_ERR;
+
+	/* parameter check */
+	if ((width != 8) && (width != 4) && (width != 1)) {
+		emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_PARAM);
+		return EMMC_ERR_PARAM;
+	}
+
+	/* state check */
+	if (mmc_drv_obj.selected != TRUE) {
+		emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2);	/* 2 = 8bit, 1 = 4bit, 0 =1bit */
+
+	/* CMD6 */
+	emmc_make_nontrans_cmd(CMD6_SWITCH,
+			       (EMMC_SWITCH_BUS_WIDTH_1 |
+				(mmc_drv_obj.bus_width << 8)));
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		/* occurred error */
+		mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
+		goto EXIT;
+	}
+
+	switch (mmc_drv_obj.bus_width) {
+	case HAL_MEMCARD_DATA_WIDTH_1_BIT:
+		SETR_32(SD_OPTION,
+			((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT15));
+		break;
+	case HAL_MEMCARD_DATA_WIDTH_4_BIT:
+		SETR_32(SD_OPTION, (GETR_32(SD_OPTION) & ~(BIT15 | BIT13)));
+		break;
+	case HAL_MEMCARD_DATA_WIDTH_8_BIT:
+		SETR_32(SD_OPTION,
+			((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT13));
+		break;
+	default:
+		goto EXIT;
+	}
+
+	/* CMD13 */
+	emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		goto EXIT;
+	}
+
+	/* CMD8 (EXT_CSD) */
+	emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000,
+			    (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
+			    EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ,
+			    HAL_MEMCARD_NOT_DMA);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		goto EXIT;
+	}
+
+	return EMMC_SUCCESS;
+
+EXIT:
+
+	emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result);
+	ERROR("BL2: emmc bus_width error end\n");
+	return result;
+}
+
+EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id)
+{
+	EMMC_ERROR_CODE result;
+	uint32_t arg;
+	uint32_t partition_config;
+
+	/* state check */
+	if (mmc_drv_obj.mount != TRUE) {
+		emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	/* id = PARTITION_ACCESS(Bit[2:0]) */
+	if ((id & ~PARTITION_ID_MASK) != 0) {
+		emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_PARAM);
+		return EMMC_ERR_PARAM;
+	}
+
+	/* EXT_CSD[179] value */
+	partition_config =
+	    (uint32_t) mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG];
+	if ((partition_config & PARTITION_ID_MASK) == id) {
+		result = EMMC_SUCCESS;
+	} else {
+
+		partition_config =
+		    (uint32_t) ((partition_config & ~PARTITION_ID_MASK) | id);
+		arg = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8);
+
+		result = emmc_set_ext_csd(arg);
+	}
+
+	return result;
+}
+
+static void set_sd_clk(uint32_t clkDiv)
+{
+	uint32_t dataL;
+
+	dataL = (GETR_32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK));
+
+	switch (clkDiv) {
+	case 1:
+		dataL |= 0x000000FFU;
+		break;		/* 1/1   */
+	case 2:
+		dataL |= 0x00000000U;
+		break;		/* 1/2   */
+	case 4:
+		dataL |= 0x00000001U;
+		break;		/* 1/4   */
+	case 8:
+		dataL |= 0x00000002U;
+		break;		/* 1/8   */
+	case 16:
+		dataL |= 0x00000004U;
+		break;		/* 1/16  */
+	case 32:
+		dataL |= 0x00000008U;
+		break;		/* 1/32  */
+	case 64:
+		dataL |= 0x00000010U;
+		break;		/* 1/64  */
+	case 128:
+		dataL |= 0x00000020U;
+		break;		/* 1/128 */
+	case 256:
+		dataL |= 0x00000040U;
+		break;		/* 1/256 */
+	case 512:
+		dataL |= 0x00000080U;
+		break;		/* 1/512 */
+	}
+
+	SETR_32(SD_CLK_CTRL, dataL);
+	mmc_drv_obj.current_freq = (uint32_t) clkDiv;
+}
+
+static void emmc_get_partition_access(void)
+{
+	uint32_t reg;
+	EMMC_ERROR_CODE result;
+
+	reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) {
+		SETR_32(SD_OPTION, 0x000060EEU);	/* 8 bits width */
+		/* CMD8 (EXT_CSD) */
+		emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U,
+				    (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
+				    EMMC_MAX_EXT_CSD_LENGTH,
+				    HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA);
+		mmc_drv_obj.get_partition_access_flag = TRUE;
+		result =
+		    emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+		mmc_drv_obj.get_partition_access_flag = FALSE;
+		if (result == EMMC_SUCCESS) {
+			mmc_drv_obj.partition_access =
+			    (EMMC_PARTITION_ID) (mmc_drv_obj.ext_csd_data[179]
+						 & PARTITION_ID_MASK);
+		} else if (result == EMMC_ERR_CMD_TIMEOUT) {
+			mmc_drv_obj.partition_access = PARTITION_ID_BOOT_1;
+		} else {
+			emmc_write_error_info(EMMC_FUNCNO_GET_PERTITION_ACCESS,
+					      result);
+			panic();
+		}
+		SETR_32(SD_OPTION, 0x0000C0EEU);	/* Initialize */
+	}
+}
+
+static uint32_t emmc_calc_tran_speed(uint32_t *freq)
+{
+	const uint32_t unit[8] = { 10000, 100000, 1000000, 10000000,
+				0, 0, 0, 0 };   /**< frequency unit (1/10) */
+	const uint32_t mult[16] = { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45,
+				52, 55, 60, 70, 80 };
+
+	uint32_t maxFreq;
+	uint32_t result;
+	uint32_t tran_speed = EMMC_CSD_TRAN_SPEED();
+
+	/* tran_speed = 0x32
+	 * unit[tran_speed&0x7] = uint[0x2] = 1000000
+	 * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26
+	 * 1000000 * 26 = 26000000 (26MHz)
+	 */
+
+	result = 1;
+	maxFreq =
+	    unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] *
+	    mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >>
+		 EMMC_TRANSPEED_MULT_SHIFT];
+
+	if (maxFreq == 0) {
+		result = 0;
+	} else if (MMC_FREQ_52MHZ <= maxFreq)
+		*freq = MMC_52MHZ;
+	else if (MMC_FREQ_26MHZ <= maxFreq)
+		*freq = MMC_26MHZ;
+	else if (MMC_FREQ_20MHZ <= maxFreq)
+		*freq = MMC_20MHZ;
+	else
+		*freq = MMC_400KHZ;
+
+	return result;
+}
+
+static uint32_t emmc_set_timeout_register_value(uint32_t freq)
+{
+	uint32_t timeoutCnt;	/* SD_OPTION   - Timeout Counter  */
+
+	switch (freq) {
+	case 1U:
+		timeoutCnt = 0xE0U;
+		break;		/* SDCLK * 2^27 */
+	case 2U:
+		timeoutCnt = 0xE0U;
+		break;		/* SDCLK * 2^27 */
+	case 4U:
+		timeoutCnt = 0xD0U;
+		break;		/* SDCLK * 2^26 */
+	case 8U:
+		timeoutCnt = 0xC0U;
+		break;		/* SDCLK * 2^25 */
+	case 16U:
+		timeoutCnt = 0xB0U;
+		break;		/* SDCLK * 2^24 */
+	case 32U:
+		timeoutCnt = 0xA0U;
+		break;		/* SDCLK * 2^23 */
+	case 64U:
+		timeoutCnt = 0x90U;
+		break;		/* SDCLK * 2^22 */
+	case 128U:
+		timeoutCnt = 0x80U;
+		break;		/* SDCLK * 2^21 */
+	case 256U:
+		timeoutCnt = 0x70U;
+		break;		/* SDCLK * 2^20 */
+	case 512U:
+		timeoutCnt = 0x70U;
+		break;		/* SDCLK * 2^20 */
+	default:
+		timeoutCnt = 0xE0U;
+		break;		/* SDCLK * 2^27 */
+	}
+
+	return timeoutCnt;
+}
+
+EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg)
+{
+	EMMC_ERROR_CODE result;
+
+	/* CMD6 */
+	emmc_make_nontrans_cmd(CMD6_SWITCH, arg);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		return result;
+	}
+
+	/* CMD13 */
+	emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		return result;
+	}
+
+	/* CMD8 (EXT_CSD) */
+	emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000,
+			    (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
+			    EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ,
+			    HAL_MEMCARD_NOT_DMA);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		return result;
+	}
+	return EMMC_SUCCESS;
+}
+
+EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq)
+{
+	/* parameter check */
+	if (freq == NULL) {
+		emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_PARAM);
+		return EMMC_ERR_PARAM;
+	}
+
+	/* state check */
+	if ((mmc_drv_obj.initialize != TRUE)
+	    || (mmc_drv_obj.card_power_enable != TRUE)) {
+		emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	/* clock is already running in the desired frequency. */
+	if ((mmc_drv_obj.clock_enable == TRUE)
+	    && (mmc_drv_obj.current_freq == *freq)) {
+		return EMMC_SUCCESS;
+	}
+
+	/* busy check */
+	if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) {
+		emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK,
+				      EMMC_ERR_CARD_BUSY);
+		return EMMC_ERR;
+	}
+
+	set_sd_clk(*freq);
+	mmc_drv_obj.clock_enable = FALSE;
+
+	return emmc_clock_ctrl(TRUE);	/* clock on */
+}
+
+EMMC_ERROR_CODE rcar_emmc_mount(void)
+{
+	EMMC_ERROR_CODE result;
+
+	/* state check */
+	if ((mmc_drv_obj.initialize != TRUE)
+	    || (mmc_drv_obj.card_power_enable != TRUE)
+	    || ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)
+	    ) {
+		emmc_write_error_info(EMMC_FUNCNO_MOUNT, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	/* initialize card (IDLE state --> Transfer state) */
+	result = emmc_card_init();
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
+		if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) {
+			/* nothing to do. */
+		}
+		return result;
+	}
+
+	/* Switching high speed mode */
+	result = emmc_high_speed();
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
+		if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) {
+			/* nothing to do. */
+		}
+		return result;
+	}
+
+	/* Changing the data bus width */
+	result = emmc_bus_width(8);
+	if (result != EMMC_SUCCESS) {
+		emmc_write_error_info_func_no(EMMC_FUNCNO_BUS_WIDTH);
+		if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) {
+			/* nothing to do. */
+		}
+		return result;
+	}
+
+	/* mount complete */
+	mmc_drv_obj.mount = TRUE;
+
+	return EMMC_SUCCESS;
+}
diff --git a/drivers/renesas/rcar/emmc/emmc_read.c b/drivers/renesas/rcar/emmc/emmc_read.c
new file mode 100644
index 0000000..b11c2c4
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_read.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch_helpers.h>
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+
+#define MIN_EMMC(a, b)        (((a) < (b)) ? (a) : (b))
+#define EMMC_RW_SECTOR_COUNT_MAX        0x0000ffffU
+
+static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual,
+		uint32_t sector_number, uint32_t count,
+		HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
+{
+	EMMC_ERROR_CODE result;
+
+	/* parameter check */
+	if ((count > EMMC_RW_SECTOR_COUNT_MAX)
+	    || (count == 0)
+	    || ((transfer_mode != HAL_MEMCARD_DMA)
+		&& (transfer_mode != HAL_MEMCARD_NOT_DMA))
+	    ) {
+		emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM);
+		return EMMC_ERR_PARAM;
+	}
+
+	/* CMD23 */
+	emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		return result;
+	}
+	SETR_32(SD_SECCNT, count);
+	SETR_32(SD_STOP, 0x00000100);
+	SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE));	/* SD_BUF Read/Write DMA Transfer enable */
+
+	/* CMD18 */
+	emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number,
+			    buff_address_virtual,
+			    count << EMMC_SECTOR_SIZE_SHIFT, HAL_MEMCARD_READ,
+			    transfer_mode);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		return result;	/* CMD18 error code */
+	}
+
+	/* CMD13 */
+	emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16);
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		return result;
+	}
+#if RCAR_BL2_DCACHE == 1
+	if (transfer_mode == HAL_MEMCARD_NOT_DMA) {
+		flush_dcache_range((uint64_t) buff_address_virtual,
+				   ((size_t) count << EMMC_SECTOR_SIZE_SHIFT));
+	}
+#endif /* RCAR_BL2_DCACHE == 1 */
+
+	/* ready status check */
+	if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0) {
+		emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR,
+				      EMMC_ERR_CARD_BUSY);
+		return EMMC_ERR_CARD_BUSY;
+	}
+
+	/* state check */
+	if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN) {
+		emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR,
+				      EMMC_ERR_CARD_STATE);
+		return EMMC_ERR_CARD_STATE;
+	}
+
+	return EMMC_SUCCESS;
+}
+
+EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual,
+				 uint32_t sector_number,
+				 uint32_t count, uint32_t feature_flags)
+{
+	uint32_t trans_count;
+	uint32_t remain;
+	EMMC_ERROR_CODE result;
+	HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
+
+	/* parameter check */
+	if (count == 0) {
+		emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM);
+		return EMMC_ERR_PARAM;
+	}
+
+	/* state check */
+	if (mmc_drv_obj.mount != TRUE) {
+		emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_STATE);
+		return EMMC_ERR_STATE;
+	}
+
+	/* DMA? */
+	if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0) {
+		transfer_mode = HAL_MEMCARD_DMA;
+	} else {
+		transfer_mode = HAL_MEMCARD_NOT_DMA;
+	}
+
+	remain = count;
+	while (remain != 0) {
+		trans_count = MIN_EMMC(remain, EMMC_RW_SECTOR_COUNT_MAX);
+		result =
+		    emmc_multiple_block_read(buff_address_virtual,
+					     sector_number, trans_count,
+					     transfer_mode);
+		if (result != EMMC_SUCCESS) {
+			return result;
+		}
+
+		buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count);
+		sector_number += trans_count;
+		remain -= trans_count;
+	}
+
+	return EMMC_SUCCESS;
+}
diff --git a/drivers/renesas/rcar/emmc/emmc_registers.h b/drivers/renesas/rcar/emmc/emmc_registers.h
new file mode 100644
index 0000000..a670ab7
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_registers.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file  emmc_registers.h
+ * @brief emmc boot driver is expecting this header file. HS-MMC module header file.
+ *
+ */
+
+#ifndef __EMMC_REGISTERS_H__
+#define __EMMC_REGISTERS_H__
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+
+/* MMC channel select */
+#define MMC_CH0		(0U)	/* SDHI2/MMC0 */
+#define MMC_CH1		(1U)	/* SDHI3/MMC1 */
+
+#if RCAR_LSI == RCAR_E3
+#define USE_MMC_CH	(MMC_CH1)	/* R-Car E3 */
+#else /* RCAR_LSI == RCAR_E3 */
+#define USE_MMC_CH	(MMC_CH0)	/* R-Car H3/M3/M3N */
+#endif /* RCAR_LSI == RCAR_E3 */
+
+#define		BIT0	(0x00000001U)
+#define		BIT1	(0x00000002U)
+#define		BIT2	(0x00000004U)
+#define		BIT3	(0x00000008U)
+#define		BIT4	(0x00000010U)
+#define		BIT5	(0x00000020U)
+#define		BIT6	(0x00000040U)
+#define		BIT7	(0x00000080U)
+#define		BIT8	(0x00000100U)
+#define		BIT9	(0x00000200U)
+#define		BIT10	(0x00000400U)
+#define		BIT11	(0x00000800U)
+#define		BIT12	(0x00001000U)
+#define		BIT13	(0x00002000U)
+#define		BIT14	(0x00004000U)
+#define		BIT15	(0x00008000U)
+#define		BIT16	(0x00010000U)
+#define		BIT17	(0x00020000U)
+#define		BIT18	(0x00040000U)
+#define		BIT19	(0x00080000U)
+#define		BIT20	(0x00100000U)
+#define		BIT21	(0x00200000U)
+#define		BIT22	(0x00400000U)
+#define		BIT23	(0x00800000U)
+#define		BIT24	(0x01000000U)
+#define		BIT25	(0x02000000U)
+#define		BIT26	(0x04000000U)
+#define		BIT27	(0x08000000U)
+#define		BIT28	(0x10000000U)
+#define		BIT29	(0x20000000U)
+#define		BIT30	(0x40000000U)
+#define		BIT31	(0x80000000U)
+
+/** @brief Clock Pulse Generator (CPG) registers
+ */
+#define	CPG_BASE		(0xE6150000U)
+
+#define	CPG_MSTPSR3		(CPG_BASE+0x0048U)	/* Module stop status register 3 */
+
+#define	CPG_SMSTPCR3		(CPG_BASE+0x013CU)	/* System module stop control register 3 */
+
+#define	CPG_SD2CKCR		(CPG_BASE+0x0268U)	/* SDHI2 clock frequency control register */
+#define CPG_SD3CKCR		(CPG_BASE+0x026CU)	/* SDHI3 clock frequency control register */
+
+#define	CPG_CPGWPR		(CPG_BASE+0x0900U)	/* CPG Write Protect Register */
+
+#if USE_MMC_CH == MMC_CH0
+#define	CPG_SDxCKCR		(CPG_SD2CKCR)	/* SDHI2/MMC0 */
+#else /* USE_MMC_CH == MMC_CH0 */
+#define	CPG_SDxCKCR		(CPG_SD3CKCR)	/* SDHI3/MMC1 */
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+/** Boot Status register
+ */
+#define  MFISBTSTSR			(0xE6260604U)
+
+#define  MFISBTSTSR_BOOT_PARTITION	(0x00000010U)
+
+/** brief eMMC registers
+ */
+#define	MMC0_SD_BASE		(0xEE140000U)
+#define MMC1_SD_BASE		(0xEE160000U)
+
+#if USE_MMC_CH == MMC_CH0
+#define	MMC_SD_BASE		(MMC0_SD_BASE)
+#else /* USE_MMC_CH == MMC_CH0 */
+#define	MMC_SD_BASE		(MMC1_SD_BASE)
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+#define SD_CMD			(MMC_SD_BASE + 0x0000U)
+#define SD_PORTSEL		(MMC_SD_BASE + 0x0008U)
+#define SD_ARG			(MMC_SD_BASE + 0x0010U)
+#define SD_ARG1			(MMC_SD_BASE + 0x0018U)
+#define SD_STOP			(MMC_SD_BASE + 0x0020U)
+#define SD_SECCNT		(MMC_SD_BASE + 0x0028U)
+#define SD_RSP10		(MMC_SD_BASE + 0x0030U)
+#define SD_RSP1			(MMC_SD_BASE + 0x0038U)
+#define SD_RSP32		(MMC_SD_BASE + 0x0040U)
+#define SD_RSP3			(MMC_SD_BASE + 0x0048U)
+#define SD_RSP54		(MMC_SD_BASE + 0x0050U)
+#define SD_RSP5			(MMC_SD_BASE + 0x0058U)
+#define SD_RSP76		(MMC_SD_BASE + 0x0060U)
+#define SD_RSP7			(MMC_SD_BASE + 0x0068U)
+#define SD_INFO1		(MMC_SD_BASE + 0x0070U)
+#define SD_INFO2		(MMC_SD_BASE + 0x0078U)
+#define SD_INFO1_MASK		(MMC_SD_BASE + 0x0080U)
+#define SD_INFO2_MASK		(MMC_SD_BASE + 0x0088U)
+#define SD_CLK_CTRL		(MMC_SD_BASE + 0x0090U)
+#define SD_SIZE			(MMC_SD_BASE + 0x0098U)
+#define SD_OPTION		(MMC_SD_BASE + 0x00A0U)
+#define SD_ERR_STS1		(MMC_SD_BASE + 0x00B0U)
+#define SD_ERR_STS2		(MMC_SD_BASE + 0x00B8U)
+#define SD_BUF0			(MMC_SD_BASE + 0x00C0U)
+#define SDIO_MODE		(MMC_SD_BASE + 0x00D0U)
+#define SDIO_INFO1		(MMC_SD_BASE + 0x00D8U)
+#define SDIO_INFO1_MASK		(MMC_SD_BASE + 0x00E0U)
+#define CC_EXT_MODE		(MMC_SD_BASE + 0x0360U)
+#define SOFT_RST		(MMC_SD_BASE + 0x0380U)
+#define VERSION			(MMC_SD_BASE + 0x0388U)
+#define HOST_MODE		(MMC_SD_BASE + 0x0390U)
+#define DM_CM_DTRAN_MODE	(MMC_SD_BASE + 0x0820U)
+#define DM_CM_DTRAN_CTRL	(MMC_SD_BASE + 0x0828U)
+#define DM_CM_RST		(MMC_SD_BASE + 0x0830U)
+#define DM_CM_INFO1		(MMC_SD_BASE + 0x0840U)
+#define DM_CM_INFO1_MASK	(MMC_SD_BASE + 0x0848U)
+#define DM_CM_INFO2		(MMC_SD_BASE + 0x0850U)
+#define DM_CM_INFO2_MASK	(MMC_SD_BASE + 0x0858U)
+#define DM_DTRAN_ADDR		(MMC_SD_BASE + 0x0880U)
+
+/** @brief SD_INFO1 Registers
+ */
+#define SD_INFO1_HPIRES				0x00010000UL	/* Response Reception Completion        */
+#define SD_INFO1_INFO10				0x00000400UL	/* Indicates the SDDAT3 state           */
+#define SD_INFO1_INFO9				0x00000200UL	/* SDDAT3 Card Insertion                        */
+#define SD_INFO1_INFO8				0x00000100UL	/* SDDAT3 Card Removal                          */
+#define SD_INFO1_INFO7				0x00000080UL	/* Write Protect                                        */
+#define SD_INFO1_INFO5				0x00000020UL	/* Indicates the ISDCD state            */
+#define SD_INFO1_INFO4				0x00000010UL	/* ISDCD Card Insertion                         */
+#define SD_INFO1_INFO3				0x00000008UL	/* ISDCD Card Removal                           */
+#define SD_INFO1_INFO2				0x00000004UL	/* Access end                                           */
+#define SD_INFO1_INFO0				0x00000001UL	/* Response end                                         */
+
+/** @brief SD_INFO2 Registers
+ */
+#define SD_INFO2_ILA				0x00008000UL	/* Illegal Access Error                 */
+#define SD_INFO2_CBSY				0x00004000UL	/* Command Type Register Busy   */
+#define SD_INFO2_SCLKDIVEN			0x00002000UL
+#define SD_INFO2_BWE				0x00000200UL	/* SD_BUF Write Enable                  */
+#define SD_INFO2_BRE				0x00000100UL	/* SD_BUF Read Enable                   */
+#define SD_INFO2_DAT0				0x00000080UL	/* SDDAT0                                               */
+#define SD_INFO2_ERR6				0x00000040UL	/* Response Timeout                             */
+#define SD_INFO2_ERR5				0x00000020UL	/* SD_BUF Illegal Read Access   */
+#define SD_INFO2_ERR4				0x00000010UL	/* SD_BUF Illegal Write Access  */
+#define SD_INFO2_ERR3				0x00000008UL	/* Data Timeout                                 */
+#define SD_INFO2_ERR2				0x00000004UL	/* END Error                                    */
+#define SD_INFO2_ERR1				0x00000002UL	/* CRC Error                                    */
+#define SD_INFO2_ERR0				0x00000001UL	/* CMD Error                                    */
+#define SD_INFO2_ALL_ERR			0x0000807FUL
+#define SD_INFO2_CLEAR				0x00000800UL	/* BIT11 The write value should always be 1. HWM_0003 */
+
+/** @brief SOFT_RST
+ */
+#define SOFT_RST_SDRST				0x00000001UL
+
+/** @brief SD_CLK_CTRL
+ */
+#define SD_CLK_CTRL_SDCLKOFFEN		0x00000200UL
+#define SD_CLK_CTRL_SCLKEN			0x00000100UL
+#define SD_CLK_CTRL_CLKDIV_MASK     0x000000FFUL
+#define SD_CLOCK_ENABLE             0x00000100UL
+#define SD_CLOCK_DISABLE            0x00000000UL
+#define SD_CLK_WRITE_MASK           0x000003FFUL
+#define SD_CLK_CLKDIV_CLEAR_MASK    0xFFFFFF0FUL
+
+/** @brief SD_OPTION
+ */
+#define SD_OPTION_TIMEOUT_CNT_MASK	0x000000F0UL
+
+/** @brief MMC Clock Frequency
+ * 200MHz * 1/x = output clock
+ */
+#define MMC_CLK_OFF			0UL	/* Clock output is disabled                                                             */
+#define MMC_400KHZ			512UL	/* 200MHz * 1/512 = 390 KHz                             */
+#define MMC_20MHZ			16UL	/* 200MHz * 1/16   = 12.5 MHz Normal speed mode         */
+#define MMC_26MHZ			8UL	/* 200MHz * 1/8   = 25 MHz High speed mode 26Mhz        */
+#define MMC_52MHZ			4UL	/* 200MHz * 1/4   = 50 MHz High speed mode 52Mhz        */
+#define MMC_100MHZ			2UL	/* 200MHz * 1/2   = 100 MHz                             */
+#define MMC_200MHZ			1UL	/* 200MHz * 1/1   = 200 MHz                             */
+
+#define MMC_FREQ_52MHZ		52000000UL
+#define MMC_FREQ_26MHZ		26000000UL
+#define MMC_FREQ_20MHZ		20000000UL
+
+/** @brief MMC Clock DIV
+ */
+#define MMC_SD_CLK_START	0x00000100UL	/* CLOCK On             */
+#define MMC_SD_CLK_STOP		(~0x00000100UL)	/* CLOCK stop   */
+#define MMC_SD_CLK_DIV1		0x000000FFUL	/* 1/1          */
+#define MMC_SD_CLK_DIV2		0x00000000UL	/* 1/2          */
+#define MMC_SD_CLK_DIV4		0x00000001UL	/* 1/4          */
+#define MMC_SD_CLK_DIV8		0x00000002UL	/* 1/8          */
+#define MMC_SD_CLK_DIV16	0x00000004UL	/* 1/16         */
+#define MMC_SD_CLK_DIV32	0x00000008UL	/* 1/32         */
+#define MMC_SD_CLK_DIV64	0x00000010UL	/* 1/64         */
+#define MMC_SD_CLK_DIV128	0x00000020UL	/* 1/128        */
+#define MMC_SD_CLK_DIV256	0x00000040UL	/* 1/256        */
+#define MMC_SD_CLK_DIV512	0x00000080UL	/* 1/512        */
+
+/** @brief DM_CM_DTRAN_MODE
+ */
+#define DM_CM_DTRAN_MODE_CH0		0x00000000UL	/* CH0(downstream)      */
+#define DM_CM_DTRAN_MODE_CH1		0x00010000UL	/* CH1(upstream)        */
+#define DM_CM_DTRAN_MODE_BIT_WIDTH	0x00000030UL
+
+/** @brief CC_EXT_MODE
+ */
+#define CC_EXT_MODE_DMASDRW_ENABLE	0x00000002UL	/* SD_BUF Read/Write DMA Transfer */
+#define CC_EXT_MODE_CLEAR			0x00001010UL	/* BIT 12 & 4 always 1. */
+
+/** @brief DM_CM_INFO_MASK
+ */
+#define DM_CM_INFO_MASK_CLEAR		0xFFFCFFFEUL
+#define DM_CM_INFO_CH0_ENABLE		0x00010001UL
+#define DM_CM_INFO_CH1_ENABLE		0x00020001UL
+
+/** @brief DM_DTRAN_ADDR
+ */
+#define DM_DTRAN_ADDR_WRITE_MASK	0xFFFFFFF8UL
+
+/** @brief DM_CM_DTRAN_CTRL
+ */
+#define DM_CM_DTRAN_CTRL_START		0x00000001UL
+
+/** @brief SYSC Registers
+ */
+#if USE_MMC_CH == MMC_CH0
+#define CPG_MSTP_MMC		(BIT12)	/* SDHI2/MMC0 */
+#else /* USE_MMC_CH == MMC_CH0 */
+#define CPG_MSTP_MMC		(BIT11)	/* SDHI3/MMC1 */
+#endif /* USE_MMC_CH == MMC_CH0 */
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+
+/* ********************************* CODE ********************************** */
+
+#endif /* __EMMC_REGISTERS_H__ */
+/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_std.h b/drivers/renesas/rcar/emmc/emmc_std.h
new file mode 100644
index 0000000..f4ce198
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_std.h
@@ -0,0 +1,474 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file  emmc_std.h
+ * @brief eMMC boot is expecting this header file
+ *
+ */
+
+#ifndef __EMMC_STD_H__
+#define __EMMC_STD_H__
+
+#include "emmc_hal.h"
+
+/* ************************ HEADER (INCLUDE) SECTION *********************** */
+
+/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
+#ifndef FALSE
+#define FALSE	0U
+#endif
+#ifndef TRUE
+#define TRUE	1U
+#endif
+
+/** @brief 64bit registers
+ **/
+#define SETR_64(r, v)                   (*(volatile uint64_t *)(r) = (v))
+#define GETR_64(r)                      (*(volatile uint64_t *)(r))
+
+/** @brief 32bit registers
+ **/
+#define SETR_32(r, v)                   (*(volatile uint32_t *)(r) = (v))
+#define GETR_32(r)                      (*(volatile uint32_t *)(r))
+
+/** @brief 16bit registers
+ */
+#define SETR_16(r, v)                   (*(volatile uint16_t *)(r) = (v))
+#define GETR_16(r)                      (*(volatile uint16_t *)(r))
+
+/** @brief 8bit registers
+ */
+#define SETR_8(r, v)                    (*(volatile uint8_t *)(r) = (v))
+#define GETR_8(r)                       (*(volatile uint8_t *)(r))
+
+/** @brief CSD register Macros
+ */
+#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
+
+#define EMMC_CID_MID()			(EMMC_GET_CID(127, 120))
+#define EMMC_CID_CBX()			(EMMC_GET_CID(113, 112))
+#define EMMC_CID_OID()			(EMMC_GET_CID(111, 104))
+#define EMMC_CID_PNM1()			(EMMC_GET_CID(103, 88))
+#define EMMC_CID_PNM2()			(EMMC_GET_CID(87, 56))
+#define EMMC_CID_PRV()			(EMMC_GET_CID(55, 48))
+#define EMMC_CID_PSN()			(EMMC_GET_CID(47, 16))
+#define EMMC_CID_MDT()			(EMMC_GET_CID(15, 8))
+#define EMMC_CID_CRC()			(EMMC_GET_CID(7, 1))
+
+/** @brief CSD register Macros
+ */
+#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
+
+#define EMMC_CSD_CSD_STRUCTURE()        (EMMC_GET_CSD(127, 126))
+#define EMMC_CSD_SPEC_VARS()            (EMMC_GET_CSD(125, 122))
+#define EMMC_CSD_TAAC()                 (EMMC_GET_CSD(119, 112))
+#define EMMC_CSD_NSAC()                 (EMMC_GET_CSD(111, 104))
+#define EMMC_CSD_TRAN_SPEED()           (EMMC_GET_CSD(103, 96))
+#define EMMC_CSD_CCC()                  (EMMC_GET_CSD(95, 84))
+#define EMMC_CSD_READ_BL_LEN()          (EMMC_GET_CSD(83, 80))
+#define EMMC_CSD_READ_BL_PARTIAL()      (EMMC_GET_CSD(79, 79))
+#define EMMC_CSD_WRITE_BLK_MISALIGN()   (EMMC_GET_CSD(78, 78))
+#define EMMC_CSD_READ_BLK_MISALIGN()    (EMMC_GET_CSD(77, 77))
+#define EMMC_CSD_DSR_IMP()              (EMMC_GET_CSD(76, 76))
+#define EMMC_CSD_C_SIZE()               (EMMC_GET_CSD(73, 62))
+#define EMMC_CSD_VDD_R_CURR_MIN()       (EMMC_GET_CSD(61, 59))
+#define EMMC_CSD_VDD_R_CURR_MAX()       (EMMC_GET_CSD(58, 56))
+#define EMMC_CSD_VDD_W_CURR_MIN()       (EMMC_GET_CSD(55, 53))
+#define EMMC_CSD_VDD_W_CURR_MAX()       (EMMC_GET_CSD(52, 50))
+#define EMMC_CSD_C_SIZE_MULT()          (EMMC_GET_CSD(49, 47))
+#define EMMC_CSD_ERASE_GRP_SIZE()       (EMMC_GET_CSD(46, 42))
+#define EMMC_CSD_ERASE_GRP_MULT()       (EMMC_GET_CSD(41, 37))
+#define EMMC_CSD_WP_GRP_SIZE()          (EMMC_GET_CSD(36, 32))
+#define EMMC_CSD_WP_GRP_ENABLE()        (EMMC_GET_CSD(31, 31))
+#define EMMC_CSD_DEFALT_ECC()           (EMMC_GET_CSD(30, 29))
+#define EMMC_CSD_R2W_FACTOR()           (EMMC_GET_CSD(28, 26))
+#define EMMC_CSD_WRITE_BL_LEN()         (EMMC_GET_CSD(25, 22))
+#define EMMC_CSD_WRITE_BL_PARTIAL()     (EMMC_GET_CSD(21, 21))
+#define EMMC_CSD_CONTENT_PROT_APP()     (EMMC_GET_CSD(16, 16))
+#define EMMC_CSD_FILE_FORMAT_GRP()      (EMMC_GET_CSD(15, 15))
+#define EMMC_CSD_COPY()                 (EMMC_GET_CSD(14, 14))
+#define EMMC_CSD_PERM_WRITE_PROTECT()   (EMMC_GET_CSD(13, 13))
+#define EMMC_CSD_TMP_WRITE_PROTECT()    (EMMC_GET_CSD(12, 12))
+#define EMMC_CSD_FILE_FORMAT()          (EMMC_GET_CSD(11, 10))
+#define EMMC_CSD_ECC()                  (EMMC_GET_CSD(9, 8))
+#define EMMC_CSD_CRC()                  (EMMC_GET_CSD(7, 1))
+
+/** @brief for sector access
+ */
+#define EMMC_4B_BOUNDARY_CHECK_MASK         0x00000003
+#define EMMC_SECTOR_SIZE_SHIFT              9U	/* 512 = 2^9 */
+#define EMMC_SECTOR_SIZE                    512
+#define EMMC_BLOCK_LENGTH                   512
+#define EMMC_BLOCK_LENGTH_DW                128
+#define EMMC_BUF_SIZE_SHIFT                 3U	/* 8byte = 2^3 */
+
+/** @brief eMMC specification clock
+ */
+#define EMMC_CLOCK_SPEC_400K                400000UL	 /**< initialize clock 400KHz */
+#define EMMC_CLOCK_SPEC_20M                 20000000UL	 /**< normal speed 20MHz */
+#define EMMC_CLOCK_SPEC_26M                 26000000UL	 /**< high speed 26MHz */
+#define EMMC_CLOCK_SPEC_52M                 52000000UL	 /**< high speed 52MHz */
+#define EMMC_CLOCK_SPEC_100M                100000000UL	 /**< high speed 100MHz */
+
+/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN)
+ */
+typedef enum {
+	EMMC_ERR = 0,				/**< unknown error */
+	EMMC_SUCCESS,				/**< OK */
+	EMMC_ERR_FROM_DMAC,			/**< DMAC allocation error */
+	EMMC_ERR_FROM_DMAC_TRANSFER,		/**< DMAC transfer error */
+	EMMC_ERR_CARD_STATUS_BIT,		/**< card status error. Non-masked error bit was set in the card status */
+	EMMC_ERR_CMD_TIMEOUT,			/**< command timeout error */
+	EMMC_ERR_DATA_TIMEOUT,			/**< data timeout error */
+	EMMC_ERR_CMD_CRC,			/**< command CRC error */
+	EMMC_ERR_DATA_CRC,			/**< data CRC error */
+	EMMC_ERR_PARAM,				/**< parameter error */
+	EMMC_ERR_RESPONSE,			/**< response error */
+	EMMC_ERR_RESPONSE_BUSY,			/**< response busy error */
+	EMMC_ERR_TRANSFER,			/**< data transfer error */
+	EMMC_ERR_READ_SECTOR,			/**< read sector error */
+	EMMC_ERR_WRITE_SECTOR,			/**< write sector error */
+	EMMC_ERR_STATE,				/**< state error */
+	EMMC_ERR_TIMEOUT,			/**< timeout error */
+	EMMC_ERR_ILLEGAL_CARD,			/**< illegal card */
+	EMMC_ERR_CARD_BUSY,			/**< Busy state */
+	EMMC_ERR_CARD_STATE,			/**< card state error */
+	EMMC_ERR_SET_TRACE,			/**< trace information error */
+	EMMC_ERR_FROM_TIMER,			/**< Timer error */
+	EMMC_ERR_FORCE_TERMINATE,		/**< Force terminate */
+	EMMC_ERR_CARD_POWER,			/**< card power fail */
+	EMMC_ERR_ERASE_SECTOR,			/**< erase sector error */
+	EMMC_ERR_INFO2				    /**< exec cmd error info2 */
+} EMMC_ERROR_CODE;
+
+/** @brief Function number */
+#define EMMC_FUNCNO_NONE						0U
+#define EMMC_FUNCNO_DRIVER_INIT						1U
+#define EMMC_FUNCNO_CARD_POWER_ON					2U
+#define EMMC_FUNCNO_MOUNT						3U
+#define EMMC_FUNCNO_CARD_INIT						4U
+#define EMMC_FUNCNO_HIGH_SPEED						5U
+#define EMMC_FUNCNO_BUS_WIDTH						6U
+#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION				7U
+#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR				8U
+#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR				9U
+#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION			10U
+#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR				11U
+#define EMMC_FUNCNO_SET_CLOCK						12U
+#define EMMC_FUNCNO_EXEC_CMD						13U
+#define EMMC_FUNCNO_READ_SECTOR						14U
+#define EMMC_FUNCNO_WRITE_SECTOR					15U
+#define EMMC_FUNCNO_ERASE_SECTOR					16U
+#define EMMC_FUNCNO_GET_PERTITION_ACCESS				17U
+/** @brief Response
+ */
+/** R1 */
+#define EMMC_R1_ERROR_MASK                      0xFDBFE080U	/* Type 'E' bit and bit14(must be 0). ignore bit22 */
+#define EMMC_R1_ERROR_MASK_WITHOUT_CRC          (0xFD3FE080U)	/* Ignore bit23 (Not check CRC error) */
+#define EMMC_R1_STATE_MASK                      0x00001E00U	/* [12:9] */
+#define EMMC_R1_READY                           0x00000100U	/* bit8 */
+#define EMMC_R1_STATE_SHIFT                     9
+
+/** R4 */
+#define EMMC_R4_RCA_MASK                        0xFFFF0000UL
+#define EMMC_R4_STATUS                          0x00008000UL
+
+/** CSD */
+#define EMMC_TRANSPEED_FREQ_UNIT_MASK           0x07	/* bit[2:0] */
+#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT          0
+#define EMMC_TRANSPEED_MULT_MASK                0x78	/* bit[6:3] */
+#define EMMC_TRANSPEED_MULT_SHIFT               3
+
+/** OCR */
+#define EMMC_HOST_OCR_VALUE                     0x40FF8080
+#define EMMC_OCR_STATUS_BIT                     0x80000000L	/* Card power up status bit */
+#define EMMC_OCR_ACCESS_MODE_MASK               0x60000000L	/* bit[30:29] */
+#define EMMC_OCR_ACCESS_MODE_SECT               0x40000000L
+#define EMMC_OCR_ACCESS_MODE_BYTE               0x00000000L
+
+/** EXT_CSD */
+#define EMMC_EXT_CSD_S_CMD_SET                      504
+#define EMMC_EXT_CSD_INI_TIMEOUT_AP                 241
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_360              239
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_195              238
+#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52            235
+#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52            234
+#define EMMC_EXT_CSD_TRIM_MULT                      232
+#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT            231
+#define EMMC_EXT_CSD_SEC_ERASE_MULT                 229
+#define EMMC_EXT_CSD_BOOT_INFO                      228
+#define EMMC_EXT_CSD_BOOT_SIZE_MULTI                226
+#define EMMC_EXT_CSD_ACC_SIZE                       225
+#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE              224
+#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT             223
+#define EMMC_EXT_CSD_PEL_WR_SEC_C                   222
+#define EMMC_EXT_CSD_HC_WP_GRP_SIZE                 221
+#define EMMC_EXT_CSD_S_C_VCC                        220
+#define EMMC_EXT_CSD_S_C_VCCQ                       219
+#define EMMC_EXT_CSD_S_A_TIMEOUT                    217
+#define EMMC_EXT_CSD_SEC_COUNT                      215
+#define EMMC_EXT_CSD_MIN_PERF_W_8_52                210
+#define EMMC_EXT_CSD_MIN_PERF_R_8_52                209
+#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52           208
+#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52           207
+#define EMMC_EXT_CSD_MIN_PERF_W_4_26                206
+#define EMMC_EXT_CSD_MIN_PERF_R_4_26                205
+#define EMMC_EXT_CSD_PWR_CL_26_360                  203
+#define EMMC_EXT_CSD_PWR_CL_52_360                  202
+#define EMMC_EXT_CSD_PWR_CL_26_195                  201
+#define EMMC_EXT_CSD_PWR_CL_52_195                  200
+#define EMMC_EXT_CSD_CARD_TYPE                      196
+#define EMMC_EXT_CSD_CSD_STRUCTURE                  194
+#define EMMC_EXT_CSD_EXT_CSD_REV                    192
+#define EMMC_EXT_CSD_CMD_SET                        191
+#define EMMC_EXT_CSD_CMD_SET_REV                    189
+#define EMMC_EXT_CSD_POWER_CLASS                    187
+#define EMMC_EXT_CSD_HS_TIMING                      185
+#define EMMC_EXT_CSD_BUS_WIDTH                      183
+#define EMMC_EXT_CSD_ERASED_MEM_CONT                181
+#define EMMC_EXT_CSD_PARTITION_CONFIG               179
+#define EMMC_EXT_CSD_BOOT_CONFIG_PROT               178
+#define EMMC_EXT_CSD_BOOT_BUS_WIDTH                 177
+#define EMMC_EXT_CSD_ERASE_GROUP_DEF                175
+#define EMMC_EXT_CSD_BOOT_WP                        173
+#define EMMC_EXT_CSD_USER_WP                        171
+#define EMMC_EXT_CSD_FW_CONFIG                      169
+#define EMMC_EXT_CSD_RPMB_SIZE_MULT                 168
+#define EMMC_EXT_CSD_RST_n_FUNCTION                 162
+#define EMMC_EXT_CSD_PARTITIONING_SUPPORT           160
+#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT              159
+#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE           156
+#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED    155
+#define EMMC_EXT_CSD_GP_SIZE_MULT                   154
+#define EMMC_EXT_CSD_ENH_SIZE_MULT                  142
+#define EMMC_EXT_CSD_ENH_START_ADDR                 139
+#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT              134
+
+#define EMMC_EXT_CSD_CARD_TYPE_26MHZ                0x01
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ                0x02
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V        0x04
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V        0x08
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK           0x0e
+
+/** SWITCH (CMD6) argument */
+#define	EXTCSD_ACCESS_BYTE	(BIT25|BIT24)
+#define	EXTCSD_SET_BITS		BIT24
+
+#define	HS_TIMING_ADD		(185<<16)	/* H'b9 */
+#define	HS_TIMING_1			(1<<8)
+#define	HS_TIMING_HS200		(2<<8)
+#define	HS_TIMING_HS400		(3<<8)
+
+#define	BUS_WIDTH_ADD		(183<<16)	/* H'b7 */
+#define	BUS_WIDTH_1			(0<<8)
+#define	BUS_WIDTH_4			(1<<8)
+#define	BUS_WIDTH_8			(2<<8)
+#define	BUS_WIDTH_4DDR		(5<<8)
+#define	BUS_WIDTH_8DDR		(6<<8)
+
+#define EMMC_SWITCH_HS_TIMING           (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1)		/**< H'03b90100 */
+#define	EMMC_SWITCH_HS_TIMING_OFF	    (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD)					/**< H'03b90000 */
+
+#define EMMC_SWITCH_BUS_WIDTH_1         (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1)		/**< H'03b70000 */
+#define EMMC_SWITCH_BUS_WIDTH_4         (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4)		/**< H'03b70100 */
+#define EMMC_SWITCH_BUS_WIDTH_8         (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8)		/**< H'03b70200 */
+#define	EMMC_SWITCH_BUS_WIDTH_4DDR      (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR)	/**< H'03b70500 */
+#define	EMMC_SWITCH_BUS_WIDTH_8DDR      (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR)	/**< H'03b70600 */
+#define EMMC_SWITCH_PARTITION_CONFIG    0x03B30000UL	/**< Partition config = 0x00 */
+
+#define TIMING_HIGH_SPEED					1UL
+#define EMMC_BOOT_PARTITION_EN_MASK	0x38U
+#define EMMC_BOOT_PARTITION_EN_SHIFT	3U
+
+/** Bus width */
+#define EMMC_BUSWIDTH_1BIT              CE_CMD_SET_DATW_1BIT
+#define EMMC_BUSWIDTH_4BIT              CE_CMD_SET_DATW_4BIT
+#define EMMC_BUSWIDTH_8BIT              CE_CMD_SET_DATW_8BIT
+
+/** for st_mmc_base */
+#define EMMC_MAX_RESPONSE_LENGTH        17
+#define EMMC_MAX_CID_LENGTH             16
+#define EMMC_MAX_CSD_LENGTH             16
+#define EMMC_MAX_EXT_CSD_LENGTH         512U
+#define EMMC_RES_REG_ALIGNED            4U
+#define EMMC_BUF_REG_ALIGNED            8U
+
+/** @brief for TAAC mask
+ */
+#define TAAC_TIME_UNIT_MASK         (0x07)
+#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
+
+/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+
+/** @brief Partition id
+ */
+typedef enum {
+	PARTITION_ID_USER = 0x0,    /**< User Area */
+	PARTITION_ID_BOOT_1 = 0x1,  /**< boot partition 1 */
+	PARTITION_ID_BOOT_2 = 0x2,  /**< boot partition 2 */
+	PARTITION_ID_RPMB = 0x3,    /**< Replay Protected Memory Block */
+	PARTITION_ID_GP_1 = 0x4,    /**< General Purpose partition 1 */
+	PARTITION_ID_GP_2 = 0x5,    /**< General Purpose partition 2 */
+	PARTITION_ID_GP_3 = 0x6,    /**< General Purpose partition 3 */
+	PARTITION_ID_GP_4 = 0x7,    /**< General Purpose partition 4 */
+	PARTITION_ID_MASK = 0x7	    /**< [2:0] */
+} EMMC_PARTITION_ID;
+
+/** @brief card state in R1 response [12:9]
+ */
+typedef enum {
+	EMMC_R1_STATE_IDLE = 0,
+	EMMC_R1_STATE_READY,
+	EMMC_R1_STATE_IDENT,
+	EMMC_R1_STATE_STBY,
+	EMMC_R1_STATE_TRAN,
+	EMMC_R1_STATE_DATA,
+	EMMC_R1_STATE_RCV,
+	EMMC_R1_STATE_PRG,
+	EMMC_R1_STATE_DIS,
+	EMMC_R1_STATE_BTST,
+	EMMC_R1_STATE_SLEP
+} EMMC_R1_STATE;
+
+typedef enum {
+	ESTATE_BEGIN = 0,
+	ESTATE_ISSUE_CMD,
+	ESTATE_NON_RESP_CMD,
+	ESTATE_RCV_RESP,
+	ESTATE_RCV_RESPONSE_BUSY,
+	ESTATE_CHECK_RESPONSE_COMPLETE,
+	ESTATE_DATA_TRANSFER,
+	ESTATE_DATA_TRANSFER_COMPLETE,
+	ESTATE_ACCESS_END,
+	ESTATE_TRANSFER_ERROR,
+	ESTATE_ERROR,
+	ESTATE_END
+} EMMC_INT_STATE;
+
+/** @brief eMMC boot driver error information
+ */
+typedef struct {
+	uint16_t num;		  /**< error no */
+	uint16_t code;		  /**< error code */
+	volatile uint32_t info1;  /**< SD_INFO1 register value. (hardware dependence) */
+	volatile uint32_t info2;  /**< SD_INFO2 register value. (hardware dependence) */
+	volatile uint32_t status1;/**< SD_ERR_STS1 register value. (hardware dependence) */
+	volatile uint32_t status2;/**< SD_ERR_STS2 register value. (hardware dependence) */
+	volatile uint32_t dm_info1;/**< DM_CM_INFO1 register value. (hardware dependence) */
+	volatile uint32_t dm_info2;/**< DM_CM_INFO2 register value. (hardware dependence) */
+} st_error_info;
+
+/** @brief Command information
+ */
+typedef struct {
+	HAL_MEMCARD_COMMAND cmd;	/**< Command information */
+	uint32_t arg;			  /**< argument */
+	HAL_MEMCARD_OPERATION dir;	/**< direction */
+	uint32_t hw;			  /**< H/W dependence. SD_CMD register value. */
+} st_command_info;
+
+/** @brief MMC driver base
+ */
+typedef struct {
+	st_error_info error_info;	/**< error information */
+	st_command_info cmd_info;	/**< command information */
+
+	/* for data transfer */
+	uint32_t *buff_address_virtual;	   /**< Dest or Src buff */
+	uint32_t *buff_address_physical;   /**< Dest or Src buff */
+	HAL_MEMCARD_DATA_WIDTH bus_width;
+					/**< bus width */
+	uint32_t trans_size;		  /**< transfer size for this command */
+	uint32_t remain_size;		  /**< remain size for this command */
+	uint32_t response_length;	  /**< response length for this command */
+	uint32_t sector_size;		   /**< sector_size */
+
+	/* clock */
+	uint32_t base_clock;		  /**< MMC host controller clock */
+	uint32_t max_freq;		  /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
+	uint32_t request_freq;		  /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */
+	uint32_t current_freq;		  /**< current MMC clock[Hz] (the closest frequency supported by HW) */
+
+	/* state flag */
+	HAL_MEMCARD_PRESENCE_STATUS card_present;
+						/**< presence status of the memory card */
+	uint32_t card_power_enable;		  /**< True : Power ON */
+	uint32_t clock_enable;			  /**< True : Clock ON */
+	uint32_t initialize;			  /**< True : initialize complete. */
+	uint32_t access_mode;			  /**< True : sector access, FALSE : byte access */
+	uint32_t mount;				  /**< True : mount complete. */
+	uint32_t selected;			  /**< True : selected card. */
+	HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
+						    /**< 0: DMA, 1:PIO */
+	uint32_t image_num;			  /**< loaded ISSW image No. ISSW have copy image. */
+	EMMC_R1_STATE current_state;		/**< card state */
+	volatile uint32_t during_cmd_processing;  /**< True : during command processing */
+	volatile uint32_t during_transfer;	  /**< True : during transfer */
+	volatile uint32_t during_dma_transfer;	  /**< True : during transfer (DMA)*/
+	volatile uint32_t dma_error_flag;	  /**< True : occurred DMAC error */
+	volatile uint32_t force_terminate;	  /**< force terminate flag */
+	volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
+	volatile uint32_t get_partition_access_flag;
+						  /**< True : get partition access processing */
+
+	EMMC_PARTITION_ID boot_partition_en;	/**< Boot partition */
+	EMMC_PARTITION_ID partition_access;	/**< Current access partition */
+
+	/* timeout */
+	uint32_t hs_timing;			/**< high speed */
+
+	/* timeout */
+	uint32_t data_timeout;			  /**< read and write data timeout.*/
+
+	/* retry */
+	uint32_t retries_after_fail;  /**< how many times to try after fail, for instance sending command */
+
+	/* interrupt */
+	volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
+	volatile uint32_t int_event2;	  /**< interrupt SD_INFO2 Event */
+	volatile uint32_t dm_event1;  /**< interrupt DM_CM_INFO1 Event */
+	volatile uint32_t dm_event2;	  /**< interrupt DM_CM_INFO2 Event */
+
+	/* response */
+	uint32_t *response;	      /**< pointer to buffer for executing command. */
+	uint32_t r1_card_status;      /**< R1 response data */
+	uint32_t r3_ocr;	      /**< R3 response data */
+	uint32_t r4_resp;	      /**< R4 response data */
+	uint32_t r5_resp;	      /**< R5 response data */
+
+	uint32_t low_clock_mode_enable;
+				      /**< True : clock mode is low. (MMC clock = Max26MHz) */
+	uint32_t reserved2;
+	uint32_t reserved3;
+	uint32_t reserved4;
+
+	/* CSD registers (4byte align) */
+	uint8_t csd_data[EMMC_MAX_CSD_LENGTH]		      /**< CSD */
+	    __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+	/* CID registers (4byte align) */
+	uint8_t cid_data[EMMC_MAX_CID_LENGTH]		      /**< CID */
+	    __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+	/* EXT CSD registers (8byte align) */
+	uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]	      /**< EXT_CSD */
+	    __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
+	/* Response registers (4byte align) */
+	uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]	      /**< other response */
+	    __attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
+} st_mmc_base;
+
+typedef int (*func) (void);
+
+/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
+
+/* ************************** FUNCTION PROTOTYPES ************************** */
+uint32_t emmc_get_csd_time(void);
+
+#define MMC_DEBUG
+/* ********************************* CODE ********************************** */
+
+/* ******************************** END ************************************ */
+#endif /* __EMMC_STD_H__ */
diff --git a/drivers/renesas/rcar/emmc/emmc_utility.c b/drivers/renesas/rcar/emmc/emmc_utility.c
new file mode 100644
index 0000000..e64947d
--- /dev/null
+++ b/drivers/renesas/rcar/emmc/emmc_utility.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_registers.h"
+#include "emmc_def.h"
+
+static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = {
+	0x00000000,		/* CMD0 */
+	0x00000701,		/* CMD1 */
+	0x00000002,		/* CMD2 */
+	0x00000003,		/* CMD3 */
+	0x00000004,		/* CMD4 */
+	0x00000505,		/* CMD5 */
+	0x00000406,		/* CMD6 */
+	0x00000007,		/* CMD7 */
+	0x00001C08,		/* CMD8 */
+	0x00000009,		/* CMD9 */
+	0x0000000A,		/* CMD10 */
+	0x00000000,		/* reserved */
+	0x0000000C,		/* CMD12 */
+	0x0000000D,		/* CMD13 */
+	0x00001C0E,		/* CMD14 */
+	0x0000000F,		/* CMD15 */
+	0x00000010,		/* CMD16 */
+	0x00000011,		/* CMD17 */
+	0x00007C12,		/* CMD18 */
+	0x00000C13,		/* CMD19 */
+	0x00000000,
+	0x00001C15,		/* CMD21 */
+	0x00000000,
+	0x00000017,		/* CMD23 */
+	0x00000018,		/* CMD24 */
+	0x00006C19,		/* CMD25 */
+	0x00000C1A,		/* CMD26 */
+	0x0000001B,		/* CMD27 */
+	0x0000001C,		/* CMD28 */
+	0x0000001D,		/* CMD29 */
+	0x0000001E,		/* CMD30 */
+	0x00001C1F,		/* CMD31 */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000423,		/* CMD35 */
+	0x00000424,		/* CMD36 */
+	0x00000000,
+	0x00000026,		/* CMD38 */
+	0x00000427,		/* CMD39 */
+	0x00000428,		/* CMD40(send cmd) */
+	0x00000000,
+	0x0000002A,		/* CMD42 */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000C31,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00007C35,
+	0x00006C36,
+	0x00000037,		/* CMD55 */
+	0x00000038,		/* CMD56(Read) */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+
+uint32_t emmc_bit_field(uint8_t *data, uint32_t top, uint32_t bottom)
+{
+	uint32_t value;
+
+	uint32_t index_top = (uint32_t) (15 - (top >> 3));
+	uint32_t index_bottom = (uint32_t) (15 - (bottom >> 3));
+
+	if (index_top == index_bottom) {
+		value = data[index_top];
+	} else if ((index_top + 1) == index_bottom) {
+		value =
+		    (uint32_t) ((data[index_top] << 8) | data[index_bottom]);
+	} else if ((index_top + 2) == index_bottom) {
+		value =
+		    (uint32_t) ((data[index_top] << 16) |
+				(data[index_top + 1] << 8) | data[index_top +
+								  2]);
+	} else {
+		value =
+		    (uint32_t) ((data[index_top] << 24) |
+				(data[index_top + 1] << 16) |
+				(data[index_top + 2] << 8) | data[index_top +
+								  3]);
+	}
+
+	value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1));
+
+	return value;
+}
+
+void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code)
+{
+
+	mmc_drv_obj.error_info.num = func_no;
+	mmc_drv_obj.error_info.code = (uint16_t) error_code;
+
+	ERROR("BL2: emmc err:func_no=0x%x code=0x%x\n", func_no, error_code);
+}
+
+void emmc_write_error_info_func_no(uint16_t func_no)
+{
+
+	mmc_drv_obj.error_info.num = func_no;
+
+	ERROR("BL2: emmc err:func_no=0x%x\n", func_no);
+}
+
+void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg)
+{
+	/* command information */
+	mmc_drv_obj.cmd_info.cmd = cmd;
+	mmc_drv_obj.cmd_info.arg = arg;
+	mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ;
+	mmc_drv_obj.cmd_info.hw =
+	    cmd_reg_hw[cmd & HAL_MEMCARD_COMMAND_INDEX_MASK];
+
+	/* clear data transfer information */
+	mmc_drv_obj.trans_size = 0;
+	mmc_drv_obj.remain_size = 0;
+	mmc_drv_obj.buff_address_virtual = NULL;
+	mmc_drv_obj.buff_address_physical = NULL;
+
+	/* response information */
+	mmc_drv_obj.response_length = 6;
+
+	switch (mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK) {
+	case HAL_MEMCARD_RESPONSE_NONE:
+		mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data;
+		mmc_drv_obj.response_length = 0;
+		break;
+	case HAL_MEMCARD_RESPONSE_R1:
+		mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
+		break;
+	case HAL_MEMCARD_RESPONSE_R1b:
+		mmc_drv_obj.cmd_info.hw |= BIT10;	/* bit10 = R1 busy bit */
+		mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
+		break;
+	case HAL_MEMCARD_RESPONSE_R2:
+		mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data;
+		mmc_drv_obj.response_length = 17;
+		break;
+	case HAL_MEMCARD_RESPONSE_R3:
+		mmc_drv_obj.response = &mmc_drv_obj.r3_ocr;
+		break;
+	case HAL_MEMCARD_RESPONSE_R4:
+		mmc_drv_obj.response = &mmc_drv_obj.r4_resp;
+		break;
+	case HAL_MEMCARD_RESPONSE_R5:
+		mmc_drv_obj.response = &mmc_drv_obj.r5_resp;
+		break;
+	default:
+		mmc_drv_obj.response = (uint32_t *) mmc_drv_obj.response_data;
+		break;
+	}
+}
+
+void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg,
+			 uint32_t *buff_address_virtual,
+			 uint32_t len,
+			 HAL_MEMCARD_OPERATION dir,
+			 HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
+{
+	emmc_make_nontrans_cmd(cmd, arg);	/* update common information */
+
+	/* for data transfer command */
+	mmc_drv_obj.cmd_info.dir = dir;
+	mmc_drv_obj.buff_address_virtual = buff_address_virtual;
+	mmc_drv_obj.buff_address_physical = buff_address_virtual;
+	mmc_drv_obj.trans_size = len;
+	mmc_drv_obj.remain_size = len;
+	mmc_drv_obj.transfer_mode = transfer_mode;
+}
+
+EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg)
+{
+	EMMC_ERROR_CODE result;
+	uint32_t freq;
+
+	/* initialize state */
+	mmc_drv_obj.mount = FALSE;
+	mmc_drv_obj.selected = FALSE;
+	mmc_drv_obj.during_transfer = FALSE;
+	mmc_drv_obj.during_cmd_processing = FALSE;
+	mmc_drv_obj.during_dma_transfer = FALSE;
+	mmc_drv_obj.dma_error_flag = FALSE;
+	mmc_drv_obj.force_terminate = FALSE;
+	mmc_drv_obj.state_machine_blocking = FALSE;
+
+	mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
+	mmc_drv_obj.max_freq = MMC_20MHZ;	/* 20MHz */
+	mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE;
+
+	/* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */
+	emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg);	/* CMD0 */
+	result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
+	if (result != EMMC_SUCCESS) {
+		return result;
+	}
+
+	/* change MMC clock(400KHz) */
+	freq = MMC_400KHZ;
+	result = emmc_set_request_mmc_clock(&freq);
+	if (result != EMMC_SUCCESS) {
+		return result;
+	}
+
+	return EMMC_SUCCESS;
+}
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
new file mode 100644
index 0000000..11d52bf
--- /dev/null
+++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <debug.h>
+#include "rcar_def.h"
+#include "cpg_registers.h"
+#include "iic_dvfs.h"
+#include "rcar_private.h"
+
+#define DVFS_RETRY_MAX				(2U)
+
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0		(0x07)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1		(0x09)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2		(0x0B)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3		(0x0E)
+#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E		(0x15)
+
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0		(0x01)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1		(0x02)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2		(0x03)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3		(0x05)
+#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E		(0x07)
+
+#define CPG_BIT_SMSTPCR9_DVFS			(0x04000000)
+
+#define IIC_DVFS_REG_BASE			(0xE60B0000)
+#define IIC_DVFS_REG_ICDR			(IIC_DVFS_REG_BASE + 0x0000)
+#define IIC_DVFS_REG_ICCR			(IIC_DVFS_REG_BASE + 0x0004)
+#define IIC_DVFS_REG_ICSR			(IIC_DVFS_REG_BASE + 0x0008)
+#define IIC_DVFS_REG_ICIC			(IIC_DVFS_REG_BASE + 0x000C)
+#define IIC_DVFS_REG_ICCL			(IIC_DVFS_REG_BASE + 0x0010)
+#define IIC_DVFS_REG_ICCH			(IIC_DVFS_REG_BASE + 0x0014)
+
+#define IIC_DVFS_BIT_ICSR_BUSY			(0x10)
+#define IIC_DVFS_BIT_ICSR_AL			(0x08)
+#define IIC_DVFS_BIT_ICSR_TACK			(0x04)
+#define IIC_DVFS_BIT_ICSR_WAIT			(0x02)
+#define IIC_DVFS_BIT_ICSR_DTE			(0x01)
+
+#define IIC_DVFS_BIT_ICCR_ENABLE		(0x80)
+#define IIC_DVFS_SET_ICCR_START			(0x94)
+#define IIC_DVFS_SET_ICCR_STOP			(0x90)
+#define	IIC_DVFS_SET_ICCR_RETRANSMISSION	(0x94)
+#define	IIC_DVFS_SET_ICCR_CHANGE		(0x81)
+#define	IIC_DVFS_SET_ICCR_STOP_READ		(0xC0)
+
+#define IIC_DVFS_BIT_ICIC_TACKE			(0x04)
+#define IIC_DVFS_BIT_ICIC_WAITE			(0x02)
+#define IIC_DVFS_BIT_ICIC_DTEE			(0x01)
+
+#define	DVFS_READ_MODE				(0x01)
+#define	DVFS_WRITE_MODE				(0x00)
+
+#define IIC_DVFS_SET_DUMMY			(0x52)
+#define IIC_DVFS_SET_BUSY_LOOP			(500000000U)
+
+typedef enum {
+	DVFS_START = 0,
+	DVFS_STOP,
+	DVFS_RETRANSMIT,
+	DVFS_READ,
+	DVFS_STOP_READ,
+	DVFS_SET_SLAVE_READ,
+	DVFS_SET_SLAVE,
+	DVFS_WRITE_ADDR,
+	DVFS_WRITE_DATA,
+	DVFS_CHANGE_SEND_TO_RECIEVE,
+	DVFS_DONE,
+} DVFS_STATE_T;
+
+#define DVFS_PROCESS			(1)
+#define DVFS_COMPLETE			(0)
+#define DVFS_ERROR			(-1)
+
+#if IMAGE_BL31
+#define IIC_DVFS_FUNC(__name, ...)					\
+static int32_t 	__attribute__ ((section (".system_ram")))		\
+dvfs_ ##__name(__VA_ARGS__)
+
+#define RCAR_DVFS_API(__name, ...)					\
+int32_t __attribute__ ((section (".system_ram"))) 			\
+rcar_iic_dvfs_ ##__name(__VA_ARGS__)
+
+#else
+#define IIC_DVFS_FUNC(__name, ...) 					\
+static int32_t dvfs_ ##__name(__VA_ARGS__)
+
+#define RCAR_DVFS_API(__name, ...)					\
+int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
+#endif
+
+IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
+{
+	uint8_t icsr_al = 0, icsr_tack = 0;
+	uint8_t reg, stop;
+	uint32_t i = 0;
+
+	stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
+	    IIC_DVFS_SET_ICCR_STOP;
+
+	reg = mmio_read_8(IIC_DVFS_REG_ICSR);
+	icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
+	icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
+
+	if (icsr_al == 0 && icsr_tack == 0)
+		return DVFS_PROCESS;
+
+	if (icsr_al) {
+		reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
+		mmio_write_8(IIC_DVFS_REG_ICSR, reg);
+
+		if (*state == DVFS_SET_SLAVE)
+			mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
+
+		do {
+			reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
+			    IIC_DVFS_BIT_ICSR_WAIT;
+		} while (reg == 0);
+
+		mmio_write_8(IIC_DVFS_REG_ICCR, stop);
+
+		reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+		mmio_write_8(IIC_DVFS_REG_ICSR, reg);
+
+		i = 0;
+		do {
+			reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
+			    IIC_DVFS_BIT_ICSR_BUSY;
+			if (reg == 0)
+				break;
+
+			if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+				panic();
+
+		} while (1);
+
+		mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
+
+		(*err)++;
+		if (*err > DVFS_RETRY_MAX)
+			return DVFS_ERROR;
+
+		*state = DVFS_START;
+
+		return DVFS_PROCESS;
+
+	}
+
+	/* icsr_tack */
+	mmio_write_8(IIC_DVFS_REG_ICCR, stop);
+
+	reg = mmio_read_8(IIC_DVFS_REG_ICIC);
+	reg &= ~(IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE);
+	mmio_write_8(IIC_DVFS_REG_ICIC, reg);
+
+	reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
+	mmio_write_8(IIC_DVFS_REG_ICSR, reg);
+
+	i = 0;
+	while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0) {
+		if (i++ > IIC_DVFS_SET_BUSY_LOOP)
+			panic();
+	}
+
+	mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+	(*err)++;
+
+	if (*err > DVFS_RETRY_MAX)
+		return DVFS_ERROR;
+
+	*state = DVFS_START;
+
+	return DVFS_PROCESS;
+}
+
+IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
+{
+	uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
+	uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
+	int32_t result = DVFS_PROCESS;
+	uint32_t reg, lsi_product;
+	uint8_t mode;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
+	mmio_write_8(IIC_DVFS_REG_ICCR, mode);
+
+	lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+	if (lsi_product == RCAR_PRODUCT_E3)
+		goto start;
+
+	reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
+	switch (reg) {
+	case MD14_MD13_TYPE_0:
+		iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_0;
+		icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_0;
+		break;
+	case MD14_MD13_TYPE_1:
+		iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_1;
+		icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_1;
+		break;
+	case MD14_MD13_TYPE_2:
+		iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_2;
+		icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_2;
+		break;
+	default:
+		iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_3;
+		icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_3;
+		break;
+	}
+start:
+	mmio_write_8(IIC_DVFS_REG_ICCL, iccl);
+	mmio_write_8(IIC_DVFS_REG_ICCH, icch);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICIC)
+	    | IIC_DVFS_BIT_ICIC_TACKE
+	    | IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE;
+
+	mmio_write_8(IIC_DVFS_REG_ICIC, mode);
+	mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_START);
+
+	*state = DVFS_SET_SLAVE;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
+{
+	uint8_t mode;
+	int32_t result;
+	uint8_t address;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
+	if (mode != IIC_DVFS_BIT_ICSR_DTE)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
+	mmio_write_8(IIC_DVFS_REG_ICIC, mode);
+
+	address = slave << 1;
+	mmio_write_8(IIC_DVFS_REG_ICDR, address);
+
+	*state = DVFS_WRITE_ADDR;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
+{
+	uint8_t mode;
+	int32_t result;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
+	if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+		return result;
+
+	mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+	mmio_write_8(IIC_DVFS_REG_ICSR, mode);
+
+	*state = DVFS_WRITE_DATA;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
+{
+	int32_t result;
+	uint8_t mode;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
+	if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+		return result;
+
+	mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+	mmio_write_8(IIC_DVFS_REG_ICSR, mode);
+
+	*state = DVFS_STOP;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(stop, DVFS_STATE_T *state, uint32_t *err)
+{
+	int32_t result;
+	uint8_t mode;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
+	if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+		return result;
+
+	mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+	mmio_write_8(IIC_DVFS_REG_ICSR, mode);
+
+	*state = DVFS_DONE;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(done, void)
+{
+	uint32_t i;
+
+	for (i = 0; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
+		if (mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY)
+			continue;
+		goto done;
+	}
+
+	panic();
+done:
+	mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+
+	return DVFS_COMPLETE;
+}
+
+IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
+	uint8_t reg_addr)
+{
+	int32_t result;
+	uint8_t mode;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
+	if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+		return result;
+
+	mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+	mmio_write_8(IIC_DVFS_REG_ICSR, mode);
+
+	*state = DVFS_RETRANSMIT;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
+{
+	int32_t result;
+	uint8_t mode;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
+	if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+		return result;
+
+	mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+	mmio_write_8(IIC_DVFS_REG_ICSR, mode);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
+	mmio_write_8(IIC_DVFS_REG_ICIC, mode);
+
+	*state = DVFS_SET_SLAVE_READ;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
+		uint8_t slave)
+{
+	uint8_t address;
+	int32_t result;
+	uint8_t mode;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
+	if (mode != IIC_DVFS_BIT_ICSR_DTE)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
+	mmio_write_8(IIC_DVFS_REG_ICIC, mode);
+
+	address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
+	mmio_write_8(IIC_DVFS_REG_ICDR, address);
+
+	*state = DVFS_CHANGE_SEND_TO_RECIEVE;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
+{
+	int32_t result;
+	uint8_t mode;
+
+	result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
+	if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+		return result;
+
+	mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+	mmio_write_8(IIC_DVFS_REG_ICSR, mode);
+
+	*state = DVFS_STOP_READ;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
+{
+	int32_t result;
+	uint8_t mode;
+
+	result = dvfs_check_error(state, err, DVFS_READ_MODE);
+	if (result == DVFS_ERROR)
+		return result;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
+	if (mode != IIC_DVFS_BIT_ICSR_WAIT)
+		return result;
+
+	mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
+	mmio_write_8(IIC_DVFS_REG_ICSR, mode);
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
+	mmio_write_8(IIC_DVFS_REG_ICIC, mode);
+
+	*state = DVFS_READ;
+
+	return result;
+}
+
+IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
+{
+	uint8_t mode;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
+	if (mode != IIC_DVFS_BIT_ICSR_DTE)
+		return DVFS_PROCESS;
+
+	mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
+	mmio_write_8(IIC_DVFS_REG_ICIC, mode);
+
+	*reg_data = mmio_read_8(IIC_DVFS_REG_ICDR);
+	*state = DVFS_DONE;
+
+	return DVFS_PROCESS;
+}
+
+RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
+{
+	DVFS_STATE_T state = DVFS_START;
+	int32_t result = DVFS_PROCESS;
+	uint32_t err = 0;
+
+	mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
+	mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+again:
+	switch (state) {
+	case DVFS_START:
+		result = dvfs_start(&state);
+		break;
+	case DVFS_SET_SLAVE:
+		result = dvfs_set_slave(&state, &err, slave);
+		break;
+	case DVFS_WRITE_ADDR:
+		result = dvfs_write_addr(&state, &err, reg_addr);
+		break;
+	case DVFS_WRITE_DATA:
+		result = dvfs_write_data(&state, &err, reg_data);
+		break;
+	case DVFS_STOP:
+		result = dvfs_stop(&state, &err);
+		break;
+	case DVFS_DONE:
+		result = dvfs_done();
+		break;
+	default:
+		panic();
+		break;
+	}
+
+	if (result == DVFS_PROCESS)
+		goto again;
+
+	return result;
+}
+
+RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
+{
+	DVFS_STATE_T state = DVFS_START;
+	int32_t result = DVFS_PROCESS;
+	uint32_t err = 0;
+
+	mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
+	mmio_write_8(IIC_DVFS_REG_ICCR, 0);
+again:
+	switch (state) {
+	case DVFS_START:
+		result = dvfs_start(&state);
+		break;
+	case DVFS_SET_SLAVE:
+		result = dvfs_set_slave(&state, &err, slave);
+		break;
+	case DVFS_WRITE_ADDR:
+		result = dvfs_write_reg_addr_read(&state, &err, reg);
+		break;
+	case DVFS_RETRANSMIT:
+		result = dvfs_retransmit(&state, &err);
+		break;
+	case DVFS_SET_SLAVE_READ:
+		result = dvfs_set_slave_read(&state, &err, slave);
+		break;
+	case DVFS_CHANGE_SEND_TO_RECIEVE:
+		result = dvfs_change_send_to_recieve(&state, &err);
+		break;
+	case DVFS_STOP_READ:
+		result = dvfs_stop_read(&state, &err);
+		break;
+	case DVFS_READ:
+		result = dvfs_read(&state, data);
+		break;
+	case DVFS_DONE:
+		result = dvfs_done();
+		break;
+	default:
+		panic();
+		break;
+	}
+
+	if (result == DVFS_PROCESS)
+		goto again;
+
+	return result;
+}
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
new file mode 100644
index 0000000..3c4a9a5
--- /dev/null
+++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IIC_DVFS_H__
+#define IIC_DVFS_H__
+
+/* PMIC slave */
+#define PMIC			(0x30)
+#define	BKUP_MODE_CNT		(0x20)
+#define	DVFS_SET_VID		(0x54)
+#define	REG_KEEP10		(0x79)
+
+/* EEPROM slave */
+#define EEPROM			(0x50)
+#define	BOARD_ID		(0x70)
+
+int32_t rcar_iic_dvfs_receive(uint8_t slave, uint8_t reg, uint8_t *data);
+int32_t rcar_iic_dvfs_send(uint8_t slave, uint8_t regr, uint8_t data);
+
+#endif
diff --git a/drivers/renesas/rcar/io/io_common.h b/drivers/renesas/rcar/io/io_common.h
new file mode 100644
index 0000000..c5729b8
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_common.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_COMMON_H__
+#define IO_COMMON_H__
+
+typedef struct io_drv_spec {
+	size_t offset;
+	size_t length;
+	uint32_t partition;
+} io_drv_spec_t;
+
+#endif
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.c b/drivers/renesas/rcar/io/io_emmcdrv.c
new file mode 100644
index 0000000..f74bd5f
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_emmcdrv.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <io_driver.h>
+#include <io_storage.h>
+#include <string.h>
+
+#include "io_common.h"
+#include "io_emmcdrv.h"
+#include "io_private.h"
+#include "emmc_config.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+#include "emmc_def.h"
+
+static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
+				io_dev_info_t **dev_info);
+static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info);
+
+typedef struct {
+	uint32_t in_use;
+	uintptr_t base;
+	ssize_t file_pos;
+	EMMC_PARTITION_ID partition;
+} file_state_t;
+
+static file_state_t current_file = { 0 };
+
+static EMMC_PARTITION_ID emmcdrv_bootpartition = PARTITION_ID_USER;
+
+static io_type_t device_type_emmcdrv(void)
+{
+	return IO_TYPE_MEMMAP;
+}
+
+static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode,
+				  ssize_t offset)
+{
+	if (mode != IO_SEEK_SET)
+		return IO_FAIL;
+
+	((file_state_t *) entity->info)->file_pos = offset;
+
+	return IO_SUCCESS;
+}
+
+static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer,
+				  size_t length, size_t *length_read)
+{
+	file_state_t *fp = (file_state_t *) entity->info;
+	uint32_t sector_add, sector_num, emmc_dma = 0;
+	int32_t result = IO_SUCCESS;
+
+	sector_add = current_file.file_pos >> EMMC_SECTOR_SIZE_SHIFT;
+	sector_num = (length + EMMC_SECTOR_SIZE - 1U) >> EMMC_SECTOR_SIZE_SHIFT;
+
+	NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%lx(%d) len=0x%lx(%d)\n",
+	       buffer,
+	       current_file.partition, current_file.file_pos,
+	       sector_add, length, sector_num);
+
+	if (buffer + length - 1 <= UINT32_MAX)
+		emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE;
+
+	if (emmc_read_sector((uint32_t *) buffer, sector_add, sector_num,
+			     emmc_dma) != EMMC_SUCCESS)
+		result = IO_FAIL;
+
+	*length_read = length;
+	fp->file_pos += length;
+
+	return result;
+}
+
+static int32_t emmcdrv_block_open(io_dev_info_t *dev_info,
+				  const uintptr_t spec, io_entity_t *entity)
+{
+	const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec;
+
+	if (current_file.in_use) {
+		WARN("mmc_block: Only one open spec at a time\n");
+		return IO_RESOURCES_EXHAUSTED;
+	}
+
+	current_file.file_pos = 0;
+	current_file.in_use = 1;
+
+	if (emmcdrv_bootpartition == PARTITION_ID_USER) {
+		emmcdrv_bootpartition = mmc_drv_obj.boot_partition_en;
+		if ((PARTITION_ID_BOOT_1 == emmcdrv_bootpartition) ||
+		    (PARTITION_ID_BOOT_2 == emmcdrv_bootpartition)) {
+			current_file.partition = emmcdrv_bootpartition;
+
+			NOTICE("BL2: eMMC boot from partition %d\n",
+			       emmcdrv_bootpartition);
+			goto done;
+		}
+		return IO_FAIL;
+	}
+
+	if (PARTITION_ID_USER == block_spec->partition ||
+	    PARTITION_ID_BOOT_1 == block_spec->partition ||
+	    PARTITION_ID_BOOT_2 == block_spec->partition)
+		current_file.partition = block_spec->partition;
+	else
+		current_file.partition = emmcdrv_bootpartition;
+
+done:
+	if (emmc_select_partition(current_file.partition) != EMMC_SUCCESS)
+		return IO_FAIL;
+
+	entity->info = (uintptr_t) &current_file;
+
+	return IO_SUCCESS;
+}
+
+static int32_t emmcdrv_block_close(io_entity_t *entity)
+{
+	memset((void *)&current_file, 0, sizeof(current_file));
+	entity->info = 0U;
+
+	return IO_SUCCESS;
+}
+
+static const io_dev_funcs_t emmcdrv_dev_funcs = {
+	.type = &device_type_emmcdrv,
+	.open = &emmcdrv_block_open,
+	.seek = &emmcdrv_block_seek,
+	.size = NULL,
+	.read = &emmcdrv_block_read,
+	.write = NULL,
+	.close = &emmcdrv_block_close,
+	.dev_init = NULL,
+	.dev_close = &emmcdrv_dev_close
+};
+
+static const io_dev_info_t emmcdrv_dev_info = {
+	.funcs = &emmcdrv_dev_funcs,
+	.info = (uintptr_t) 0
+};
+
+static const io_dev_connector_t emmcdrv_dev_connector = {
+	&emmcdrv_dev_open,
+};
+
+static int32_t emmcdrv_dev_open(const uintptr_t spec __attribute__ ((unused)),
+				io_dev_info_t **dev_info)
+{
+	*dev_info = (io_dev_info_t *) &emmcdrv_dev_info;
+
+	return IO_SUCCESS;
+}
+
+static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info)
+{
+	return IO_SUCCESS;
+}
+
+int32_t rcar_register_io_dev_emmcdrv(const io_dev_connector_t **dev_con)
+{
+	int32_t rc;
+
+	rc = io_register_device(&emmcdrv_dev_info);
+	if (rc == IO_SUCCESS)
+		*dev_con = &emmcdrv_dev_connector;
+
+	return rc;
+}
diff --git a/drivers/renesas/rcar/io/io_emmcdrv.h b/drivers/renesas/rcar/io/io_emmcdrv.h
new file mode 100644
index 0000000..82c6c51
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_emmcdrv.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_EMMCDRV_H__
+#define IO_EMMCDRV_H__
+
+struct io_dev_connector;
+int32_t rcar_register_io_dev_emmcdrv(const io_dev_connector_t **connector);
+
+#endif
diff --git a/drivers/renesas/rcar/io/io_memdrv.c b/drivers/renesas/rcar/io/io_memdrv.c
new file mode 100644
index 0000000..e55fd64
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_memdrv.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <io_driver.h>
+#include <io_storage.h>
+#include <string.h>
+
+#include "io_common.h"
+#include "io_private.h"
+#include "io_memdrv.h"
+#include "rcar_def.h"
+
+extern void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len);
+
+static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)),
+			       io_dev_info_t **dev_info);
+static int32_t memdrv_dev_close(io_dev_info_t *dev_info);
+
+/* As we need to be able to keep state for seek, only one file can be open
+ * at a time. Make this a structure and point to the entity->info. When we
+ * can malloc memory we can change this to support more open files.
+ */
+typedef struct {
+	uint32_t in_use;
+	uintptr_t base;
+	ssize_t file_pos;
+} file_state_t;
+
+static file_state_t current_file = { 0 };
+
+static io_type_t device_type_memdrv(void)
+{
+	return IO_TYPE_MEMMAP;
+}
+
+static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
+				 io_entity_t *entity)
+{
+	const io_drv_spec_t *block_spec = (io_drv_spec_t *) spec;
+
+	/* Since we need to track open state for seek() we only allow one open
+	 * spec at a time. When we have dynamic memory we can malloc and set
+	 * entity->info.
+	 */
+	if (current_file.in_use)
+		return IO_RESOURCES_EXHAUSTED;
+
+	/* File cursor offset for seek and incremental reads etc. */
+	current_file.base = block_spec->offset;
+	current_file.file_pos = 0;
+	current_file.in_use = 1;
+
+	entity->info = (uintptr_t) &current_file;
+
+	return IO_SUCCESS;
+}
+
+static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode,
+				 ssize_t offset)
+{
+	if (mode != IO_SEEK_SET)
+		return IO_FAIL;
+
+	((file_state_t *) entity->info)->file_pos = offset;
+
+	return IO_SUCCESS;
+}
+
+static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer,
+				 size_t length, size_t *cnt)
+{
+	file_state_t *fp;
+
+	fp = (file_state_t *) entity->info;
+
+	NOTICE("BL2: dst=0x%lx src=0x%lx len=%ld(0x%lx)\n",
+	       buffer, fp->base + fp->file_pos, length, length);
+
+	if (FLASH_MEMORY_SIZE < fp->file_pos + length) {
+		ERROR("BL2: check load image (source address)\n");
+		return IO_FAIL;
+	}
+
+	rcar_dma_exec(buffer, fp->base + fp->file_pos, length);
+	fp->file_pos += length;
+	*cnt = length;
+
+	return IO_SUCCESS;
+}
+
+static int32_t memdrv_block_close(io_entity_t *entity)
+{
+	entity->info = 0U;
+
+	memset((void *)&current_file, 0, sizeof(current_file));
+
+	return IO_SUCCESS;
+}
+
+static const io_dev_funcs_t memdrv_dev_funcs = {
+	.type = &device_type_memdrv,
+	.open = &memdrv_block_open,
+	.seek = &memdrv_block_seek,
+	.size = NULL,
+	.read = &memdrv_block_read,
+	.write = NULL,
+	.close = &memdrv_block_close,
+	.dev_init = NULL,
+	.dev_close = &memdrv_dev_close,
+};
+
+static const io_dev_info_t memdrv_dev_info = {
+	.funcs = &memdrv_dev_funcs,
+	.info = 0,
+};
+
+static const io_dev_connector_t memdrv_dev_connector = {
+	.dev_open = &memdrv_dev_open
+};
+
+static int32_t memdrv_dev_open(const uintptr_t dev __attribute__ ((unused)),
+			       io_dev_info_t **dev_info)
+{
+	*dev_info = (io_dev_info_t *) &memdrv_dev_info;
+
+	return IO_SUCCESS;
+}
+
+static int32_t memdrv_dev_close(io_dev_info_t *dev_info)
+{
+	return IO_SUCCESS;
+}
+
+int32_t rcar_register_io_dev_memdrv(const io_dev_connector_t **dev_con)
+{
+	int32_t result;
+
+	result = io_register_device(&memdrv_dev_info);
+	if (result == IO_SUCCESS)
+		*dev_con = &memdrv_dev_connector;
+
+	return result;
+}
diff --git a/drivers/renesas/rcar/io/io_memdrv.h b/drivers/renesas/rcar/io/io_memdrv.h
new file mode 100644
index 0000000..41727d3
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_memdrv.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_MEMDRV_H__
+#define IO_MEMDRV_H__
+
+struct io_dev_connector;
+int32_t rcar_register_io_dev_memdrv(const io_dev_connector_t **connector);
+
+#endif
diff --git a/drivers/renesas/rcar/io/io_private.h b/drivers/renesas/rcar/io/io_private.h
new file mode 100644
index 0000000..d0e66c0
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_private.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_PRIVATE_H_
+#define IO_PRIVATE_H_
+
+/*
+ * Return codes reported by 'io_*' APIs
+ * The value of fail should not overlap with define of the errno.
+ * The errno is in "include/lib/stdlib/sys/errno.h".
+ */
+#define IO_SUCCESS		(0)
+#define IO_FAIL			(-0x81)
+#define IO_NOT_SUPPORTED	(-0x82)
+#define IO_RESOURCES_EXHAUSTED	(-0x83)
+
+#endif
diff --git a/drivers/renesas/rcar/io/io_rcar.c b/drivers/renesas/rcar/io/io_rcar.c
new file mode 100644
index 0000000..4293c51
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_rcar.c
@@ -0,0 +1,640 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <auth_mod.h>
+#include <bl_common.h>
+#include <debug.h>
+#include <errno.h>
+#include <firmware_image_package.h>
+#include <io_driver.h>
+#include <io_storage.h>
+#include <platform.h>
+#include <platform_def.h>
+#include <stdint.h>
+#include <string.h>
+#include <uuid.h>
+#include <mmio.h>
+#include <arch_helpers.h>
+#include "io_rcar.h"
+#include "io_common.h"
+#include "io_private.h"
+extern int32_t plat_get_drv_source(uint32_t id, uintptr_t *dev,
+				   uintptr_t *image_spec);
+
+extern int auth_mod_verify_img(unsigned int img_id, void *ptr,
+				unsigned int len);
+
+static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__ ((unused)),
+			     io_dev_info_t **dev_info);
+static int32_t rcar_dev_close(io_dev_info_t *dev_info);
+
+typedef struct {
+	const int32_t name;
+	const uint32_t offset;
+	const uint32_t attr;
+} plat_rcar_name_offset_t;
+
+typedef struct {
+	/* Put position above the struct to allow {0} on static init.
+	 * It is a workaround for a known bug in GCC
+	 * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
+	 */
+	uint32_t position;
+	uint32_t no_load;
+	uintptr_t offset;
+	uint32_t size;
+	uintptr_t dst;
+	uintptr_t partition;	/* for eMMC */
+	/* RCAR_EMMC_PARTITION_BOOT_0 */
+	/* RCAR_EMMC_PARTITION_BOOT_1 */
+	/* RCAR_EMMC_PARTITION_USER   */
+} file_state_t;
+
+#define RCAR_GET_FLASH_ADR(a, b)	((uint32_t)((0x40000U * (a)) + (b)))
+#define RCAR_ATTR_SET_CALCADDR(a)	((a) & 0xF)
+#define RCAR_ATTR_SET_ISNOLOAD(a)	(((a) & 0x1) << 16U)
+#define RCAR_ATTR_SET_CERTOFF(a)	(((a) & 0xF) << 8U)
+#define RCAR_ATTR_SET_ALL(a, b, c)	((uint32_t)(RCAR_ATTR_SET_CALCADDR(a) |\
+					RCAR_ATTR_SET_ISNOLOAD(b) | 	\
+					RCAR_ATTR_SET_CERTOFF(c)))
+
+#define RCAR_ATTR_GET_CALCADDR(a)	((a) & 0xFU)
+#define RCAR_ATTR_GET_ISNOLOAD(a)	(((a) >> 16) & 0x1U)
+#define RCAR_ATTR_GET_CERTOFF(a)	((uint32_t)(((a) >> 8) & 0xFU))
+
+#define RCAR_MAX_BL3X_IMAGE		(8U)
+#define RCAR_SECTOR6_CERT_OFFSET	(0x400U)
+#define RCAR_SDRAM_certESS		(0x43F00000U)
+#define RCAR_CERT_SIZE			(0x800U)
+#define RCAR_CERT_INFO_SIZE_OFFSET	(0x264U)
+#define RCAR_CERT_INFO_DST_OFFSET	(0x154U)
+#define RCAR_CERT_INFO_SIZE_OFFSET1	(0x364U)
+#define RCAR_CERT_INFO_DST_OFFSET1	(0x1D4U)
+#define RCAR_CERT_INFO_SIZE_OFFSET2	(0x464U)
+#define RCAR_CERT_INFO_DST_OFFSET2	(0x254U)
+#define RCAR_CERT_LOAD			(1U)
+
+#define RCAR_FLASH_CERT_HEADER		RCAR_GET_FLASH_ADR(6U, 0U)
+#define RCAR_EMMC_CERT_HEADER		(0x00030000U)
+
+#define RCAR_COUNT_LOAD_BL33		(2U)
+#define RCAR_COUNT_LOAD_BL33X		(3U)
+
+static const plat_rcar_name_offset_t name_offset[] = {
+	{BL31_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(0, 0, 0)},
+
+	/* BL3-2 is optional in the platform */
+	{BL32_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(1, 0, 1)},
+	{BL33_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(2, 0, 2)},
+	{BL332_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(3, 0, 3)},
+	{BL333_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(4, 0, 4)},
+	{BL334_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(5, 0, 5)},
+	{BL335_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(6, 0, 6)},
+	{BL336_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(7, 0, 7)},
+	{BL337_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(8, 0, 8)},
+	{BL338_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(9, 0, 9)},
+};
+
+#if TRUSTED_BOARD_BOOT
+static const plat_rcar_name_offset_t cert_offset[] = {
+	/* Certificates */
+	{TRUSTED_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 0)},
+	{SOC_FW_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 0)},
+	{TRUSTED_OS_FW_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 0)},
+	{NON_TRUSTED_FW_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 0)},
+	{SOC_FW_CONTENT_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 0)},
+	{TRUSTED_OS_FW_CONTENT_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 1)},
+	{NON_TRUSTED_FW_CONTENT_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 2)},
+	{BL332_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 3)},
+	{BL333_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 4)},
+	{BL334_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 5)},
+	{BL335_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 6)},
+	{BL336_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 7)},
+	{BL337_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 8)},
+	{BL338_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0, 1, 9)},
+};
+#endif /* TRUSTED_BOARD_BOOT */
+
+static file_state_t current_file = { 0 };
+
+static uintptr_t rcar_handle, rcar_spec;
+static uint64_t rcar_image_header[RCAR_MAX_BL3X_IMAGE + 2U] = { 0U };
+static uint64_t rcar_image_header_prttn[RCAR_MAX_BL3X_IMAGE + 2U] = { 0U };
+static uint64_t rcar_image_number = { 0U };
+static uint32_t rcar_cert_load = { 0U };
+
+static io_type_t device_type_rcar(void)
+{
+	return IO_TYPE_FIRMWARE_IMAGE_PACKAGE;
+}
+
+int32_t rcar_get_certificate(const int32_t name, uint32_t *cert)
+{
+#if TRUSTED_BOARD_BOOT
+	int32_t i;
+	for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
+		if (name != cert_offset[i].name)
+			continue;
+
+		*cert = RCAR_CERT_SIZE;
+		*cert *= RCAR_ATTR_GET_CERTOFF(cert_offset[i].attr);
+		*cert += RCAR_SDRAM_certESS;
+		return 0;
+	}
+#endif
+	return -EINVAL;
+}
+
+static int32_t file_to_offset(const int32_t name, uintptr_t *offset,
+			      uint32_t *cert, uint32_t *no_load,
+			      uintptr_t *partition)
+{
+	uint32_t addr;
+	int32_t i;
+
+	for (i = 0; i < ARRAY_SIZE(name_offset); i++) {
+		if (name != name_offset[i].name)
+			continue;
+
+		addr = RCAR_ATTR_GET_CALCADDR(name_offset[i].attr);
+		if (rcar_image_number + 2 < addr)
+			continue;
+
+		*offset = rcar_image_header[addr];
+		*cert = RCAR_CERT_SIZE;
+		*cert *= RCAR_ATTR_GET_CERTOFF(name_offset[i].attr);
+		*cert += RCAR_SDRAM_certESS;
+		*no_load = RCAR_ATTR_GET_ISNOLOAD(name_offset[i].attr);
+		*partition = rcar_image_header_prttn[addr];
+		return IO_SUCCESS;
+	}
+
+#if TRUSTED_BOARD_BOOT
+	for (i = 0; i < ARRAY_SIZE(cert_offset); i++) {
+		if (name != cert_offset[i].name)
+			continue;
+
+		*no_load = RCAR_ATTR_GET_ISNOLOAD(cert_offset[i].attr);
+		*partition = 0U;
+		*offset = 0U;
+		*cert = 0U;
+		return IO_SUCCESS;
+	}
+#endif
+	return -EINVAL;
+}
+
+#define RCAR_BOOT_KEY_CERT_NEW	(0xE6300F00U)
+#define	RCAR_CERT_MAGIC_NUM	(0xE291F358U)
+
+void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *dst)
+{
+	uint32_t seed, val, info_1, info_2;
+	uintptr_t size, dsth, dstl;
+
+	cert &= 0xFFFFFFFFU;
+
+	seed = mmio_read_32(RCAR_BOOT_KEY_CERT_NEW);
+	val = mmio_read_32(RCAR_BOOT_KEY_CERT_NEW + 0xC);
+	info_1 = (val >> 18) & 0x3U;
+	val = mmio_read_32(cert + 0xC);
+	info_2 = (val >> 21) & 0x3;
+
+	if (seed == RCAR_CERT_MAGIC_NUM) {
+		if (info_1 != 1) {
+			ERROR("BL2: Cert is invalid.\n");
+			*dst = 0;
+			*len = 0;
+			return;
+		}
+
+		if (info_2 > 2) {
+			ERROR("BL2: Cert is invalid.\n");
+			*dst = 0;
+			*len = 0;
+			return;
+		}
+
+		switch (info_2) {
+		case 2:
+			size = cert + RCAR_CERT_INFO_SIZE_OFFSET2;
+			dstl = cert + RCAR_CERT_INFO_DST_OFFSET2;
+			break;
+		case 1:
+			size = cert + RCAR_CERT_INFO_SIZE_OFFSET1;
+			dstl = cert + RCAR_CERT_INFO_DST_OFFSET1;
+			break;
+		case 0:
+			size = cert + RCAR_CERT_INFO_SIZE_OFFSET;
+			dstl = cert + RCAR_CERT_INFO_DST_OFFSET;
+			break;
+		}
+
+		*len = mmio_read_32(size) * 4U;
+		dsth = dstl + 4U;
+		*dst = ((uintptr_t) mmio_read_32(dsth) << 32) +
+		    ((uintptr_t) mmio_read_32(dstl));
+		return;
+	}
+
+	size = cert + RCAR_CERT_INFO_SIZE_OFFSET;
+	*len = mmio_read_32(size) * 4U;
+	dstl = cert + RCAR_CERT_INFO_DST_OFFSET;
+	dsth = dstl + 4U;
+	*dst = ((uintptr_t) mmio_read_32(dsth) << 32) +
+	    ((uintptr_t) mmio_read_32(dstl));
+}
+
+static int32_t check_load_area(uintptr_t dst, uintptr_t len)
+{
+	uint32_t legacy = dst + len <= UINT32_MAX - 1 ? 1 : 0;
+	uintptr_t dram_start, dram_end;
+	uintptr_t prot_start, prot_end;
+	int32_t result = IO_SUCCESS;
+
+	dram_start = legacy ? DRAM1_BASE : DRAM_40BIT_BASE;
+
+	dram_end = legacy ? DRAM1_BASE + DRAM1_SIZE :
+	    DRAM_40BIT_BASE + DRAM_40BIT_SIZE;
+
+	prot_start = legacy ? DRAM_PROTECTED_BASE : DRAM_40BIT_PROTECTED_BASE;
+
+	prot_end = prot_start + DRAM_PROTECTED_SIZE;
+
+	if (dst < dram_start || dst > dram_end - len) {
+		ERROR("BL2: dst address is on the protected area.\n");
+		result = IO_FAIL;
+		goto done;
+	}
+
+	/* load image is within SDRAM protected area */
+	if (dst >= prot_start && dst < prot_end) {
+		ERROR("BL2: dst address is on the protected area.\n");
+		result = IO_FAIL;
+	}
+
+	if (dst < prot_start && dst > prot_start - len) {
+		ERROR("BL2: loaded data is on the protected area.\n");
+		result = IO_FAIL;
+	}
+done:
+	if (result == IO_FAIL)
+		ERROR("BL2: Out of range : dst=0x%lx len=0x%lx\n", dst, len);
+
+	return result;
+}
+
+static int32_t load_bl33x(void)
+{
+	static int32_t loaded = IO_NOT_SUPPORTED;
+	uintptr_t dst, partition, handle;
+	uint32_t noload, cert, len, i;
+	uintptr_t offset;
+	int32_t rc;
+	size_t cnt;
+	const int32_t img[] = {
+		BL33_IMAGE_ID,
+		BL332_IMAGE_ID,
+		BL333_IMAGE_ID,
+		BL334_IMAGE_ID,
+		BL335_IMAGE_ID,
+		BL336_IMAGE_ID,
+		BL337_IMAGE_ID,
+		BL338_IMAGE_ID
+	};
+
+	if (loaded != IO_NOT_SUPPORTED)
+		return loaded;
+
+	for (i = 1; i < rcar_image_number; i++) {
+		rc = file_to_offset(img[i], &offset, &cert, &noload,
+				    &partition);
+		if (rc != IO_SUCCESS) {
+			WARN("load_bl33x: failed to get offset\n");
+			loaded = IO_FAIL;
+			return loaded;
+		}
+
+		rcar_read_certificate((uint64_t) cert, &len, &dst);
+		((io_drv_spec_t *) rcar_spec)->partition = partition;
+
+		rc = io_open(rcar_handle, rcar_spec, &handle);
+		if (rc != IO_SUCCESS) {
+			WARN("Failed to open FIP (%i)\n", rc);
+			loaded = IO_FAIL;
+			return loaded;
+		}
+
+		rc = io_seek(handle, IO_SEEK_SET, offset);
+		if (rc != IO_SUCCESS) {
+			WARN("load_bl33x: failed to seek\n");
+			loaded = IO_FAIL;
+			return loaded;
+		}
+
+		rc = check_load_area(dst, len);
+		if (rc != IO_SUCCESS) {
+			WARN("load_bl33x: check load area\n");
+			loaded = IO_FAIL;
+			return loaded;
+		}
+
+		rc = io_read(handle, dst, len, &cnt);
+		if (rc != IO_SUCCESS) {
+			WARN("load_bl33x: failed to read\n");
+			loaded = IO_FAIL;
+			return loaded;
+		}
+#if TRUSTED_BOARD_BOOT
+		rc = auth_mod_verify_img(img[i], (void *)dst, len);
+		if (rc) {
+			memset((void *)dst, 0x00, len);
+			loaded = IO_FAIL;
+			return loaded;
+		}
+#endif
+		io_close(handle);
+	}
+
+	loaded = IO_SUCCESS;
+
+	return loaded;
+}
+
+static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t name)
+{
+	uint64_t header[64] __aligned(FLASH_TRANS_SIZE_UNIT) = {
+	0};
+	uintptr_t handle;
+	ssize_t offset;
+	uint32_t i;
+	int32_t rc;
+	size_t cnt;
+
+	/* Obtain a reference to the image by querying the platform layer */
+	rc = plat_get_drv_source(name, &rcar_handle, &rcar_spec);
+	if (rc != IO_SUCCESS) {
+		WARN("Failed to obtain reference to img %ld (%i)\n", name, rc);
+		return IO_FAIL;
+	}
+
+	if (RCAR_CERT_LOAD == rcar_cert_load)
+		return IO_SUCCESS;
+
+	rc = io_open(rcar_handle, rcar_spec, &handle);
+	if (rc != IO_SUCCESS) {
+		WARN("Failed to access img %ld (%i)\n", name, rc);
+		return IO_FAIL;
+	}
+
+	/* get start address list   */
+	/* [0] address num          */
+	/* [1] BL33-1 image address */
+	/* [2] BL33-2 image address */
+	/* [3] BL33-3 image address */
+	/* [4] BL33-4 image address */
+	/* [5] BL33-5 image address */
+	/* [6] BL33-6 image address */
+	/* [7] BL33-7 image address */
+	/* [8] BL33-8 image address */
+	offset = name == EMMC_DEV_ID ? RCAR_EMMC_CERT_HEADER :
+	    RCAR_FLASH_CERT_HEADER;
+	rc = io_seek(handle, IO_SEEK_SET, offset);
+	if (rc != IO_SUCCESS) {
+		WARN("Firmware Image Package header failed to seek\n");
+		goto error;
+	}
+#if RCAR_BL2_DCACHE == 1
+	inv_dcache_range((uint64_t) header, sizeof(header));
+#endif
+	rc = io_read(handle, (uintptr_t) &header, sizeof(header), &cnt);
+	if (rc != IO_SUCCESS) {
+		WARN("Firmware Image Package header failed to read\n");
+		goto error;
+	}
+
+	rcar_image_number = header[0];
+	for (i = 0; i < rcar_image_number + 2; i++) {
+		rcar_image_header[i] = header[i * 2 + 1];
+		rcar_image_header_prttn[i] = header[i * 2 + 2];
+	}
+
+	if (rcar_image_number == 0 || rcar_image_number > RCAR_MAX_BL3X_IMAGE) {
+		WARN("Firmware Image Package header check failed.\n");
+		goto error;
+	}
+
+	rc = io_seek(handle, IO_SEEK_SET, offset + RCAR_SECTOR6_CERT_OFFSET);
+	if (rc != IO_SUCCESS) {
+		WARN("Firmware Image Package header failed to seek cert\n");
+		goto error;
+	}
+#if RCAR_BL2_DCACHE == 1
+	inv_dcache_range(RCAR_SDRAM_certESS,
+			 RCAR_CERT_SIZE * (2 + rcar_image_number));
+#endif
+	rc = io_read(handle, RCAR_SDRAM_certESS,
+		     RCAR_CERT_SIZE * (2 + rcar_image_number), &cnt);
+	if (rc != IO_SUCCESS) {
+		WARN("cert file read error.\n");
+		goto error;
+	}
+
+	rcar_cert_load = RCAR_CERT_LOAD;
+error:
+
+	if (rc != IO_SUCCESS)
+		rc = IO_FAIL;
+
+	io_close(handle);
+
+	return rc;
+
+}
+
+static int32_t rcar_file_open(io_dev_info_t *info, const uintptr_t file_spec,
+			      io_entity_t *entity)
+{
+	const io_drv_spec_t *spec = (io_drv_spec_t *) file_spec;
+	uintptr_t partition, offset, dst;
+	uint32_t noload, cert, len;
+	int32_t rc;
+
+	/* Only one file open at a time. We need to  track state (ie, file
+	 * cursor position). Since the header lives at * offset zero, this entry
+	 * should never be zero in an active file.
+	 * Once the system supports dynamic memory allocation we will allow more
+	 * than one open file at a time. */
+	if (current_file.offset != 0U) {
+		WARN("rcar_file_open : Only one open file at a time.\n");
+		return IO_RESOURCES_EXHAUSTED;
+	}
+
+	rc = file_to_offset(spec->offset, &offset, &cert, &noload, &partition);
+	if (rc != IO_SUCCESS) {
+		WARN("Failed to open file name %ld (%i)\n", spec->offset, rc);
+		return IO_FAIL;
+	}
+
+	if (noload) {
+		current_file.offset = 1;
+		current_file.dst = 0;
+		current_file.size = 1;
+		current_file.position = 0;
+		current_file.no_load = noload;
+		current_file.partition = 0;
+		entity->info = (uintptr_t) &current_file;
+
+		return IO_SUCCESS;
+	}
+
+	rcar_read_certificate((uint64_t) cert, &len, &dst);
+
+	/*----------------*
+	 * Baylibre: HACK *
+	 *----------------*/
+	if (BL31_IMAGE_ID == spec->offset && len < RCAR_TRUSTED_SRAM_SIZE) {
+		WARN("r-car ignoring the BL31 size from certificate,"
+		     "using RCAR_TRUSTED_SRAM_SIZE instead\n");
+		len = RCAR_TRUSTED_SRAM_SIZE;
+	}
+
+	current_file.partition = partition;
+	current_file.no_load = noload;
+	current_file.offset = offset;
+	current_file.position = 0;
+	current_file.size = len;
+	current_file.dst = dst;
+	entity->info = (uintptr_t) &current_file;
+
+	return IO_SUCCESS;
+}
+
+static int32_t rcar_file_len(io_entity_t *entity, size_t *length)
+{
+	*length = ((file_state_t *) entity->info)->size;
+
+	NOTICE("%s: len: 0x%08lx\n", __func__, *length);
+
+	return IO_SUCCESS;
+}
+
+static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer,
+			      size_t length, size_t *cnt)
+{
+	file_state_t *fp = (file_state_t *) entity->info;
+	ssize_t offset = fp->offset + fp->position;
+	uintptr_t handle;
+	int32_t rc;
+
+#ifdef SPD_NONE
+	static uint32_t load_bl33x_counter = 1;
+#else
+	static uint32_t load_bl33x_counter;
+#endif
+	if (current_file.no_load) {
+		*cnt = length;
+		return IO_SUCCESS;
+	}
+
+	((io_drv_spec_t *) rcar_spec)->partition = fp->partition;
+
+	rc = io_open(rcar_handle, rcar_spec, &handle);
+	if (rc != IO_SUCCESS) {
+		WARN("Failed to open FIP (%i)\n", rc);
+		return IO_FAIL;
+	}
+
+	rc = io_seek(handle, IO_SEEK_SET, offset);
+	if (rc != IO_SUCCESS) {
+		WARN("rcar_file_read: failed to seek\n");
+		goto error;
+	}
+
+	if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33) {
+		rc = check_load_area(buffer, length);
+		if (rc != IO_SUCCESS) {
+			WARN("rcar_file_read: load area err\n");
+			goto error;
+		}
+	}
+
+	rc = io_read(handle, buffer, length, cnt);
+	if (rc != IO_SUCCESS) {
+		WARN("Failed to read payload (%i)\n", rc);
+		goto error;
+	}
+
+	fp->position += *cnt;
+	io_close(handle);
+
+	load_bl33x_counter += 1;
+	if (load_bl33x_counter == RCAR_COUNT_LOAD_BL33X)
+		return load_bl33x();
+
+	return IO_SUCCESS;
+error:
+	io_close(handle);
+	return IO_FAIL;
+}
+
+static int32_t rcar_file_close(io_entity_t *entity)
+{
+	if (current_file.offset)
+		memset(&current_file, 0, sizeof(current_file));
+
+	entity->info = 0U;
+
+	return IO_SUCCESS;
+}
+
+static const io_dev_funcs_t rcar_dev_funcs = {
+	.type = &device_type_rcar,
+	.open = &rcar_file_open,
+	.seek = NULL,
+	.size = &rcar_file_len,
+	.read = &rcar_file_read,
+	.write = NULL,
+	.close = &rcar_file_close,
+	.dev_init = &rcar_dev_init,
+	.dev_close = &rcar_dev_close,
+};
+
+static const io_dev_info_t rcar_dev_info = {
+	.funcs = &rcar_dev_funcs,
+	.info = (uintptr_t) 0
+};
+
+static const io_dev_connector_t rcar_dev_connector = {
+	.dev_open = &rcar_dev_open
+};
+
+static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__ ((unused)),
+			     io_dev_info_t **dev_info)
+{
+	*dev_info = (io_dev_info_t *) &rcar_dev_info;
+
+	return IO_SUCCESS;
+}
+
+static int32_t rcar_dev_close(io_dev_info_t *dev_info)
+{
+	rcar_handle = 0;
+	rcar_spec = 0;
+
+	return IO_SUCCESS;
+}
+
+int32_t rcar_register_io_dev(const io_dev_connector_t **dev_con)
+{
+	int32_t result;
+
+	result = io_register_device(&rcar_dev_info);
+	if (result == IO_SUCCESS)
+		*dev_con = &rcar_dev_connector;
+
+	return result;
+}
diff --git a/drivers/renesas/rcar/io/io_rcar.h b/drivers/renesas/rcar/io/io_rcar.h
new file mode 100644
index 0000000..2420902
--- /dev/null
+++ b/drivers/renesas/rcar/io/io_rcar.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IO_RCAR_H__
+#define IO_RCAR_H__
+
+int32_t rcar_register_io_dev(const io_dev_connector_t **dev_con);
+int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
+void rcar_read_certificate(uint64_t cert, uint32_t *size, uintptr_t *dest);
+
+#endif
diff --git a/drivers/renesas/rcar/pwrc/call_sram.S b/drivers/renesas/rcar/pwrc/call_sram.S
new file mode 100644
index 0000000..7c96b7e
--- /dev/null
+++ b/drivers/renesas/rcar/pwrc/call_sram.S
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include "rcar_def.h"
+
+.global rcar_pwrc_switch_stack
+.global rcar_pwrc_save_generic_timer
+.global rcar_pwrc_restore_generic_timer
+
+#define OFFSET_SP_X9_X10	(0x00)
+#define OFFSET_CNTFID0		(0x10)
+#define OFFSET_CNTPCT_EL0	(0x18)
+#define OFFSET_TIMER_COUNT	(0x20)
+
+/*
+ * x0 : jump address,
+ * x1 : stack address,
+ * x2 : arg,
+ * x3 : stack address (temporary)
+ */
+func rcar_pwrc_switch_stack
+
+	/* lr to stack */
+	stp	x29, x30, [sp,#-16]
+
+	/* change stack pointer */
+	mov	x3, sp
+	mov	sp, x1
+
+	/* save stack pointer */
+	sub	sp, sp, #16
+	stp	x0, x3, [sp]
+
+	/* data synchronization barrier */
+	dsb	sy
+
+	/* jump to code */
+	mov	x1, x0
+	mov	x0, x2
+	blr	x1
+
+	/* load stack pointer */
+	ldp 	x0, x2, [sp,#0]
+
+	/* change stack pointer */
+	mov	sp, x2
+
+	/* return */
+	ldp	x29, x30, [sp,#-16]
+	ret
+endfunc rcar_pwrc_switch_stack
+
+/* x0 : stack pointer base address */
+func rcar_pwrc_save_generic_timer
+
+	stp	x9, x10, [x0, #OFFSET_SP_X9_X10]
+
+	/* save CNTFID0 and cntpct_el0 */
+	mov_imm	x10, (RCAR_CNTC_BASE + CNTFID_OFF)
+	ldr	x9, [x10]
+	mrs	x10, cntpct_el0
+	stp	x9, x10, [x0, #OFFSET_CNTFID0]
+
+	ldp	x9, x10, [x0, #OFFSET_SP_X9_X10]
+
+	ret
+endfunc rcar_pwrc_save_generic_timer
+
+/* x0 : Stack pointer base address */
+func rcar_pwrc_restore_generic_timer
+
+	stp	x9, x10, [x0, #OFFSET_SP_X9_X10]
+
+	/* restore CNTFID0 and cntpct_el0 */
+	ldr	x10, [x0, #OFFSET_CNTFID0]
+	mov_imm	x9, (RCAR_CNTC_BASE + CNTFID_OFF)
+	str	x10, [x9]
+	ldp	x9, x10, [x0, #OFFSET_CNTPCT_EL0]
+	add	x9, x9, x10
+	str	x9, [x0, #OFFSET_TIMER_COUNT]
+
+	ldp	x9, x10, [x0, #OFFSET_SP_X9_X10]
+
+	ret
+endfunc rcar_pwrc_restore_generic_timer
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
new file mode 100644
index 0000000..6dfc0b6
--- /dev/null
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -0,0 +1,790 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <bakery_lock.h>
+#include <debug.h>
+#include <mmio.h>
+#include <string.h>
+#include <xlat_tables_v2.h>
+#include "iic_dvfs.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "pwrc.h"
+
+/*
+ * Someday there will be a generic power controller api. At the moment each
+ * platform has its own pwrc so just exporting functions should be acceptable.
+ */
+RCAR_INSTANTIATE_LOCK
+
+#define	WUP_IRQ_SHIFT				(0U)
+#define	WUP_FIQ_SHIFT				(8U)
+#define	WUP_CSD_SHIFT				(16U)
+#define	BIT_SOFTRESET				(1U<<15)
+#define	BIT_CA53_SCU				(1U<<21)
+#define	BIT_CA57_SCU				(1U<<12)
+#define	REQ_RESUME				(1U<<1)
+#define	REQ_OFF					(1U<<0)
+#define	STATUS_PWRUP				(1U<<4)
+#define	STATUS_PWRDOWN				(1U<<0)
+#define	STATE_CA57_CPU				(27U)
+#define	STATE_CA53_CPU				(22U)
+#define	MODE_L2_DOWN				(0x00000002U)
+#define	CPU_PWR_OFF				(0x00000003U)
+#define	RCAR_PSTR_MASK				(0x00000003U)
+#define	ST_ALL_STANDBY				(0x00003333U)
+/* Suspend to ram	*/
+#define	DBSC4_REG_BASE				(0xE6790000U)
+#define	DBSC4_REG_DBSYSCNT0			(DBSC4_REG_BASE + 0x0100U)
+#define	DBSC4_REG_DBACEN			(DBSC4_REG_BASE + 0x0200U)
+#define	DBSC4_REG_DBCMD				(DBSC4_REG_BASE + 0x0208U)
+#define	DBSC4_REG_DBRFEN			(DBSC4_REG_BASE + 0x0204U)
+#define	DBSC4_REG_DBWAIT			(DBSC4_REG_BASE + 0x0210U)
+#define	DBSC4_REG_DBCALCNF			(DBSC4_REG_BASE + 0x0424U)
+#define	DBSC4_REG_DBPDLK0			(DBSC4_REG_BASE + 0x0620U)
+#define	DBSC4_REG_DBPDRGA0			(DBSC4_REG_BASE + 0x0624U)
+#define	DBSC4_REG_DBPDRGD0			(DBSC4_REG_BASE + 0x0628U)
+#define	DBSC4_REG_DBCAM0CTRL0			(DBSC4_REG_BASE + 0x0940U)
+#define	DBSC4_REG_DBCAM0STAT0			(DBSC4_REG_BASE + 0x0980U)
+#define	DBSC4_REG_DBCAM1STAT0			(DBSC4_REG_BASE + 0x0990U)
+#define	DBSC4_REG_DBCAM2STAT0			(DBSC4_REG_BASE + 0x09A0U)
+#define	DBSC4_REG_DBCAM3STAT0			(DBSC4_REG_BASE + 0x09B0U)
+#define	DBSC4_BIT_DBACEN_ACCEN			((uint32_t)(1U << 0))
+#define	DBSC4_BIT_DBRFEN_ARFEN			((uint32_t)(1U << 0))
+#define	DBSC4_BIT_DBCAMxSTAT0			(0x00000001U)
+#define	DBSC4_SET_DBCMD_OPC_PRE			(0x04000000U)
+#define	DBSC4_SET_DBCMD_OPC_SR			(0x0A000000U)
+#define	DBSC4_SET_DBCMD_OPC_PD			(0x08000000U)
+#define	DBSC4_SET_DBCMD_OPC_MRW			(0x0E000000U)
+#define	DBSC4_SET_DBCMD_CH_ALL			(0x00800000U)
+#define	DBSC4_SET_DBCMD_RANK_ALL		(0x00040000U)
+#define	DBSC4_SET_DBCMD_ARG_ALL			(0x00000010U)
+#define	DBSC4_SET_DBCMD_ARG_ENTER		(0x00000000U)
+#define	DBSC4_SET_DBCMD_ARG_MRW_ODTC		(0x00000B00U)
+#define	DBSC4_SET_DBSYSCNT0_WRITE_ENABLE	(0x00001234U)
+#define	DBSC4_SET_DBSYSCNT0_WRITE_DISABLE	(0x00000000U)
+#define	DBSC4_SET_DBPDLK0_PHY_ACCESS		(0x0000A55AU)
+#define	DBSC4_SET_DBPDRGA0_ACIOCR0		(0x0000001AU)
+#define	DBSC4_SET_DBPDRGD0_ACIOCR0		(0x33C03C11U)
+#define	DBSC4_SET_DBPDRGA0_DXCCR		(0x00000020U)
+#define	DBSC4_SET_DBPDRGD0_DXCCR		(0x00181006U)
+#define	DBSC4_SET_DBPDRGA0_PGCR1		(0x00000003U)
+#define	DBSC4_SET_DBPDRGD0_PGCR1		(0x0380C600U)
+#define	DBSC4_SET_DBPDRGA0_ACIOCR1		(0x0000001BU)
+#define	DBSC4_SET_DBPDRGD0_ACIOCR1		(0xAAAAAAAAU)
+#define	DBSC4_SET_DBPDRGA0_ACIOCR3		(0x0000001DU)
+#define	DBSC4_SET_DBPDRGD0_ACIOCR3		(0xAAAAAAAAU)
+#define	DBSC4_SET_DBPDRGA0_ACIOCR5		(0x0000001FU)
+#define	DBSC4_SET_DBPDRGD0_ACIOCR5		(0x000000AAU)
+#define	DBSC4_SET_DBPDRGA0_DX0GCR2		(0x000000A2U)
+#define	DBSC4_SET_DBPDRGD0_DX0GCR2		(0xAAAA0000U)
+#define	DBSC4_SET_DBPDRGA0_DX1GCR2		(0x000000C2U)
+#define	DBSC4_SET_DBPDRGD0_DX1GCR2		(0xAAAA0000U)
+#define	DBSC4_SET_DBPDRGA0_DX2GCR2		(0x000000E2U)
+#define	DBSC4_SET_DBPDRGD0_DX2GCR2		(0xAAAA0000U)
+#define	DBSC4_SET_DBPDRGA0_DX3GCR2		(0x00000102U)
+#define	DBSC4_SET_DBPDRGD0_DX3GCR2		(0xAAAA0000U)
+#define	DBSC4_SET_DBPDRGA0_ZQCR			(0x00000090U)
+#define	DBSC4_SET_DBPDRGD0_ZQCR_MD19_0		(0x04058904U)
+#define	DBSC4_SET_DBPDRGD0_ZQCR_MD19_1		(0x04058A04U)
+#define	DBSC4_SET_DBPDRGA0_DX0GCR0		(0x000000A0U)
+#define	DBSC4_SET_DBPDRGD0_DX0GCR0		(0x7C0002E5U)
+#define	DBSC4_SET_DBPDRGA0_DX1GCR0		(0x000000C0U)
+#define	DBSC4_SET_DBPDRGD0_DX1GCR0		(0x7C0002E5U)
+#define	DBSC4_SET_DBPDRGA0_DX2GCR0		(0x000000E0U)
+#define	DBSC4_SET_DBPDRGD0_DX2GCR0		(0x7C0002E5U)
+#define	DBSC4_SET_DBPDRGA0_DX3GCR0		(0x00000100U)
+#define	DBSC4_SET_DBPDRGD0_DX3GCR0		(0x7C0002E5U)
+#define	DBSC4_SET_DBPDRGA0_DX0GCR1		(0x000000A1U)
+#define	DBSC4_SET_DBPDRGD0_DX0GCR1		(0x55550000U)
+#define	DBSC4_SET_DBPDRGA0_DX1GCR1		(0x000000C1U)
+#define	DBSC4_SET_DBPDRGD0_DX1GCR1		(0x55550000U)
+#define	DBSC4_SET_DBPDRGA0_DX2GCR1		(0x000000E1U)
+#define	DBSC4_SET_DBPDRGD0_DX2GCR1		(0x55550000U)
+#define	DBSC4_SET_DBPDRGA0_DX3GCR1		(0x00000101U)
+#define	DBSC4_SET_DBPDRGD0_DX3GCR1		(0x55550000U)
+#define	DBSC4_SET_DBPDRGA0_DX0GCR3		(0x000000A3U)
+#define	DBSC4_SET_DBPDRGD0_DX0GCR3		(0x00008484U)
+#define	DBSC4_SET_DBPDRGA0_DX1GCR3		(0x000000C3U)
+#define	DBSC4_SET_DBPDRGD0_DX1GCR3		(0x00008484U)
+#define	DBSC4_SET_DBPDRGA0_DX2GCR3		(0x000000E3U)
+#define	DBSC4_SET_DBPDRGD0_DX2GCR3		(0x00008484U)
+#define	DBSC4_SET_DBPDRGA0_DX3GCR3		(0x00000103U)
+#define	DBSC4_SET_DBPDRGD0_DX3GCR3		(0x00008484U)
+#define	RST_BASE				(0xE6160000U)
+#define	RST_MODEMR				(RST_BASE + 0x0060U)
+#define	RST_MODEMR_BIT0				(0x00000001U)
+#define RCAR_CONV_MICROSEC			(1000000U)
+
+#if PMIC_ROHM_BD9571
+#define	BIT_BKUP_CTRL_OUT			((uint8_t)(1U << 4))
+#define	PMIC_BKUP_MODE_CNT			(0x20U)
+#define	PMIC_QLLM_CNT				(0x27U)
+#define	PMIC_RETRY_MAX				(100U)
+#endif
+#define	SCTLR_EL3_M_BIT				((uint32_t)1U << 0)
+#define	RCAR_CA53CPU_NUM_MAX			(4U)
+#define	RCAR_CA57CPU_NUM_MAX			(4U)
+#define IS_A53A57(c) 	((c) == RCAR_CLUSTER_A53A57)
+#define IS_CA57(c) 	((c) == RCAR_CLUSTER_CA57)
+#define IS_CA53(c) 	((c) == RCAR_CLUSTER_CA53)
+
+#ifndef __ASSEMBLY__
+IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
+IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
+IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
+#endif
+
+#if RCAR_SYSTEM_SUSPEND
+static void __attribute__ ((section (".system_ram")))
+	rcar_pwrc_micro_delay(uint64_t micro_sec)
+{
+	uint64_t freq, base, val;
+	uint64_t wait_time = 0;
+
+	freq = read_cntfrq_el0();
+	base = read_cntpct_el0();
+
+	while (micro_sec > wait_time) {
+		val = read_cntpct_el0() - base;
+		wait_time = val * RCAR_CONV_MICROSEC / freq;
+	}
+}
+#endif
+
+uint32_t rcar_pwrc_status(uint64_t mpidr)
+{
+	uint32_t ret = 0;
+	uint64_t cm, cpu;
+	uint32_t reg;
+	uint32_t c;
+
+	rcar_lock_get();
+
+	c = rcar_pwrc_get_cluster();
+	cm = mpidr & MPIDR_CLUSTER_MASK;
+
+	if (!IS_A53A57(c) && cm != 0) {
+		ret = RCAR_INVALID;
+		goto done;
+	}
+
+	reg = mmio_read_32(RCAR_PRR);
+	cpu = mpidr & MPIDR_CPU_MASK;
+
+	if (IS_CA53(c))
+		if (reg & (1 << (STATE_CA53_CPU + cpu)))
+			ret = RCAR_INVALID;
+	if (IS_CA57(c))
+		if (reg & (1 << (STATE_CA57_CPU + cpu)))
+			ret = RCAR_INVALID;
+done:
+	rcar_lock_release();
+
+	return ret;
+}
+
+static void scu_power_up(uint64_t mpidr)
+{
+	uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
+	uint32_t c, sysc_reg_bit;
+
+	c = rcar_pwrc_get_mpidr_cluster(mpidr);
+	reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
+	sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU;
+	reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3;
+	reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3;
+	reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3;
+
+	if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0)
+		return;
+
+	if (mmio_read_32(reg_cpumcr) != 0)
+		mmio_write_32(reg_cpumcr, 0);
+
+	mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
+	mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
+
+	do {
+		while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0)
+			;
+		mmio_write_32(reg_pwron, 1);
+	} while (mmio_read_32(reg_pwrer) & 1);
+
+	while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
+		;
+	mmio_write_32(RCAR_SYSCISR, sysc_reg_bit);
+	while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
+		;
+}
+
+void rcar_pwrc_cpuon(uint64_t mpidr)
+{
+	uint32_t res_data, on_data;
+	uintptr_t res_reg, on_reg;
+	uint32_t limit, c;
+	uint64_t cpu;
+
+	rcar_lock_get();
+
+	c = rcar_pwrc_get_mpidr_cluster(mpidr);
+	res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT;
+	on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR;
+	limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000;
+
+	res_data = mmio_read_32(res_reg) | limit;
+	scu_power_up(mpidr);
+	cpu = mpidr & MPIDR_CPU_MASK;
+	on_data = 1 << cpu;
+	mmio_write_32(RCAR_CPGWPR, ~on_data);
+	mmio_write_32(on_reg, on_data);
+	mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
+
+	rcar_lock_release();
+}
+
+void rcar_pwrc_cpuoff(uint64_t mpidr)
+{
+	uint32_t c;
+	uintptr_t reg;
+	uint64_t cpu;
+
+	rcar_lock_get();
+
+	cpu = mpidr & MPIDR_CPU_MASK;
+	c = rcar_pwrc_get_mpidr_cluster(mpidr);
+	reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR;
+
+	if (read_mpidr_el1() != mpidr)
+		panic();
+
+	mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
+	mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
+
+	rcar_lock_release();
+}
+
+void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
+{
+	uint32_t c, shift_irq, shift_fiq;
+	uintptr_t reg;
+	uint64_t cpu;
+
+	rcar_lock_get();
+
+	cpu = mpidr & MPIDR_CPU_MASK;
+	c = rcar_pwrc_get_mpidr_cluster(mpidr);
+	reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
+
+	shift_irq = WUP_IRQ_SHIFT + cpu;
+	shift_fiq = WUP_FIQ_SHIFT + cpu;
+
+	mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) &
+		      ~((uint32_t) 1 << shift_fiq));
+	rcar_lock_release();
+}
+
+void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
+{
+	uint32_t c, shift_irq, shift_fiq;
+	uintptr_t reg;
+	uint64_t cpu;
+
+	rcar_lock_get();
+
+	cpu = mpidr & MPIDR_CPU_MASK;
+	c = rcar_pwrc_get_mpidr_cluster(mpidr);
+	reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
+
+	shift_irq = WUP_IRQ_SHIFT + cpu;
+	shift_fiq = WUP_FIQ_SHIFT + cpu;
+
+	mmio_write_32(reg, ((uint32_t) 1 << shift_irq) |
+		      ((uint32_t) 1 << shift_fiq));
+	rcar_lock_release();
+}
+
+void rcar_pwrc_clusteroff(uint64_t mpidr)
+{
+	uint32_t c, product, cut, reg;
+	uintptr_t dst;
+
+	rcar_lock_get();
+
+	reg = mmio_read_32(RCAR_PRR);
+	product = reg & RCAR_PRODUCT_MASK;
+	cut = reg & RCAR_CUT_MASK;
+
+	c = rcar_pwrc_get_mpidr_cluster(mpidr);
+	dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
+
+	if (RCAR_PRODUCT_M3 == product && cut <= RCAR_M3_CUT_VER11)
+		goto done;
+
+	if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20)
+		goto done;
+
+	/* all of the CPUs in the cluster is in the CoreStandby mode */
+	mmio_write_32(dst, MODE_L2_DOWN);
+done:
+	rcar_lock_release();
+}
+
+#if !PMIC_ROHM_BD9571
+void rcar_pwrc_system_reset(void)
+{
+	mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET);
+}
+#endif /* PMIC_ROHM_BD9571 */
+
+#define	RST_CA53_CPU0_BARH		(0xE6160080U)
+#define	RST_CA53_CPU0_BARL		(0xE6160084U)
+#define	RST_CA57_CPU0_BARH		(0xE61600C0U)
+#define	RST_CA57_CPU0_BARL		(0xE61600C4U)
+
+void rcar_pwrc_setup(void)
+{
+	uintptr_t rst_barh;
+	uintptr_t rst_barl;
+	uint32_t i, j;
+	uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF;
+
+	const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
+		RCAR_CLUSTER_CA53,
+		RCAR_CLUSTER_CA57
+	};
+	const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = {
+		RST_CA53_CPU0_BARH,
+		RST_CA57_CPU0_BARH
+	};
+	const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = {
+		RST_CA53_CPU0_BARL,
+		RST_CA57_CPU0_BARL
+	};
+
+	for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
+		rst_barh = reg_barh[i];
+		rst_barl = reg_barl[i];
+		for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) {
+			mmio_write_32(rst_barh, 0);
+			mmio_write_32(rst_barl, (uint32_t) reset);
+			rst_barh += 0x10;
+			rst_barl += 0x10;
+		}
+	}
+
+	rcar_lock_init();
+}
+
+#if RCAR_SYSTEM_SUSPEND
+#define DBCAM_FLUSH(__bit)		\
+do {					\
+	;				\
+} while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0))
+
+
+static void __attribute__ ((section(".system_ram")))
+	rcar_pwrc_set_self_refresh(void)
+{
+	uint32_t reg = mmio_read_32(RCAR_PRR);
+	uint32_t cut, product;
+
+	product = reg & RCAR_PRODUCT_MASK;
+	cut = reg & RCAR_CUT_MASK;
+
+	if (product == RCAR_PRODUCT_M3)
+		goto self_refresh;
+
+	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+		goto self_refresh;
+
+	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
+
+self_refresh:
+
+	/* Set the Self-Refresh mode */
+	mmio_write_32(DBSC4_REG_DBACEN, 0);
+
+	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+		rcar_pwrc_micro_delay(100);
+	else if (product == RCAR_PRODUCT_H3) {
+		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
+		DBCAM_FLUSH(0);
+		DBCAM_FLUSH(1);
+		DBCAM_FLUSH(2);
+		DBCAM_FLUSH(3);
+		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
+	} else if (product == RCAR_PRODUCT_M3) {
+		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
+		DBCAM_FLUSH(0);
+		DBCAM_FLUSH(1);
+		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
+	} else {
+		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
+		DBCAM_FLUSH(0);
+		mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
+	}
+
+	/* Set the SDRAM calibration configuration register */
+	mmio_write_32(DBSC4_REG_DBCALCNF, 0);
+
+	reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
+	    DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
+	mmio_write_32(DBSC4_REG_DBCMD, reg);
+	while (mmio_read_32(DBSC4_REG_DBWAIT))
+		;
+
+	/* Self-Refresh entry command   */
+	reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
+	    DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
+	mmio_write_32(DBSC4_REG_DBCMD, reg);
+	while (mmio_read_32(DBSC4_REG_DBWAIT))
+		;
+
+	/* Mode Register Write command. (ODT disabled)  */
+	reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL |
+	    DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC;
+	mmio_write_32(DBSC4_REG_DBCMD, reg);
+	while (mmio_read_32(DBSC4_REG_DBWAIT))
+		;
+
+	/* Power Down entry command     */
+	reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL |
+	    DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
+	mmio_write_32(DBSC4_REG_DBCMD, reg);
+	while (mmio_read_32(DBSC4_REG_DBWAIT))
+		;
+
+	/* Set the auto-refresh enable register */
+	mmio_write_32(DBSC4_REG_DBRFEN, 0U);
+	rcar_pwrc_micro_delay(1U);
+
+	if (product == RCAR_PRODUCT_M3)
+		return;
+
+	if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+		return;
+
+	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
+}
+
+static void __attribute__ ((section(".system_ram")))
+    rcar_pwrc_set_self_refresh_e3(void)
+{
+	uint32_t ddr_md;
+	uint32_t reg;
+
+	ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0;
+
+	/* Write enable */
+	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
+	mmio_write_32(DBSC4_REG_DBACEN, 0);
+	DBCAM_FLUSH(0);
+
+	reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
+	    DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
+	mmio_write_32(DBSC4_REG_DBCMD, reg);
+	while (mmio_read_32(DBSC4_REG_DBWAIT))
+		;
+
+	reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
+	    DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
+	mmio_write_32(DBSC4_REG_DBCMD, reg);
+	while (mmio_read_32(DBSC4_REG_DBWAIT))
+		;
+
+	/* Set the auto-refresh enable register */
+	/* Set the ARFEN bit to 0 in the DBRFEN */
+	mmio_write_32(DBSC4_REG_DBRFEN, 0);
+
+	mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
+
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0);
+
+	/* DDR_DXCCR */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR);
+
+	/* DDR_PGCR1 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1);
+
+	/* DDR_ACIOCR1 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1);
+
+	/* DDR_ACIOCR3 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3);
+
+	/* DDR_ACIOCR5 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5);
+
+	/* DDR_DX0GCR2 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2);
+
+	/* DDR_DX1GCR2 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2);
+
+	/* DDR_DX2GCR2 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2);
+
+	/* DDR_DX3GCR2 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2);
+
+	/* DDR_ZQCR */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);
+
+	mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ?
+		      DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 :
+		      DBSC4_SET_DBPDRGD0_ZQCR_MD19_1);
+
+	/* DDR_DX0GCR0 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0);
+
+	/* DDR_DX1GCR0 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0);
+
+	/* DDR_DX2GCR0 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0);
+
+	/* DDR_DX3GCR0 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0);
+
+	/* DDR_DX0GCR1 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1);
+
+	/* DDR_DX1GCR1 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1);
+
+	/* DDR_DX2GCR1 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1);
+
+	/* DDR_DX3GCR1 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1);
+
+	/* DDR_DX0GCR3 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3);
+
+	/* DDR_DX1GCR3 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3);
+
+	/* DDR_DX2GCR3 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3);
+
+	/* DDR_DX3GCR3 */
+	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);
+	mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3);
+
+	/* Write disable */
+	mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
+}
+
+void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
+    rcar_pwrc_go_suspend_to_ram(void)
+{
+#if PMIC_ROHM_BD9571
+	int32_t rc = -1, qllm = -1;
+	uint8_t mode;
+	uint32_t i;
+#endif
+	uint32_t reg, product;
+
+	reg = mmio_read_32(RCAR_PRR);
+	product = reg & RCAR_PRODUCT_MASK;
+
+	if (product != RCAR_PRODUCT_E3)
+		rcar_pwrc_set_self_refresh();
+	else
+		rcar_pwrc_set_self_refresh_e3();
+
+#if PMIC_ROHM_BD9571
+	/* Set QLLM Cnt Disable */
+	for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++)
+		qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0);
+
+	/* Set trigger of power down to PMIV */
+	for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) {
+		rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode);
+		if (rc == 0) {
+			mode |= BIT_BKUP_CTRL_OUT;
+			rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode);
+		}
+	}
+#endif
+	wfi();
+
+	while (1)
+		;
+}
+
+void rcar_pwrc_set_suspend_to_ram(void)
+{
+	uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram;
+	uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE +
+				       DEVICE_SRAM_STACK_SIZE);
+	uint32_t sctlr;
+
+	rcar_pwrc_code_copy_to_system_ram();
+	rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
+
+	/* disable MMU */
+	sctlr = (uint32_t) read_sctlr_el3();
+	sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT;
+	write_sctlr_el3((uint64_t) sctlr);
+
+	rcar_pwrc_switch_stack(jump, stack, NULL);
+}
+
+void rcar_pwrc_init_suspend_to_ram(void)
+{
+#if PMIC_ROHM_BD9571
+	uint8_t mode;
+#endif
+	rcar_pwrc_code_copy_to_system_ram();
+
+#if PMIC_ROHM_BD9571
+	if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
+		panic();
+
+	mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT);
+	if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode))
+		panic();
+#endif
+}
+
+void rcar_pwrc_suspend_to_ram(void)
+{
+#if RCAR_SYSTEM_RESET_KEEPON_DDR
+	int32_t error;
+
+	rcar_pwrc_code_copy_to_system_ram();
+	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
+	if (error) {
+		ERROR("Failed send KEEP10 init ret=%d \n", error);
+		return;
+	}
+#endif
+	rcar_pwrc_set_suspend_to_ram();
+}
+#endif
+
+void rcar_pwrc_code_copy_to_system_ram(void)
+{
+	int ret __attribute__ ((unused));	/* in assert */
+	uint32_t attr;
+	struct device_sram_t {
+		uintptr_t base;
+		size_t len;
+	} sram = {
+		.base = (uintptr_t) DEVICE_SRAM_BASE,
+		.len = DEVICE_SRAM_SIZE,
+	};
+	struct ddr_code_t {
+		void *base;
+		size_t len;
+	} code = {
+		.base = (void *) SRAM_COPY_START,
+		.len = SYSTEM_RAM_END - SYSTEM_RAM_START,
+	};
+
+	attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER;
+	ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
+	assert(ret == 0);
+
+	memcpy((void *)sram.base, code.base, code.len);
+	flush_dcache_range((uint64_t) sram.base, code.len);
+
+	/* Invalidate instruction cache */
+	plat_invalidate_icache();
+	dsb();
+	isb();
+
+	attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
+	ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
+	assert(ret == 0);
+}
+
+uint32_t rcar_pwrc_get_cluster(void)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(RCAR_PRR);
+
+	if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
+		return RCAR_CLUSTER_CA57;
+
+	if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+		return RCAR_CLUSTER_CA53;
+
+	return RCAR_CLUSTER_A53A57;
+}
+
+uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
+{
+	uint32_t c = rcar_pwrc_get_cluster();
+
+	if (IS_A53A57(c)) {
+		if (mpidr & MPIDR_CLUSTER_MASK)
+			return RCAR_CLUSTER_CA53;
+
+		return RCAR_CLUSTER_CA57;
+	}
+
+	return c;
+}
+
+uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
+{
+	uint32_t reg = mmio_read_32(RCAR_PRR);
+	uint32_t count = 0, i;
+
+	if (IS_A53A57(c) || IS_CA53(c)) {
+		if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
+			goto count_ca57;
+
+		for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) {
+			if (reg & (1 << (STATE_CA53_CPU + i)))
+				continue;
+			count++;
+		}
+	}
+
+count_ca57:
+	if (IS_A53A57(c) || IS_CA57(c)) {
+		if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
+			goto done;
+
+		for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
+			if (reg & (1 << (STATE_CA57_CPU + i)))
+				continue;
+			count++;
+		}
+	}
+
+done:
+	return count;
+}
diff --git a/drivers/renesas/rcar/pwrc/pwrc.h b/drivers/renesas/rcar/pwrc/pwrc.h
new file mode 100644
index 0000000..166886e
--- /dev/null
+++ b/drivers/renesas/rcar/pwrc/pwrc.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_PWRC_H__
+#define RCAR_PWRC_H__
+
+#define PPOFFR_OFF		0x0
+#define PPONR_OFF		0x4
+#define PCOFFR_OFF		0x8
+#define PWKUPR_OFF		0xc
+#define PSYSR_OFF		0x10
+
+#define PWKUPR_WEN		(1ull << 31)
+
+#define PSYSR_AFF_L2		(1 << 31)
+#define PSYSR_AFF_L1		(1 << 30)
+#define PSYSR_AFF_L0		(1 << 29)
+#define PSYSR_WEN		(1 << 28)
+#define PSYSR_PC		(1 << 27)
+#define PSYSR_PP		(1 << 26)
+
+#define PSYSR_WK_SHIFT		(24)
+#define PSYSR_WK_MASK		(0x3)
+#define PSYSR_WK(x)		(((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK)
+
+#define WKUP_COLD		0x0
+#define WKUP_RESET		0x1
+#define WKUP_PPONR		0x2
+#define WKUP_GICREQ		0x3
+
+#define	RCAR_INVALID		(0xffffffffU)
+#define PSYSR_INVALID		0xffffffff
+
+#define	RCAR_CLUSTER_A53A57	(0U)
+#define	RCAR_CLUSTER_CA53	(1U)
+#define	RCAR_CLUSTER_CA57	(2U)
+
+#ifndef __ASSEMBLY__
+void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
+void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr);
+void rcar_pwrc_clusteroff(uint64_t mpidr);
+void rcar_pwrc_cpuoff(uint64_t mpidr);
+void rcar_pwrc_cpuon(uint64_t mpidr);
+void rcar_pwrc_setup(void);
+
+uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr);
+uint32_t rcar_pwrc_status(uint64_t mpidr);
+uint32_t rcar_pwrc_get_cluster(void);
+uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr);
+uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type);
+void plat_secondary_reset(void);
+
+void rcar_pwrc_code_copy_to_system_ram(void);
+
+#if !PMIC_ROHM_BD9571
+void rcar_pwrc_system_reset(void);
+#endif
+
+#if RCAR_SYSTEM_SUSPEND
+void rcar_pwrc_go_suspend_to_ram(void);
+void rcar_pwrc_set_suspend_to_ram(void);
+void rcar_pwrc_init_suspend_to_ram(void);
+void rcar_pwrc_suspend_to_ram(void);
+#endif
+
+extern void rcar_pwrc_save_generic_timer(uint64_t *rcar_stack_generic_timer);
+extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack,
+				       void *arg);
+
+extern uint64_t rcar_stack_generic_timer[5];
+
+#endif
+
+#endif
diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/rcar/rom/rom_api.c
new file mode 100644
index 0000000..c14de55
--- /dev/null
+++ b/drivers/renesas/rcar/rom/rom_api.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <stdint.h>
+#include "rcar_def.h"
+#include "rom_api.h"
+
+typedef uint32_t(*rom_secure_boot_api_f) (uint32_t *key, uint32_t *cert,
+					  rom_read_flash_f pFuncReadFlash);
+
+typedef uint32_t(*rom_get_lcs_api_f) (uint32_t *lcs);
+
+#define OLD_API_TABLE1	(0U)	/* H3 Ver.1.0/Ver.1.1 */
+#define OLD_API_TABLE2	(1U)	/* H3 Ver.2.0 */
+#define OLD_API_TABLE3	(2U)	/* M3 Ver.1.0 */
+#define NEW_API_TABLE	(3U)	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+#define API_TABLE_MAX	(4U)	/* table max */
+				/* Later than H3 Ver.2.0 */
+
+static uint32_t get_table_index(void)
+{
+	uint32_t product;
+	uint32_t cut_ver;
+	uint32_t index;
+
+	product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+	cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+
+	switch (product) {
+	case RCAR_PRODUCT_H3:
+		if (cut_ver == RCAR_CUT_VER10)
+			index = OLD_API_TABLE1;
+		else if (cut_ver == RCAR_CUT_VER11)
+			index = OLD_API_TABLE1;
+		else if (cut_ver == RCAR_CUT_VER20)
+			index = OLD_API_TABLE2;
+		else
+			/* Later than H3 Ver.2.0 */
+			index = NEW_API_TABLE;
+		break;
+	case RCAR_PRODUCT_M3:
+		if (cut_ver == RCAR_CUT_VER10)
+			index = OLD_API_TABLE3;
+		else
+			/* M3 Ver.1.1 or later */
+			index = NEW_API_TABLE;
+		break;
+	default:
+		index = NEW_API_TABLE;
+		break;
+	}
+
+	return index;
+}
+
+uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert,
+			     rom_read_flash_f read_flash)
+{
+	static const uintptr_t rom_api_table[API_TABLE_MAX] = {
+		0xEB10DD64U,	/* H3 Ver.1.0/Ver.1.1 */
+		0xEB116ED4U,	/* H3 Ver.2.0 */
+		0xEB1102FCU,	/* M3 Ver.1.0 */
+		0xEB100180U	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+	};
+	rom_secure_boot_api_f secure_boot;
+	uint32_t index;
+
+	index = get_table_index();
+	secure_boot = (rom_secure_boot_api_f) rom_api_table[index];
+
+	return secure_boot(key, cert, read_flash);
+}
+
+uint32_t rcar_rom_get_lcs(uint32_t *lcs)
+{
+	static const uintptr_t rom_get_lcs_table[API_TABLE_MAX] = {
+		0xEB10DFE0U,	/* H3 Ver.1.0/Ver.1.1 */
+		0xEB117150U,	/* H3 Ver.2.0 */
+		0xEB110578U,	/* M3 Ver.1.0 */
+		0xEB10018CU	/* H3 Ver.3.0, M3 Ver.1.1 or later, M3N, E3 */
+	};
+	rom_get_lcs_api_f get_lcs;
+	uint32_t index;
+
+	index = get_table_index();
+	get_lcs = (rom_get_lcs_api_f) rom_get_lcs_table[index];
+
+	return get_lcs(lcs);
+}
diff --git a/drivers/renesas/rcar/rom/rom_api.h b/drivers/renesas/rcar/rom/rom_api.h
new file mode 100644
index 0000000..85105ef
--- /dev/null
+++ b/drivers/renesas/rcar/rom/rom_api.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ROM_API_H__
+#define ROM_API_H__
+
+#include <stdint.h>
+
+#define SBROM_OK				(0x00000000U)
+#define SBROM_ILLEGAL_INPUT_PARAM_ERR		(0x0B000001U)
+#define SBROM_ILLEGAL_OEM_HASH_VALUE_ERR	(0x0B000008U)
+#define SBROM_ILLEGAL_LCS_FOR_OPERATION_ERR	(0x0B000010U)
+#define SBROM_HASH_NOT_PROGRAMMED_ERR		(0x0B000100U)
+#define SBROM_PUB_KEY_HASH_VALIDATION_FAILURE	(0xF1000006U)
+#define SBROM_RSA_SIG_VERIFICATION_FAILED	(0xF1000007U)
+
+#define LCS_CM					(0x0U)
+#define LCS_DM					(0x1U)
+#define LCS_SD					(0x3U)
+#define LCS_SE					(0x5U)
+#define LCS_FA					(0x7U)
+
+typedef uint32_t(*rom_read_flash_f) (uint64_t src, uint8_t *dst, uint32_t len);
+uint32_t rcar_rom_secure_boot_api(uint32_t *key, uint32_t *cert,
+				  rom_read_flash_f f);
+uint32_t rcar_rom_get_lcs(uint32_t *lcs);
+
+#endif
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/rcar/rpc/rpc_driver.c
new file mode 100644
index 0000000..bc7424a
--- /dev/null
+++ b/drivers/renesas/rcar/rpc/rpc_driver.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <stdint.h>
+#include <string.h>
+#include "cpg_registers.h"
+#include "rpc_registers.h"
+#include "debug.h"
+#include "rcar_private.h"
+
+#define MSTPSR9_RPC_BIT		(0x00020000U)
+#define RPC_CMNCR_MD_BIT	(0x80000000U)
+
+static void rpc_enable(void)
+{
+	/* Enable clock supply to RPC. */
+	mstpcr_write(CPG_SMSTPCR9, CPG_MSTPSR9, MSTPSR9_RPC_BIT);
+}
+
+static void rpc_setup(void)
+{
+	if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
+		mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
+}
+
+void rcar_rpc_init(void)
+{
+	rpc_enable();
+	rpc_setup();
+}
diff --git a/drivers/renesas/rcar/rpc/rpc_registers.h b/drivers/renesas/rcar/rpc/rpc_registers.h
new file mode 100644
index 0000000..326519d
--- /dev/null
+++ b/drivers/renesas/rcar/rpc/rpc_registers.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RPC_REGISTER_H__
+#define RPC_REGISTER_H__
+
+#define RPC_BASE	(0xEE200000U)
+#define RPC_CMNCR	(RPC_BASE + 0x0000U)
+#define RPC_SSLDR	(RPC_BASE + 0x0004U)
+#define RPC_DRCR	(RPC_BASE + 0x000CU)
+#define RPC_DRCMR	(RPC_BASE + 0x0010U)
+#define RPC_DRENR	(RPC_BASE + 0x001CU)
+#define RPC_SMCR	(RPC_BASE + 0x0020U)
+#define RPC_SMCMR	(RPC_BASE + 0x0024U)
+#define RPC_SMENR	(RPC_BASE + 0x0030U)
+#define RPC_CMNSR	(RPC_BASE + 0x0048U)
+#define RPC_DRDMCR	(RPC_BASE + 0x0058U)
+#define RPC_DRDRENR	(RPC_BASE + 0x005CU)
+#define RPC_PHYCNT	(RPC_BASE + 0x007CU)
+#define RPC_PHYINT	(RPC_BASE + 0x0088U)
+
+#endif
diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S
new file mode 100644
index 0000000..1cc0d59
--- /dev/null
+++ b/drivers/renesas/rcar/scif/scif.S
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+#define	SCIF_INTERNAL_CLK	0
+#define	SCIF_EXTARNAL_CLK	1
+#define	SCIF_CLK		SCIF_INTERNAL_CLK
+
+/* product register */
+#define	PRR			(0xFFF00044)
+#define	PRR_PRODUCT_MASK	(0x00007F00)
+#define	PRR_CUT_MASK		(0x000000FF)
+#define	PRR_PRODUCT_H3_VER_10	(0x00004F00)
+#define	PRR_PRODUCT_E3		(0x00005700)
+
+/* module stop */
+#define	CPG_BASE		(0xE6150000)
+#define	CPG_SMSTPCR3		(0x013C)
+#define	CPG_MSTPSR3		(0x0048)
+#define	MSTP310			(1 << 10)
+#define	CPG_CPGWPR		(0x0900)
+
+/* scif */
+#define	SCIF2_BASE		(0xE6E88000)
+#define	SCIF_SCSMR		(0x00)
+#define	SCIF_SCBRR		(0x04)
+#define	SCIF_SCSCR		(0x08)
+#define	SCIF_SCFTDR		(0x0C)
+#define	SCIF_SCFSR		(0x10)
+#define	SCIF_SCFRDR		(0x14)
+#define	SCIF_SCFCR		(0x18)
+#define	SCIF_SCFDR		(0x1C)
+#define	SCIF_SCSPTR		(0x20)
+#define	SCIF_SCLSR		(0x24)
+#define	SCIF_DL			(0x30)
+#define	SCIF_CKS		(0x34)
+
+/* mode pin */
+#define	RST_MODEMR		(0xE6160060)
+#define	MODEMR_MD12		(0x00001000)
+
+#define	SCSMR_CA_MASK		(1 << 7)
+#define	SCSMR_CA_ASYNC		(0x0000)
+#define	SCSMR_CHR_MASK		(1 << 6)
+#define	SCSMR_CHR_8		(0x0000)
+#define	SCSMR_PE_MASK		(1 << 5)
+#define	SCSMR_PE_DIS		(0x0000)
+#define	SCSMR_STOP_MASK		(1 << 3)
+#define	SCSMR_STOP_1		(0x0000)
+#define	SCSMR_CKS_MASK		(3 << 0)
+#define	SCSMR_CKS_DIV1		(0x0000)
+#define	SCSMR_INIT_DATA		(SCSMR_CA_ASYNC +	\
+					 SCSMR_CHR_8 +		\
+					 SCSMR_PE_DIS +		\
+					 SCSMR_STOP_1 +		\
+					 SCSMR_CKS_DIV1)
+#define	SCBRR_115200BPS		(17)
+#define	SCBRR_115200BPS_E3_SSCG	(15)
+#define	SCBRR_230400BPS		(8)
+
+#define	SCSCR_TE_MASK		(1 << 5)
+#define	SCSCR_TE_DIS		(0x0000)
+#define	SCSCR_TE_EN		(0x0020)
+#define	SCSCR_RE_MASK		(1 << 4)
+#define	SCSCR_RE_DIS		(0x0000)
+#define	SCSCR_RE_EN		(0x0010)
+#define	SCSCR_CKE_MASK		(3 << 0)
+#define	SCSCR_CKE_INT		(0x0000)
+#define 	SCSCR_CKE_BRG		(0x0002)
+#if SCIF_CLK == SCIF_EXTARNAL_CLK
+#define	SCSCR_CKE_INT_CLK	(SCSCR_CKE_BRG)
+#else
+#define	SCSCR_CKE_INT_CLK	(SCSCR_CKE_INT)
+#endif
+#define	SCFSR_INIT_DATA		(0x0000)
+#define	SCFCR_TTRG_MASK		(3 << 4)
+#define	SCFCR_TTRG_8		(0x0000)
+#define	SCFCR_TTRG_0		(0x0030)
+#define	SCFCR_TFRST_MASK	(1 << 2)
+#define	SCFCR_TFRST_DIS		(0x0000)
+#define	SCFCR_TFRST_EN		(0x0004)
+#define	SCFCR_RFRS_MASK		(1 << 1)
+#define	SCFCR_RFRS_DIS		(0x0000)
+#define	SCFCR_RFRS_EN		(0x0002)
+#define	SCFCR_INIT_DATA		(SCFCR_TTRG_8)
+#define	SCFDR_T_MASK		(0x1f << 8)
+#define	DL_INIT_DATA		(8)
+#define	CKS_CKS_DIV_MASK	(1 << 15)
+#define	CKS_CKS_DIV_CLK		(0x0000)
+#define	CKS_XIN_MASK		(1 << 14)
+#define	CKS_XIN_SCIF_CLK	(0x0000)
+#define	CKS_INIT_DATA		(CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK)
+
+	.globl	console_init
+	.globl	console_uninit
+	.globl	console_putc
+	.globl	console_core_init
+	.globl	console_core_putc
+	.globl	console_getc
+	.globl	console_flush
+
+	/*
+	 *  The console base is in the data section and not in .bss
+	 *  even though it is zero-init. In particular, this allows
+	 *  the console functions to start using this variable before
+	 *  the runtime memory is initialized for images which do not
+	 *  need to copy the .data section from ROM to RAM.
+	 */
+	/* -----------------------------------------------
+	 * int console_init(unsigned long base_addr,
+	 * unsigned int uart_clk, unsigned int baud_rate)
+	 * Function to initialize the console without a
+	 * C Runtime to print debug information. It saves
+	 * the console base to the data section.
+	 * In: x0 - console base address
+	 *     w1 - Uart clock in Hz
+	 *     w2 - Baud rate
+	 * out: return 1 on success.
+	 * Clobber list : x1 - x3
+	 * -----------------------------------------------
+	 */
+func console_init
+	b	console_core_init
+endfunc console_init
+
+func console_uninit
+	ret
+endfunc console_uninit
+
+	/* -----------------------------------------------
+	 * int console_core_init(unsigned long base_addr,
+	 * unsigned int uart_clk, unsigned int baud_rate)
+	 * Function to initialize the console without a
+	 * C Runtime to print debug information. This
+	 * function will be accessed by console_init and
+	 * crash reporting.
+	 * In: x0 - console base address
+	 *     w1 - Uart clock in Hz
+	 *     w2 - Baud rate
+	 * Out: return 1 on success
+	 * Clobber list : x1, x2
+	 * -----------------------------------------------
+	 */
+func console_core_init
+	ldr	x0, =CPG_BASE
+	ldr	w1, [x0, #CPG_SMSTPCR3]
+	and	w1, w1, #~MSTP310		/* MSTP310=0 */
+	mvn	w2, w1
+	str	w2, [x0, #CPG_CPGWPR]
+	str	w1, [x0, #CPG_SMSTPCR3]
+5:
+	ldr w1, [x0, #CPG_MSTPSR3]
+	and w1, w1, #MSTP310
+	cbnz w1, 5b
+
+	ldr	x0, =SCIF2_BASE
+	/* Clear bits TE and RE in SCSCR to 0 */
+	mov	w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS)
+	strh	w1, [x0, #SCIF_SCSCR]
+	/* Set bits TFRST and RFRST in SCFCR to 1 */
+	ldrh	w1, [x0, #SCIF_SCFCR]
+	orr	w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN)
+	strh	w1, [x0, #SCIF_SCFCR]
+	/* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER
+	   in SCLSR, then clear them to 0 */
+	mov	w1, #SCFSR_INIT_DATA
+	strh	w1, [x0, #SCIF_SCFSR]
+	mov	w1, #0
+	strh	w1, [x0, #SCIF_SCLSR]
+	/* Set bits CKE[1:0] in SCSCR */
+	ldrh	w1, [x0, #SCIF_SCSCR]
+	and	w1, w1, #~SCSCR_CKE_MASK
+	mov	w2, #SCSCR_CKE_INT_CLK
+	orr	w1, w1, w2
+	strh	w1, [x0, #SCIF_SCSCR]
+	/* Set data transfer format in SCSMR */
+	mov	w1, #SCSMR_INIT_DATA
+	strh	w1, [x0, #SCIF_SCSMR]
+	/* Set value in SCBRR */
+#if SCIF_CLK == SCIF_INTERNAL_CLK
+	ldr	x1, =PRR
+	ldr	w1, [x1]
+	and	w1, w1, #(PRR_PRODUCT_MASK | PRR_CUT_MASK)
+	mov	w2, #PRR_PRODUCT_H3_VER_10
+	cmp	w1, w2
+	beq	3f
+	and	w1, w1, #PRR_PRODUCT_MASK
+	mov	w2, #PRR_PRODUCT_E3
+	cmp	w1, w2
+	bne	4f
+
+	ldr	x1, =RST_MODEMR
+	ldr	w1, [x1]
+	and	w1, w1, #MODEMR_MD12
+	mov	w2, #MODEMR_MD12
+	cmp	w1, w2
+	bne	4f
+
+	mov	w1, #SCBRR_115200BPS_E3_SSCG
+	b	2f
+4:
+	mov	w1, #SCBRR_115200BPS
+	b	2f
+3:
+	mov	w1, #SCBRR_230400BPS
+2:
+	strb	w1, [x0, SCIF_SCBRR]
+#else
+	mov	w1, #DL_INIT_DATA
+	strh	w1, [x0, #SCIF_DL]
+	mov	w1, #CKS_INIT_DATA
+	strh	w1, [x0, #SCIF_CKS]
+#endif
+	/* 1-bit interval elapsed */
+	mov	w1, #100
+1:
+	subs	w1, w1, #1
+	cbnz	w1, 1b
+	/*
+	 * Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR
+	 * Clear bits FRST and RFRST to 0
+	 */
+	mov	w1, #SCFCR_INIT_DATA
+	strh	w1, [x0, #SCIF_SCFCR]
+	/* Set bits TE and RE in SCSCR to 1 */
+	ldrh	w1, [x0, #SCIF_SCSCR]
+	orr	w1, w1, #(SCSCR_TE_EN + SCSCR_RE_EN)
+	strh	w1, [x0, #SCIF_SCSCR]
+	mov	x0, #1
+
+	ret
+endfunc console_core_init
+
+	/* ---------------------------------------------
+	 * int console_putc(int c)
+	 * Function to output a character over the
+	 * console. It returns the character printed on
+	 * success or -1 on error.
+	 * In : x0 - character to be printed
+	 * Out : return -1 on error else return character.
+	 * Clobber list : x1, x2
+	 * ---------------------------------------------
+	 */
+func console_putc
+	b	console_core_putc
+endfunc console_putc
+
+	/* --------------------------------------------------------
+	 * int console_core_putc(int c, unsigned int base_addr)
+	 * Function to output a character over the console. It
+	 * returns the character printed on success or -1 on error.
+	 * In : w0 - character to be printed
+	 *      x1 - console base address
+	 * Out : return -1 on error else return character.
+	 * Clobber list : x2
+	 * --------------------------------------------------------
+	 */
+func console_core_putc
+	ldr	x1, =SCIF2_BASE
+	cmp	w0, #0xA
+	/* Prepend '\r' to '\n' */
+	bne	2f
+1:
+	/* Check if the transmit FIFO is full */
+	ldrh	w2, [x1, #SCIF_SCFDR]
+	ubfx	w2, w2, #8, #5
+	cmp	w2, #16
+	bcs	1b
+	mov	w2, #0x0D
+	strb	w2, [x1, #SCIF_SCFTDR]
+2:
+	/* Check if the transmit FIFO is full */
+	ldrh	w2, [x1, #SCIF_SCFDR]
+	ubfx	w2, w2, #8, #5
+	cmp	w2, #16
+	bcs	2b
+	strb	w0, [x1, #SCIF_SCFTDR]
+
+	ret
+endfunc console_core_putc
+
+	/* ---------------------------------------------
+	 * int console_getc(void)
+	 * Function to get a character from the console.
+	 * It returns the character grabbed on success
+	 * or -1 on error.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_getc
+	mov	w0, #-1
+	ret
+endfunc console_getc
+
+	/* ---------------------------------------------
+	 * int console_flush(void)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output. It returns 0
+	 * upon successful completion, otherwise it
+	 * returns -1.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_flush
+	ldr	x0, =SCIF2_BASE
+1:
+	ldrh	w1, [x0, #SCIF_SCFDR]
+	ubfx	w1, w1, #8, #5
+	cmp	w1, #0
+	bne	1b
+
+	mov x0, #100
+	mov x3, x30
+	bl rcar_micro_delay
+	mov x30, x3
+
+	ldr	x0, =SCIF2_BASE
+	ldrh	w1, [x0, #SCIF_SCSCR]
+	and	w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)
+	strh	w1, [x0, #SCIF_SCSCR]
+
+	mov	w0, #0
+	ret
+endfunc console_flush
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c
new file mode 100644
index 0000000..6df47b9
--- /dev/null
+++ b/drivers/renesas/rcar/watchdog/swdt.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <debug.h>
+#include <gicv2.h>
+#include <mmio.h>
+#include "rcar_def.h"
+
+extern void gicd_set_icenabler(uintptr_t base, unsigned int id);
+
+#define RST_BASE			(0xE6160000U)
+#define RST_WDTRSTCR			(RST_BASE + 0x0054U)
+#define SWDT_BASE			(0xE6030000U)
+#define SWDT_WTCNT			(SWDT_BASE + 0x0000U)
+#define SWDT_WTCSRA			(SWDT_BASE + 0x0004U)
+#define SWDT_WTCSRB			(SWDT_BASE + 0x0008U)
+#define SWDT_GICD_BASE			(0xF1010000U)
+#define SWDT_GICC_BASE			(0xF1020000U)
+#define SWDT_GICD_CTLR			(SWDT_GICD_BASE + 0x0000U)
+#define SWDT_GICD_IGROUPR		(SWDT_GICD_BASE + 0x0080U)
+#define SWDT_GICD_ISPRIORITYR		(SWDT_GICD_BASE + 0x0400U)
+#define SWDT_GICC_CTLR			(SWDT_GICC_BASE + 0x0000U)
+#define SWDT_GICC_PMR			(SWDT_GICC_BASE + 0x0004U)
+#define SWDT_GICD_ITARGETSR		(SWDT_GICD_BASE + 0x0800U)
+#define IGROUPR_NUM			(16U)
+#define ISPRIORITY_NUM			(128U)
+#define ITARGET_MASK			(0x03U)
+
+#define WDTRSTCR_UPPER_BYTE		(0xA55A0000U)
+#define WTCSRA_UPPER_BYTE		(0xA5A5A500U)
+#define WTCSRB_UPPER_BYTE		(0xA5A5A500U)
+#define WTCNT_UPPER_BYTE		(0x5A5A0000U)
+#define WTCNT_RESET_VALUE		(0xF488U)
+#define WTCSRA_BIT_CKS			(0x0007U)
+#define WTCSRB_BIT_CKS			(0x003FU)
+#define SWDT_RSTMSK			(1U << 1U)
+#define WTCSRA_WOVFE			(1U << 3U)
+#define WTCSRA_WRFLG			(1U << 5U)
+#define SWDT_ENABLE			(1U << 7U)
+
+#define WDTRSTCR_MASK_ALL		(0x0000FFFFU)
+#define WTCSRA_MASK_ALL			(0x000000FFU)
+#define WTCNT_INIT_DATA			(WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE)
+#define WTCSRA_INIT_DATA		(WTCSRA_UPPER_BYTE + 0x0FU)
+#define WTCSRB_INIT_DATA		(WTCSRB_UPPER_BYTE + 0x21U)
+
+#define WTCNT_COUNT_8p13k		(0x10000U - 40687U)
+#define WTCNT_COUNT_8p13k_H3VER10	(0x10000U - 20343U)
+#define WTCNT_COUNT_8p22k		(0x10000U - 41115U)
+#define WTCNT_COUNT_7p81k		(0x10000U - 39062U)
+#define WTCSRA_CKS_DIV16		(0x00000002U)
+
+static void swdt_disable(void)
+{
+	uint32_t rmsk;
+
+	rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
+	rmsk |= SWDT_RSTMSK;
+	mmio_write_32(RST_WDTRSTCR, WDTRSTCR_UPPER_BYTE | rmsk);
+
+	mmio_write_32(SWDT_WTCNT, WTCNT_INIT_DATA);
+	mmio_write_32(SWDT_WTCSRA, WTCSRA_INIT_DATA);
+	mmio_write_32(SWDT_WTCSRB, WTCSRB_INIT_DATA);
+
+	/* Set the interrupt clear enable register */
+	gicd_set_icenabler(RCAR_GICD_BASE, ARM_IRQ_SEC_WDT);
+}
+
+void rcar_swdt_init(void)
+{
+	uint32_t rmsk, val, sr;
+#if (RCAR_LSI != RCAR_E3)
+	uint32_t reg, product_cut, chk_data;
+
+	reg = mmio_read_32(RCAR_PRR);
+	product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+
+	reg = mmio_read_32(RCAR_MODEMR);
+	chk_data = reg & CHECK_MD13_MD14;
+#endif
+	/* stop watchdog */
+	if (mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE)
+		mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE);
+
+	mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
+		      WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
+
+#if (RCAR_LSI == RCAR_E3)
+	mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
+#else
+	val = WTCNT_UPPER_BYTE;
+
+	switch (chk_data) {
+	case MD14_MD13_TYPE_0:
+	case MD14_MD13_TYPE_2:
+		val |= WTCNT_COUNT_8p13k;
+		break;
+	case MD14_MD13_TYPE_1:
+		val |= WTCNT_COUNT_8p22k;
+		break;
+	case MD14_MD13_TYPE_3:
+		val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ?
+		    WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
+		break;
+	default:
+		ERROR("MODEMR ERROR value = %x\n", chk_data);
+		panic();
+		break;
+	}
+
+	mmio_write_32(SWDT_WTCNT, val);
+#endif
+	rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
+	rmsk |= SWDT_RSTMSK | WDTRSTCR_UPPER_BYTE;
+	mmio_write_32(RST_WDTRSTCR, rmsk);
+
+	while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U)
+		;
+
+	/* Start the System WatchDog Timer */
+	sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL;
+	mmio_write_32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE));
+}
+
+void rcar_swdt_release(void)
+{
+	uintptr_t itarget = SWDT_GICD_ITARGETSR +
+	    (ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
+	uint32_t i;
+
+	write_daifset(DAIF_FIQ_BIT);
+	swdt_disable();
+	gicv2_cpuif_disable();
+
+	for (i = 0; i < IGROUPR_NUM; i++)
+		mmio_write_32(SWDT_GICD_IGROUPR + i * 4, 0U);
+
+	for (i = 0; i < ISPRIORITY_NUM; i++)
+		mmio_write_32(SWDT_GICD_ISPRIORITYR + i * 4, 0U);
+
+	mmio_write_32(itarget, 0U);
+	mmio_write_32(SWDT_GICD_CTLR, 0U);
+	mmio_write_32(SWDT_GICC_CTLR, 0U);
+	mmio_write_32(SWDT_GICC_PMR, 0U);
+}
+
+void rcar_swdt_exec(uint64_t p)
+{
+	gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
+	rcar_swdt_release();
+	ERROR("\n");
+	ERROR("System WDT overflow, occured address is %p\n", (void *)p);
+	panic();
+}
diff --git a/drivers/staging/renesas/rcar/ddr/boot_init_dram.h b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h
new file mode 100644
index 0000000..7ec2930
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/boot_init_dram.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	__BOOT_INIT_DRAM_
+#define	__BOOT_INIT_DRAM_
+
+extern int32_t rcar_dram_init(void);
+
+#define INITDRAM_OK (0)
+#define INITDRAM_NG (0xffffffff)
+#define INITDRAM_ERR_I (0xffffffff)
+#define INITDRAM_ERR_O (0xfffffffe)
+#define INITDRAM_ERR_T (0xfffffff0)
+
+#endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr.mk b/drivers/staging/renesas/rcar/ddr/ddr.mk
new file mode 100644
index 0000000..ef13413
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_E3})
+    include drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
+else
+    include drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
+endif
+
+BL2_SOURCES += drivers/staging/renesas/rcar/ddr/dram_sub_func.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h
new file mode 100644
index 0000000..80e3eec
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef BOOT_INIT_DRAM_REGDEF_E3_H_
+#define BOOT_INIT_DRAM_REGDEF_E3_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif				/* __cplusplus */
+
+#define				BIT0						0x00000001U
+#define				BIT11						0x00000800U
+#define				BIT30						0x40000000U
+
+/* DBSC registers */
+
+#define				DBSC_E3_DBSYSCONF1         0xE6790004U
+#define				DBSC_E3_DBPHYCONF0         0xE6790010U
+#define				DBSC_E3_DBKIND             0xE6790020U
+#define				DBSC_E3_DBMEMCONF00        0xE6790030U
+#define				DBSC_E3_DBSYSCNT0          0xE6790100U
+#define				DBSC_E3_DBACEN             0xE6790200U
+#define				DBSC_E3_DBRFEN             0xE6790204U
+#define				DBSC_E3_DBCMD              0xE6790208U
+#define				DBSC_E3_DBWAIT             0xE6790210U
+#define				DBSC_E3_DBTR0              0xE6790300U
+#define				DBSC_E3_DBTR1              0xE6790304U
+#define				DBSC_E3_DBTR2              0xE6790308U
+#define				DBSC_E3_DBTR3              0xE679030CU
+#define				DBSC_E3_DBTR4              0xE6790310U
+#define				DBSC_E3_DBTR5              0xE6790314U
+#define				DBSC_E3_DBTR6              0xE6790318U
+#define				DBSC_E3_DBTR7              0xE679031CU
+#define				DBSC_E3_DBTR8              0xE6790320U
+#define				DBSC_E3_DBTR9              0xE6790324U
+#define				DBSC_E3_DBTR10             0xE6790328U
+#define				DBSC_E3_DBTR11             0xE679032CU
+#define				DBSC_E3_DBTR12             0xE6790330U
+#define				DBSC_E3_DBTR13             0xE6790334U
+#define				DBSC_E3_DBTR14             0xE6790338U
+#define				DBSC_E3_DBTR15             0xE679033CU
+#define				DBSC_E3_DBTR16             0xE6790340U
+#define				DBSC_E3_DBTR17             0xE6790344U
+#define				DBSC_E3_DBTR18             0xE6790348U
+#define				DBSC_E3_DBTR19             0xE679034CU
+#define				DBSC_E3_DBTR20             0xE6790350U
+#define				DBSC_E3_DBTR21             0xE6790354U
+#define				DBSC_E3_DBBL               0xE6790400U
+#define				DBSC_E3_DBRFCNF1           0xE6790414U
+#define				DBSC_E3_DBRFCNF2           0xE6790418U
+#define				DBSC_E3_DBCALCNF           0xE6790424U
+#define				DBSC_E3_DBODT0             0xE6790460U
+#define				DBSC_E3_DBADJ0             0xE6790500U
+#define				DBSC_E3_DBDFICUPDCNF       0xE679052CU
+#define				DBSC_E3_DBDFICNT0          0xE6790604U
+#define				DBSC_E3_DBPDLK0            0xE6790620U
+#define				DBSC_E3_DBPDRGA0           0xE6790624U
+#define				DBSC_E3_DBPDRGD0           0xE6790628U
+#define				DBSC_E3_DBBUS0CNF1         0xE6790804U
+#define				DBSC_E3_DBCAM0CNF1         0xE6790904U
+#define				DBSC_E3_DBCAM0CNF2         0xE6790908U
+#define				DBSC_E3_DBCAM0STAT0        0xE6790980U
+#define				DBSC_E3_DBBCAMDIS          0xE67909FCU
+#define				DBSC_E3_DBSCHCNT0          0xE6791000U
+#define				DBSC_E3_DBSCHSZ0           0xE6791010U
+#define				DBSC_E3_DBSCHRW0           0xE6791020U
+#define				DBSC_E3_DBSCHRW1           0xE6791024U
+#define				DBSC_E3_DBSCHQOS00         0xE6791030U
+#define				DBSC_E3_DBSCHQOS01         0xE6791034U
+#define				DBSC_E3_DBSCHQOS02         0xE6791038U
+#define				DBSC_E3_DBSCHQOS03         0xE679103CU
+#define				DBSC_E3_DBSCHQOS40         0xE6791070U
+#define				DBSC_E3_DBSCHQOS41         0xE6791074U
+#define				DBSC_E3_DBSCHQOS42         0xE6791078U
+#define				DBSC_E3_DBSCHQOS43         0xE679107CU
+#define				DBSC_E3_DBSCHQOS90         0xE67910C0U
+#define				DBSC_E3_DBSCHQOS91         0xE67910C4U
+#define				DBSC_E3_DBSCHQOS92         0xE67910C8U
+#define				DBSC_E3_DBSCHQOS93         0xE67910CCU
+#define				DBSC_E3_DBSCHQOS130        0xE6791100U
+#define				DBSC_E3_DBSCHQOS131        0xE6791104U
+#define				DBSC_E3_DBSCHQOS132        0xE6791108U
+#define				DBSC_E3_DBSCHQOS133        0xE679110CU
+#define				DBSC_E3_DBSCHQOS140        0xE6791110U
+#define				DBSC_E3_DBSCHQOS141        0xE6791114U
+#define				DBSC_E3_DBSCHQOS142        0xE6791118U
+#define				DBSC_E3_DBSCHQOS143        0xE679111CU
+#define				DBSC_E3_DBSCHQOS150        0xE6791120U
+#define				DBSC_E3_DBSCHQOS151        0xE6791124U
+#define				DBSC_E3_DBSCHQOS152        0xE6791128U
+#define				DBSC_E3_DBSCHQOS153        0xE679112CU
+#define				DBSC_E3_SCFCTST0           0xE6791700U
+#define				DBSC_E3_SCFCTST1           0xE6791708U
+#define				DBSC_E3_SCFCTST2           0xE679170CU
+
+/* CPG registers */
+
+#define				CPG_SRCR4                  0xE61500BCU
+#define				CPG_PLLECR                 0xE61500D0U
+#define				CPG_CPGWPR                 0xE6150900U
+#define				CPG_CPGWPCR                0xE6150904U
+#define				CPG_SRSTCLR4               0xE6150950U
+
+/* MODE Monitor registers */
+
+#define				RST_MODEMR                 0xE6160060U
+
+#ifdef __cplusplus
+}
+#endif				/* __cplusplus */
+#endif				/* BOOT_INIT_DRAM_REGDEF_E3_H_ */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
new file mode 100644
index 0000000..2b93891
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_a.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
new file mode 100644
index 0000000..800105e
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
@@ -0,0 +1,1544 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#include <stdint.h>
+#include <debug.h>
+
+#include "boot_init_dram_regdef_e3.h"
+#include "ddr_init_e3.h"
+
+#include "../dram_sub_func.h"
+
+/*  rev.0.04 add variables */
+/*******************************************************************************
+ *  variables
+ ******************************************************************************/
+uint32_t ddrBackup;
+
+/*  rev.0.03 add Prototypes */
+/*******************************************************************************
+ *  Prototypes
+ ******************************************************************************/
+/* static uint32_t init_ddr(void); rev.0.04 */
+/* static uint32_t recovery_from_backup_mode(void);  rev.0.04 */
+/* int32_t dram_update_boot_status(uint32_t status); rev.0.04 */
+
+/*  rev.0.03 add Comment */
+/*******************************************************************************
+ *  register write/read function
+ ******************************************************************************/
+static void    WriteReg_32(uint32_t a, uint32_t v)
+{
+    (*(volatile uint32_t*)(uintptr_t)a) = v;
+} /*  WriteReg_32 */
+
+static uint32_t ReadReg_32(uint32_t a)
+{
+    uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
+    return w;
+} /*  ReadReg_32 */
+
+/*  rev.0.04 add Comment */
+/*******************************************************************************
+ *  Initialize ddr
+ ******************************************************************************/
+uint32_t init_ddr(void)
+{
+
+   uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
+   uint32_t ddr_md;
+
+/* rev.0.08 */
+   uint32_t RegVal,j;
+   uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
+   uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
+   uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
+
+/* rev.0.08 */
+   if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
+     pdqsr_ctl  = 1;
+     lcdl_ctl   = 1;
+    }else {
+     pdqsr_ctl  = 0;
+     lcdl_ctl   = 0;
+   }
+
+   /*  Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
+   ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
+
+   /*  1584Mbps setting */
+   if (ddr_md==0){
+      /* CPG setting ===============================================*/
+      WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
+      WriteReg_32(CPG_CPGWPCR,0xA5A50000);
+
+      WriteReg_32(CPG_SRCR4,0x20000000);
+
+      WriteReg_32(0xE61500DC,0xe2200000);  /*  Change to 1584Mbps */
+      while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
+
+      WriteReg_32(CPG_SRSTCLR4,0x20000000);
+
+      WriteReg_32(CPG_CPGWPCR,0xA5A50001);
+
+      /* CPG setting ===============================================*/
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_E3_DBKIND,0x00000007);
+
+
+#if RCAR_DRAM_DDR3L_MEMCONF == 0
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02); /*  1GB */
+#elif RCAR_DRAM_DDR3L_MEMCONF == 1
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /*  2GB(default) */
+#elif RCAR_DRAM_DDR3L_MEMCONF == 2
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02); /*  4GB */
+#else
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /*  2GB */
+#endif
+
+#if RCAR_DRAM_DDR3L_MEMDUAL == 1
+         RegVal_R2 = (ReadReg_32(0xE6790614));
+         WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /*  MCS1_N/MODT1 are activated. */
+#endif
+
+
+
+   WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR1,0x00000008);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR1,0x00000009);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR2,0x00000000);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
+      WriteReg_32(DBSC_E3_DBTR5,0x00000027);
+      WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
+      WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
+      WriteReg_32(DBSC_E3_DBTR6,0x00000020);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR7,0x00060006);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR8,0x00000020);
+      WriteReg_32(DBSC_E3_DBTR9,0x00000006);
+      WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
+      WriteReg_32(DBSC_E3_DBTR12,0x00120012);
+      WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
+      WriteReg_32(DBSC_E3_DBTR14,0x00140005);
+      WriteReg_32(DBSC_E3_DBTR15,0x00050004);
+      WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
+      WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR8,0x00000021);
+      WriteReg_32(DBSC_E3_DBTR9,0x00000007);
+      WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
+      WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR12,0x00140014);
+      WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
+      WriteReg_32(DBSC_E3_DBTR14,0x00170006);
+      WriteReg_32(DBSC_E3_DBTR15,0x00060005);
+      WriteReg_32(DBSC_E3_DBTR16,0x09210507);
+      WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR18,0x00000200);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR19,0x01000040);
+      WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
+      WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR21,0x00040004);
+   WriteReg_32(DBSC_E3_DBBL,0x00000000);
+   WriteReg_32(DBSC_E3_DBODT0,0x00000001);
+   WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
+   WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
+   } /*  ddr_md */
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step0( INITBYP )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
+   WriteReg_32(DBSC_E3_DBCMD,0x01840001);
+   WriteReg_32(DBSC_E3_DBCMD,0x08840000);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058904);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A04);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step2( DRAMRST/DRAMINT training )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      if (REFRESH_RATE > 3900) {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018);  /*            [7]SRT=0 */
+      } else {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098);  /*            [7]SRT=1 */
+      }
+   } else {                                        /*  1856Mbps */
+      if (REFRESH_RATE > 3900) {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020);  /*            [7]SRT=0 */
+      } else {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0);  /*            [7]SRT=1 */
+      } /*  REFRESH_RATE */
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010181);
+   WriteReg_32(DBSC_E3_DBCMD,0x08840001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step3( WL/QSG training )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010601);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step4( WLADJ training )
+    ***************************************************************************/
+   for ( i = 0; i<4; i++){
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+      if ( RegVal_R6 > 0 ){
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+      } else {
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+      } /*  RegVal_R6 */
+   } /*  for i */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
+
+   /* rev.0.08 */
+   if (pdqsr_ctl == 1){}else{
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+
+   }
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step5678( RdWrbitRdWreye )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
+
+   /* rev.0.08 */
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+if (pdqsr_ctl == 1){
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+}
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+if (pdqsr_ctl == 1){
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+}
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+if (pdqsr_ctl == 1){
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+}
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step3_2( DQS Gate Training )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step5-2_7-2( Rd bit Rd eye )
+    ***************************************************************************/
+   for ( i = 0; i < 4; i++){
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+      RegVal_R12 = (RegVal_R5 >> 0x2);
+      if ( RegVal_R12 < RegVal_R6 ){
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+      } else {
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+      } /*  RegVal_R12 < RegVal_R6 */
+   } /*  for i */
+
+/* rev.0.08 */
+   if (pdqsr_ctl == 1){}else{
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+
+   }
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+
+/* rev.0.08 */
+   if (lcdl_ctl == 1){
+       for (i=0; i< 4; i++) {
+          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+          dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+          bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
+          bdlcount_0c_div2  = (bdlcount_0c >> 1);
+          bdlcount_0c_div4  = (bdlcount_0c >> 2);
+          bdlcount_0c_div8  = (bdlcount_0c >> 3);
+          bdlcount_0c_div16 = (bdlcount_0c >> 4);
+
+          if (ddr_md==0){                                 /*  1584Mbps */
+             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
+             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
+          } else {                                        /*  1856Mbps */
+             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
+             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
+          } /*  ddr_md */
+
+          if (dqsgd_0c > lcdl_judge1) {
+             if (dqsgd_0c <= lcdl_judge2) {
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
+              } else {
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+                gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
+                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal      ) & 0x0000001f;
+                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j=0; j< 4; j++) {
+                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] <<8*j);
+                }
+                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal      ) & 0x0000001f;
+                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j=0; j< 4; j++) {
+                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] <<8*j);
+                }
+                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+             }
+          }
+       }
+       WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
+       WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
+   }
+
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
+
+   WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
+   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_E3_DBACEN,0x00000001);
+
+/* rev.0.08 */
+   if (pdqsr_ctl == 1){
+   WriteReg_32(0xE67F0018,0x00000001);
+   RegVal = ReadReg_32(0x40000000);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
+   WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+
+   }
+
+
+   /*  rev.0.03 add Comment */
+   /****************************************************************************
+    *  Initial_Step9( Initial End )
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+
+#ifdef ddr_qos_init_setting /*  only for non qos_init */
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
+   WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
+   WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
+   WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
+   WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
+   WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
+   WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
+   WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
+   WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
+   WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
+   WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
+   WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
+   WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
+   WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
+   WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
+
+/* rev.0.08 */
+   if (pdqsr_ctl == 1){}else{
+   WriteReg_32(0xE67F0018,0x00000001);
+   }
+
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+#endif
+
+   return 1;   /*  rev.0.04 Restore the return code */
+
+} /*  init_ddr */
+
+/*  rev.0.04 add function */
+uint32_t recovery_from_backup_mode(void)
+{
+
+   /****************************************************************************
+    *  recovery_Step0(DBSC Setting 1) / same "init_ddr"
+    ***************************************************************************/
+   uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
+   uint32_t ddr_md;
+   uint32_t err;
+
+
+/* rev.0.08 */
+   uint32_t RegVal,j;
+   uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
+   uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
+   uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
+
+/* rev.0.08 */
+   if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
+     pdqsr_ctl  = 1;
+     lcdl_ctl   = 1;
+    }else {
+     pdqsr_ctl  = 0;
+     lcdl_ctl   = 0;
+   }
+
+
+   /*  Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
+   ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
+
+   /*  1584Mbps setting */
+   if (ddr_md==0){
+   /* CPG setting ===============================================*/
+   WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
+   WriteReg_32(CPG_CPGWPCR,0xA5A50000);
+
+   WriteReg_32(CPG_SRCR4,0x20000000);
+
+   WriteReg_32(0xE61500DC,0xe2200000);  /*  Change to 1584Mbps */
+   while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
+
+   WriteReg_32(CPG_SRSTCLR4,0x20000000);
+
+   WriteReg_32(CPG_CPGWPCR,0xA5A50001);
+
+   /* CPG setting ===============================================*/
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_E3_DBKIND,0x00000007);
+
+#if RCAR_DRAM_DDR3L_MEMCONF == 0
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02);
+#elif RCAR_DRAM_DDR3L_MEMCONF == 1
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
+#elif RCAR_DRAM_DDR3L_MEMCONF == 2
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02);
+#else
+   WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
+#endif
+
+/* rev.0.08 */
+#if RCAR_DRAM_DDR3L_MEMDUAL == 1
+         RegVal_R2 = (ReadReg_32(0xE6790614));
+         WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /*  MCS1_N/MODT1 are activated. */
+#endif
+
+   WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR1,0x00000008);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR1,0x00000009);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR2,0x00000000);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
+      WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
+      WriteReg_32(DBSC_E3_DBTR5,0x00000027);
+      WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
+      WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
+      WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
+      WriteReg_32(DBSC_E3_DBTR6,0x00000020);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR7,0x00060006);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR8,0x00000020);
+      WriteReg_32(DBSC_E3_DBTR9,0x00000006);
+      WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
+      WriteReg_32(DBSC_E3_DBTR12,0x00120012);
+      WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
+      WriteReg_32(DBSC_E3_DBTR14,0x00140005);
+      WriteReg_32(DBSC_E3_DBTR15,0x00050004);
+      WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
+      WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR8,0x00000021);
+      WriteReg_32(DBSC_E3_DBTR9,0x00000007);
+      WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
+      WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
+      WriteReg_32(DBSC_E3_DBTR12,0x00140014);
+      WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
+      WriteReg_32(DBSC_E3_DBTR14,0x00170006);
+      WriteReg_32(DBSC_E3_DBTR15,0x00060005);
+      WriteReg_32(DBSC_E3_DBTR16,0x09210507);
+      WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR18,0x00000200);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBTR19,0x01000040);
+      WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
+      WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBTR21,0x00040004);
+   WriteReg_32(DBSC_E3_DBBL,0x00000000);
+   WriteReg_32(DBSC_E3_DBODT0,0x00000001);
+   WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
+   WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
+   WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
+   WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
+      WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
+   } /*  ddr_md */
+
+   /****************************************************************************
+    *  recovery_Step1(PHY setting 1)
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
+   WriteReg_32(DBSC_E3_DBCMD,0x01840001);
+   WriteReg_32(DBSC_E3_DBCMD,0x0A840000);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008); /*  DDR_PLLCR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003); /*  DDR_PGCR1 */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020); /*  DDR_DXCCR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A); /*  DDR_ACIOCR0 */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      if (REFRESH_RATE > 3900) {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018);  /*            [7]SRT=0 */
+      } else {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098);  /*            [7]SRT=1 */
+      }
+   } else {                                        /*  1856Mbps */
+      if (REFRESH_RATE > 3900) {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020);  /*            [7]SRT=0 */
+      } else {
+          WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0);  /*            [7]SRT=1 */
+      } /*  REFRESH_RATE */
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021); /*  DDR_DSGCR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x40010000);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /*  DDR_ZQ0DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /*  DDR_ZQ1DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0xC4285FBF);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /*  DDR_ZQ2DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00050001);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   /*  ddr backupmode end */
+   if(ddrBackup) {
+      NOTICE("[WARM_BOOT]");
+   } else {
+      NOTICE("[COLD_BOOT]");
+   } /*  ddrBackup */
+   err=dram_update_boot_status(ddrBackup);
+   if(err){
+      NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
+      return INITDRAM_ERR_I;
+   } /*  err */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /*  DDR_ZQ0DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /*  DDR_ZQ1DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x04285FBF);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /*  DDR_ZQ2DR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x08000000);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00000003);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /*  DDR_ZQCR */
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
+   } /*  ddr_md */
+
+/* rev0.08 */
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000000C);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x18000040);
+
+   /****************************************************************************
+    *  recovery_Step2(PHY setting 2)
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
+
+   WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
+   WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
+
+   /*  Select setting value in bps */
+   if (ddr_md==0){                                 /*  1584Mbps */
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
+   } else {                                        /*  1856Mbps */
+      WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
+   } /*  ddr_md */
+
+   WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
+   WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
+   WriteReg_32(DBSC_E3_DBCMD,0x0A840001);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
+
+   WriteReg_32(DBSC_E3_DBCMD,0x00000000);
+
+   WriteReg_32(DBSC_E3_DBCMD,0x04840010);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /*  DDR_PIR */
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010701);
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /*  DDR_PGSR0 */
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   for ( i = 0; i<4; i++)
+   {
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+
+      if ( RegVal_R6 > 0 ){
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
+      } else {
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
+      } /*  RegVal_R6 */
+   } /*  for i */
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
+
+   /* rev.0.08 */
+   if (pdqsr_ctl == 1){}else{
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+
+   }
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
+
+
+   /* rev.0.08 */
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+if (pdqsr_ctl == 1){
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+}
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+if (pdqsr_ctl == 1){
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+}
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+if (pdqsr_ctl == 1){
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+}
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+   for ( i = 0; i < 4; i++){
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+      RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
+      RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+      WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
+      RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+      RegVal_R12 = (RegVal_R5 >> 0x2);
+
+      if ( RegVal_R12 < RegVal_R6 ){
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
+      } else {
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+         WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+         WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
+      } /*  RegVal_R12 < RegVal_R6 */
+   } /*  for i */
+
+/* rev.0.08 */
+   if (pdqsr_ctl == 1){}else{
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+
+   }
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
+   while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
+
+
+/* rev.0.08 */
+   if (lcdl_ctl == 1){
+       for (i=0; i< 4; i++) {
+          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
+          dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
+          WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
+          bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
+          bdlcount_0c_div2  = (bdlcount_0c >> 1);
+          bdlcount_0c_div4  = (bdlcount_0c >> 2);
+          bdlcount_0c_div8  = (bdlcount_0c >> 3);
+          bdlcount_0c_div16 = (bdlcount_0c >> 4);
+
+          if (ddr_md==0){                                 /*  1584Mbps */
+             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
+             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
+          } else {                                        /*  1856Mbps */
+             lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
+             lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
+          } /*  ddr_md */
+
+          if (dqsgd_0c > lcdl_judge1) {
+             if (dqsgd_0c <= lcdl_judge2) {
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
+              } else {
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
+                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+                gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
+                WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
+                rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
+                WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal      ) & 0x0000001f;
+                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j=0; j< 4; j++) {
+                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] <<8*j);
+                }
+                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
+                rbd_0c[0] = (RegVal      ) & 0x0000001f;
+                rbd_0c[1] = (RegVal >>  8) & 0x0000001f;
+                rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
+                rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
+                WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
+                RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
+                for (j=0; j< 4; j++) {
+                    rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
+                    if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
+                    RegVal = RegVal | (rbd_0c[j] <<8*j);
+                }
+                WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
+             }
+          }
+       }
+       WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
+       WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
+   }
+
+
+
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
+   while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
+
+   /****************************************************************************
+    *  recovery_Step3(DBSC Setting 2)
+    ***************************************************************************/
+   WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
+   WriteReg_32(DBSC_E3_DBACEN,0x00000001);
+
+/* rev.0.08 */
+   if (pdqsr_ctl == 1){
+   WriteReg_32(0xE67F0018,0x00000001);
+   RegVal = ReadReg_32(0x40000000);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
+   WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+   WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
+   WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
+
+   }
+
+
+   WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+
+#ifdef ddr_qos_init_setting /*  only for non qos_init */
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
+   WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
+   WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
+   WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
+   WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
+   WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
+   WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
+   WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
+   WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
+   WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
+   WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
+   WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
+   WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
+   WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
+   WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
+   WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
+   WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
+   WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
+   WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
+   WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
+   WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
+   WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
+
+/* rev.0.08 */
+   if (pdqsr_ctl == 1){}else{
+   WriteReg_32(0xE67F0018,0x00000001);
+   }
+
+   WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
+#endif
+
+   return 1;
+
+} /*  recovery_from_backup_mode */
+
+/*******************************************************************************
+ *      init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps
+ ******************************************************************************/
+
+/*******************************************************************************
+ *  DDR Initialize entry for IPL
+ ******************************************************************************/
+int32_t InitDram(void)
+{
+    uint32_t dataL;
+    uint32_t failcount;
+    uint32_t md=0;
+    uint32_t ddr=0;
+
+    md = *((volatile uint32_t*)RST_MODEMR);
+    ddr = (md & 0x00080000) >> 19;
+    if(ddr == 0x0){
+        NOTICE("BL2: DDR1584(%s)", RCAR_E3_DDR_VERSION);
+    }
+    else if(ddr == 0x1){
+        NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
+    } /*  ddr */
+
+    dram_get_boot_status(&ddrBackup);
+
+    if(ddrBackup==DRAM_BOOT_STATUS_WARM){
+        dataL=recovery_from_backup_mode(); /*  WARM boot */
+    } else {
+        dataL=init_ddr();                  /*  COLD boot */
+    } /*  ddrBackup */
+
+    if(dataL==1){
+        failcount =0;
+    } else {
+        failcount =1;
+    } /*  dataL */
+
+    NOTICE("..%d\n",failcount); /*  rev.0.05 */
+
+    if(failcount==0){
+        return INITDRAM_OK;
+    } else {
+        return INITDRAM_NG;
+    } /*  failcount */
+} /*  InitDram */
+
+/*******************************************************************************
+ *  END
+ ******************************************************************************/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
new file mode 100644
index 0000000..b202b02
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#pragma once
+#include <stdint.h>
+
+#ifndef	__DDR_INIT_E3_
+#define	__DDR_INIT_E3_
+
+#define RCAR_E3_DDR_VERSION    "rev.0.09"
+
+#ifdef ddr_qos_init_setting
+   #define REFRESH_RATE  3900               /*  Average periodic refresh interval[ns]. Support 3900,7800 */
+#else
+   #if RCAR_REF_INT == 0
+      #define REFRESH_RATE  3900
+   #elif RCAR_REF_INT == 1
+      #define REFRESH_RATE  7800
+   #else
+      #define REFRESH_RATE  3900
+   #endif
+#endif
+
+extern int32_t InitDram(void);
+#define INITDRAM_OK (0)
+#define INITDRAM_NG (0xffffffff)
+#define INITDRAM_ERR_I (0xffffffff)
+#define INITDRAM_ERR_O (0xfffffffe)
+#define INITDRAM_ERR_T (0xfffffff0)
+
+#endif /* __DDR_INIT_E3_ */
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
new file mode 100644
index 0000000..d729131
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -0,0 +1,4467 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+#include <mmio.h>
+#include <debug.h>
+#include "ddr_regdef.h"
+#include "init_dram_tbl_h3.h"
+#include "init_dram_tbl_m3.h"
+#include "init_dram_tbl_h3ver2.h"
+#include "init_dram_tbl_m3n.h"
+#include "boot_init_dram_regdef.h"
+#include "boot_init_dram.h"
+#include "dram_sub_func.h"
+#include "micro_delay.h"
+
+#define DDR_BACKUPMODE
+#define FATAL_MSG(x) NOTICE(x)
+
+/*******************************************************************************
+ *	variables
+ ******************************************************************************/
+#ifdef RCAR_DDR_FIXED_LSI_TYPE
+#ifndef RCAR_AUTO
+#define RCAR_AUTO	99
+#define RCAR_H3	0
+#define RCAR_M3	1
+#define RCAR_M3N	2
+#define RCAR_E3	3		/*  NON */
+#define RCAR_H3N	4
+
+#define RCAR_CUT_10	0
+#define RCAR_CUT_11	1
+#define RCAR_CUT_20	10
+#define RCAR_CUT_30	20
+#endif
+#ifndef RCAR_LSI
+#define RCAR_LSI	RCAR_AUTO
+#endif
+#if(RCAR_LSI==RCAR_AUTO)
+static uint32_t Prr_Product;
+static uint32_t Prr_Cut;
+#else
+#if(RCAR_LSI==RCAR_H3)
+static const uint32_t Prr_Product = PRR_PRODUCT_H3;
+#elif(RCAR_LSI==RCAR_M3)
+static const uint32_t Prr_Product = PRR_PRODUCT_M3;
+#elif(RCAR_LSI==RCAR_M3N)
+static const uint32_t Prr_Product = PRR_PRODUCT_M3N;
+#elif(RCAR_LSI==RCAR_H3N)
+static const uint32_t Prr_Product = PRR_PRODUCT_H3;
+#endif /* RCAR_LSI */
+
+#ifndef RCAR_LSI_CUT
+static uint32_t Prr_Cut;
+#else /* RCAR_LSI_CUT */
+#if(RCAR_LSI_CUT==RCAR_CUT_10)
+static const uint32_t Prr_Cut = PRR_PRODUCT_10;
+#elif(RCAR_LSI_CUT==RCAR_CUT_11)
+static const uint32_t Prr_Cut = PRR_PRODUCT_11;
+#elif(RCAR_LSI_CUT==RCAR_CUT_20)
+static const uint32_t Prr_Cut = PRR_PRODUCT_20;
+#elif(RCAR_LSI_CUT==RCAR_CUT_30)
+static const uint32_t Prr_Cut = PRR_PRODUCT_30;
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_AUTO_NON */
+#else /* RCAR_DDR_FIXED_LSI_TYPE */
+static uint32_t Prr_Product;
+static uint32_t Prr_Cut;
+#endif /* RCAR_DDR_FIXED_LSI_TYPE */
+
+char *pRCAR_DDR_VERSION;
+uint32_t _cnf_BOARDTYPE;
+static uint32_t *pDDR_REGDEF_TBL;
+static uint32_t brd_clk;
+static uint32_t brd_clkdiv;
+static uint32_t brd_clkdiva;
+static uint32_t ddr_mbps;
+static uint32_t ddr_mbpsdiv;
+static uint32_t ddr_tccd;
+static struct _boardcnf *Boardcnf;
+uint32_t ddr_phyvalid;
+uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
+static uint32_t ch_have_this_cs[CS_CNT];
+static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2];
+
+static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t max_density;
+static uint32_t ddr0800_mul;
+static uint32_t ddr_mul;
+static uint32_t ddr_mbps;
+static uint32_t DDR_PHY_SLICE_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_G_REGSET_OFS;
+static uint32_t DDR_PI_REGSET_OFS;
+static uint32_t DDR_PHY_SLICE_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_V_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_I_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_G_REGSET_SIZE;
+static uint32_t DDR_PI_REGSET_SIZE;
+static uint32_t DDR_PHY_SLICE_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_V_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_I_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_G_REGSET_NUM;
+static uint32_t DDR_PI_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_I_NUM;
+#define DDR_PHY_REGSET_MAX 128
+#define DDR_PI_REGSET_MAX 320
+static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
+static uint32_t Pll3Mode;
+static uint32_t loop_max;
+#ifdef DDR_BACKUPMODE
+uint32_t ddrBackup;
+/* #define DDR_BACKUPMODE_HALF           //for Half channel(ch0,1 only) */
+#endif
+
+#ifdef ddr_qos_init_setting	/*  only for non qos_init */
+#define OPERATING_FREQ			(400U)	/* Mhz */
+#define BASE_SUB_SLOT_NUM		(0x6U)
+#define SUB_SLOT_CYCLE			(0x7EU)	/* 126 */
+#define QOSWT_WTSET0_CYCLE		((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+
+uint32_t get_refperiod(void)
+{
+	return QOSWT_WTSET0_CYCLE;
+}
+#else /*  ddr_qos_init_setting // only for non qos_init */
+extern uint32_t get_refperiod(void);
+#endif /* ddr_qos_init_setting // only for non qos_init */
+
+#define _reg_PHY_RX_CAL_X_NUM 11
+static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
+	_reg_PHY_RX_CAL_DQ0,
+	_reg_PHY_RX_CAL_DQ1,
+	_reg_PHY_RX_CAL_DQ2,
+	_reg_PHY_RX_CAL_DQ3,
+	_reg_PHY_RX_CAL_DQ4,
+	_reg_PHY_RX_CAL_DQ5,
+	_reg_PHY_RX_CAL_DQ6,
+	_reg_PHY_RX_CAL_DQ7,
+	_reg_PHY_RX_CAL_DM,
+	_reg_PHY_RX_CAL_DQS,
+	_reg_PHY_RX_CAL_FDBK
+};
+
+#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10
+static const uint32_t
+    _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
+	_reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQ3_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQ4_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQ5_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQ6_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQ7_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDM_SLAVE_DELAY,
+	_reg_PHY_CLK_WRDQS_SLAVE_DELAY
+};
+
+#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9
+static const uint32_t
+    _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
+	_reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY
+};
+
+#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9
+static const uint32_t
+    _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
+	_reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY,
+	_reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY
+};
+
+#define _reg_PHY_PAD_TERM_X_NUM 8
+static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
+	_reg_PHY_PAD_FDBK_TERM,
+	_reg_PHY_PAD_DATA_TERM,
+	_reg_PHY_PAD_DQS_TERM,
+	_reg_PHY_PAD_ADDR_TERM,
+	_reg_PHY_PAD_CLK_TERM,
+	_reg_PHY_PAD_CKE_TERM,
+	_reg_PHY_PAD_RST_TERM,
+	_reg_PHY_PAD_CS_TERM
+};
+
+#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10
+static const uint32_t
+    _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
+	_reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
+	_reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
+	_reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
+	_reg_PHY_ADR3_CLK_WR_SLAVE_DELAY,
+	_reg_PHY_ADR4_CLK_WR_SLAVE_DELAY,
+	_reg_PHY_ADR5_CLK_WR_SLAVE_DELAY,
+
+	_reg_PHY_GRP_SLAVE_DELAY_0,
+	_reg_PHY_GRP_SLAVE_DELAY_1,
+	_reg_PHY_GRP_SLAVE_DELAY_2,
+	_reg_PHY_GRP_SLAVE_DELAY_3
+};
+
+/*******************************************************************************
+ *	Prototypes
+ ******************************************************************************/
+static inline int32_t vch_nxt(int32_t pos);
+static void cpg_write_32(uint32_t a, uint32_t v);
+static void pll3_control(uint32_t high);
+static inline void dsb_sev(void);
+static void wait_dbcmd(void);
+static void send_dbcmd(uint32_t cmd);
+static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
+static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
+static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
+static inline uint32_t ddr_regdef(uint32_t _regdef);
+static inline uint32_t ddr_regdef_adr(uint32_t _regdef);
+static inline uint32_t ddr_regdef_lsb(uint32_t _regdef);
+static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
+			 uint32_t val);
+static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
+static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
+static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
+static void ddr_setval_ach(uint32_t regdef, uint32_t val);
+static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
+static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p);
+/* NOT USED
+static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p);
+*/
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p);
+static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
+static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val);
+static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef);
+static uint32_t ddrphy_regif_chk(void);
+static inline void ddrphy_regif_idle();
+static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
+			 uint16_t cyc);
+static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
+			 uint16_t * js2);
+static int16_t _f_scale_adj(int16_t ps);
+static void ddrtbl_load(void);
+static void ddr_config_sub(void);
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz);
+static void ddr_config_sub_h3v1x(void);
+static void ddr_config(void);
+static void dbsc_regset(void);
+static void dbsc_regset_post(void);
+static uint32_t dfi_init_start(void);
+static void change_lpddr4_en(uint32_t mode);
+static uint32_t set_term_code(void);
+static void ddr_register_set(uint32_t ch);
+static inline uint32_t wait_freqchgreq(uint32_t assert);
+static inline void set_freqchgack(uint32_t assert);
+static inline void set_dfifrequency(uint32_t freq);
+static uint32_t pll3_freq(uint32_t on);
+static void update_dly(void);
+static uint32_t pi_training_go(void);
+static uint32_t init_ddr(void);
+static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
+static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t wdqdm_man1(void);
+static uint32_t wdqdm_man(void);
+static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t rdqdm_man1(void);
+static uint32_t rdqdm_man(void);
+
+static int32_t _find_change(uint64_t val, uint32_t dir);
+static uint32_t _rx_offset_cal_updn(uint32_t code);
+static uint32_t rx_offset_cal(void);
+static uint32_t rx_offset_cal_hw(void);
+static void adjust_rddqs_latency(void);
+static void adjust_wpath_latency(void);
+
+struct DdrtData {
+	int32_t init_temp;	/*  Initial Temperature (do) */
+	uint32_t init_cal[4];	/*  Initial io-code (4 is for H3) */
+	uint32_t tcomp_cal[4];	/*  Temperature compensated io-code (4 is for H3) */
+};
+struct DdrtData tcal;
+
+static void pvtcode_update(void);
+static void pvtcode_update2(void);
+static void ddr_padcal_tcompensate_getinit(uint32_t override);
+
+/*******************************************************************************
+ *	load board configuration
+ ******************************************************************************/
+#include "boot_init_dram_config.c"
+
+/*******************************************************************************
+ *	macro for channel selection loop
+ ******************************************************************************/
+static inline int32_t vch_nxt(int32_t pos)
+{
+	int32_t posn;
+
+	for (posn = pos; posn < DRAM_CH_CNT; posn++) {
+		if (ddr_phyvalid & (1U << posn))
+			break;
+	}
+	return posn;
+}
+
+#define foreach_vch(ch) \
+for(ch=vch_nxt(0);ch<DRAM_CH_CNT;ch=vch_nxt(ch+1))
+
+#define foreach_ech(ch) \
+for(ch=0;ch<DRAM_CH_CNT;ch++)
+
+/*******************************************************************************
+ *	Printing functions
+ ******************************************************************************/
+#define MSG_LF(...)
+
+/*******************************************************************************
+ *	clock settings, reset control
+ ******************************************************************************/
+static void cpg_write_32(uint32_t a, uint32_t v)
+{
+	mmio_write_32(CPG_CPGWPR, ~v);
+	mmio_write_32(a, v);
+}
+
+static void pll3_control(uint32_t high)
+{
+	uint32_t dataL, dataDIV, dataMUL, tmpDIV;
+
+	/* PLL3 disable */
+	dataL = mmio_read_32(CPG_PLLECR);
+	dataL &= ~CPG_PLLECR_PLL3E_BIT;
+	cpg_write_32(CPG_PLLECR, dataL);
+	dsb_sev();
+	cpg_write_32(CPG_FRQCRD, 0x00030003);	/* PLL3 DIV resetting */
+	dsb_sev();
+
+	/* PLL3 enable */
+	dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
+	cpg_write_32(CPG_ZB3CKCR, dataL);	/* zb3 clk stop */
+	dsb_sev();
+
+	/* PLL3 Restart */
+	dataL = mmio_read_32(CPG_PLLECR);
+	dataL |= CPG_PLLECR_PLL3E_BIT;
+	cpg_write_32(CPG_PLLECR, dataL);
+	dsb_sev();
+
+	do {
+		dataL = mmio_read_32(CPG_PLLECR);
+	} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+	dsb_sev();
+
+	if (high) {
+		/* High frequency */
+		tmpDIV =
+		    (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
+		    (ddr_mul * brd_clk * ddr_mbpsdiv + 1);
+		dataMUL =
+		    ((ddr_mul * (tmpDIV + 1) - 1) << 24) | (brd_clkdiva << 7);
+		if (tmpDIV) {
+			dataDIV = tmpDIV + 1;
+		} else {
+			dataDIV = 0;
+		}
+		Pll3Mode = 1;
+		loop_max = 2;
+	} else {
+		/* Low frequency */
+		tmpDIV =
+		    (1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
+		    (ddr0800_mul * brd_clk * ddr_mbpsdiv + 1);
+		dataMUL =
+		    ((ddr0800_mul * (tmpDIV + 1) -
+		      1) << 24) | (brd_clkdiva << 7);
+		if (tmpDIV) {
+			dataDIV = tmpDIV + 1;
+		} else {
+			dataDIV = 0;
+		}
+		Pll3Mode = 0;
+		loop_max = 8;
+	}
+
+	dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+	cpg_write_32(CPG_FRQCRD, dataL);	/* PLL3 DIV resetting */
+	dsb_sev();
+
+	dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+	cpg_write_32(CPG_FRQCRB, dataL);	/* DIV SET KICK */
+	dsb_sev();
+
+	/* PLL3 FREQ */
+	cpg_write_32(CPG_PLL3CR, dataMUL);	/* Set PLL3 freq */
+	dsb_sev();
+
+	do {
+		dataL = mmio_read_32(CPG_PLLECR);
+	} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+	dsb_sev();
+
+	dataL =
+	    (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+	cpg_write_32(CPG_FRQCRD, dataL);	/* PLL3 DIV resetting */
+	dsb_sev();
+
+	dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+	cpg_write_32(CPG_FRQCRB, dataL);	/* DIV SET KICK */
+	dsb_sev();
+
+	do {
+		dataL = mmio_read_32(CPG_PLLECR);
+	} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
+	dsb_sev();
+
+	dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
+	cpg_write_32(CPG_ZB3CKCR, dataL);	/* zb3 clk start */
+	dsb_sev();
+
+	return;
+}
+
+/*******************************************************************************
+ *	barrier
+ ******************************************************************************/
+static inline void dsb_sev(void)
+{
+	__asm__ __volatile__("dsb sy");
+}
+
+/*******************************************************************************
+ *	DDR memory register access
+ ******************************************************************************/
+static void wait_dbcmd(void)
+{
+	uint32_t dataL;
+	/* dummy read */
+	dataL = mmio_read_32(DBSC_DBCMD);
+	dsb_sev();
+	while (1) {
+		/* wait DBCMD 1=busy, 0=ready */
+		dataL = mmio_read_32(DBSC_DBWAIT);
+		dsb_sev();
+		if ((dataL & 0x00000001) == 0x00)
+			break;
+	}
+}
+
+static void send_dbcmd(uint32_t cmd)
+{
+	/* dummy read */
+	wait_dbcmd();
+	mmio_write_32(DBSC_DBCMD, cmd);
+	dsb_sev();
+}
+
+/*******************************************************************************
+ *	DDRPHY register access (raw)
+ ******************************************************************************/
+static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
+{
+	uint32_t val;
+	uint32_t loop;
+
+	val = 0;
+	if ((PRR_PRODUCT_M3N != Prr_Product)
+	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+		dsb_sev();
+
+		while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+			dsb_sev();
+		}
+		dsb_sev();
+
+		for (loop = 0; loop < loop_max; loop++) {
+			val = mmio_read_32(DBSC_DBPDRGD(phyno));
+			dsb_sev();
+		}
+		(void)val;
+	} else {
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000);
+		dsb_sev();
+		while (mmio_read_32(DBSC_DBPDRGA(phyno)) !=
+		       (regadd | 0x0000C000)) {
+			dsb_sev();
+		};
+		val = mmio_read_32(DBSC_DBPDRGA(phyno));
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
+		while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+			dsb_sev();
+		};
+		dsb_sev();
+
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
+		while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+			dsb_sev();
+		};
+
+		dsb_sev();
+		val = mmio_read_32(DBSC_DBPDRGD(phyno));
+		dsb_sev();
+		(void)val;
+	}
+	return val;
+}
+
+static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
+{
+	uint32_t val;
+	uint32_t loop;
+
+	if ((PRR_PRODUCT_M3N != Prr_Product)
+	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+		dsb_sev();
+		for (loop = 0; loop < loop_max; loop++) {
+			val = mmio_read_32(DBSC_DBPDRGA(phyno));
+			dsb_sev();
+		}
+		mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
+		dsb_sev();
+
+		for (loop = 0; loop < loop_max; loop++) {
+			val = mmio_read_32(DBSC_DBPDRGD(phyno));
+			dsb_sev();
+		}
+	} else {
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+		dsb_sev();
+
+		while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+			dsb_sev();
+		};
+		dsb_sev();
+
+		mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
+		dsb_sev();
+
+		while (mmio_read_32(DBSC_DBPDRGA(phyno)) !=
+		       (regadd | 0x00008000)) {
+			dsb_sev();
+		};
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
+
+		while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+			dsb_sev();
+		};
+		dsb_sev();
+
+		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+	}
+	(void)val;
+}
+
+static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
+{
+	uint32_t ch;
+	uint32_t val;
+	uint32_t loop;
+
+	if ((PRR_PRODUCT_M3N != Prr_Product)
+	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+		foreach_vch(ch) {
+			mmio_write_32(DBSC_DBPDRGA(ch), regadd);
+			dsb_sev();
+		}
+
+		foreach_vch(ch) {
+			mmio_write_32(DBSC_DBPDRGD(ch), regdata);
+			dsb_sev();
+		}
+
+		for (loop = 0; loop < loop_max; loop++) {
+			val = mmio_read_32(DBSC_DBPDRGD(0));
+			dsb_sev();
+		}
+		(void)val;
+	} else {
+		foreach_vch(ch) {
+			reg_ddrphy_write(ch, regadd, regdata);
+			dsb_sev();
+		}
+	}
+}
+
+static inline void ddrphy_regif_idle()
+{
+	uint32_t val;
+
+	val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS));
+	dsb_sev();
+	(void)val;
+}
+
+/*******************************************************************************
+ *	DDRPHY register access (field modify)
+ ******************************************************************************/
+static inline uint32_t ddr_regdef(uint32_t _regdef)
+{
+	return pDDR_REGDEF_TBL[_regdef];
+}
+
+static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
+{
+	return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]);
+}
+
+static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
+{
+	return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]);
+}
+
+static inline uint32_t ddr_regdef_len(uint32_t _regdef)
+{
+	return DDR_REGDEF_LEN(pDDR_REGDEF_TBL[_regdef]);
+}
+
+static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
+			 uint32_t val)
+{
+	uint32_t adr;
+	uint32_t lsb;
+	uint32_t len;
+	uint32_t msk;
+	uint32_t tmp;
+	uint32_t regdef;
+
+	regdef = ddr_regdef(_regdef);
+	adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
+	len = DDR_REGDEF_LEN(regdef);
+	lsb = DDR_REGDEF_LSB(regdef);
+	if (len == 0x20)
+		msk = 0xffffffff;
+	else
+		msk = ((1U << len) - 1) << lsb;
+
+	tmp = reg_ddrphy_read(ch, adr);
+	tmp = (tmp & (~msk)) | ((val << lsb) & msk);
+	reg_ddrphy_write(ch, adr, tmp);
+}
+
+static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
+{
+	uint32_t adr;
+	uint32_t lsb;
+	uint32_t len;
+	uint32_t msk;
+	uint32_t tmp;
+	uint32_t regdef;
+
+	regdef = ddr_regdef(_regdef);
+	adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
+	len = DDR_REGDEF_LEN(regdef);
+	lsb = DDR_REGDEF_LSB(regdef);
+	if (len == 0x20)
+		msk = 0xffffffff;
+	else
+		msk = ((1U << len) - 1);
+
+	tmp = reg_ddrphy_read(ch, adr);
+	tmp = (tmp >> lsb) & msk;
+
+	return tmp;
+}
+
+static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
+{
+	ddr_setval_s(ch, 0, regdef, val);
+}
+
+static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
+{
+	uint32_t ch;
+
+	foreach_vch(ch)
+	    ddr_setval_s(ch, slice, regdef, val);
+}
+
+static void ddr_setval_ach(uint32_t regdef, uint32_t val)
+{
+	ddr_setval_ach_s(0, regdef, val);
+}
+
+static void ddr_setval_ach_as(uint32_t regdef, uint32_t val)
+{
+	uint32_t slice;
+
+	for (slice = 0; slice < SLICE_CNT; slice++)
+		ddr_setval_ach_s(slice, regdef, val);
+}
+
+static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
+{
+	return ddr_getval_s(ch, 0, regdef);
+}
+
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
+{
+	uint32_t ch;
+
+	foreach_vch(ch)
+	    p[ch] = ddr_getval_s(ch, 0, regdef);
+	return p[0];
+}
+
+/* NOT_USED
+static uint32_t ddr_getval_ach_s(uint32_t slice, uint32_t regdef, uint32_t *p)
+{
+	uint32_t ch;
+
+	foreach_vch(ch)
+		p[ch] = ddr_getval_s(ch, slice, regdef);
+	return p[0];
+}
+*/
+
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
+{
+	uint32_t ch, slice;
+	uint32_t *pp;
+
+	pp = p;
+	foreach_vch(ch)
+	    for (slice = 0; slice < SLICE_CNT; slice++)
+		*pp++ = ddr_getval_s(ch, slice, regdef);
+	return p[0];
+}
+
+/*******************************************************************************
+ *	handling functions for setteing ddrphy value table
+ ******************************************************************************/
+static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size)
+{
+	uint32_t i;
+
+	for (i = 0; i < size; i++) {
+		to[i] = from[i];
+	}
+}
+
+static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val)
+{
+	uint32_t adr;
+	uint32_t lsb;
+	uint32_t len;
+	uint32_t msk;
+	uint32_t tmp;
+	uint32_t adrmsk;
+	uint32_t regdef;
+
+	regdef = ddr_regdef(_regdef);
+	adr = DDR_REGDEF_ADR(regdef);
+	len = DDR_REGDEF_LEN(regdef);
+	lsb = DDR_REGDEF_LSB(regdef);
+	if (len == 0x20)
+		msk = 0xffffffff;
+	else
+		msk = ((1U << len) - 1) << lsb;
+
+	if (adr < 0x400) {
+		adrmsk = 0xff;
+	} else {
+		adrmsk = 0x7f;
+	}
+
+	tmp = tbl[adr & adrmsk];
+	tmp = (tmp & (~msk)) | ((val << lsb) & msk);
+	tbl[adr & adrmsk] = tmp;
+}
+
+static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef)
+{
+	uint32_t adr;
+	uint32_t lsb;
+	uint32_t len;
+	uint32_t msk;
+	uint32_t tmp;
+	uint32_t adrmsk;
+	uint32_t regdef;
+
+	regdef = ddr_regdef(_regdef);
+	adr = DDR_REGDEF_ADR(regdef);
+	len = DDR_REGDEF_LEN(regdef);
+	lsb = DDR_REGDEF_LSB(regdef);
+	if (len == 0x20)
+		msk = 0xffffffff;
+	else
+		msk = ((1U << len) - 1);
+
+	if (adr < 0x400) {
+		adrmsk = 0xff;
+	} else {
+		adrmsk = 0x7f;
+	}
+
+	tmp = tbl[adr & adrmsk];
+	tmp = (tmp >> lsb) & msk;
+
+	return tmp;
+}
+
+/*******************************************************************************
+ *	DDRPHY register access handling
+ ******************************************************************************/
+static uint32_t ddrphy_regif_chk(void)
+{
+	uint32_t tmp_ach[DRAM_CH_CNT];
+	uint32_t ch;
+	uint32_t err;
+	uint32_t PI_VERSION_CODE;
+
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+	    || (Prr_Product == PRR_PRODUCT_M3)) {
+		PI_VERSION_CODE = 0x2041;	/* H3 Ver.1.x/M3-W */
+	} else {
+		PI_VERSION_CODE = 0x2040;	/* H3 Ver.2.0 or later/M3-N/V3H */
+	}
+
+	ddr_getval_ach(_reg_PI_VERSION, (uint32_t *) tmp_ach);
+	err = 0;
+	foreach_vch(ch) {
+		if (PI_VERSION_CODE != tmp_ach[ch])
+			err = 1;
+	}
+	return err;
+}
+
+/*******************************************************************************
+ *	functions and parameters for timing setting
+ ******************************************************************************/
+struct _jedec_spec1 {
+	uint16_t fx3;
+	uint8_t RLwoDBI;
+	uint8_t RLwDBI;
+	uint8_t WL;
+	uint8_t nWR;
+	uint8_t nRTP;
+	uint8_t MR1;
+	uint8_t MR2;
+};
+#define JS1_USABLEC_SPEC_LO 2
+#define JS1_USABLEC_SPEC_HI 5
+#define JS1_FREQ_TBL_NUM 8
+#define JS1_MR1(f) (0x04 | ((f)<<4))
+#define JS1_MR2(f) (0x00 | ((f)<<3) | (f))
+const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
+/*A	{  800,  6,  6,  4,  6 , 8, JS1_MR1(0), JS1_MR2(0) },   533.333Mbps*/
+/*A	{ 1600, 10, 12,  6, 10 , 8, JS1_MR1(1), JS1_MR2(1) },  1066.666Mbps*/
+/*A	{ 2400, 14, 16,  8, 16 , 8, JS1_MR1(2), JS1_MR2(2) },  1600.000Mbps*/
+	 /*B*/ {800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40},	/*  533.333Mbps */
+	 /*B*/ {1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40},	/* 1066.666Mbps */
+	 /*B*/ {2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40},	/* 1600.000Mbps */
+	 /*A*/ {3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3)},	/* 2133.333Mbps */
+	 /*A*/ {4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4)},	/* 2666.666Mbps */
+	 /*A*/ {4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5)},	/* 3200.000Mbps */
+	 /*A*/ {5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6)},	/* 3733.333Mbps */
+	 /*A*/ {6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7)}	/* 4266.666Mbps */
+};
+
+struct _jedec_spec2 {
+	uint16_t ps;
+	uint16_t cyc;
+};
+
+#define JS2_tSR 0
+#define JS2_tXP 1
+#define JS2_tRTP 2
+#define JS2_tRCD 3
+#define JS2_tRPpb 4
+#define JS2_tRPab 5
+#define JS2_tRAS 6
+#define JS2_tWR 7
+#define JS2_tWTR 8
+#define JS2_tRRD 9
+#define JS2_tPPD 10
+#define JS2_tFAW 11
+#define JS2_tDQSCK 12
+#define JS2_tCKEHCMD 13
+#define JS2_tCKELCMD 14
+#define JS2_tCKELPD 15
+#define JS2_tMRR 16
+#define JS2_tMRW 17
+#define JS2_tMRD 18
+#define JS2_tZQCALns 19
+#define JS2_tZQLAT 20
+#define JS2_tIEdly 21
+#define JS2_TBLCNT 22
+
+#define JS2_tRCpb (JS2_TBLCNT)
+#define JS2_tRCab (JS2_TBLCNT+1)
+#define JS2_tRFCpb (JS2_TBLCNT+2)
+#define JS2_tRFCab (JS2_TBLCNT+3)
+#define JS2_CNT (JS2_TBLCNT+4)
+
+#ifndef JS2_DERATE
+#define JS2_DERATE 0
+#endif
+const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
+	{
+/*tSR   */ {15000, 3},
+/*tXP   */ {7500, 3},
+/*tRTP  */ {7500, 8},
+/*tRCD  */ {18000, 4},
+/*tRPpb */ {18000, 3},
+/*tRPab */ {21000, 3},
+/*tRAS  */ {42000, 3},
+/*tWR   */ {18000, 4},
+/*tWTR  */ {10000, 8},
+/*tRRD  */ {10000, 4},
+/*tPPD  */ {0, 0},
+/*tFAW  */ {40000, 0},
+/*tDQSCK*/ {3500, 0},
+/*tCKEHCMD*/ {7500, 3},
+/*tCKELCMD*/ {7500, 3},
+/*tCKELPD*/ {7500, 3},
+/*tMRR*/ {0, 8},
+/*tMRW*/ {10000, 10},
+/*tMRD*/ {14000, 10},
+/*tZQCALns*/ {1000 * 10, 0},
+/*tZQLAT*/ {30000, 10},
+/*tIEdly*/ {12500, 0}
+	 }, {
+/*tSR   */ {15000, 3},
+/*tXP   */ {7500, 3},
+/*tRTP  */ {7500, 8},
+/*tRCD  */ {19875, 4},
+/*tRPpb */ {19875, 3},
+/*tRPab */ {22875, 3},
+/*tRAS  */ {43875, 3},
+/*tWR   */ {18000, 4},
+/*tWTR  */ {10000, 8},
+/*tRRD  */ {11875, 4},
+/*tPPD  */ {0, 0},
+/*tFAW  */ {40000, 0},
+/*tDQSCK*/ {3600, 0},
+/*tCKEHCMD*/ {7500, 3},
+/*tCKELCMD*/ {7500, 3},
+/*tCKELPD*/ {7500, 3},
+/*tMRR*/ {0, 8},
+/*tMRW*/ {10000, 10},
+/*tMRD*/ {14000, 10},
+/*tZQCALns*/ {1000 * 10, 0},
+/*tZQLAT*/ {30000, 10},
+/*tIEdly*/ {12500, 0}
+	     }
+};
+
+/* pb, ab */
+const uint16_t jedec_spec2_tRFC_pb_ab[2][7] = {
+/*	4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non)	*/
+	{
+	 60, 90, 90, 140, 140, 280, 280},
+	{
+	 130, 180, 180, 280, 280, 560, 560}
+};
+
+static uint32_t js1_ind;
+static uint16_t js2[JS2_CNT];
+static uint8_t RL;
+static uint8_t WL;
+
+static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
+			 uint16_t cyc)
+{
+	uint32_t tmp;
+	uint32_t div;
+
+	tmp = (((uint32_t) (ps) + 9) / 10) * ddr_mbps;
+	div = tmp / (200000 * ddr_mbpsdiv);
+	if (tmp != (div * 200000 * ddr_mbpsdiv))
+		div = div + 1;
+
+	if (div > cyc)
+		return (uint16_t) div;
+	return cyc;
+}
+
+static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
+			 uint16_t * js2)
+{
+	int i;
+
+	for (i = 0; i < JS2_TBLCNT; i++) {
+		js2[i] = _f_scale(ddr_mbps, ddr_mbpsdiv,
+				  1UL * jedec_spec2[JS2_DERATE][i].ps,
+				  jedec_spec2[JS2_DERATE][i].cyc);
+	}
+
+	js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb];
+	js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab];
+}
+
+/* scaler for DELAY value */
+static int16_t _f_scale_adj(int16_t ps)
+{
+	int32_t tmp;
+	/*
+	   tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
+	   = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
+	   = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
+	 */
+	tmp =
+	    (int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps /
+	    (int32_t) ddr_mbpsdiv;
+	tmp = (int32_t) tmp / (int32_t) 15625;
+
+	return (int16_t) tmp;
+}
+
+const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
+	{
+	 _reg_PI_MR1_DATA_F0_0,
+	 _reg_PI_MR1_DATA_F0_1,
+	 _reg_PI_MR1_DATA_F0_2,
+	 _reg_PI_MR1_DATA_F0_3},
+	{
+	 _reg_PI_MR1_DATA_F1_0,
+	 _reg_PI_MR1_DATA_F1_1,
+	 _reg_PI_MR1_DATA_F1_2,
+	 _reg_PI_MR1_DATA_F1_3}
+};
+
+const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = {
+	{
+	 _reg_PI_MR2_DATA_F0_0,
+	 _reg_PI_MR2_DATA_F0_1,
+	 _reg_PI_MR2_DATA_F0_2,
+	 _reg_PI_MR2_DATA_F0_3},
+	{
+	 _reg_PI_MR2_DATA_F1_0,
+	 _reg_PI_MR2_DATA_F1_1,
+	 _reg_PI_MR2_DATA_F1_2,
+	 _reg_PI_MR2_DATA_F1_3}
+};
+
+const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = {
+	{
+	 _reg_PI_MR3_DATA_F0_0,
+	 _reg_PI_MR3_DATA_F0_1,
+	 _reg_PI_MR3_DATA_F0_2,
+	 _reg_PI_MR3_DATA_F0_3},
+	{
+	 _reg_PI_MR3_DATA_F1_0,
+	 _reg_PI_MR3_DATA_F1_1,
+	 _reg_PI_MR3_DATA_F1_2,
+	 _reg_PI_MR3_DATA_F1_3}
+};
+
+const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = {
+	{
+	 _reg_PI_MR11_DATA_F0_0,
+	 _reg_PI_MR11_DATA_F0_1,
+	 _reg_PI_MR11_DATA_F0_2,
+	 _reg_PI_MR11_DATA_F0_3},
+	{
+	 _reg_PI_MR11_DATA_F1_0,
+	 _reg_PI_MR11_DATA_F1_1,
+	 _reg_PI_MR11_DATA_F1_2,
+	 _reg_PI_MR11_DATA_F1_3}
+};
+
+const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = {
+	{
+	 _reg_PI_MR12_DATA_F0_0,
+	 _reg_PI_MR12_DATA_F0_1,
+	 _reg_PI_MR12_DATA_F0_2,
+	 _reg_PI_MR12_DATA_F0_3},
+	{
+	 _reg_PI_MR12_DATA_F1_0,
+	 _reg_PI_MR12_DATA_F1_1,
+	 _reg_PI_MR12_DATA_F1_2,
+	 _reg_PI_MR12_DATA_F1_3}
+};
+
+const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = {
+	{
+	 _reg_PI_MR14_DATA_F0_0,
+	 _reg_PI_MR14_DATA_F0_1,
+	 _reg_PI_MR14_DATA_F0_2,
+	 _reg_PI_MR14_DATA_F0_3},
+	{
+	 _reg_PI_MR14_DATA_F1_0,
+	 _reg_PI_MR14_DATA_F1_1,
+	 _reg_PI_MR14_DATA_F1_2,
+	 _reg_PI_MR14_DATA_F1_3}
+};
+
+/*******************************************************************************
+ * regif pll w/a   ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA )
+ *******************************************************************************/
+static void regif_pll_wa(void)
+{
+	uint32_t ch;
+
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
+				   (0x0064U <<
+				    ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
+				   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+						 _reg_PHY_PLL_CTRL));
+
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
+				   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+						 _reg_PHY_LP4_BOOT_PLL_CTRL));
+
+	} else {
+		/*  PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
+				   (0x5064U <<
+				    ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
+
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
+				   (ddrtbl_getval
+				    (_cnf_DDR_PHY_ADR_G_REGSET,
+				     _reg_PHY_PLL_CTRL_TOP) << 16) |
+				   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+						 _reg_PHY_PLL_CTRL));
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA),
+				   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+						 _reg_PHY_PLL_CTRL_CA));
+
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
+				   (ddrtbl_getval
+				    (_cnf_DDR_PHY_ADR_G_REGSET,
+				     _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) |
+				   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+						 _reg_PHY_LP4_BOOT_PLL_CTRL));
+		reg_ddrphy_write_a(ddr_regdef_adr
+				   (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
+				   ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+						 _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
+	}
+
+	/* protect register interface */
+	ddrphy_regif_idle();
+	pll3_control(0);
+
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		/*  non */
+	} else {
+		reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
+				   (0x01U <<
+				    ddr_regdef_lsb(_reg_PHY_DLL_RST_EN)));
+		ddrphy_regif_idle();
+	}
+
+	/***********************************************************************
+	init start
+	***********************************************************************/
+	/* dbdficnt0:
+	 * dfi_dram_clk_disable=1
+	 * dfi_frequency = 0
+	 * freq_ratio = 01 (2:1)
+	 * init_start =0
+	 */
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
+	dsb_sev();
+
+	/* dbdficnt0:
+	 * dfi_dram_clk_disable=1
+	 * dfi_frequency = 0
+	 * freq_ratio = 01 (2:1)
+	 * init_start =1
+	 */
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
+	dsb_sev();
+
+	foreach_ech(ch)
+	    if (((Boardcnf->phyvalid) & (1U << ch)))
+		while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ;
+	dsb_sev();
+}
+
+/*******************************************************************************
+ *	load table data into DDR registers
+ ******************************************************************************/
+static void ddrtbl_load(void)
+{
+	int i;
+	uint32_t slice;
+	uint32_t csab;
+	uint32_t adr;
+	uint32_t dataL;
+	uint32_t tmp[3];
+	uint16_t dataS;
+
+	/***********************************************************************
+	TIMING REGISTERS
+	***********************************************************************/
+	/* search jedec_spec1 index */
+	for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) {
+		if (js1[i].fx3 * 2 * ddr_mbpsdiv >= ddr_mbps * 3)
+			break;
+	}
+	if (JS1_USABLEC_SPEC_HI < i)
+		js1_ind = JS1_USABLEC_SPEC_HI;
+	else
+		js1_ind = i;
+
+	if (Boardcnf->dbi_en)
+		RL = js1[js1_ind].RLwDBI;
+	else
+		RL = js1[js1_ind].RLwoDBI;
+
+	WL = js1[js1_ind].WL;
+
+	/* calculate jedec_spec2 */
+	_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
+
+	/***********************************************************************
+	PREPARE TBL
+	***********************************************************************/
+	if (Prr_Product == PRR_PRODUCT_H3) {
+		if (Prr_Cut <= PRR_PRODUCT_11) {
+			/*  H3 Ver.1.x */
+			_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+				 DDR_PHY_SLICE_REGSET_H3,
+				 DDR_PHY_SLICE_REGSET_NUM_H3);
+			_tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
+				 DDR_PHY_ADR_V_REGSET_H3,
+				 DDR_PHY_ADR_V_REGSET_NUM_H3);
+			_tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
+				 DDR_PHY_ADR_I_REGSET_H3,
+				 DDR_PHY_ADR_I_REGSET_NUM_H3);
+			_tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
+				 DDR_PHY_ADR_G_REGSET_H3,
+				 DDR_PHY_ADR_G_REGSET_NUM_H3);
+			_tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3,
+				 DDR_PI_REGSET_NUM_H3);
+
+			DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3;
+			DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3;
+			DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3;
+			DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3;
+			DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3;
+			DDR_PHY_SLICE_REGSET_SIZE =
+			    DDR_PHY_SLICE_REGSET_SIZE_H3;
+			DDR_PHY_ADR_V_REGSET_SIZE =
+			    DDR_PHY_ADR_V_REGSET_SIZE_H3;
+			DDR_PHY_ADR_I_REGSET_SIZE =
+			    DDR_PHY_ADR_I_REGSET_SIZE_H3;
+			DDR_PHY_ADR_G_REGSET_SIZE =
+			    DDR_PHY_ADR_G_REGSET_SIZE_H3;
+			DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3;
+			DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3;
+			DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3;
+			DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3;
+			DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3;
+			DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3;
+
+			DDR_PHY_ADR_I_NUM = 1;
+		} else {
+			/*  H3 Ver.2.0 or later */
+			_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+				 DDR_PHY_SLICE_REGSET_H3VER2,
+				 DDR_PHY_SLICE_REGSET_NUM_H3VER2);
+			_tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
+				 DDR_PHY_ADR_V_REGSET_H3VER2,
+				 DDR_PHY_ADR_V_REGSET_NUM_H3VER2);
+			_tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
+				 DDR_PHY_ADR_G_REGSET_H3VER2,
+				 DDR_PHY_ADR_G_REGSET_NUM_H3VER2);
+			_tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2,
+				 DDR_PI_REGSET_NUM_H3VER2);
+
+			DDR_PHY_SLICE_REGSET_OFS =
+			    DDR_PHY_SLICE_REGSET_OFS_H3VER2;
+			DDR_PHY_ADR_V_REGSET_OFS =
+			    DDR_PHY_ADR_V_REGSET_OFS_H3VER2;
+			DDR_PHY_ADR_G_REGSET_OFS =
+			    DDR_PHY_ADR_G_REGSET_OFS_H3VER2;
+			DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2;
+			DDR_PHY_SLICE_REGSET_SIZE =
+			    DDR_PHY_SLICE_REGSET_SIZE_H3VER2;
+			DDR_PHY_ADR_V_REGSET_SIZE =
+			    DDR_PHY_ADR_V_REGSET_SIZE_H3VER2;
+			DDR_PHY_ADR_G_REGSET_SIZE =
+			    DDR_PHY_ADR_G_REGSET_SIZE_H3VER2;
+			DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2;
+			DDR_PHY_SLICE_REGSET_NUM =
+			    DDR_PHY_SLICE_REGSET_NUM_H3VER2;
+			DDR_PHY_ADR_V_REGSET_NUM =
+			    DDR_PHY_ADR_V_REGSET_NUM_H3VER2;
+			DDR_PHY_ADR_G_REGSET_NUM =
+			    DDR_PHY_ADR_G_REGSET_NUM_H3VER2;
+			DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2;
+
+			DDR_PHY_ADR_I_NUM = 0;
+		}
+	} else if (Prr_Product == PRR_PRODUCT_M3) {
+		/*  M3-W */
+		_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+			 DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3);
+		_tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
+			 DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3);
+		_tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
+			 DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3);
+		_tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
+			 DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3);
+		_tblcopy(_cnf_DDR_PI_REGSET,
+			 DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3);
+
+		DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3;
+		DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3;
+		DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3;
+		DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3;
+		DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3;
+		DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3;
+		DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3;
+		DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3;
+		DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3;
+		DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3;
+		DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3;
+		DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3;
+		DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3;
+		DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3;
+		DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3;
+
+		DDR_PHY_ADR_I_NUM = 2;
+	} else {
+		/*  M3-N/V3H */
+		_tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+			 DDR_PHY_SLICE_REGSET_M3N,
+			 DDR_PHY_SLICE_REGSET_NUM_M3N);
+		_tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N,
+			 DDR_PHY_ADR_V_REGSET_NUM_M3N);
+		_tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N,
+			 DDR_PHY_ADR_I_REGSET_NUM_M3N);
+		_tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N,
+			 DDR_PHY_ADR_G_REGSET_NUM_M3N);
+		_tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N,
+			 DDR_PI_REGSET_NUM_M3N);
+
+		DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N;
+		DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N;
+		DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N;
+		DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N;
+		DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N;
+		DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N;
+		DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N;
+		DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N;
+		DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N;
+		DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N;
+		DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N;
+		DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N;
+		DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N;
+		DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N;
+		DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N;
+
+		DDR_PHY_ADR_I_NUM = 2;
+	}
+
+	/***********************************************************************
+	PLL CODE CHANGE
+	***********************************************************************/
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL,
+			      0x1142);
+		ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+			      _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142);
+	}
+
+	/***********************************************************************
+	on fly gate adjust
+	***********************************************************************/
+	if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) {
+		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+			      _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
+	}
+
+	/***********************************************************************
+	Adjust PI paramters
+	***********************************************************************/
+#ifdef _def_LPDDR4_ODT
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_0,
+		      _def_LPDDR4_ODT);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_1,
+		      _def_LPDDR4_ODT);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_2,
+		      _def_LPDDR4_ODT);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F0_3,
+		      _def_LPDDR4_ODT);
+
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_0,
+		      _def_LPDDR4_ODT);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_1,
+		      _def_LPDDR4_ODT);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_2,
+		      _def_LPDDR4_ODT);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_F1_3,
+		      _def_LPDDR4_ODT);
+#endif /* _def_LPDDR4_ODT */
+
+#ifdef _def_LPDDR4_VREFCA
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_0,
+		      _def_LPDDR4_VREFCA);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_1,
+		      _def_LPDDR4_VREFCA);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_2,
+		      _def_LPDDR4_VREFCA);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_3,
+		      _def_LPDDR4_VREFCA);
+
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_0,
+		      _def_LPDDR4_VREFCA);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_1,
+		      _def_LPDDR4_VREFCA);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_2,
+		      _def_LPDDR4_VREFCA);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_3,
+		      _def_LPDDR4_VREFCA);
+#endif /* _def_LPDDR4_VREFCA */
+	if ((Prr_Product == PRR_PRODUCT_M3N)
+	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+		js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7;
+		if (js2[JS2_tIEdly] > (RL))
+			js2[JS2_tIEdly] = RL;
+	} else if ((Prr_Product == PRR_PRODUCT_H3)
+		   && (Prr_Cut > PRR_PRODUCT_11)) {
+		js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4;
+	} else if ((Prr_Product == PRR_PRODUCT_H3)
+		   && (Prr_Cut <= PRR_PRODUCT_11)) {
+		js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
+	}
+
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
+	    || (Prr_Product == PRR_PRODUCT_M3N)
+	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+		if ((js2[JS2_tIEdly]) >= 0x1e)
+			dataS = 0x1e;
+		else
+			dataS = js2[JS2_tIEdly];
+	} else {
+		if ((js2[JS2_tIEdly]) >= 0x0e)
+			dataS = 0x0e;
+		else
+			dataS = js2[JS2_tIEdly];
+	}
+
+	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
+	ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
+		      (dataS - 2));
+	if ((Prr_Product == PRR_PRODUCT_M3N)
+	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+			      _reg_PHY_RDDATA_EN_OE_DLY, dataS);
+	}
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
+
+	if (ddrtbl_getval
+	    (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) {
+		dataL = WL - 1;
+	} else {
+		dataL = WL;
+	}
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2);
+	ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL);
+
+	if (Boardcnf->dbi_en) {
+		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
+			      0x01);
+		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+			      _reg_PHY_WDQLVL_DATADM_MASK, 0x000);
+	} else {
+		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
+			      0x00);
+		ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+			      _reg_PHY_WDQLVL_DATADM_MASK, 0x100);
+	}
+
+	tmp[0] = js1[js1_ind].MR1;
+	tmp[1] = js1[js1_ind].MR2;
+	dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
+	if (Boardcnf->dbi_en)
+		tmp[2] = dataL | 0xc0;
+	else
+		tmp[2] = dataL & (~0xc0);
+
+	for (i = 0; i < 2; i++) {
+		for (csab = 0; csab < CSAB_CNT; csab++) {
+			ddrtbl_setval(_cnf_DDR_PI_REGSET,
+				      _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]);
+			ddrtbl_setval(_cnf_DDR_PI_REGSET,
+				      _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]);
+			ddrtbl_setval(_cnf_DDR_PI_REGSET,
+				      _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]);
+		}
+	}
+
+	/***********************************************************************
+	 DDRPHY INT START
+	***********************************************************************/
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		/*  non */
+	} else {
+		regif_pll_wa();
+	}
+
+	/***********************************************************************
+	FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety)
+	***********************************************************************/
+	ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01);
+	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
+
+	/***********************************************************************
+	SET DATA SLICE TABLE
+	***********************************************************************/
+	for (slice = 0; slice < SLICE_CNT; slice++) {
+		adr =
+		    DDR_PHY_SLICE_REGSET_OFS +
+		    DDR_PHY_SLICE_REGSET_SIZE * slice;
+		for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) {
+			reg_ddrphy_write_a(adr + i,
+					   _cnf_DDR_PHY_SLICE_REGSET[i]);
+		}
+	}
+
+	/***********************************************************************
+	SET ADR SLICE TABLE
+	***********************************************************************/
+	adr = DDR_PHY_ADR_V_REGSET_OFS;
+	for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
+		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
+	}
+
+	if (DDR_PHY_ADR_I_NUM > 0) {
+		for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) {
+			adr =
+			    DDR_PHY_ADR_I_REGSET_OFS +
+			    DDR_PHY_ADR_I_REGSET_SIZE * slice;
+			for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) {
+				reg_ddrphy_write_a(adr + i,
+						   _cnf_DDR_PHY_ADR_I_REGSET
+						   [i]);
+			}
+		}
+	}
+
+	/***********************************************************************
+	SET ADRCTRL SLICE TABLE
+	***********************************************************************/
+	adr = DDR_PHY_ADR_G_REGSET_OFS;
+	for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
+		reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
+	}
+
+	/***********************************************************************
+	SET PI REGISTERS
+	***********************************************************************/
+	adr = DDR_PI_REGSET_OFS;
+	for (i = 0; i < DDR_PI_REGSET_NUM; i++) {
+		reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
+	}
+}
+
+/*******************************************************************************
+ *	CONFIGURE DDR REGISTERS
+ ******************************************************************************/
+static void ddr_config_sub(void)
+{
+	int32_t i;
+	uint32_t ch, slice;
+	uint32_t dataL;
+	uint32_t tmp;
+	uint8_t high_byte[SLICE_CNT];
+	foreach_vch(ch) {
+	/***********************************************************************
+	BOARD SETTINGS (DQ,DM,VREF_DRIVING)
+	***********************************************************************/
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			high_byte[slice] =
+			    (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
+			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
+				     Boardcnf->ch[ch].dq_swap[slice]);
+			ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
+				     Boardcnf->ch[ch].dm_swap[slice]);
+			if (high_byte[slice]) {
+				/* HIGHER 16 BYTE */
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+					     0x00);
+			} else {
+				/* LOWER 16 BYTE */
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+					     0x01);
+			}
+		}
+
+	/***********************************************************************
+		BOARD SETTINGS (CA,ADDR_SEL)
+	***********************************************************************/
+		const uint32_t _par_CALVL_DEVICE_MAP = 1;
+		dataL = Boardcnf->ch[ch].ca_swap | 0x00888888;
+
+		/* --- ADR_CALVL_SWIZZLE --- */
+		if (Prr_Product == PRR_PRODUCT_M3) {
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+				   0x00000000);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+				   0x00000000);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
+				   _par_CALVL_DEVICE_MAP);
+		} else {
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL);
+			ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
+			ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
+				   _par_CALVL_DEVICE_MAP);
+		}
+
+		/* --- ADR_ADDR_SEL --- */
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Prr_Cut > PRR_PRODUCT_11)) {
+			dataL = 0x00FFFFFF & Boardcnf->ch[ch].ca_swap;
+		} else {
+			dataL = 0;
+			tmp = Boardcnf->ch[ch].ca_swap;
+			for (i = 0; i < 6; i++) {
+				dataL |= ((tmp & 0x0f) << (i * 5));
+				tmp = tmp >> 4;
+			}
+		}
+		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL);
+
+	/***********************************************************************
+		BOARD SETTINGS (BYTE_ORDER_SEL)
+	***********************************************************************/
+		if (Prr_Product == PRR_PRODUCT_M3) {
+			/* --- DATA_BYTE_SWAP --- */
+			dataL = 0;
+			tmp = Boardcnf->ch[ch].dqs_swap;
+			for (i = 0; i < 4; i++) {
+				dataL |= ((tmp & 0x03) << (i * 2));
+				tmp = tmp >> 4;
+			}
+		} else {
+			/* --- DATA_BYTE_SWAP --- */
+			dataL = Boardcnf->ch[ch].dqs_swap;
+			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
+			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
+				   (dataL) & 0x0f);
+			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
+				   (dataL >> 4 * 1) & 0x0f);
+			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
+				   (dataL >> 4 * 2) & 0x0f);
+			ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
+				   (dataL >> 4 * 3) & 0x0f);
+
+			ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00);
+		}
+		ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL);
+	}
+}
+
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
+{
+	uint32_t slice;
+	uint32_t tmp;
+	uint32_t tgt;
+	if (ddr_csn / 2) {
+		tgt = 3;
+	} else {
+		tgt = 1;
+	}
+
+	for (slice = 0; slice < SLICE_CNT; slice++) {
+		tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		if (tgt == tmp)
+			break;
+	}
+	tmp = Boardcnf->ch[ch].ca_swap;
+	if (slice % 2)
+		tmp |= 0x00888888;
+	*p_swz = tmp;
+}
+
+static void ddr_config_sub_h3v1x(void)
+{
+	uint32_t ch, slice;
+	uint32_t dataL;
+	uint32_t tmp;
+	uint8_t high_byte[SLICE_CNT];
+
+	foreach_vch(ch) {
+		uint32_t ca_swizzle;
+		uint32_t ca;
+		uint32_t csmap;
+	/***********************************************************************
+		BOARD SETTINGS (DQ,DM,VREF_DRIVING)
+	***********************************************************************/
+		csmap = 0;
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+			high_byte[slice] = tmp % 2;
+			if (tmp == 1 && (slice >= 2))
+				csmap |= 0x05;
+			if (tmp == 3 && (slice >= 2))
+				csmap |= 0x50;
+			ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
+				     Boardcnf->ch[ch].dq_swap[slice]);
+			if (high_byte[slice]) {
+				/* HIGHER 16 BYTE */
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+					     0x00);
+			} else {
+				/* LOWER 16 BYTE */
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+					     0x01);
+			}
+		}
+	/***********************************************************************
+		BOARD SETTINGS (CA,ADDR_SEL)
+	***********************************************************************/
+		ca = Boardcnf->ch[ch].ca_swap;
+		ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
+		ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
+
+		get_ca_swizzle(ch, 0, &ca_swizzle);
+
+		ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle);
+		ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000);
+		ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000);
+		ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000);
+		ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01);
+
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			const uint8_t o_mr15 = 0x55;
+			const uint8_t o_mr20 = 0x55;
+			const uint16_t o_mr32_mr40 = 0x5a3c;
+			uint32_t o_inv;
+			uint32_t inv;
+			uint32_t bit_soc;
+			uint32_t bit_mem;
+			uint32_t j;
+
+			ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM,
+				     0x01);
+			ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START,
+				     0x08);
+
+			if (high_byte[slice])
+				o_inv = o_mr20;
+			else
+				o_inv = o_mr15;
+
+			tmp = Boardcnf->ch[ch].dq_swap[slice];
+			inv = 0;
+			j = 0;
+			for (bit_soc = 0; bit_soc < 8; bit_soc++) {
+				bit_mem = (tmp >> (4 * bit_soc)) & 0x0f;
+				j |= (1U << bit_mem);
+				if (o_inv & (1U << bit_mem))
+					inv |= (1U << bit_soc);
+			}
+			dataL = o_mr32_mr40;
+			if (!high_byte[slice])
+				dataL |= (inv << 24);
+			if (high_byte[slice])
+				dataL |= (inv << 16);
+			ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
+				     dataL);
+		}
+	}
+}
+
+static void ddr_config(void)
+{
+	int32_t i;
+	uint32_t ch, slice;
+	uint32_t dataL;
+	uint32_t tmp;
+
+	/***********************************************************************
+	configure ddrphy registers
+	***********************************************************************/
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		ddr_config_sub_h3v1x();
+	} else {
+		ddr_config_sub();	/*  H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
+	}
+
+	/***********************************************************************
+	WDQ_USER_PATT
+	***********************************************************************/
+	foreach_vch(ch) {
+		union {
+			uint32_t ui32[4];
+			uint8_t ui8[16];
+		} patt;
+		uint16_t patm;
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			patm = 0;
+			for (i = 0; i < 16; i++) {
+				tmp = Boardcnf->ch[ch].wdqlvl_patt[i];
+				patt.ui8[i] = tmp & 0xff;
+				if (tmp & 0x100)
+					patm |= (1U << i);
+			}
+			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
+				     patt.ui32[0]);
+			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
+				     patt.ui32[1]);
+			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
+				     patt.ui32[2]);
+			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
+				     patt.ui32[3]);
+			ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
+		}
+	}
+
+	/***********************************************************************
+	CACS DLY
+	***********************************************************************/
+	dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
+	set_dfifrequency(0x1f);
+	foreach_vch(ch) {
+		int16_t adj;
+		for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
+			adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+			ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+				   dataL + adj);
+		}
+	}
+	set_dfifrequency(0x00);
+
+	/***********************************************************************
+	WDQDM DLY
+	***********************************************************************/
+	dataL = Boardcnf->dqdm_dly_w;
+	foreach_vch(ch) {
+		int8_t _adj;
+		int16_t adj;
+		uint32_t dq;
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			for (i = 0; i <= 8; i++) {
+				dq = slice * 8 + i;
+				if (i == 8)
+					_adj = Boardcnf->ch[ch].dm_adj_w[slice];
+				else
+					_adj = Boardcnf->ch[ch].dq_adj_w[dq];
+				adj = _f_scale_adj(_adj);
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
+					     dataL + adj);
+			}
+		}
+	}
+
+	/***********************************************************************
+	RDQDM DLY
+	***********************************************************************/
+	dataL = Boardcnf->dqdm_dly_r;
+	foreach_vch(ch) {
+		int8_t _adj;
+		int16_t adj;
+		uint32_t dq;
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			for (i = 0; i <= 8; i++) {
+				dq = slice * 8 + i;
+				if (i == 8)
+					_adj = Boardcnf->ch[ch].dm_adj_r[slice];
+				else
+					_adj = Boardcnf->ch[ch].dq_adj_r[dq];
+				adj = _f_scale_adj(_adj);
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
+					     [i], dataL + adj);
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+					     [i], dataL + adj);
+			}
+		}
+	}
+}
+
+/*******************************************************************************
+ *	DBSC register setting functions
+ ******************************************************************************/
+static void dbsc_regset_pre(void)
+{
+	uint32_t ch, csab;
+	uint32_t dataL;
+
+	/***********************************************************************
+	PRIMARY SETTINGS
+	***********************************************************************/
+	/* LPDDR4, BL=16, DFI interface */
+	mmio_write_32(DBSC_DBKIND, 0x0000000a);
+	mmio_write_32(DBSC_DBBL, 0x00000002);
+	mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+
+	/* FREQRATIO=2 */
+	mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+
+	/* Chanel map (H3 Ver.1.x) */
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+		mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
+
+	/* DRAM SIZE REGISTER:
+	 * set all ranks as density=0(4Gb) for PHY initialization
+	 */
+	foreach_vch(ch)
+	    for (csab = 0; csab < 4; csab++)
+		mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0));
+
+	if (Prr_Product == PRR_PRODUCT_M3) {
+		dataL = 0xe4e4e4e4;
+		foreach_ech(ch) {
+			if ((ddr_phyvalid & (1U << ch)))
+				dataL = (dataL & (~(0x000000FF << (ch * 8))))
+				    | (((Boardcnf->ch[ch].dqs_swap & 0x0003)
+					| ((Boardcnf->ch[ch].dqs_swap & 0x0030)
+					   >> 2)
+					| ((Boardcnf->ch[ch].dqs_swap & 0x0300)
+					   >> 4)
+					| ((Boardcnf->ch[ch].dqs_swap & 0x3000)
+					   >> 6)) << (ch * 8));
+		}
+		mmio_write_32(DBSC_DBBSWAP, dataL);
+	}
+}
+
+static void dbsc_regset(void)
+{
+	int32_t i;
+	uint32_t ch;
+	uint32_t dataL;
+	uint32_t tmp[4];
+
+	/* RFC */
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20)
+	    && (max_density == 0)) {
+		js2[JS2_tRFCpb] =
+		    _f_scale(ddr_mbps, ddr_mbpsdiv,
+			     1UL * jedec_spec2_tRFC_pb_ab[0][1] * 1000, 0);
+		js2[JS2_tRFCab] =
+		    _f_scale(ddr_mbps, ddr_mbpsdiv,
+			     1UL * jedec_spec2_tRFC_pb_ab[1][1] * 1000, 0);
+	} else {
+		js2[JS2_tRFCpb] = _f_scale(ddr_mbps, ddr_mbpsdiv,
+					   1UL *
+					   jedec_spec2_tRFC_pb_ab[0]
+					   [max_density] * 1000, 0);
+		js2[JS2_tRFCab] =
+		    _f_scale(ddr_mbps, ddr_mbpsdiv,
+			     1UL * jedec_spec2_tRFC_pb_ab[1][max_density] *
+			     1000, 0);
+	}
+
+	/* DBTR0.CL  : RL */
+	mmio_write_32(DBSC_DBTR(0), RL);
+
+	/* DBTR1.CWL : WL */
+	mmio_write_32(DBSC_DBTR(1), WL);
+
+	/* DBTR2.AL  : 0 */
+	mmio_write_32(DBSC_DBTR(2), 0);
+
+	/* DBTR3.TRCD: tRCD */
+	mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]);
+
+	/* DBTR4.TRPA,TRP: tRPab,tRPpb */
+	mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]);
+
+	/* DBTR5.TRC : use tRCpb */
+	mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]);
+
+	/* DBTR6.TRAS : tRAS */
+	mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]);
+
+	/* DBTR7.TRRD : tRRD */
+	mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]);
+
+	/* DBTR8.TFAW : tFAW */
+	mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]);
+
+	/* DBTR9.TRDPR : tRTP */
+	mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]);
+
+	/* DBTR10.TWR : nWR */
+	mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR);
+
+	/* DBTR11.TRDWR : RL + tDQSCK + BL/2 + Rounddown(tRPST) - WL + tWPRE */
+	mmio_write_32(DBSC_DBTR(11),
+		      RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2);
+
+	/* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
+	dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR];
+	mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL);
+
+	/* DBTR13.TRFCPB,TRFCAB : tRFCpb, tRFCab */
+	mmio_write_32(DBSC_DBTR(13), (js2[JS2_tRFCab]));
+
+	/* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
+	mmio_write_32(DBSC_DBTR(14),
+		      (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD]));
+
+	/* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
+	mmio_write_32(DBSC_DBTR(15), (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD]));
+
+	/* DBTR16 */
+	/* WDQL : tphy_wrlat + tphy_wrdata */
+	tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
+	/* DQENLTNCY : tphy_wrlat = WL-2 */
+	tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
+	/* DQL : tphy_rdlat + trdata_en */
+	/* it is not important for dbsc */
+	tmp[2] = RL + 16;
+	/* DQIENLTNCY : trdata_en */
+	tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1;
+	mmio_write_32(DBSC_DBTR(16),
+		      (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+	/* DBTR24 */
+	/* WRCSLAT = WRLAT -5 */
+	tmp[0] -= 5;
+	/* WRCSGAP = 5 */
+	tmp[1] = 5;
+	/* RDCSLAT = RDLAT_ADJ +2 */
+	tmp[2] = tmp[3] + 2;
+	/* RDCSGAP = 6 */
+	if (Prr_Product == PRR_PRODUCT_M3) {
+		tmp[3] = 4;
+	} else {
+		tmp[3] = 6;
+	}
+	mmio_write_32(DBSC_DBTR(24),
+		      (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+	/* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
+	mmio_write_32(DBSC_DBTR(17),
+		      (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16));
+
+	/* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
+	mmio_write_32(DBSC_DBTR(18), 0);
+
+	/* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */
+	mmio_write_32(DBSC_DBTR(19), 0);
+
+	/* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
+	dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD];
+	mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL);
+
+	/* DBTR21.TCCD */
+	/* DBTR23.TCCD */
+	/* H3 Ver.1.0 cannot use TBTR23 feature */
+	if (ddr_tccd == 8 &&
+	    !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10))
+	    ) {
+		dataL = 8;
+		mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+		mmio_write_32(DBSC_DBTR(23), 0x00000002);
+	} else if (ddr_tccd <= 11) {
+		dataL = 11;
+		mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+		mmio_write_32(DBSC_DBTR(23), 0x00000000);
+	} else {
+		dataL = ddr_tccd;
+		mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL);
+		mmio_write_32(DBSC_DBTR(23), 0x00000000);
+	}
+
+	/* DBTR22.ZQLAT : */
+	dataL = js2[JS2_tZQCALns] * 100;	/*  1000 * 1000 ps */
+	dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20);
+	mmio_write_32(DBSC_DBTR(22), dataL);
+
+	/* DBTR25 : do not use in LPDDR4 */
+	mmio_write_32(DBSC_DBTR(25), 0);
+
+	/* DBRNK : */
+	/*
+	 * DBSC_DBRNK2 rkrr
+	 * DBSC_DBRNK3 rkrw
+	 * DBSC_DBRNK4 rkwr
+	 * DBSC_DBRNK5 rkww
+	 */
+#define _par_DBRNK_VAL		(0x7007)
+
+	for (i = 0; i < 4; i++) {
+		uint32_t dataL2;
+		dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) {
+			dataL += 1;
+		}
+		dataL2 = 0;
+		foreach_vch(ch) {
+			dataL2 = dataL2 | (dataL << (4 * ch));
+		}
+		mmio_write_32(DBSC_DBRNK(2 + i), dataL2);
+	}
+	mmio_write_32(DBSC_DBADJ0, 0x00000000);
+
+	/***********************************************************************
+	timing registers for Scheduler
+	***********************************************************************/
+	/* SCFCTST0 */
+	/* SCFCTST0 ACT-ACT */
+	tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps;
+	/* SCFCTST0 RDA-ACT */
+	tmp[2] =
+	    1UL * ((16 / 2) + js2[JS2_tRTP] - 8 +
+		   js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps;
+	/* SCFCTST0 WRA-ACT */
+	tmp[1] =
+	    1UL * (WL + 1 + (16 / 2) +
+		   js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps;
+	/* SCFCTST0 PRE-ACT */
+	tmp[0] = 1UL * js2[JS2_tRPpb];
+	mmio_write_32(DBSC_SCFCTST0,
+		      (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+	/* SCFCTST1 */
+	/* SCFCTST1 RD-WR */
+	tmp[3] =
+	    1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv /
+	    ddr_mbps;
+	/* SCFCTST1 WR-RD */
+	tmp[2] =
+	    1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv /
+	    ddr_mbps;
+	/* SCFCTST1 ACT-RD/WR */
+	tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps;
+	/* SCFCTST1 ASYNCOFS */
+	tmp[0] = 12;
+	mmio_write_32(DBSC_SCFCTST1,
+		      (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+	/* DBSCHRW1 */
+	/* DBSCHRW1 SCTRFCAB */
+	tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps;
+	dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
+		 + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
+		 + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
+	if (tmp[0] < dataL)
+		tmp[0] = dataL;
+	mmio_write_32(DBSC_DBSCHRW1, tmp[0]);
+
+	/***********************************************************************
+	QOS and CAM
+	***********************************************************************/
+#ifdef ddr_qos_init_setting	/*  only for non qos_init */
+	/*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
+	mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+	/*0(fillunit),8(dirtymax),4(dirtymin) */
+	mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+	/*stop_tolerance */
+	mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+	/*rd-wr/wr-rd toggle priority */
+	mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+	mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+	mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037);
+
+	/* QoS Settings */
+	mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
+	mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
+	mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U);
+	mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U);
+	mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U);
+	mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
+	mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U);
+	mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U);
+	mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U);
+	mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
+	mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
+	mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U);
+	mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U);
+	mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U);
+	mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U);
+	mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U);
+	mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U);
+	mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
+	mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
+	mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U);
+	mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
+	mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
+	mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U);
+	mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U);
+	mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U);
+	mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U);
+	mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U);
+	mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U);
+
+	mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* ddr_qos_init_setting */
+	/* H3 Ver.1.1 need to set monitor function */
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) {
+		mmio_write_32(DBSC_DBMONCONF4, 0x00700000);
+	}
+
+	if (Prr_Product == PRR_PRODUCT_H3) {
+		if (Prr_Cut == PRR_PRODUCT_10) {
+			/* resrdis, simple mode, sc off */
+			mmio_write_32(DBSC_DBBCAMDIS, 0x00000007);
+		} else if (Prr_Cut == PRR_PRODUCT_11) {
+			/* resrdis, simple mode         */
+			mmio_write_32(DBSC_DBBCAMDIS, 0x00000005);
+		} else if (Prr_Cut < PRR_PRODUCT_30) {
+			/* H3 Ver.2.0                   */
+			/* resrdis                      */
+			mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+		} else {	/* H3 Ver.3.0(include H3N)      */
+			/* exprespque                   */
+			mmio_write_32(DBSC_DBBCAMDIS, 0x00000010);
+		}
+	} else {		/* M3-W/M3-N/V3H                */
+		/* resrdis                      */
+		mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+	}
+}
+
+static void dbsc_regset_post(void)
+{
+	uint32_t ch, cs;
+	uint32_t dataL;
+	uint32_t slice, rdlat_max, rdlat_min;
+
+	rdlat_max = 0;
+	rdlat_min = 0xffff;
+	foreach_vch(ch) {
+		for (cs = 0; cs < CS_CNT; cs++) {
+			if ((ch_have_this_cs[cs] & (1U << ch)) != 0) {
+				for (slice = 0; slice < SLICE_CNT; slice++) {
+					ddr_setval_s(ch, slice,
+						     _reg_PHY_PER_CS_TRAINING_INDEX,
+						     cs);
+					dataL =
+					    ddr_getval_s(ch, slice,
+							 _reg_PHY_RDDQS_LATENCY_ADJUST);
+					if (dataL > rdlat_max)
+						rdlat_max = dataL;
+					if (dataL < rdlat_min)
+						rdlat_min = dataL;
+				}
+			}
+		}
+	}
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) {
+		mmio_write_32(DBSC_DBTR(24),
+			      ((rdlat_max * 2 - rdlat_min + 4) << 24) +
+			      ((rdlat_min + 2) << 16) +
+			      mmio_read_32(DBSC_DBTR(24)));
+	} else {
+		mmio_write_32(DBSC_DBTR(24),
+			      ((rdlat_max + 2) << 24) +
+			      ((rdlat_max + 2) << 16) +
+			      mmio_read_32(DBSC_DBTR(24)));
+	}
+
+	/* set ddr density information */
+	foreach_ech(ch) {
+		for (cs = 0; cs < CS_CNT; cs++) {
+			if (ddr_density[ch][cs] == 0xff) {
+				mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00);
+			} else {
+				mmio_write_32(DBSC_DBMEMCONF(ch, cs),
+					      DBMEMCONF_REGD(ddr_density[ch]
+							     [cs]));
+			}
+		}
+		mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000);
+		mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000);
+	}
+
+	mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+
+	/*set DBI */
+	if (Boardcnf->dbi_en)
+		mmio_write_32(DBSC_DBDBICNT, 0x00000003);
+
+	/* H3 Ver.2.0 or later/M3-N/V3H DBI wa */
+	if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
+	     || (Prr_Product == PRR_PRODUCT_M3N)
+	     || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+		reg_ddrphy_write_a(0x00001010, 0x01000000);
+
+	/*set REFCYCLE */
+	dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
+	mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff));
+	mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
+#if RCAR_REWT_TRAINING != 0
+	/* Periodic-WriteDQ Training seeting */
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) {
+		/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
+	} else {
+		/* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H -> Periodic-WriteDQ Training seeting */
+
+		/* Periodic WriteDQ Training seeting */
+		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
+
+		ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04);
+		ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F);
+		ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50);
+		ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300);
+
+		ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP,
+			       ddrtbl_getval(_cnf_DDR_PI_REGSET,
+					     _reg_PI_WDQLVL_CS_MAP));
+		ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f);
+		ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
+		ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
+		ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01);
+		ddr_setval_ach(_reg_PI_TREF_F0, 0x0000);
+		ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
+		ddr_setval_ach(_reg_PI_TREF_F2, 0x0000);
+
+		if (Prr_Product == PRR_PRODUCT_M3) {
+			ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02);
+		} else {
+			ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02);
+		}
+		ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01);
+
+		/* DFI_PHYMSTR_ACK , WTmode setting */
+		mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);	/* DFI_PHYMSTR_ACK: WTmode =b'01 */
+	}
+#endif /* RCAR_REWT_TRAINING */
+	/* periodic dram zqcal and phy ctrl update enable */
+	mmio_write_32(DBSC_DBCALCNF, 0x01000010);
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+		/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
+	} else {
+#if RCAR_DRAM_SPLIT == 2
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Boardcnf->phyvalid == 0x05))
+			mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001);
+		else
+			mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
+#else /* RCAR_DRAM_SPLIT == 2 */
+		mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
+#endif /* RCAR_DRAM_SPLIT == 2 */
+	}
+
+#ifdef DDR_BACKUPMODE
+	if (ddrBackup == DRAM_BOOT_STATUS_WARM) {
+#ifdef DDR_BACKUPMODE_HALF	/* for Half channel(ch0,1 only) */
+		PutStr(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
+		send_dbcmd(0x08040001);
+		wait_dbcmd();
+		send_dbcmd(0x0A040001);
+		wait_dbcmd();
+		send_dbcmd(0x04040010);
+		wait_dbcmd();
+
+		if (Prr_Product == PRR_PRODUCT_H3) {
+			send_dbcmd(0x08140001);
+			wait_dbcmd();
+			send_dbcmd(0x0A140001);
+			wait_dbcmd();
+			send_dbcmd(0x04140010);
+			wait_dbcmd();
+		}
+#else /* DDR_BACKUPMODE_HALF                              //for All channels */
+		send_dbcmd(0x08840001);
+		wait_dbcmd();
+		send_dbcmd(0x0A840001);
+		wait_dbcmd();
+
+		send_dbcmd(0x04840010);
+		wait_dbcmd();
+#endif /* DDR_BACKUPMODE_HALF */
+	}
+#endif /* DDR_BACKUPMODE */
+
+	mmio_write_32(DBSC_DBRFEN, 0x00000001);
+	/* dram access enable */
+	mmio_write_32(DBSC_DBACEN, 0x00000001);
+
+	MSG_LF("dbsc_regset_post(done)");
+
+}
+
+/*******************************************************************************
+ *	DFI_INIT_START
+ ******************************************************************************/
+static uint32_t dfi_init_start(void)
+{
+	uint32_t ch;
+	uint32_t phytrainingok;
+	uint32_t retry;
+	uint32_t dataL;
+	const uint32_t RETRY_MAX = 0x10000;
+
+	/***********************************************************************
+	set IE=1 when init_start_disable==0
+	***********************************************************************/
+	if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_MODE_0) &
+	    0x01) {
+		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
+	} else {
+		ddr_setval_ach_as(_reg_PHY_IE_MODE,
+				  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+						_reg_PHY_IE_MODE));
+	}
+
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+
+	/***********************************************************************
+		PLL3 Disable
+	***********************************************************************/
+		/* protect register interface */
+		ddrphy_regif_idle();
+
+		pll3_control(0);
+
+	/***********************************************************************
+		init start
+	***********************************************************************/
+		/* dbdficnt0:
+		 * dfi_dram_clk_disable=1
+		 * dfi_frequency = 0
+		 * freq_ratio = 01 (2:1)
+		 * init_start =0
+		 */
+		foreach_vch(ch)
+		    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
+		dsb_sev();
+
+		/* dbdficnt0:
+		 * dfi_dram_clk_disable=1
+		 * dfi_frequency = 0
+		 * freq_ratio = 01 (2:1)
+		 * init_start =1
+		 */
+		foreach_vch(ch)
+		    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
+		dsb_sev();
+
+	} else {
+		ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02);
+		dsb_sev();
+		ddrphy_regif_idle();
+	}
+
+	/* dll_rst negate */
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01);
+	dsb_sev();
+
+	/***********************************************************************
+	wait init_complete
+	***********************************************************************/
+	phytrainingok = 0;
+	retry = 0;
+	while (retry++ < RETRY_MAX) {
+		foreach_vch(ch) {
+			dataL = mmio_read_32(DBSC_INITCOMP(ch));
+			if (dataL & 0x00000001)
+				phytrainingok |= (1U << ch);
+		}
+		dsb_sev();
+		if (phytrainingok == ddr_phyvalid)
+			break;
+		if (retry % 256 == 0)
+			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
+	}
+
+	/***********************************************************************
+	all ch ok?
+	***********************************************************************/
+	if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) {
+		return (0xff);
+	}
+	/* dbdficnt0:
+	 * dfi_dram_clk_disable=0
+	 * dfi_frequency = 0
+	 * freq_ratio = 01 (2:1)
+	 * init_start =0
+	 */
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010);
+	dsb_sev();
+
+	return 0;
+}
+
+/*******************************************************************************
+ *	drivablity setting : CMOS MODE ON/OFF
+ ******************************************************************************/
+static void change_lpddr4_en(uint32_t mode)
+{
+	uint32_t ch;
+	uint32_t i;
+	uint32_t dataL;
+	const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
+		_reg_PHY_PAD_ADDR_DRIVE,
+		_reg_PHY_PAD_CLK_DRIVE,
+		_reg_PHY_PAD_CS_DRIVE
+	};
+
+	for (i = 0; i < 3; i++) {
+		foreach_vch(ch) {
+			dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
+			if (mode) {
+				dataL |= (1U << 14);
+			} else {
+				dataL &= ~(1U << 14);
+			}
+			ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL);
+		}
+	}
+}
+
+/*******************************************************************************
+ *	drivablity setting
+ ******************************************************************************/
+static uint32_t set_term_code(void)
+{
+	int32_t i;
+	uint32_t ch, index;
+	uint32_t dataL;
+	uint32_t chip_id[2];
+	uint32_t term_code;
+	uint32_t override;
+	term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+				  _reg_PHY_PAD_DATA_TERM);
+	override = 0;
+	for (i = 0; i < 2; i++)
+		chip_id[i] = mmio_read_32(LIFEC_CHIPID(i));
+
+	index = 0;
+	while (1) {
+		if (TermcodeBySample[index][0] == 0xffffffff) {
+			break;
+		}
+		if ((TermcodeBySample[index][0] == chip_id[0])
+		    && (TermcodeBySample[index][1] == chip_id[1])) {
+			term_code = TermcodeBySample[index][2];
+			override = 1;
+			break;
+		}
+		index++;
+	}
+
+	if (override) {
+		for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
+			dataL =
+			    ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+					  _reg_PHY_PAD_TERM_X[index]);
+			dataL = (dataL & ~0x0001ffff) | term_code;
+			ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL);
+		}
+	} else if ((Prr_Product == PRR_PRODUCT_M3)
+		   && (Prr_Cut == PRR_PRODUCT_10)) {
+		/*  non */
+	} else {
+		ddr_setval_ach_as(_reg_PHY_IE_MODE,
+				  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+						_reg_PHY_IE_MODE));
+		ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
+			       (ddrtbl_getval
+				(_cnf_DDR_PHY_ADR_G_REGSET,
+				 _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000));
+		ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01);
+		ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01);
+		foreach_vch(ch) {
+			do {
+				dataL =
+				    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
+			} while (!(dataL & 0x00800000));
+		}
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+			foreach_vch(ch) {
+				uint32_t pvtr;
+				uint32_t pvtp;
+				uint32_t pvtn;
+				dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
+				pvtr = (dataL >> 12) & 0x1f;
+				pvtr += 8;
+				if (pvtr > 0x1f)
+					pvtr = 0x1f;
+				dataL =
+				    ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
+				pvtn = (dataL >> 6) & 0x03f;
+				pvtp = (dataL >> 0) & 0x03f;
+
+				for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
+				     index++) {
+					dataL =
+					    ddrtbl_getval
+					    (_cnf_DDR_PHY_ADR_G_REGSET,
+					     _reg_PHY_PAD_TERM_X[index]);
+					dataL = (dataL & ~0x0001ffff)
+					    | (pvtr << 12)
+					    | (pvtn << 6)
+					    | (pvtp);
+					ddr_setval(ch,
+						   _reg_PHY_PAD_TERM_X[index],
+						   dataL);
+				}
+			}
+		} else {	/*  M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
+			foreach_vch(ch) {
+				for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
+				     index++) {
+					dataL =
+					    ddr_getval(ch,
+						       _reg_PHY_PAD_TERM_X
+						       [index]);
+					ddr_setval(ch,
+						   _reg_PHY_PAD_TERM_X[index],
+						   (dataL & 0xFFFE0FFF) |
+						   0x00015000);
+				}
+			}
+		}
+	}
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		/*  non */
+	} else {
+		ddr_padcal_tcompensate_getinit(override);
+	}
+	return 0;
+}
+
+/*******************************************************************************
+ *	DDR mode register setting
+ ******************************************************************************/
+static void ddr_register_set(uint32_t ch)
+{
+	int32_t fspwp;
+	uint32_t chind;
+	uint32_t tmp;
+
+	chind = ch << 20;
+	for (fspwp = 1; fspwp >= 0; fspwp--) {
+		/*MR13,fspwp */
+		send_dbcmd(0x0e040d08 | chind | (fspwp << 6));
+
+		tmp =
+		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
+				  _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]);
+		send_dbcmd(0x0e040100 | chind | tmp);
+
+		tmp =
+		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
+				  _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]);
+		send_dbcmd(0x0e040200 | chind | tmp);
+
+		tmp =
+		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
+				  _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]);
+		send_dbcmd(0x0e040300 | chind | tmp);
+
+		tmp =
+		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
+				  _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]);
+		send_dbcmd(0x0e040b00 | chind | tmp);
+
+		tmp =
+		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
+				  _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]);
+		send_dbcmd(0x0e040c00 | chind | tmp);
+
+		tmp =
+		    ddrtbl_getval(_cnf_DDR_PI_REGSET,
+				  _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]);
+		send_dbcmd(0x0e040e00 | chind | tmp);
+		/* MR22 */
+		send_dbcmd(0x0e041600 | chind | 0x16);
+	}
+}
+
+/*******************************************************************************
+ *	Training handshake functions
+ ******************************************************************************/
+static inline uint32_t wait_freqchgreq(uint32_t assert)
+{
+	uint32_t dataL;
+	uint32_t count;
+	uint32_t ch;
+	count = 100000;
+
+	/* H3 Ver.1.x cannot see frqchg_req */
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		return 0;
+	}
+
+	if (assert) {
+		do {
+			dataL = 1;
+			foreach_vch(ch) {
+				dataL &= mmio_read_32(DBSC_DBPDSTAT(ch));
+			}
+			count = count - 1;
+		} while (((dataL & 0x01) != 0x01) & (count != 0));
+	} else {
+		do {
+			dataL = 0;
+			foreach_vch(ch) {
+				dataL |= mmio_read_32(DBSC_DBPDSTAT(ch));
+			}
+			count = count - 1;
+		} while (((dataL & 0x01) != 0x00) & (count != 0));
+	}
+
+	return (count == 0);
+}
+
+static inline void set_freqchgack(uint32_t assert)
+{
+	uint32_t ch;
+	uint32_t dataL;
+	if (assert)
+		dataL = 0x0CF20000;
+	else
+		dataL = 0x00000000;
+
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBPDCNT2(ch), dataL);
+}
+
+static inline void set_dfifrequency(uint32_t freq)
+{
+	uint32_t ch;
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		foreach_vch(ch)
+		    mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
+	} else {
+		foreach_vch(ch) {
+			mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24,
+					   (freq << 24));
+		}
+	}
+	dsb_sev();
+}
+
+static uint32_t pll3_freq(uint32_t on)
+{
+	uint32_t timeout;
+
+	timeout = wait_freqchgreq(1);
+
+	if (timeout) {
+		return (1);
+	}
+
+	pll3_control(on);
+	set_dfifrequency(on);
+
+	set_freqchgack(1);
+	timeout = wait_freqchgreq(0);
+	set_freqchgack(0);
+
+	if (timeout) {
+		FATAL_MSG("Time out[2]");
+		return (1);
+	}
+	return (0);
+}
+
+/*******************************************************************************
+ *	update dly
+ ******************************************************************************/
+static void update_dly(void)
+{
+	ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01);
+	ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01);
+}
+
+/*******************************************************************************
+ *	training by pi
+ ******************************************************************************/
+static uint32_t pi_training_go(void)
+{
+	uint32_t flag;
+	uint32_t dataL;
+	uint32_t retry;
+	const uint32_t RETRY_MAX = 4096 * 16;
+	uint32_t ch;
+
+	uint32_t mst_ch;
+	uint32_t cur_frq;
+	uint32_t complete;
+	uint32_t frqchg_req;
+
+	/* ********************************************************************* */
+
+	/***********************************************************************
+	pi_start
+	***********************************************************************/
+	ddr_setval_ach(_reg_PI_START, 0x01);
+	foreach_vch(ch)
+	    ddr_getval(ch, _reg_PI_INT_STATUS);
+
+	/* set dfi_phymstr_ack = 1 */
+	mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001);
+	dsb_sev();
+
+	/***********************************************************************
+	wait pi_int_status[0]
+	***********************************************************************/
+	mst_ch = 0;
+	flag = 0;
+	complete = 0;
+	cur_frq = 0;
+	retry = RETRY_MAX;
+	do {
+		frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
+
+		/* H3 Ver.1.x cannot see frqchg_req */
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+			if ((retry % 4096) == 1) {
+				frqchg_req = 1;
+			} else {
+				frqchg_req = 0;
+			}
+		}
+
+		if (frqchg_req) {
+			if (cur_frq) {
+				/* Low frequency */
+				flag = pll3_freq(0);
+				cur_frq = 0;
+			} else {
+				/* High frequency */
+				flag = pll3_freq(1);
+				cur_frq = 1;
+			}
+			if (flag)
+				break;
+		} else {
+			if (cur_frq) {
+				foreach_vch(ch) {
+					if (complete & (1U << ch))
+						continue;
+					dataL =
+					    ddr_getval(ch, _reg_PI_INT_STATUS);
+					if (dataL & 0x01) {
+						complete |= (1U << ch);
+					}
+				}
+				if (complete == ddr_phyvalid)
+					break;
+			}
+		}
+	} while (--retry);
+	foreach_vch(ch) {
+		/* dummy read */
+		dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
+		dataL = ddr_getval(ch, _reg_PI_INT_STATUS);
+		ddr_setval(ch, _reg_PI_INT_ACK, dataL);
+	}
+	if (ddrphy_regif_chk()) {
+		return (0xfd);
+	}
+	return complete;
+}
+
+/*******************************************************************************
+ *	Initialize ddr
+ ******************************************************************************/
+static uint32_t init_ddr(void)
+{
+	int32_t i;
+	uint32_t dataL;
+	uint32_t phytrainingok;
+	uint32_t ch;
+	uint32_t err;
+
+	MSG_LF("init_ddr:0\n");
+
+#ifdef DDR_BACKUPMODE
+	rcar_dram_get_boot_status(&ddrBackup);
+#endif
+
+	/***********************************************************************
+	unlock phy
+	***********************************************************************/
+	/* Unlock DDRPHY register(AGAIN) */
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A);
+	dsb_sev();
+
+	if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
+	     || (Prr_Product == PRR_PRODUCT_M3N)
+	     || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en))
+		reg_ddrphy_write_a(0x00001010, 0x01000001);
+	else
+		reg_ddrphy_write_a(0x00001010, 0x00000001);
+	/***********************************************************************
+	dbsc register pre-setting
+	***********************************************************************/
+	dbsc_regset_pre();
+
+	/***********************************************************************
+	load ddrphy registers
+	***********************************************************************/
+
+	ddrtbl_load();
+
+	/***********************************************************************
+	configure ddrphy registers
+	***********************************************************************/
+	ddr_config();
+
+	/***********************************************************************
+	dfi_reset assert
+	***********************************************************************/
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x01);
+	dsb_sev();
+
+	/***********************************************************************
+	dbsc register set
+	***********************************************************************/
+	dbsc_regset();
+	MSG_LF("init_ddr:1\n");
+
+	/***********************************************************************
+	dfi_reset negate
+	***********************************************************************/
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBPDCNT0(ch), 0x00);
+	dsb_sev();
+
+	/***********************************************************************
+	dfi_init_start (start ddrphy)
+	***********************************************************************/
+	err = dfi_init_start();
+	if (err) {
+		return INITDRAM_ERR_I;
+	}
+	MSG_LF("init_ddr:2\n");
+
+	/***********************************************************************
+	ddr backupmode end
+	***********************************************************************/
+#ifdef DDR_BACKUPMODE
+	if (ddrBackup) {
+		NOTICE("[WARM_BOOT]");
+	} else {
+		NOTICE("[COLD_BOOT]");
+	}
+	err = rcar_dram_update_boot_status(ddrBackup);
+	if (err) {
+		NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
+		return INITDRAM_ERR_I;
+	}
+#endif
+	MSG_LF("init_ddr:3\n");
+
+	/***********************************************************************
+	override term code after dfi_init_complete
+	***********************************************************************/
+	err = set_term_code();
+	if (err) {
+		return INITDRAM_ERR_I;
+	}
+	MSG_LF("init_ddr:4\n");
+
+	/***********************************************************************
+	rx offset calibration
+	***********************************************************************/
+	if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N)
+	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+		err = rx_offset_cal_hw();
+	} else {
+		err = rx_offset_cal();
+	}
+	if (err)
+		return (INITDRAM_ERR_O);
+	MSG_LF("init_ddr:5\n");
+
+	/***********************************************************************
+	set ie_mode=1
+	***********************************************************************/
+	ddr_setval_ach_as(_reg_PHY_IE_MODE,
+			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+					_reg_PHY_IE_MODE));
+
+	/***********************************************************************
+	check register i/f is alive
+	***********************************************************************/
+	err = ddrphy_regif_chk();
+	if (err) {
+		return (INITDRAM_ERR_O);
+	}
+	MSG_LF("init_ddr:6\n");
+
+	/***********************************************************************
+	phy initialize end
+	***********************************************************************/
+
+	/***********************************************************************
+	setup DDR mode registers
+	***********************************************************************/
+	/* CMOS MODE */
+	change_lpddr4_en(0);
+
+	ch = 0x08;
+
+	/* PDE */
+	send_dbcmd(0x08040000 | (0x00100000 * ch));
+
+	/* PDX */
+	send_dbcmd(0x08040001 | (0x00100000 * ch));
+
+	/* MR22 (ODTCS & RQZ */
+	send_dbcmd(0x0e041600 | (0x00100000 * ch) | 0x16);
+
+	/* ZQCAL start */
+	send_dbcmd(0x0d04004F | (0x00100000 * ch));
+	rcar_micro_delay(100);
+
+	/* ZQLAT */
+	send_dbcmd(0x0d040051 | (0x00100000 * ch));
+
+	/***********************************************************************
+	Thermal sensor setting
+	***********************************************************************/
+	/* THCTR Bit6: PONM=0 , Bit0: THSST=1   */
+	dataL =
+	    ((*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBF) | 0x00000001;
+	*((volatile uint32_t *)THS1_THCTR) = dataL;
+
+	/***********************************************************************
+	setup DDR mode registers
+	***********************************************************************/
+	foreach_vch(ch) {
+		ddr_register_set(ch);
+	}
+	/* LPDDR4 MODE */
+	change_lpddr4_en(1);
+
+	MSG_LF("init_ddr:7\n");
+
+	/***********************************************************************
+	mask CS_MAP if RANKx is not found
+	***********************************************************************/
+	foreach_vch(ch) {
+		dataL = ddr_getval(ch, _reg_PI_CS_MAP);
+		if (!(ch_have_this_cs[0] & (1U << ch)))
+			dataL = dataL & 0x0a;
+		if (!(ch_have_this_cs[1] & (1U << ch)))
+			dataL = dataL & 0x05;
+		ddr_setval(ch, _reg_PI_CS_MAP, dataL);
+	}
+
+	/***********************************************************************
+	exec pi_training
+	***********************************************************************/
+	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
+	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
+
+	phytrainingok = pi_training_go();
+
+	if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
+		return (INITDRAM_ERR_T | phytrainingok);
+	}
+
+	MSG_LF("init_ddr:8\n");
+
+	/***********************************************************************
+	CACS DLY ADJUST
+	***********************************************************************/
+	dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
+	foreach_vch(ch) {
+		int16_t adj;
+		for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
+			adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
+			ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+				   dataL + adj);
+		}
+	}
+	update_dly();
+	MSG_LF("init_ddr:9\n");
+
+	/***********************************************************************
+	H3 fix rd latency to avoid bug in elasitic buffe
+	***********************************************************************/
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		adjust_rddqs_latency();
+	}
+
+	/***********************************************************************
+	Adjust Write path latency
+	***********************************************************************/
+	if (ddrtbl_getval
+	    (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD))
+		adjust_wpath_latency();
+
+	/***********************************************************************
+	RDQLVL Training
+	***********************************************************************/
+	if ((Prr_Product == PRR_PRODUCT_H3) || (Prr_Product == PRR_PRODUCT_M3)) {
+		ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
+	} else {
+		ddr_setval_ach_as(_reg_PHY_IE_MODE,
+				  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+						_reg_PHY_IE_MODE));
+	}
+
+	err = rdqdm_man();
+	if (err) {
+		return (INITDRAM_ERR_T);
+	}
+	update_dly();
+	MSG_LF("init_ddr:10\n");
+
+	/***********************************************************************
+	WDQLVL Training
+	***********************************************************************/
+	err = wdqdm_man();
+	if (err) {
+		return (INITDRAM_ERR_T);
+	}
+	update_dly();
+	MSG_LF("init_ddr:11\n");
+
+	/***********************************************************************
+	training complete, setup dbsc
+	***********************************************************************/
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
+	    || (Prr_Product == PRR_PRODUCT_M3N)
+	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+		ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00);
+		ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00);
+	}
+
+	dbsc_regset_post();
+	MSG_LF("init_ddr:12\n");
+
+	return phytrainingok;
+}
+
+/*******************************************************************************
+ *	SW LEVELING COMMON
+ ******************************************************************************/
+static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
+{
+	uint32_t ch;
+	uint32_t dataL;
+	uint32_t retry;
+	uint32_t waiting;
+	uint32_t err;
+
+	const uint32_t RETRY_MAX = 0x1000;
+
+	err = 0;
+	/* set EXIT -> OP_DONE is cleared */
+	ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
+
+	/* kick */
+	foreach_vch(ch) {
+		if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) {
+			ddr_setval(ch, reg_cs, ddr_csn);
+			ddr_setval(ch, reg_kick, 0x01);
+		}
+	}
+	foreach_vch(ch) {
+		/*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */
+		ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+	}
+	waiting = ch_have_this_cs[ddr_csn % 2];
+	dsb_sev();
+	retry = RETRY_MAX;
+	do {
+		foreach_vch(ch) {
+			if (!(waiting & (1U << ch)))
+				continue;
+			dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+			if (dataL & 0x01)
+				waiting &= ~(1U << ch);
+		}
+		retry--;
+	} while (waiting && (retry > 0));
+	if (retry == 0) {
+		err = 1;
+	}
+
+	dsb_sev();
+	/* set EXIT -> OP_DONE is cleared */
+	ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
+	dsb_sev();
+
+	return err;
+}
+
+/*******************************************************************************
+ *	WDQ TRAINING
+ ******************************************************************************/
+static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
+{
+	int32_t i, k;
+	uint32_t cs, slice;
+	uint32_t dataL;
+
+	/***********************************************************************
+	clr of training results buffer
+	***********************************************************************/
+	cs = ddr_csn % 2;
+	dataL = Boardcnf->dqdm_dly_w;
+	for (slice = 0; slice < SLICE_CNT; slice++) {
+		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+			continue;
+
+		for (i = 0; i <= 8; i++) {
+			if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch))
+				wdqdm_dly[ch][cs][slice][i] =
+				    wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
+			else
+				wdqdm_dly[ch][cs][slice][i] = dataL;
+			wdqdm_le[ch][cs][slice][i] = 0;
+			wdqdm_te[ch][cs][slice][i] = 0;
+		}
+		wdqdm_st[ch][cs][slice] = 0;
+		wdqdm_win[ch][cs][slice] = 0;
+	}
+}
+
+static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
+{
+	int32_t i, k;
+	uint32_t cs, slice;
+	uint32_t dataL;
+	uint32_t err;
+	const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0;
+
+	int32_t min_win;
+	int32_t win;
+	int8_t _adj;
+	int16_t adj;
+	uint32_t dq;
+
+	/***********************************************************************
+	analysis of training results
+	***********************************************************************/
+	err = 0;
+	for (slice = 0; slice < SLICE_CNT; slice += 1) {
+		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+			continue;
+
+		cs = ddr_csn % 2;
+		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
+		ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
+		for (i = 0; i < 9; i++) {
+			dq = slice * 8 + i;
+			if (i == 8)
+				_adj = Boardcnf->ch[ch].dm_adj_w[slice];
+			else
+				_adj = Boardcnf->ch[ch].dq_adj_w[dq];
+			adj = _f_scale_adj(_adj);
+
+			dataL =
+			    ddr_getval_s(ch, slice,
+					 _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
+			ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
+				     dataL);
+			wdqdm_dly[ch][cs][slice][i] = dataL;
+		}
+		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
+		dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
+		wdqdm_st[ch][cs][slice] = dataL;
+		min_win = INT_LEAST32_MAX;
+		for (i = 0; i <= 8; i++) {
+			ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
+				     i);
+
+			dataL =
+			    ddr_getval_s(ch, slice,
+					 _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
+			wdqdm_te[ch][cs][slice][i] = dataL;
+			dataL =
+			    ddr_getval_s(ch, slice,
+					 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
+			wdqdm_le[ch][cs][slice][i] = dataL;
+			win =
+			    (int32_t) wdqdm_te[ch][cs][slice][i] -
+			    wdqdm_le[ch][cs][slice][i];
+			if (min_win > win)
+				min_win = win;
+			if (dataL >= _par_WDQLVL_RETRY_THRES)
+				err = 2;
+		}
+		wdqdm_win[ch][cs][slice] = min_win;
+		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01);
+	}
+	return err;
+}
+
+static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
+{
+	uint32_t i;
+	uint32_t ch, slice;
+	uint32_t tgt_cs, src_cs;
+	uint32_t tmp_r;
+
+	/***********************************************************************
+	copy of training results
+	***********************************************************************/
+	foreach_vch(ch) {
+		for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) {
+			for (slice = 0; slice < SLICE_CNT; slice++) {
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_PER_CS_TRAINING_INDEX,
+					     tgt_cs);
+				src_cs = ddr_csn % 2;
+				if (!(ch_have_this_cs[1] & (1U << ch)))
+					src_cs = 0;
+				for (i = 0; i <= 4; i += 4) {
+					if (restore)
+						tmp_r =
+						    rdqdm_dly[ch][tgt_cs][slice]
+						    [i];
+					else
+						tmp_r =
+						    rdqdm_dly[ch][src_cs][slice]
+						    [i];
+
+					ddr_setval_s(ch, slice,
+						     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+						     [i], tmp_r);
+				}
+			}
+		}
+	}
+}
+
+static uint32_t wdqdm_man1(void)
+{
+	int32_t k;
+	uint32_t ch, cs, slice;
+	uint32_t ddr_csn;
+	uint32_t dataL;
+	uint32_t err;
+	uint32_t err_flg;
+
+	/***********************************************************************
+	manual execution of training
+	***********************************************************************/
+	uint32_t high_dq[DRAM_CH_CNT];
+	uint32_t mr14_csab0_bak[DRAM_CH_CNT];
+
+	foreach_vch(ch) {
+		high_dq[ch] = 0;
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+			if (k >= 2)
+				high_dq[ch] |= (1U << slice);
+		}
+	}
+
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+		ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x00);
+
+	err = 0;
+	/* CLEAR PREV RESULT */
+	for (cs = 0; cs < CS_CNT; cs++) {
+		ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
+		if (((Prr_Product == PRR_PRODUCT_H3)
+		     && (Prr_Cut > PRR_PRODUCT_11))
+		    || (Prr_Product == PRR_PRODUCT_M3N)
+		    || (Prr_Product == PRR_PRODUCT_V3H)) {
+			ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS,
+					  0x01);
+		} else {
+			ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS,
+					  0x01);
+		}
+	}
+	ddrphy_regif_idle();
+
+	err_flg = 0;
+
+	for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+			foreach_vch(ch) {
+				dataL = mmio_read_32(DBSC_DBDFICNT(ch));
+				dataL &= ~(0x00ffU << 16);
+
+				if (ddr_csn >= 2)
+					k = (high_dq[ch] ^ 0x0f);
+				else
+					k = high_dq[ch];
+				dataL |= (k << 16);
+				mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+				ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k);
+			}
+		}
+		if (((Prr_Product == PRR_PRODUCT_H3)
+		     && (Prr_Cut <= PRR_PRODUCT_11))
+		    || ((Prr_Product == PRR_PRODUCT_M3)
+			&& (Prr_Cut == PRR_PRODUCT_10))) {
+			wdqdm_cp(ddr_csn, 0);
+		}
+
+		foreach_vch(ch) {
+			dataL =
+			    ddr_getval(ch,
+				       _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]);
+			ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL);
+		}
+
+		/* KICK WDQLVL */
+		err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ);
+		if (err)
+			goto err_exit;
+
+		if (ddr_csn == 0)
+			foreach_vch(ch) {
+			mr14_csab0_bak[ch] =
+			    ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]);
+		} else
+			foreach_vch(ch) {
+			ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0],
+				   mr14_csab0_bak[ch]);
+			}
+		foreach_vch(ch) {
+			if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
+				wdqdm_clr1(ch, ddr_csn);
+				continue;
+			}
+			err = wdqdm_ana1(ch, ddr_csn);
+			if (err)
+				err_flg |= (1U << (ddr_csn * 4 + ch));
+			ddrphy_regif_idle();
+		}
+	}
+err_exit:
+	ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
+	foreach_vch(ch) {
+		dataL = mmio_read_32(DBSC_DBDFICNT(ch));
+		dataL &= ~(0x00ffU << 16);
+		mmio_write_32(DBSC_DBDFICNT(ch), dataL);
+		ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
+	}
+	return (err_flg | err);
+}
+
+static uint32_t wdqdm_man(void)
+{
+	uint32_t err, retry_cnt;
+	const uint32_t retry_max = 0x10;
+
+	ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
+	    || (Prr_Product == PRR_PRODUCT_M3N)
+	    || (Prr_Product == PRR_PRODUCT_V3H)) {
+		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
+			       (DBSC_DBTR(12) & 0xFF) + 1);
+	} else {
+		ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
+			       (DBSC_DBTR(12) & 0xFF) + 1);
+	}
+	ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF));
+
+	retry_cnt = 0;
+	do {
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+			err = wdqdm_man1();
+		} else {
+			uint32_t ch, ddr_csn, mr14_bkup[4][4];
+
+			ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
+			ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
+				       0x01);
+			if ((Prr_Product == PRR_PRODUCT_M3N)
+			    || (Prr_Product == PRR_PRODUCT_V3H)) {
+				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
+					       0x0C);
+			} else {
+				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C);
+			}
+			dsb_sev();
+			err = wdqdm_man1();
+			foreach_vch(ch) {
+				for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+					mr14_bkup[ch][ddr_csn] =
+					    ddr_getval(ch,
+						       _reg_PI_MR14_DATA_Fx_CSx
+						       [1][ddr_csn]);
+					dsb_sev();
+				}
+			}
+
+			if ((Prr_Product == PRR_PRODUCT_M3N)
+			    || (Prr_Product == PRR_PRODUCT_V3H)) {
+				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
+					       0x04);
+			} else {
+				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04);
+			}
+			pvtcode_update();
+			err = wdqdm_man1();
+			foreach_vch(ch) {
+				for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+					mr14_bkup[ch][ddr_csn] =
+					    (mr14_bkup[ch][ddr_csn] +
+					     ddr_getval(ch,
+							_reg_PI_MR14_DATA_Fx_CSx
+							[1][ddr_csn])) / 2;
+					ddr_setval(ch,
+						   _reg_PI_MR14_DATA_Fx_CSx[1]
+						   [ddr_csn],
+						   mr14_bkup[ch][ddr_csn]);
+				}
+			}
+
+			ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
+				       0x00);
+			if ((Prr_Product == PRR_PRODUCT_M3N)
+			    || (Prr_Product == PRR_PRODUCT_V3H)) {
+				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
+					       0x00);
+				ddr_setval_ach
+				    (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1,
+				     0x00);
+				ddr_setval_ach
+				    (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1,
+				     0x00);
+			} else {
+				ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00);
+				ddr_setval_ach
+				    (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT,
+				     0x00);
+				ddr_setval_ach
+				    (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT,
+				     0x00);
+			}
+			ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE,
+				       0x00);
+
+			pvtcode_update2();
+			err = wdqdm_man1();
+			ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
+		}
+	} while (err && (++retry_cnt < retry_max));
+
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) {
+		wdqdm_cp(0, 1);
+	}
+
+	return (retry_cnt >= retry_max);
+}
+
+/*******************************************************************************
+ *	RDQ TRAINING
+ ******************************************************************************/
+static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
+{
+	int32_t i, k;
+	uint32_t cs, slice;
+	uint32_t dataL;
+
+	/***********************************************************************
+	clr of training results buffer
+	***********************************************************************/
+	cs = ddr_csn % 2;
+	dataL = Boardcnf->dqdm_dly_r;
+	for (slice = 0; slice < SLICE_CNT; slice++) {
+		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+			continue;
+
+		for (i = 0; i <= 8; i++) {
+			if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) {
+				rdqdm_dly[ch][cs][slice][i] =
+				    rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
+				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
+				    rdqdm_dly[ch][CS_CNT - 1 - cs][slice +
+								   SLICE_CNT]
+				    [i];
+			} else {
+				rdqdm_dly[ch][cs][slice][i] = dataL;
+				rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+			}
+			rdqdm_le[ch][cs][slice][i] = 0;
+			rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
+			rdqdm_te[ch][cs][slice][i] = 0;
+			rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0;
+			rdqdm_nw[ch][cs][slice][i] = 0;
+			rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0;
+		}
+		rdqdm_st[ch][cs][slice] = 0;
+		rdqdm_win[ch][cs][slice] = 0;
+	}
+}
+
+static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
+{
+	int32_t i, k;
+	uint32_t cs, slice;
+	uint32_t dataL;
+	uint32_t err;
+	int8_t _adj;
+	int16_t adj;
+	uint32_t dq;
+
+	/***********************************************************************
+	analysis of training results
+	***********************************************************************/
+	err = 0;
+	for (slice = 0; slice < SLICE_CNT; slice++) {
+		int32_t min_win;
+		int32_t win;
+		uint32_t rdq_status_obs_select;
+		k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+		if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+			continue;
+
+		cs = ddr_csn % 2;
+		ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
+		ddrphy_regif_idle();
+
+		ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
+		ddrphy_regif_idle();
+
+		for (i = 0; i <= 8; i++) {
+			dq = slice * 8 + i;
+			if (i == 8)
+				_adj = Boardcnf->ch[ch].dm_adj_r[slice];
+			else
+				_adj = Boardcnf->ch[ch].dq_adj_r[dq];
+
+			adj = _f_scale_adj(_adj);
+
+			dataL =
+			    ddr_getval_s(ch, slice,
+					 _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) +
+			    adj;
+			ddr_setval_s(ch, slice,
+				     _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
+				     dataL);
+			rdqdm_dly[ch][cs][slice][i] = dataL;
+
+			dataL =
+			    ddr_getval_s(ch, slice,
+					 _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) +
+			    adj;
+			ddr_setval_s(ch, slice,
+				     _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
+				     dataL);
+			rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL;
+		}
+		min_win = INT_LEAST32_MAX;
+		for (i = 0; i <= 8; i++) {
+			dataL =
+			    ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
+			rdqdm_st[ch][cs][slice] = dataL;
+			rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL;
+			/* k : rise/fall */
+			for (k = 0; k < 2; k++) {
+				if (i == 8) {
+					rdq_status_obs_select = 16 + 8 * k;
+				} else {
+					rdq_status_obs_select = i + k * 8;
+				}
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
+					     rdq_status_obs_select);
+
+				dataL =
+				    ddr_getval_s(ch, slice,
+						 _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
+				rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
+				    dataL;
+
+				dataL =
+				    ddr_getval_s(ch, slice,
+						 _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
+				rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
+				    dataL;
+
+				dataL =
+				    ddr_getval_s(ch, slice,
+						 _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
+				rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
+				    dataL;
+
+				win =
+				    (int32_t) rdqdm_te[ch][cs][slice +
+							       SLICE_CNT *
+							       k][i] -
+				    rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
+				if (i != 8) {
+					if (min_win > win)
+						min_win = win;
+				}
+			}
+		}
+		rdqdm_win[ch][cs][slice] = min_win;
+		if (min_win <= 0) {
+			err = 2;
+		}
+	}
+	return (err);
+}
+
+static uint32_t rdqdm_man1(void)
+{
+	uint32_t ch;
+	uint32_t ddr_csn;
+	uint32_t err;
+
+	/***********************************************************************
+	manual execution of training
+	***********************************************************************/
+	err = 0;
+
+	for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+		/* KICK RDQLVL */
+		err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
+		if (err)
+			goto err_exit;
+
+		foreach_vch(ch) {
+			if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
+				rdqdm_clr1(ch, ddr_csn);
+				ddrphy_regif_idle();
+				continue;
+			}
+			err = rdqdm_ana1(ch, ddr_csn);
+			ddrphy_regif_idle();
+			if (err)
+				goto err_exit;
+		}
+	}
+err_exit:
+	return (err);
+}
+
+static uint32_t rdqdm_man(void)
+{
+	uint32_t err, retry_cnt;
+	const uint32_t retry_max = 0x01;
+
+	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
+			  0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+						     _reg_PHY_DQ_TSEL_ENABLE));
+	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
+			  0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+						     _reg_PHY_DQS_TSEL_ENABLE));
+	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
+			  0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+						     _reg_PHY_DQ_TSEL_SELECT));
+	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
+			  0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+						     _reg_PHY_DQS_TSEL_SELECT));
+
+	retry_cnt = 0;
+	do {
+		err = rdqdm_man1();
+		ddrphy_regif_idle();
+	} while (err && (++retry_cnt < retry_max));
+	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
+			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+					_reg_PHY_DQ_TSEL_ENABLE));
+	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
+			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+					_reg_PHY_DQS_TSEL_ENABLE));
+	ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
+			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+					_reg_PHY_DQ_TSEL_SELECT));
+	ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
+			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+					_reg_PHY_DQS_TSEL_SELECT));
+
+	return (retry_cnt >= retry_max);
+}
+
+/*******************************************************************************
+ *	rx offset calibration
+ ******************************************************************************/
+static int32_t _find_change(uint64_t val, uint32_t dir)
+{
+	int32_t i;
+	uint32_t startval;
+	uint32_t curval;
+	const uint32_t VAL_END = 0x3f;
+
+	if (dir == 0) {
+		startval = (val & 0x01);
+		for (i = 1; i <= VAL_END; i++) {
+			curval = (val >> i) & 0x01;
+			if (curval != startval)
+				return (i);
+		}
+		return (VAL_END);
+	} else {
+		startval = (val >> dir) & 0x01;
+		for (i = dir - 1; i >= 0; i--) {
+			curval = (val >> i) & 0x01;
+			if (curval != startval)
+				return (i);
+		}
+		return (0);
+	}
+}
+
+static uint32_t _rx_offset_cal_updn(uint32_t code)
+{
+	const uint32_t CODE_MAX = 0x40;
+	uint32_t tmp;
+
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
+		if (code == 0)
+			tmp = (1U << 6) | (CODE_MAX - 1);
+		else if (code <= 0x20)
+			tmp =
+			    ((CODE_MAX - 1 -
+			      (0x20 - code) * 2) << 6) | (CODE_MAX - 1);
+		else
+			tmp =
+			    ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 -
+						     (code - 0x20) * 2);
+	} else {
+		if (code == 0)
+			tmp = (1U << 6) | (CODE_MAX - 1);
+		else
+			tmp = (code << 6) | (CODE_MAX - code);
+	}
+	return tmp;
+}
+
+/* #define RX_OFFSET_FAST */
+static uint32_t rx_offset_cal(void)
+{
+	uint32_t index;
+	uint32_t code;
+	const uint32_t CODE_MAX = 0x40;
+	const uint32_t CODE_STEP = 2;
+	uint32_t ch, slice;
+	uint32_t tmp;
+	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
+	uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
+#ifdef RX_OFFSET_FAST
+	uint32_t adr_st;
+	adr_st = ddr_regdef_adr(_reg_PHY_RX_CAL_X[0]);
+#endif
+	ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
+	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
+	foreach_vch(ch) {
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+				val[ch][slice][index] = 0;
+			}
+		}
+	}
+
+	for (code = 0; code < CODE_MAX / CODE_STEP; code++) {
+		tmp = _rx_offset_cal_updn(code * CODE_STEP);
+#ifdef RX_OFFSET_FAST
+		tmp = tmp | (tmp << 16);
+		for (index = 0; index < (_reg_PHY_RX_CAL_X_NUM + 1) / 2;
+		     index++) {
+			for (slice = 0; slice < 4; slice++)
+				reg_ddrphy_write_a(adr_st + 0x80 * slice +
+						   index, tmp);
+		}
+#else
+		for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+			ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
+		}
+#endif
+		dsb_sev();
+		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as);
+
+		foreach_vch(ch) {
+			for (slice = 0; slice < SLICE_CNT; slice++) {
+				tmp = tmp_ach_as[ch][slice];
+				for (index = 0; index < _reg_PHY_RX_CAL_X_NUM;
+				     index++) {
+					if (tmp & (1U << index)) {
+						val[ch][slice][index] |=
+						    (1ULL << code);
+					} else {
+						val[ch][slice][index] &=
+						    ~(1ULL << code);
+					}
+				}
+			}
+		}
+	}
+	foreach_vch(ch) {
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+				uint64_t tmpval;
+				int32_t lsb, msb;
+				tmpval = val[ch][slice][index];
+				lsb = _find_change(tmpval, 0);
+				msb =
+				    _find_change(tmpval,
+						 (CODE_MAX / CODE_STEP) - 1);
+				tmp = (lsb + msb) >> 1;
+
+				tmp = _rx_offset_cal_updn(tmp * CODE_STEP);
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_RX_CAL_X[index], tmp);
+			}
+		}
+	}
+	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
+	ddr_setval_ach_as(_reg_PHY_IE_MODE,
+			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+					_reg_PHY_IE_MODE));
+
+	return 0;
+}
+
+static uint32_t rx_offset_cal_hw(void)
+{
+	uint32_t ch, slice;
+	uint32_t retry;
+	uint32_t complete;
+	uint32_t tmp;
+	uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
+
+	ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
+	ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
+	ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
+	ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
+
+	retry = 0;
+	while (retry < 4096) {
+		if ((retry & 0xff) == 0) {
+			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
+		}
+		foreach_vch(ch)
+		    for (slice = 0; slice < SLICE_CNT; slice++)
+			tmp_ach_as[ch][slice] =
+			    ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
+
+		complete = 1;
+		foreach_vch(ch) {
+			for (slice = 0; slice < SLICE_CNT; slice++) {
+				tmp = tmp_ach_as[ch][slice];
+				tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f);
+				if (((Prr_Product == PRR_PRODUCT_H3)
+				     && (Prr_Cut > PRR_PRODUCT_11))
+				    || (Prr_Product == PRR_PRODUCT_M3N)
+				    || (Prr_Product == PRR_PRODUCT_V3H)) {
+					if (tmp != 0x3E)
+						complete = 0;
+				} else {
+					if (tmp != 0x40)
+						complete = 0;
+				}
+			}
+		}
+		if (complete)
+			break;
+
+		retry++;
+	}
+	ddr_setval_ach_as(_reg_PHY_IE_MODE,
+			  ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+					_reg_PHY_IE_MODE));
+
+	return (complete == 0);
+}
+
+/*******************************************************************************
+ *	adjust rddqs latency
+ ******************************************************************************/
+static void adjust_rddqs_latency(void)
+{
+	uint32_t ch, slice;
+	uint32_t dly;
+	uint32_t maxlatx2;
+	uint32_t tmp;
+	uint32_t rdlat_adjx2[SLICE_CNT];
+	foreach_vch(ch) {
+		maxlatx2 = 0;
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX,
+				     0x00);
+
+			dly =
+			    ddr_getval_s(ch, slice,
+					 _reg_PHY_RDDQS_GATE_SLAVE_DELAY);
+			tmp =
+			    ddr_getval_s(ch, slice,
+					 _reg_PHY_RDDQS_LATENCY_ADJUST);
+			/* note gate_slave_delay[9] is always 0 */
+			tmp = (tmp << 1) + (dly >> 8);
+			rdlat_adjx2[slice] = tmp;
+			if (maxlatx2 < tmp)
+				maxlatx2 = tmp;
+		}
+		maxlatx2 = ((maxlatx2 + 1) >> 1) << 1;
+		for (slice = 0; slice < SLICE_CNT; slice++) {
+			tmp = maxlatx2 - rdlat_adjx2[slice];
+			tmp = (tmp >> 1);
+			if (tmp) {
+				ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE,
+					     ddr_getval_s(ch, slice,
+							  _reg_PHY_RPTR_UPDATE)
+					     + 1);
+			}
+		}
+	}
+}
+
+/*******************************************************************************
+ *	adjust wpath latency
+ ******************************************************************************/
+static void adjust_wpath_latency(void)
+{
+	uint32_t ch, cs, slice;
+	uint32_t dly;
+	uint32_t wpath_add;
+	const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180;
+
+	foreach_vch(ch) {
+		for (slice = 0; slice < SLICE_CNT; slice += 1) {
+			for (cs = 0; cs < CS_CNT; cs++) {
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_PER_CS_TRAINING_INDEX,
+					     cs);
+				ddr_getval_s(ch, slice,
+					     _reg_PHY_PER_CS_TRAINING_INDEX);
+				dly =
+				    ddr_getval_s(ch, slice,
+						 _reg_PHY_CLK_WRDQS_SLAVE_DELAY);
+				if (dly <= _par_EARLY_THRESHOLD_VAL)
+					continue;
+
+				wpath_add =
+				    ddr_getval_s(ch, slice,
+						 _reg_PHY_WRITE_PATH_LAT_ADD);
+				ddr_setval_s(ch, slice,
+					     _reg_PHY_WRITE_PATH_LAT_ADD,
+					     wpath_add - 1);
+			}
+		}
+	}
+}
+
+/*******************************************************************************
+ *	DDR Initialize entry
+ ******************************************************************************/
+int32_t rcar_dram_init(void)
+{
+	uint32_t ch, cs;
+	uint32_t dataL;
+	uint32_t bus_mbps, bus_mbpsdiv;
+	uint32_t tmp_tccd;
+	uint32_t failcount;
+
+	/***********************************************************************
+	Thermal sensor setting
+	***********************************************************************/
+	dataL = *((volatile uint32_t *)CPG_MSTPSR5);
+	if (dataL & BIT22) {	/*  case THS/TSC Standby */
+		dataL &= ~(BIT22);
+		*((volatile uint32_t *)CPG_CPGWPR) = ~dataL;
+		*((volatile uint32_t *)CPG_SMSTPCR5) = dataL;
+		while ((BIT22) & *((volatile uint32_t *)CPG_MSTPSR5)) ;	/*  wait bit=0 */
+	}
+
+	/* THCTR Bit6: PONM=0 , Bit0: THSST=0   */
+	dataL = (*((volatile uint32_t *)THS1_THCTR)) & 0xFFFFFFBE;
+	*((volatile uint32_t *)THS1_THCTR) = dataL;
+
+	/***********************************************************************
+	Judge product and cut
+	***********************************************************************/
+#ifdef RCAR_DDR_FIXED_LSI_TYPE
+#if(RCAR_LSI==RCAR_AUTO)
+	Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+	Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#else /* RCAR_LSI */
+#ifndef RCAR_LSI_CUT
+	Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_LSI */
+#else /* RCAR_DDR_FIXED_LSI_TYPE */
+	Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+	Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#endif /* RCAR_DDR_FIXED_LSI_TYPE */
+
+	if (Prr_Product == PRR_PRODUCT_H3) {
+		if (Prr_Cut <= PRR_PRODUCT_11) {
+			pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[0][0];
+		} else {
+			pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[2][0];
+		}
+	} else if (Prr_Product == PRR_PRODUCT_M3) {
+		pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[1][0];
+	} else if ((Prr_Product == PRR_PRODUCT_M3N)
+		   || (Prr_Product == PRR_PRODUCT_V3H)) {
+		pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[3][0];
+	} else {
+		FATAL_MSG("DDR:Unknown Product");
+		return 0xff;
+	}
+
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+		/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
+	} else {
+		mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+	}
+
+	/***********************************************************************
+	Judge board type
+	***********************************************************************/
+	_cnf_BOARDTYPE = boardcnf_get_brd_type();
+	if (_cnf_BOARDTYPE >= BOARDNUM) {
+		FATAL_MSG("DDR:Unknown Board");
+		return 0xff;
+	}
+	Boardcnf = (struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
+
+/* RCAR_DRAM_SPLIT_2CH           (2U) */
+#if RCAR_DRAM_SPLIT == 2
+	/***********************************************************************
+	H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split
+	***********************************************************************/
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) {
+		mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006);
+		ddr_phyvalid = 0x03;
+	} else {
+		ddr_phyvalid = Boardcnf->phyvalid;
+	}
+#else /* RCAR_DRAM_SPLIT_2CH */
+	ddr_phyvalid = Boardcnf->phyvalid;
+#endif /* RCAR_DRAM_SPLIT_2CH */
+
+	max_density = 0;
+
+	for (cs = 0; cs < CS_CNT; cs++) {
+		ch_have_this_cs[cs] = 0;
+	}
+
+	foreach_ech(ch)
+	    for (cs = 0; cs < CS_CNT; cs++)
+		ddr_density[ch][cs] = 0xff;
+
+	foreach_vch(ch) {
+		for (cs = 0; cs < CS_CNT; cs++) {
+			dataL = Boardcnf->ch[ch].ddr_density[cs];
+			ddr_density[ch][cs] = dataL;
+
+			if (dataL == 0xff)
+				continue;
+			if (dataL > max_density)
+				max_density = dataL;
+			if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3)
+			    && (Prr_Cut <= PRR_PRODUCT_11))
+				continue;
+			ch_have_this_cs[cs] |= (1U << ch);
+		}
+	}
+
+	/***********************************************************************
+	Judge board clock frequency (in MHz)
+	***********************************************************************/
+	boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv);
+	if ((brd_clk / brd_clkdiv) > 25) {
+		brd_clkdiva = 1;
+	} else {
+		brd_clkdiva = 0;
+	}
+
+	/***********************************************************************
+	Judge ddr operating frequency clock(in Mbps)
+	***********************************************************************/
+	boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv);
+
+	ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
+
+	ddr_mul =
+	    CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
+		    brd_clkdiv * (brd_clkdiva + 1));
+
+	/***********************************************************************
+	Adjust tccd
+	***********************************************************************/
+	dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
+	switch (dataL) {
+	case 0:
+		bus_mbps = brd_clk * 0x60 * 2;
+		bus_mbpsdiv = brd_clkdiv * 1;
+		break;
+	case 1:
+		bus_mbps = brd_clk * 0x50 * 2;
+		bus_mbpsdiv = brd_clkdiv * 1;
+		break;
+	case 2:
+		bus_mbps = brd_clk * 0x40 * 2;
+		bus_mbpsdiv = brd_clkdiv * 1;
+		break;
+	case 3:
+		bus_mbps = brd_clk * 0x60 * 2;
+		bus_mbpsdiv = brd_clkdiv * 2;
+		break;
+	default:
+		bus_mbps = brd_clk * 0x60 * 2;
+		bus_mbpsdiv = brd_clkdiv * 2;
+		break;
+	}
+	tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv);
+	if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv)
+		tmp_tccd = tmp_tccd + 1;
+
+	if (tmp_tccd < 8)
+		ddr_tccd = 8;
+	else
+		ddr_tccd = tmp_tccd;
+
+	NOTICE("BL2: DDR%d(%s)", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
+
+	MSG_LF("Start\n");
+
+	/***********************************************************************
+	PLL Setting
+	***********************************************************************/
+	pll3_control(1);
+
+	/***********************************************************************
+	initialize DDR
+	***********************************************************************/
+	dataL = init_ddr();
+	if (dataL == ddr_phyvalid) {
+		failcount = 0;
+	} else {
+		failcount = 1;
+	}
+
+	NOTICE("..%d\n", failcount);
+
+	foreach_vch(ch)
+	    mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
+	if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
+	    || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+		/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
+	} else {
+		mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+	}
+
+	if (failcount == 0) {
+		return INITDRAM_OK;
+	} else {
+		return INITDRAM_NG;
+	}
+}
+
+void pvtcode_update(void)
+{
+	uint32_t ch;
+	uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
+	int32_t pvtp_tmp, pvtn_tmp;
+
+	foreach_vch(ch) {
+		pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6;
+		pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0;
+
+		if (8912 * pvtp_init > 44230) {
+			pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000;
+		} else {
+			pvtp_tmp =
+			    -((-(5000 + 8912 * pvtp_init - 44230)) / 10000);
+		}
+		pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000;
+
+		pvtn[ch] = pvtn_tmp + pvtn_init;
+		pvtp[ch] = pvtp_tmp + pvtp_init;
+
+		if (pvtn[ch] > 63) {
+			pvtn[ch] = 63;
+			pvtp[ch] =
+			    (pvtp_tmp) * (63 - 6 * pvtn_tmp -
+					  pvtn_init) / (pvtn_tmp) +
+			    6 * pvtp_tmp + pvtp_init;
+		}
+		if ((Prr_Product == PRR_PRODUCT_H3)
+		    && (Prr_Cut <= PRR_PRODUCT_11)) {
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
+								       tcomp_cal
+								       [ch] &
+								       0xfffff000));
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
+								       tcomp_cal
+								       [ch] &
+								       0xfffff000));
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
+								       tcomp_cal
+								       [ch] &
+								       0xfffff000));
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
+								       tcomp_cal
+								       [ch] &
+								       0xfffff000));
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) | (tcal.
+								       tcomp_cal
+								       [ch] &
+								       0xfffff000));
+		} else {
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) |
+					 0x00035000);
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) |
+					 0x00015000);
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) |
+					 0x00015000);
+
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) |
+					 0x00015000);
+			reg_ddrphy_write(ch,
+					 ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+					 pvtp[ch] | (pvtn[ch] << 6) |
+					 0x00015000);
+		}
+	}
+}
+
+void pvtcode_update2(void)
+{
+	uint32_t ch;
+	foreach_vch(ch) {
+		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+				 tcal.init_cal[ch] | 0x00020000);
+		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+				 tcal.init_cal[ch]);
+		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+				 tcal.init_cal[ch]);
+		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+				 tcal.init_cal[ch]);
+		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+				 tcal.init_cal[ch]);
+	}
+}
+
+void ddr_padcal_tcompensate_getinit(uint32_t override)
+{
+	uint32_t ch;
+	uint32_t dataL;
+	uint32_t pvtp, pvtn;
+
+	tcal.init_temp = 0;
+	for (ch = 0; ch < 4; ch++) {
+		tcal.init_cal[ch] = 0;
+		tcal.tcomp_cal[ch] = 0;
+	}
+
+	foreach_vch(ch) {
+		tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
+		tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
+	}
+
+	if (!override) {
+		dataL = *((volatile uint32_t *)THS1_TEMP);
+		if (dataL < 2800) {
+			tcal.init_temp =
+			    (143 * (int32_t) dataL - 359000) / 1000;
+		} else {
+			tcal.init_temp =
+			    (121 * (int32_t) dataL - 296300) / 1000;
+		}
+
+		foreach_vch(ch) {
+			pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
+			pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
+			if ((int32_t) pvtp >
+			    ((tcal.init_temp * 29 - 3625) / 1000))
+				pvtp =
+				    (int32_t) pvtp +
+				    ((3625 - tcal.init_temp * 29) / 1000);
+			else
+				pvtp = 0;
+
+			if ((int32_t) pvtn >
+			    ((tcal.init_temp * 54 - 6750) / 1000))
+				pvtn =
+				    (int32_t) pvtn +
+				    ((6750 - tcal.init_temp * 54) / 1000);
+			else
+				pvtn = 0;
+
+			if ((Prr_Product == PRR_PRODUCT_H3)
+			    && (Prr_Cut <= PRR_PRODUCT_11)) {
+				tcal.init_cal[ch] =
+				    (tcal.
+				     init_cal[ch] & 0xfffff000) | (pvtn << 6) |
+				    (pvtp);
+			} else {
+				tcal.init_cal[ch] =
+				    0x00015000 | (pvtn << 6) | (pvtp);
+			}
+		}
+		tcal.init_temp = 125;
+	}
+}
+
+#ifndef ddr_qos_init_setting
+/*  for QoS init */
+uint8_t get_boardcnf_phyvalid(void)
+{
+/*       return Boardcnf->phyvalid; */
+	return ddr_phyvalid;
+}
+#endif /* ddr_qos_init_setting */
+
+/*******************************************************************************
+ *	END
+ ******************************************************************************/
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
new file mode 100644
index 0000000..3d94da5
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -0,0 +1,1478 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define BOARDNUM 16
+#define BOARD_JUDGE_AUTO
+
+static uint32_t _board_judge(void);
+
+static uint32_t boardcnf_get_brd_type(void)
+{
+	return _board_judge();
+}
+
+struct _boardcnf_ch {
+	uint8_t ddr_density[CS_CNT];
+	uint32_t ca_swap;
+	uint16_t dqs_swap;
+	uint32_t dq_swap[SLICE_CNT];
+	uint8_t dm_swap[SLICE_CNT];
+	uint16_t wdqlvl_patt[16];
+	int8_t cacs_adj[10];
+	int8_t dm_adj_w[SLICE_CNT];
+	int8_t dq_adj_w[SLICE_CNT * 8];
+	int8_t dm_adj_r[SLICE_CNT];
+	int8_t dq_adj_r[SLICE_CNT * 8];
+};
+
+struct _boardcnf {
+	uint8_t phyvalid;
+	uint8_t dbi_en;
+	uint16_t cacs_dly;
+	int16_t cacs_dly_adj;
+	uint16_t dqdm_dly_w;
+	uint16_t dqdm_dly_r;
+	struct _boardcnf_ch ch[DRAM_CH_CNT];
+};
+
+#define WDQLVL_PAT {\
+	0x00AA,\
+	0x0055,\
+	0x00AA,\
+	0x0155,\
+	0x01CC,\
+	0x0133,\
+	0x00CC,\
+	0x0033,\
+	0x00F0,\
+	0x010F,\
+	0x01F0,\
+	0x010F,\
+	0x00F0,\
+	0x00F0,\
+	0x000F,\
+	0x010F}
+
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+	{
+/* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */
+	 .phyvalid = 0x03,
+	 .dbi_en = 0x01,
+	 .cacs_dly = 0x02c0,
+	 .cacs_dly_adj = 0,
+	 .dqdm_dly_w = 0x0300,
+	 .dqdm_dly_r = 0x00a0,
+	 .ch = {
+		{
+		 {0x02, 0x02},
+		 0x00543210U,
+		 0x3201U,
+		 {0x70612543, 0x43251670, 0x45326170, 0x10672534},
+		 {0x08, 0x08, 0x08, 0x08},
+		 WDQLVL_PAT,
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0}
+		 },
+
+		{
+		 {0x02, 0x02},
+		 0x00543210,
+		 0x2310,
+		 {0x01327654, 0x34526107, 0x35421670, 0x70615324},
+		 {0x08, 0x08, 0x08, 0x08},
+		 WDQLVL_PAT,
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0}
+		 }
+		}
+	 },
+/* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */
+	{
+	 0x03,
+	 0x01,
+	 0x2c0,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00345201,
+	   0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00302154,
+	   0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */
+	{
+	 0x0f,
+	 0x00,
+	 0x300,
+	 -320,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x3210,
+	   {0x20741365, 0x34256107, 0x57460321, 0x70614532},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x3102,
+	   {0x23547610, 0x34526107, 0x67452310, 0x32106754},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x0213,
+	   {0x30216754, 0x67453210, 0x70165243, 0x07162345},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x0213,
+	   {0x01327654, 0x70615432, 0x54760123, 0x07162345},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	 {
+	  {
+	   {0x02, 0xFF},
+	   0x00543210U,
+	   0x3201,
+	   {0x70612543, 0x43251670, 0x45326170, 0x10672534},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xFF},
+	   0x00543210,
+	   0x2310,
+	   {0x01327654, 0x34526107, 0x35421670, 0x70615324},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */
+	{
+	 0x0f,
+	 0x00,
+	 0x2c0,
+	 -320,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0xff},
+	   0x00315024,
+	   0x3120,
+	   {0x30671254, 0x26541037, 0x17054623, 0x12307645},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00025143,
+	   0x3210,
+	   {0x70613542, 0x16245307, 0x30712645, 0x21706354},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00523104,
+	   0x2301,
+	   {0x70613542, 0x16245307, 0x30712645, 0x21706354},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00153402,
+	   0x2031,
+	   {0x30671254, 0x26541037, 0x17054623, 0x12307645},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */
+	{
+	 0x03,
+	 0x01,
+	 0x2c0,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0xff},
+	   0x00345201,
+	   0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00302154,
+	   0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */
+	{
+	 0x0f,
+	 0x00,
+	 0x300,
+	 -320,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x3210,
+	   {0x20741365, 0x34256107, 0x57460321, 0x70614532},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x3102,
+	   {0x23547610, 0x34526107, 0x67452310, 0x32106754},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x0213,
+	   {0x30216754, 0x67453210, 0x70165243, 0x07162345},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x0213,
+	   {0x01327654, 0x70615432, 0x54760123, 0x07162345},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */
+	{
+	 0x0f,
+	 0x01,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x2310,
+	   {0x70631425, 0x34527016, 0x43527610, 0x32104567},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00105432,
+	   0x3210,
+	   {0x43256107, 0x07162354, 0x10234567, 0x01235467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x2301,
+	   {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x2301,
+	   {0x12034765, 0x23105467, 0x23017645, 0x32106745},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */
+	{
+#if RCAR_DRAM_CHANNEL == 5
+	 0x05,
+#else
+	 0x0f,
+#endif
+	 0x01,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x2310,
+	   {0x70631425, 0x34527016, 0x43527610, 0x32104567},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x2301,
+	   {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+#else
+	  {
+	   {0x02, 0x02},
+	   0x00105432,
+	   0x3210,
+	   {0x43256107, 0x07162354, 0x10234567, 0x01235467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+#endif
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x2301,
+	   {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00543210,
+	   0x2301,
+	   {0x12034765, 0x23105467, 0x23017645, 0x32106745},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */
+	{
+	 0x0f,
+	 0x01,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x3210,
+	   {0x27645310, 0x75346210, 0x53467210, 0x23674510},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00543210,
+	   0x2301,
+	   {0x23764510, 0x43257610, 0x43752610, 0x37652401},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {-128, -128, -128, -128, -128, -128, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00452103,
+	   0x3210,
+	   {0x32764510, 0x43257610, 0x43752610, 0x26573401},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0xff},
+	   0x00520413,
+	   0x2301,
+	   {0x47652301, 0x75346210, 0x53467210, 0x32674501},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {30, 30, 30, 30, 30, 30, 30, 30,
+	    30, 30},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */
+	{
+	 0x01,
+	 0x01,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00345201,
+	   0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */
+	{
+	 0x01,
+	 0x01,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00342501,
+	   0x3201,
+	   {0x10672534, 0x43257106, 0x34527601, 0x71605243},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[12] RENESAS CONDOR board with V3H/SoC */
+	{
+	 0x01,
+	 0x1,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00501342,
+	   0x3201,
+	   {0x70562134, 0x34526071, 0x23147506, 0x12430567},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[13] RENESAS KRIEK board with PM3/SoC */
+	{
+	 0x05,
+	 0x00,
+	 0x2c0,
+	 -320,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00345201,
+	   0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00302154,
+	   0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00302154,
+	   0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0xff, 0xff},
+	   0,
+	   0,
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */
+	{
+#if RCAR_DRAM_CHANNEL == 5
+	 0x05,
+#else
+	 0x0f,
+#endif
+	 0x01,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x04, 0xff},
+	   0x00543210,
+	   0x2310,
+	   {0x70631425, 0x34527016, 0x43527610, 0x32104567},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
+	  {
+	   {0x04, 0xff},
+	   0x00543210,
+	   0x2301,
+	   {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+#else
+	  {
+	   {0x04, 0xff},
+	   0x00105432,
+	   0x3210,
+	   {0x43256107, 0x07162354, 0x10234567, 0x01235467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+#endif
+	  {
+	   {0x04, 0xff},
+	   0x00543210,
+	   0x2301,
+	   {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x04, 0xff},
+	   0x00543210,
+	   0x2301,
+	   {0x12034765, 0x23105467, 0x23017645, 0x32106745},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 },
+/* boardcnf[15] RENESAS KRIEK board with H3N */
+	{
+	 0x05,
+	 0x01,
+	 0x300,
+	 0,
+	 0x300,
+	 0x0a0,
+	 {
+	  {
+	   {0x02, 0x02},
+	   0x00345201,
+	   0x3201,
+	   {0x01672543, 0x45367012, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00302154,
+	   0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0x02, 0x02},
+	   0x00302154,
+	   0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	  {
+	   {0xff, 0xff},
+	   0,
+	   0,
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   }
+	  }
+	 }
+};
+
+void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
+{
+	uint32_t md;
+
+	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_10)) {
+		*clk = 50;
+		*div = 3;
+	} else {
+		md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3;
+		switch (md) {
+		case 0x0:
+			*clk = 50;
+			*div = 3;
+			break;
+		case 0x1:
+			*clk = 60;
+			*div = 3;
+			break;
+		case 0x2:
+			*clk = 75;
+			*div = 3;
+			break;
+		case 0x3:
+			*clk = 100;
+			*div = 3;
+			break;
+		}
+	}
+}
+
+void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
+{
+	uint32_t md;
+
+	md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
+	md = (md | (md >> 1)) & 0x3;
+	switch (md) {
+	case 0x0:
+		*mbps = 3200;
+		*div = 1;
+		break;
+	case 0x1:
+		*mbps = 2800;
+		*div = 1;
+		break;
+	case 0x2:
+		*mbps = 2400;
+		*div = 1;
+		break;
+	case 0x3:
+		*mbps = 1600;
+		*div = 1;
+		break;
+	}
+}
+
+#define _def_REFPERIOD  1890
+
+#define M3_SAMPLE_TT_A84        0xB866CC10, 0x3B250421
+#define M3_SAMPLE_TT_A85        0xB866CC10, 0x3AA50421
+#define M3_SAMPLE_TT_A86        0xB866CC10, 0x3AA48421
+#define M3_SAMPLE_FF_B45        0xB866CC10, 0x3AB00C21
+#define M3_SAMPLE_FF_B49        0xB866CC10, 0x39B10C21
+#define M3_SAMPLE_FF_B56        0xB866CC10, 0x3AAF8C21
+#define M3_SAMPLE_SS_E24        0xB866CC10, 0x3BA39421
+#define M3_SAMPLE_SS_E28        0xB866CC10, 0x3C231421
+#define M3_SAMPLE_SS_E32        0xB866CC10, 0x3C241421
+
+static const uint32_t TermcodeBySample[20][3] = {
+	{M3_SAMPLE_TT_A84, 0x000158D5},
+	{M3_SAMPLE_TT_A85, 0x00015955},
+	{M3_SAMPLE_TT_A86, 0x00015955},
+	{M3_SAMPLE_FF_B45, 0x00015690},
+	{M3_SAMPLE_FF_B49, 0x00015753},
+	{M3_SAMPLE_FF_B56, 0x00015793},
+	{M3_SAMPLE_SS_E24, 0x00015996},
+	{M3_SAMPLE_SS_E28, 0x000159D7},
+	{M3_SAMPLE_SS_E32, 0x00015997},
+	{0xFFFFFFFF, 0xFFFFFFFF, 0x0001554F}
+};
+
+#ifdef BOARD_JUDGE_AUTO
+/*
+ * SAMPLE board detect function
+ */
+#define PFC_PMMR   	0xE6060000U
+#define PFC_PUEN5	0xE6060414U
+#define PFC_PUEN6	0xE6060418U
+#define PFC_PUD5	0xE6060454U
+#define PFC_PUD6	0xE6060458U
+#define GPIO_INDT5	0xE605500CU
+#define GPIO_INDT6	0xE605540CU
+
+#define BIT25 		(1<<25)
+#define BIT22 		(1<<22)
+#define BIT15 		(1<<15)
+#define BIT0  		(1)
+#define GPIO_GPSR6 	(0xE6060118U)
+
+#if (RCAR_GEN3_ULCB == 0)
+static void pfc_write_and_poll(uint32_t a, uint32_t v)
+{
+	mmio_write_32(PFC_PMMR, ~v);
+	v = ~mmio_read_32(PFC_PMMR);
+	mmio_write_32(a, v);
+	while (v != mmio_read_32(a)) ;
+	dsb_sev();
+}
+#endif
+
+#ifndef RCAR_GEN3_ULCB
+#define RCAR_GEN3_ULCB		0
+#endif
+
+#if (RCAR_GEN3_ULCB == 0)	/* non Starter Kit */
+
+static uint32_t opencheck_SSI_WS6(void)
+{
+	uint32_t dataL, down, up;
+	uint32_t gpsr6_bak;
+	uint32_t puen5_bak;
+	uint32_t pud5_bak;
+
+	gpsr6_bak = mmio_read_32(GPIO_GPSR6);
+	puen5_bak = mmio_read_32(PFC_PUEN5);
+	pud5_bak = mmio_read_32(PFC_PUD5);
+	dsb_sev();
+
+	dataL = (gpsr6_bak & ~BIT15);
+	pfc_write_and_poll(GPIO_GPSR6, dataL);
+
+	/* Pull-Up/Down Enable (PUEN5[22]=1) */
+	dataL = puen5_bak;
+	dataL |= (BIT22);
+	pfc_write_and_poll(PFC_PUEN5, dataL);
+
+	/* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */
+	dataL = pud5_bak;
+	dataL &= ~(BIT22);
+	pfc_write_and_poll(PFC_PUD5, dataL);
+	/* GPSR6[15]=SSI_WS6 */
+	rcar_micro_delay(10);
+	down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1;
+	dsb_sev();
+
+	/* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */
+	dataL = pud5_bak;
+	dataL |= (BIT22);
+	pfc_write_and_poll(PFC_PUD5, dataL);
+
+	/* GPSR6[15]=SSI_WS6 */
+	rcar_micro_delay(10);
+	up = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1;
+
+	dsb_sev();
+
+	pfc_write_and_poll(GPIO_GPSR6, gpsr6_bak);
+	pfc_write_and_poll(PFC_PUEN5, puen5_bak);
+	pfc_write_and_poll(PFC_PUD5, pud5_bak);
+
+	if (down == up) {
+		/* Same = Connect */
+		return 0;
+	}
+
+	/* Diff = Open */
+	return 1;
+}
+
+#endif
+
+static uint32_t _board_judge(void)
+{
+	uint32_t brd;
+#if (RCAR_GEN3_ULCB==1)
+	/* Starter Kit */
+	if (Prr_Product == PRR_PRODUCT_H3) {
+		if (Prr_Cut <= PRR_PRODUCT_11) {
+			/* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */
+			brd = 2;
+		} else {
+			/* RENESAS Starter Kit(H3 Ver.2.0 or later/SIP) board */
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+			brd = 7;
+#else
+			brd = 8;
+#endif
+		}
+	} else if (Prr_Product == PRR_PRODUCT_M3) {
+		/* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
+		brd = 3;
+	} else {
+		/* RENESAS Starter Kit(M3-N/SIP) board */
+		brd = 11;
+	}
+#else
+	uint32_t usb2_ovc_open;
+
+	usb2_ovc_open = opencheck_SSI_WS6();
+
+	/* RENESAS Eva-borad */
+	if (Prr_Product == PRR_PRODUCT_V3H) {
+		/* RENESAS Condor board */
+		brd = 12;
+	} else if (usb2_ovc_open) {
+		if (Prr_Product == PRR_PRODUCT_M3N) {
+			/* RENESAS Kriek board with M3-N */
+			brd = 10;
+		} else if (Prr_Product == PRR_PRODUCT_M3) {
+			/* RENESAS Kriek board with M3-W */
+			brd = 1;
+		} else if (Prr_Cut <= PRR_PRODUCT_11) {
+			/* RENESAS Kriek board with PM3 */
+			brd = 13;
+		} else {
+			/* RENESAS Kriek board with H3N */
+			brd = 15;
+		}
+	} else {
+		if (Prr_Product == PRR_PRODUCT_H3) {
+			if (Prr_Cut <= PRR_PRODUCT_11) {
+				/* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */
+				brd = 2;
+			} else if (Prr_Cut < PRR_PRODUCT_30) {
+				/* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */
+				brd = 7;	//  8Gbit/1rank
+			} else {
+				/* RENESAS SALVATOR-X (H3 Ver.3.0/SIP) */
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+				brd = 7;
+#else
+				brd = 8;
+#endif
+			}
+		} else if (Prr_Product == PRR_PRODUCT_M3N) {
+			/* RENESAS SALVATOR-X (M3-N/SIP) */
+			brd = 11;
+		} else {
+			/* RENESAS SALVATOR-X (M3-W/SIP) */
+			brd = 0;
+		}
+	}
+#endif
+	return brd;
+}
+#endif
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
new file mode 100644
index 0000000..91562b0
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define RCAR_DDR_VERSION        "rev.0.33"
+#define DRAM_CH_CNT		(0x04)
+#define SLICE_CNT		(0x04)
+#define CS_CNT			(0x02)
+
+/* order : CS0A, CS0B, CS1A, CS1B */
+#define CSAB_CNT		(CS_CNT * 2)
+
+/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
+#define CHAB_CNT		(DRAM_CH_CNT * 2)
+
+/* pll setting */
+#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) /((b) * (diva)))
+#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
+
+/* for ddr deisity setting */
+#define DBMEMCONF_REG(d3, row, bank, col, dw) 	\
+	((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
+
+#define DBMEMCONF_REGD(density) 		\
+(DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29-3-10-2), 3, 10, 2))
+
+#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
+
+/* refresh mode */
+#define DBSC_REFINTS		(0x0)
+
+/* system registers */
+#define CPG_BASE		(0xE6150000U)
+#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
+
+#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
+#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
+#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
+#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
+
+#define CPG_FRQCRB_KICK_BIT	(1U<<31)
+#define CPG_PLLECR_PLL3E_BIT	(1U<<3)
+#define CPG_PLLECR_PLL3ST_BIT	(1U<<11)
+#define CPG_ZB3CKCR_ZB3ST_BIT	(1U<<11)
+
+#define RST_BASE		(0xE6160000U)
+#define RST_MODEMR		(RST_BASE + 0x0060U)
+
+#define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
+
+/* Product Register */
+#define PRR			(0xFFF00044U)
+#define PRR_PRODUCT_MASK	(0x00007F00U)
+#define PRR_CUT_MASK		(0x000000FFU)
+#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3   */
+#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3-W */
+#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3-N */
+#define PRR_PRODUCT_V3H		(0x00005600U)	/* R-Car V3H  */
+#define PRR_PRODUCT_10		(0x00U)	/*   Ver.1.0  */
+#define PRR_PRODUCT_11		(0x01U)	/*   Ver.1.1  */
+#define PRR_PRODUCT_20		(0x10U)	/*   Ver.2.0  */
+#define PRR_PRODUCT_30		(0x20U)	/*   Ver.3.0  */
+
+/* DBSC registers */
+#define DBSC_DBSYSCONF1		0xE6790004U
+#define DBSC_DBPHYCONF0		0xE6790010U
+#define DBSC_DBKIND		0xE6790020U
+
+#define DBSC_DBMEMCONF(ch, cs)	(0xE6790030U + 0x10U * (ch) + 0x04U * (cs))
+#define DBSC_DBMEMCONF_0_0	0xE6790030U
+#define DBSC_DBMEMCONF_0_1	0xE6790034U
+#define DBSC_DBMEMCONF_0_2	0xE6790038U
+#define DBSC_DBMEMCONF_0_3	0xE679003CU
+#define DBSC_DBMEMCONF_1_2	0xE6790048U
+#define DBSC_DBMEMCONF_1_3	0xE679004CU
+#define DBSC_DBMEMCONF_1_0	0xE6790040U
+#define DBSC_DBMEMCONF_1_1	0xE6790044U
+#define DBSC_DBMEMCONF_2_0	0xE6790050U
+#define DBSC_DBMEMCONF_2_1	0xE6790054U
+#define DBSC_DBMEMCONF_2_2	0xE6790058U
+#define DBSC_DBMEMCONF_2_3	0xE679005CU
+#define DBSC_DBMEMCONF_3_0	0xE6790060U
+#define DBSC_DBMEMCONF_3_1	0xE6790064U
+#define DBSC_DBMEMCONF_3_2	0xE6790068U
+#define DBSC_DBMEMCONF_3_3	0xE679006CU
+
+#define DBSC_DBSYSCNT0		0xE6790100U
+
+#define DBSC_DBACEN		0xE6790200U
+#define DBSC_DBRFEN		0xE6790204U
+#define DBSC_DBCMD		0xE6790208U
+#define DBSC_DBWAIT		0xE6790210U
+#define DBSC_DBSYSCTRL0		0xE6790280U
+
+#define DBSC_DBTR(x)		(0xE6790300U + 0x04U * (x))
+#define DBSC_DBTR0		0xE6790300U
+#define DBSC_DBTR1		0xE6790304U
+#define DBSC_DBTR3		0xE679030CU
+#define DBSC_DBTR4		0xE6790310U
+#define DBSC_DBTR5		0xE6790314U
+#define DBSC_DBTR6		0xE6790318U
+#define DBSC_DBTR7		0xE679031CU
+#define DBSC_DBTR8		0xE6790320U
+#define DBSC_DBTR9		0xE6790324U
+#define DBSC_DBTR10		0xE6790328U
+#define DBSC_DBTR11		0xE679032CU
+#define DBSC_DBTR12		0xE6790330U
+#define DBSC_DBTR13		0xE6790334U
+#define DBSC_DBTR14		0xE6790338U
+#define DBSC_DBTR15		0xE679033CU
+#define DBSC_DBTR16		0xE6790340U
+#define DBSC_DBTR17		0xE6790344U
+#define DBSC_DBTR18		0xE6790348U
+#define DBSC_DBTR19		0xE679034CU
+#define DBSC_DBTR20		0xE6790350U
+#define DBSC_DBTR21		0xE6790354U
+#define DBSC_DBTR22		0xE6790358U
+#define DBSC_DBTR23		0xE679035CU
+#define DBSC_DBTR24		0xE6790360U
+#define DBSC_DBTR25		0xE6790364U
+#define DBSC_DBTR26		0xE6790368U
+
+#define DBSC_DBBL		0xE6790400U
+#define DBSC_DBRFCNF1		0xE6790414U
+#define DBSC_DBRFCNF2		0xE6790418U
+#define DBSC_DBTSPCNF		0xE6790420U
+#define DBSC_DBCALCNF		0xE6790424U
+#define DBSC_DBRNK(x)		(0xE6790430U + 0x04U * (x))
+#define DBSC_DBRNK2		0xE6790438U
+#define DBSC_DBRNK3		0xE679043CU
+#define DBSC_DBRNK4		0xE6790440U
+#define DBSC_DBRNK5		0xE6790444U
+#define DBSC_DBODT(x)		(0xE6790460U + 0x04U * (x))
+
+#define DBSC_DBADJ0		0xE6790500U
+#define DBSC_DBDBICNT		0xE6790518U
+#define DBSC_DBDFIPMSTRCNF	0xE6790520U
+#define DBSC_DBDFICUPDCNF	0xE679052CU
+
+#define DBSC_INITCOMP(ch)	(0xE6790600U + 0x40U * (ch))
+#define DBSC_INITCOMP_0		0xE6790600U
+#define DBSC_INITCOMP_1		0xE6790640U
+#define DBSC_INITCOMP_2		0xE6790680U
+#define DBSC_INITCOMP_3		0xE67906C0U
+
+#define DBSC_DBDFICNT(ch)	(0xE6790604U + 0x40U * (ch))
+#define DBSC_DBDFICNT_0		0xE6790604U
+#define DBSC_DBDFICNT_1		0xE6790644U
+#define DBSC_DBDFICNT_2		0xE6790684U
+#define DBSC_DBDFICNT_3		0xE67906C4U
+
+#define DBSC_DBPDCNT0(ch)	(0xE6790610U + 0x40U * (ch))
+#define DBSC_DBPDCNT0_0		0xE6790610U
+#define DBSC_DBPDCNT0_1		0xE6790650U
+#define DBSC_DBPDCNT0_2		0xE6790690U
+#define DBSC_DBPDCNT0_3		0xE67906D0U
+
+#define DBSC_DBPDCNT1(ch)	(0xE6790614U + 0x40U * (ch))
+#define DBSC_DBPDCNT1_0		0xE6790614U
+#define DBSC_DBPDCNT1_1		0xE6790654U
+#define DBSC_DBPDCNT1_2		0xE6790694U
+#define DBSC_DBPDCNT1_3		0xE67906D4U
+
+#define DBSC_DBPDCNT2(ch)	(0xE6790618U + 0x40U * (ch))
+#define DBSC_DBPDCNT2_0		0xE6790618U
+#define DBSC_DBPDCNT2_1		0xE6790658U
+#define DBSC_DBPDCNT2_2		0xE6790698U
+#define DBSC_DBPDCNT2_3		0xE67906D8U
+
+#define DBSC_DBPDCNT3(ch)	(0xE679061CU + 0x40U * (ch))
+#define DBSC_DBPDCNT3_0		0xE679061CU
+#define DBSC_DBPDCNT3_1		0xE679065CU
+#define DBSC_DBPDCNT3_2		0xE679069CU
+#define DBSC_DBPDCNT3_3		0xE67906DCU
+
+#define DBSC_DBPDLK(ch)		(0xE6790620U + 0x40U * (ch))
+#define DBSC_DBPDLK_0		0xE6790620U
+#define DBSC_DBPDLK_1		0xE6790660U
+#define DBSC_DBPDLK_2		0xE67906a0U
+#define DBSC_DBPDLK_3		0xE67906e0U
+
+#define DBSC_DBPDRGA(ch)	(0xE6790624U + 0x40U * (ch))
+#define DBSC_DBPDRGD(ch)	(0xE6790628U + 0x40U * (ch))
+#define DBSC_DBPDRGA_0		0xE6790624U
+#define DBSC_DBPDRGD_0		0xE6790628U
+#define DBSC_DBPDRGA_1		0xE6790664U
+#define DBSC_DBPDRGD_1		0xE6790668U
+#define DBSC_DBPDRGA_2		0xE67906A4U
+#define DBSC_DBPDRGD_2		0xE67906A8U
+#define DBSC_DBPDRGA_3		0xE67906E4U
+#define DBSC_DBPDRGD_3		0xE67906E8U
+
+#define DBSC_DBPDSTAT(ch)	(0xE6790630U + 0x40U * (ch))
+#define DBSC_DBPDSTAT_0		0xE6790630U
+#define DBSC_DBPDSTAT_1		0xE6790670U
+#define DBSC_DBPDSTAT_2		0xE67906B0U
+#define DBSC_DBPDSTAT_3		0xE67906F0U
+
+#define DBSC_DBBUS0CNF0		0xE6790800U
+#define DBSC_DBBUS0CNF1		0xE6790804U
+
+#define DBSC_DBCAM0CNF1		0xE6790904U
+#define DBSC_DBCAM0CNF2		0xE6790908U
+#define DBSC_DBCAM0CNF3		0xE679090CU
+#define DBSC_DBBSWAP		0xE67909F0U
+#define DBSC_DBBCAMDIS		0xE67909FCU
+#define DBSC_DBSCHCNT0		0xE6791000U
+#define DBSC_DBSCHCNT1		0xE6791004U
+#define DBSC_DBSCHSZ0		0xE6791010U
+#define DBSC_DBSCHRW0		0xE6791020U
+#define DBSC_DBSCHRW1		0xE6791024U
+
+#define DBSC_DBSCHQOS_0(x)	(0xE6791030U +0x10U * (x))
+#define DBSC_DBSCHQOS_1(x)	(0xE6791034U +0x10U * (x))
+#define DBSC_DBSCHQOS_2(x)	(0xE6791038U +0x10U * (x))
+#define DBSC_DBSCHQOS_3(x)	(0xE679103CU +0x10U * (x))
+
+#define DBSC_DBSCTR0		0xE6791700U
+#define DBSC_DBSCTR1		0xE6791708U
+#define DBSC_DBSCHRW2		0xE679170CU
+
+#define DBSC_SCFCTST01(x)	(0xE6791700U + 0x08U * (x))
+#define DBSC_SCFCTST0		0xE6791700U
+#define DBSC_SCFCTST1		0xE6791708U
+#define DBSC_SCFCTST2		0xE679170CU
+
+#define DBSC_DBMRRDR(chab)	(0xE6791800U + 0x04U * (chab))
+#define DBSC_DBMRRDR_0		0xE6791800U
+#define DBSC_DBMRRDR_1		0xE6791804U
+#define DBSC_DBMRRDR_2		0xE6791808U
+#define DBSC_DBMRRDR_3		0xE679180CU
+#define DBSC_DBMRRDR_4		0xE6791810U
+#define DBSC_DBMRRDR_5		0xE6791814U
+#define DBSC_DBMRRDR_6		0xE6791818U
+#define DBSC_DBMRRDR_7		0xE679181CU
+
+#define DBSC_DBMEMSWAPCONF0	0xE6792000U
+
+#define DBSC_DBMONCONF4		0xE6793010U
+
+#define DBSC_PLL_LOCK(ch)	(0xE6794054U + 0x100U * (ch))
+#define DBSC_PLL_LOCK_0		0xE6794054U
+#define DBSC_PLL_LOCK_1		0xE6794154U
+#define DBSC_PLL_LOCK_2		0xE6794254U
+#define DBSC_PLL_LOCK_3		0xE6794354U
+
+/* STAT registers */
+#define MSTAT_SL_INIT		0xE67E8000U
+#define MSTAT_REF_ARS		0xE67E8004U
+#define MSTATQ_STATQC		0xE67E8008U
+#define MSTATQ_WTENABLE		0xE67E8030U
+#define MSTATQ_WTREFRESH	0xE67E8034U
+#define MSTATQ_WTSETTING0	0xE67E8038U
+#define MSTATQ_WTSETTING1	0xE67E803CU
+
+#define QOS_BASE1		(0xE67F0000U)
+#define QOSCTRL_RAS		(QOS_BASE1 + 0x0000U)
+#define QOSCTRL_FIXTH		(QOS_BASE1 + 0x0004U)
+#define QOSCTRL_RAEN		(QOS_BASE1 + 0x0018U)
+#define QOSCTRL_REGGD		(QOS_BASE1 + 0x0020U)
+#define QOSCTRL_DANN		(QOS_BASE1 + 0x0030U)
+#define QOSCTRL_DANT		(QOS_BASE1 + 0x0038U)
+#define QOSCTRL_EC		(QOS_BASE1 + 0x003CU)
+#define QOSCTRL_EMS		(QOS_BASE1 + 0x0040U)
+#define QOSCTRL_INSFC		(QOS_BASE1 + 0x0050U)
+#define QOSCTRL_BERR		(QOS_BASE1 + 0x0054U)
+#define QOSCTRL_RACNT0		(QOS_BASE1 + 0x0080U)
+#define QOSCTRL_STATGEN0	(QOS_BASE1 + 0x0088U)
+
+/* other module */
+#define THS1_THCTR		0xE6198020U
+#define THS1_TEMP		0xE6198028U
+
+#define	DBSC_BASE		(0xE6790000U)
+#define DBSC_DBSCHQOS00		(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS01		(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS02		(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS03		(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS40		(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS41		(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS42		(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS43		(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS90		(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS91		(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS92		(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS93		(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS120	(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS121	(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS122	(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS123	(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS130	(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS131	(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS132	(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS133	(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS140	(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS141	(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS142	(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS143	(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS150	(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS151	(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS152	(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS153	(DBSC_BASE + 0x112CU)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
new file mode 100644
index 0000000..875f953
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_b.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
new file mode 100644
index 0000000..b29c773
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
@@ -0,0 +1,5886 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define _reg_PHY_DQ_DM_SWIZZLE0                            0x00000000U
+#define _reg_PHY_DQ_DM_SWIZZLE1                            0x00000001U
+#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY                 0x00000002U
+#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY             0x00000003U
+#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE                   0x00000004U
+#define _reg_PHY_CLK_BYPASS_OVERRIDE                       0x00000005U
+#define _reg_PHY_SW_WRDQ0_SHIFT                            0x00000006U
+#define _reg_PHY_SW_WRDQ1_SHIFT                            0x00000007U
+#define _reg_PHY_SW_WRDQ2_SHIFT                            0x00000008U
+#define _reg_PHY_SW_WRDQ3_SHIFT                            0x00000009U
+#define _reg_PHY_SW_WRDQ4_SHIFT                            0x0000000aU
+#define _reg_PHY_SW_WRDQ5_SHIFT                            0x0000000bU
+#define _reg_PHY_SW_WRDQ6_SHIFT                            0x0000000cU
+#define _reg_PHY_SW_WRDQ7_SHIFT                            0x0000000dU
+#define _reg_PHY_SW_WRDM_SHIFT                             0x0000000eU
+#define _reg_PHY_SW_WRDQS_SHIFT                            0x0000000fU
+#define _reg_PHY_DQ_TSEL_ENABLE                            0x00000010U
+#define _reg_PHY_DQ_TSEL_SELECT                            0x00000011U
+#define _reg_PHY_DQS_TSEL_ENABLE                           0x00000012U
+#define _reg_PHY_DQS_TSEL_SELECT                           0x00000013U
+#define _reg_PHY_TWO_CYC_PREAMBLE                          0x00000014U
+#define _reg_PHY_DBI_MODE                                  0x00000015U
+#define _reg_PHY_PER_RANK_CS_MAP                           0x00000016U
+#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN              0x00000017U
+#define _reg_PHY_PER_CS_TRAINING_INDEX                     0x00000018U
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY                 0x00000019U
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY                    0x0000001aU
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY               0x0000001bU
+#define _reg_PHY_LP4_BOOT_RPTR_UPDATE                      0x0000001cU
+#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY           0x0000001dU
+#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST             0x0000001eU
+#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE              0x0000001fU
+#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY                 0x00000020U
+#define _reg_PHY_LPBK_CONTROL                              0x00000021U
+#define _reg_PHY_LPBK_DFX_TIMEOUT_EN                       0x00000022U
+#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL                0x00000023U
+#define _reg_PHY_AUTO_TIMING_MARGIN_OBS                    0x00000024U
+#define _reg_PHY_SLICE_PWR_RDC_DISABLE                     0x00000025U
+#define _reg_PHY_PRBS_PATTERN_START                        0x00000026U
+#define _reg_PHY_PRBS_PATTERN_MASK                         0x00000027U
+#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY               0x00000028U
+#define _reg_PHY_GATE_ERROR_DELAY_SELECT                   0x00000029U
+#define _reg_SC_PHY_SNAP_OBS_REGS                          0x0000002aU
+#define _reg_PHY_LPDDR                                     0x0000002bU
+#define _reg_PHY_LPDDR_TYPE                                0x0000002cU
+#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY                    0x0000002dU
+#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY                    0x0000002eU
+#define _reg_ON_FLY_GATE_ADJUST_EN                         0x0000002fU
+#define _reg_PHY_GATE_TRACKING_OBS                         0x00000030U
+#define _reg_PHY_DFI40_POLARITY                            0x00000031U
+#define _reg_PHY_LP4_PST_AMBLE                             0x00000032U
+#define _reg_PHY_RDLVL_PATT8                               0x00000033U
+#define _reg_PHY_RDLVL_PATT9                               0x00000034U
+#define _reg_PHY_RDLVL_PATT10                              0x00000035U
+#define _reg_PHY_RDLVL_PATT11                              0x00000036U
+#define _reg_PHY_LP4_RDLVL_PATT8                           0x00000037U
+#define _reg_PHY_LP4_RDLVL_PATT9                           0x00000038U
+#define _reg_PHY_LP4_RDLVL_PATT10                          0x00000039U
+#define _reg_PHY_LP4_RDLVL_PATT11                          0x0000003aU
+#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE                     0x0000003bU
+#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE                   0x0000003cU
+#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT                0x0000003dU
+#define _reg_PHY_RDDQ_ENC_OBS_SELECT                       0x0000003eU
+#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT                   0x0000003fU
+#define _reg_PHY_WR_ENC_OBS_SELECT                         0x00000040U
+#define _reg_PHY_WR_SHIFT_OBS_SELECT                       0x00000041U
+#define _reg_PHY_FIFO_PTR_OBS_SELECT                       0x00000042U
+#define _reg_PHY_LVL_DEBUG_MODE                            0x00000043U
+#define _reg_SC_PHY_LVL_DEBUG_CONT                         0x00000044U
+#define _reg_PHY_WRLVL_CAPTURE_CNT                         0x00000045U
+#define _reg_PHY_WRLVL_UPDT_WAIT_CNT                       0x00000046U
+#define _reg_PHY_WRLVL_DQ_MASK                             0x00000047U
+#define _reg_PHY_GTLVL_CAPTURE_CNT                         0x00000048U
+#define _reg_PHY_GTLVL_UPDT_WAIT_CNT                       0x00000049U
+#define _reg_PHY_RDLVL_CAPTURE_CNT                         0x0000004aU
+#define _reg_PHY_RDLVL_UPDT_WAIT_CNT                       0x0000004bU
+#define _reg_PHY_RDLVL_OP_MODE                             0x0000004cU
+#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT                 0x0000004dU
+#define _reg_PHY_RDLVL_DATA_MASK                           0x0000004eU
+#define _reg_PHY_RDLVL_DATA_SWIZZLE                        0x0000004fU
+#define _reg_PHY_WDQLVL_BURST_CNT                          0x00000050U
+#define _reg_PHY_WDQLVL_PATT                               0x00000051U
+#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET           0x00000052U
+#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT                      0x00000053U
+#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT                    0x00000054U
+#define _reg_PHY_WDQLVL_QTR_DLY_STEP                       0x00000055U
+#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS                0x00000056U
+#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS                   0x00000057U
+#define _reg_PHY_WDQLVL_DATADM_MASK                        0x00000058U
+#define _reg_PHY_USER_PATT0                                0x00000059U
+#define _reg_PHY_USER_PATT1                                0x0000005aU
+#define _reg_PHY_USER_PATT2                                0x0000005bU
+#define _reg_PHY_USER_PATT3                                0x0000005cU
+#define _reg_PHY_USER_PATT4                                0x0000005dU
+#define _reg_PHY_DQ_SWIZZLING                              0x0000005eU
+#define _reg_PHY_CALVL_VREF_DRIVING_SLICE                  0x0000005fU
+#define _reg_SC_PHY_MANUAL_CLEAR                           0x00000060U
+#define _reg_PHY_FIFO_PTR_OBS                              0x00000061U
+#define _reg_PHY_LPBK_RESULT_OBS                           0x00000062U
+#define _reg_PHY_LPBK_ERROR_COUNT_OBS                      0x00000063U
+#define _reg_PHY_MASTER_DLY_LOCK_OBS                       0x00000064U
+#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS                      0x00000065U
+#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS                0x00000066U
+#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS       0x00000067U
+#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS       0x00000068U
+#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS                0x00000069U
+#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS                0x0000006aU
+#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS                 0x0000006bU
+#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS                  0x0000006cU
+#define _reg_PHY_WR_SHIFT_OBS                              0x0000006dU
+#define _reg_PHY_WRLVL_HARD0_DELAY_OBS                     0x0000006eU
+#define _reg_PHY_WRLVL_HARD1_DELAY_OBS                     0x0000006fU
+#define _reg_PHY_WRLVL_STATUS_OBS                          0x00000070U
+#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS                0x00000071U
+#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS                0x00000072U
+#define _reg_PHY_WRLVL_ERROR_OBS                           0x00000073U
+#define _reg_PHY_GTLVL_HARD0_DELAY_OBS                     0x00000074U
+#define _reg_PHY_GTLVL_HARD1_DELAY_OBS                     0x00000075U
+#define _reg_PHY_GTLVL_STATUS_OBS                          0x00000076U
+#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS                 0x00000077U
+#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS                 0x00000078U
+#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS            0x00000079U
+#define _reg_PHY_RDLVL_STATUS_OBS                          0x0000007aU
+#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS                    0x0000007bU
+#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS                    0x0000007cU
+#define _reg_PHY_WDQLVL_STATUS_OBS                         0x0000007dU
+#define _reg_PHY_DDL_MODE                                  0x0000007eU
+#define _reg_PHY_DDL_TEST_OBS                              0x0000007fU
+#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS                     0x00000080U
+#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD                   0x00000081U
+#define _reg_PHY_LP4_WDQS_OE_EXTEND                        0x00000082U
+#define _reg_SC_PHY_RX_CAL_START                           0x00000083U
+#define _reg_PHY_RX_CAL_OVERRIDE                           0x00000084U
+#define _reg_PHY_RX_CAL_SAMPLE_WAIT                        0x00000085U
+#define _reg_PHY_RX_CAL_DQ0                                0x00000086U
+#define _reg_PHY_RX_CAL_DQ1                                0x00000087U
+#define _reg_PHY_RX_CAL_DQ2                                0x00000088U
+#define _reg_PHY_RX_CAL_DQ3                                0x00000089U
+#define _reg_PHY_RX_CAL_DQ4                                0x0000008aU
+#define _reg_PHY_RX_CAL_DQ5                                0x0000008bU
+#define _reg_PHY_RX_CAL_DQ6                                0x0000008cU
+#define _reg_PHY_RX_CAL_DQ7                                0x0000008dU
+#define _reg_PHY_RX_CAL_DM                                 0x0000008eU
+#define _reg_PHY_RX_CAL_DQS                                0x0000008fU
+#define _reg_PHY_RX_CAL_FDBK                               0x00000090U
+#define _reg_PHY_RX_CAL_OBS                                0x00000091U
+#define _reg_PHY_RX_CAL_LOCK_OBS                           0x00000092U
+#define _reg_PHY_RX_CAL_DISABLE                            0x00000093U
+#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY                     0x00000094U
+#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY                     0x00000095U
+#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY                     0x00000096U
+#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY                     0x00000097U
+#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY                     0x00000098U
+#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY                     0x00000099U
+#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY                     0x0000009aU
+#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY                     0x0000009bU
+#define _reg_PHY_CLK_WRDM_SLAVE_DELAY                      0x0000009cU
+#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY                     0x0000009dU
+#define _reg_PHY_WRLVL_THRESHOLD_ADJUST                    0x0000009eU
+#define _reg_PHY_RDDQ0_SLAVE_DELAY                         0x0000009fU
+#define _reg_PHY_RDDQ1_SLAVE_DELAY                         0x000000a0U
+#define _reg_PHY_RDDQ2_SLAVE_DELAY                         0x000000a1U
+#define _reg_PHY_RDDQ3_SLAVE_DELAY                         0x000000a2U
+#define _reg_PHY_RDDQ4_SLAVE_DELAY                         0x000000a3U
+#define _reg_PHY_RDDQ5_SLAVE_DELAY                         0x000000a4U
+#define _reg_PHY_RDDQ6_SLAVE_DELAY                         0x000000a5U
+#define _reg_PHY_RDDQ7_SLAVE_DELAY                         0x000000a6U
+#define _reg_PHY_RDDM_SLAVE_DELAY                          0x000000a7U
+#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY                0x000000a8U
+#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY                0x000000a9U
+#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY                0x000000aaU
+#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY                0x000000abU
+#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY                0x000000acU
+#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY                0x000000adU
+#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY                0x000000aeU
+#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY                0x000000afU
+#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY                0x000000b0U
+#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY                0x000000b1U
+#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY                0x000000b2U
+#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY                0x000000b3U
+#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY                0x000000b4U
+#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY                0x000000b5U
+#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY                0x000000b6U
+#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY                0x000000b7U
+#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY                 0x000000b8U
+#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY                 0x000000b9U
+#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY                    0x000000baU
+#define _reg_PHY_RDDQS_LATENCY_ADJUST                      0x000000bbU
+#define _reg_PHY_WRITE_PATH_LAT_ADD                        0x000000bcU
+#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD               0x000000bdU
+#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD              0x000000beU
+#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO                    0x000000bfU
+#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START                 0x000000c0U
+#define _reg_PHY_GTLVL_LAT_ADJ_START                       0x000000c1U
+#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START                 0x000000c2U
+#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START              0x000000c3U
+#define _reg_PHY_FDBK_PWR_CTRL                             0x000000c4U
+#define _reg_PHY_DQ_OE_TIMING                              0x000000c5U
+#define _reg_PHY_DQ_TSEL_RD_TIMING                         0x000000c6U
+#define _reg_PHY_DQ_TSEL_WR_TIMING                         0x000000c7U
+#define _reg_PHY_DQS_OE_TIMING                             0x000000c8U
+#define _reg_PHY_DQS_TSEL_RD_TIMING                        0x000000c9U
+#define _reg_PHY_DQS_OE_RD_TIMING                          0x000000caU
+#define _reg_PHY_DQS_TSEL_WR_TIMING                        0x000000cbU
+#define _reg_PHY_PER_CS_TRAINING_EN                        0x000000ccU
+#define _reg_PHY_DQ_IE_TIMING                              0x000000cdU
+#define _reg_PHY_DQS_IE_TIMING                             0x000000ceU
+#define _reg_PHY_RDDATA_EN_IE_DLY                          0x000000cfU
+#define _reg_PHY_IE_MODE                                   0x000000d0U
+#define _reg_PHY_RDDATA_EN_DLY                             0x000000d1U
+#define _reg_PHY_RDDATA_EN_TSEL_DLY                        0x000000d2U
+#define _reg_PHY_RDDATA_EN_OE_DLY                          0x000000d3U
+#define _reg_PHY_SW_MASTER_MODE                            0x000000d4U
+#define _reg_PHY_MASTER_DELAY_START                        0x000000d5U
+#define _reg_PHY_MASTER_DELAY_STEP                         0x000000d6U
+#define _reg_PHY_MASTER_DELAY_WAIT                         0x000000d7U
+#define _reg_PHY_MASTER_DELAY_HALF_MEASURE                 0x000000d8U
+#define _reg_PHY_RPTR_UPDATE                               0x000000d9U
+#define _reg_PHY_WRLVL_DLY_STEP                            0x000000daU
+#define _reg_PHY_WRLVL_RESP_WAIT_CNT                       0x000000dbU
+#define _reg_PHY_GTLVL_DLY_STEP                            0x000000dcU
+#define _reg_PHY_GTLVL_RESP_WAIT_CNT                       0x000000ddU
+#define _reg_PHY_GTLVL_BACK_STEP                           0x000000deU
+#define _reg_PHY_GTLVL_FINAL_STEP                          0x000000dfU
+#define _reg_PHY_WDQLVL_DLY_STEP                           0x000000e0U
+#define _reg_PHY_TOGGLE_PRE_SUPPORT                        0x000000e1U
+#define _reg_PHY_RDLVL_DLY_STEP                            0x000000e2U
+#define _reg_PHY_WRPATH_GATE_DISABLE                       0x000000e3U
+#define _reg_PHY_WRPATH_GATE_TIMING                        0x000000e4U
+#define _reg_PHY_ADR0_SW_WRADDR_SHIFT                      0x000000e5U
+#define _reg_PHY_ADR1_SW_WRADDR_SHIFT                      0x000000e6U
+#define _reg_PHY_ADR2_SW_WRADDR_SHIFT                      0x000000e7U
+#define _reg_PHY_ADR3_SW_WRADDR_SHIFT                      0x000000e8U
+#define _reg_PHY_ADR4_SW_WRADDR_SHIFT                      0x000000e9U
+#define _reg_PHY_ADR5_SW_WRADDR_SHIFT                      0x000000eaU
+#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY             0x000000ebU
+#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE                   0x000000ecU
+#define _reg_SC_PHY_ADR_MANUAL_CLEAR                       0x000000edU
+#define _reg_PHY_ADR_LPBK_RESULT_OBS                       0x000000eeU
+#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS                  0x000000efU
+#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT            0x000000f0U
+#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS                   0x000000f1U
+#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS                  0x000000f2U
+#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS                 0x000000f3U
+#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE                 0x000000f4U
+#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT                0x000000f5U
+#define _reg_SC_PHY_ADR_SNAP_OBS_REGS                      0x000000f6U
+#define _reg_PHY_ADR_TSEL_ENABLE                           0x000000f7U
+#define _reg_PHY_ADR_LPBK_CONTROL                          0x000000f8U
+#define _reg_PHY_ADR_PRBS_PATTERN_START                    0x000000f9U
+#define _reg_PHY_ADR_PRBS_PATTERN_MASK                     0x000000faU
+#define _reg_PHY_ADR_PWR_RDC_DISABLE                       0x000000fbU
+#define _reg_PHY_ADR_TYPE                                  0x000000fcU
+#define _reg_PHY_ADR_WRADDR_SHIFT_OBS                      0x000000fdU
+#define _reg_PHY_ADR_IE_MODE                               0x000000feU
+#define _reg_PHY_ADR_DDL_MODE                              0x000000ffU
+#define _reg_PHY_ADR_DDL_TEST_OBS                          0x00000100U
+#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS                 0x00000101U
+#define _reg_PHY_ADR_CALVL_START                           0x00000102U
+#define _reg_PHY_ADR_CALVL_COARSE_DLY                      0x00000103U
+#define _reg_PHY_ADR_CALVL_QTR                             0x00000104U
+#define _reg_PHY_ADR_CALVL_SWIZZLE0                        0x00000105U
+#define _reg_PHY_ADR_CALVL_SWIZZLE1                        0x00000106U
+#define _reg_PHY_ADR_CALVL_SWIZZLE0_0                      0x00000107U
+#define _reg_PHY_ADR_CALVL_SWIZZLE1_0                      0x00000108U
+#define _reg_PHY_ADR_CALVL_SWIZZLE0_1                      0x00000109U
+#define _reg_PHY_ADR_CALVL_SWIZZLE1_1                      0x0000010aU
+#define _reg_PHY_ADR_CALVL_DEVICE_MAP                      0x0000010bU
+#define _reg_PHY_ADR_CALVL_RANK_CTRL                       0x0000010cU
+#define _reg_PHY_ADR_CALVL_NUM_PATTERNS                    0x0000010dU
+#define _reg_PHY_ADR_CALVL_CAPTURE_CNT                     0x0000010eU
+#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT                   0x0000010fU
+#define _reg_PHY_ADR_CALVL_DEBUG_MODE                      0x00000110U
+#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT                   0x00000111U
+#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR                    0x00000112U
+#define _reg_PHY_ADR_CALVL_OBS_SELECT                      0x00000113U
+#define _reg_PHY_ADR_CALVL_OBS0                            0x00000114U
+#define _reg_PHY_ADR_CALVL_OBS1                            0x00000115U
+#define _reg_PHY_ADR_CALVL_RESULT                          0x00000116U
+#define _reg_PHY_ADR_CALVL_FG_0                            0x00000117U
+#define _reg_PHY_ADR_CALVL_BG_0                            0x00000118U
+#define _reg_PHY_ADR_CALVL_FG_1                            0x00000119U
+#define _reg_PHY_ADR_CALVL_BG_1                            0x0000011aU
+#define _reg_PHY_ADR_CALVL_FG_2                            0x0000011bU
+#define _reg_PHY_ADR_CALVL_BG_2                            0x0000011cU
+#define _reg_PHY_ADR_CALVL_FG_3                            0x0000011dU
+#define _reg_PHY_ADR_CALVL_BG_3                            0x0000011eU
+#define _reg_PHY_ADR_ADDR_SEL                              0x0000011fU
+#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY                    0x00000120U
+#define _reg_PHY_ADR_BIT_MASK                              0x00000121U
+#define _reg_PHY_ADR_SEG_MASK                              0x00000122U
+#define _reg_PHY_ADR_CALVL_TRAIN_MASK                      0x00000123U
+#define _reg_PHY_ADR_CSLVL_TRAIN_MASK                      0x00000124U
+#define _reg_PHY_ADR_SW_TXIO_CTRL                          0x00000125U
+#define _reg_PHY_ADR_TSEL_SELECT                           0x00000126U
+#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY                   0x00000127U
+#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY                   0x00000128U
+#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY                   0x00000129U
+#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY                   0x0000012aU
+#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY                   0x0000012bU
+#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY                   0x0000012cU
+#define _reg_PHY_ADR_SW_MASTER_MODE                        0x0000012dU
+#define _reg_PHY_ADR_MASTER_DELAY_START                    0x0000012eU
+#define _reg_PHY_ADR_MASTER_DELAY_STEP                     0x0000012fU
+#define _reg_PHY_ADR_MASTER_DELAY_WAIT                     0x00000130U
+#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE             0x00000131U
+#define _reg_PHY_ADR_CALVL_DLY_STEP                        0x00000132U
+#define _reg_PHY_FREQ_SEL                                  0x00000133U
+#define _reg_PHY_FREQ_SEL_FROM_REGIF                       0x00000134U
+#define _reg_PHY_FREQ_SEL_MULTICAST_EN                     0x00000135U
+#define _reg_PHY_FREQ_SEL_INDEX                            0x00000136U
+#define _reg_PHY_SW_GRP_SHIFT_0                            0x00000137U
+#define _reg_PHY_SW_GRP_SHIFT_1                            0x00000138U
+#define _reg_PHY_SW_GRP_SHIFT_2                            0x00000139U
+#define _reg_PHY_SW_GRP_SHIFT_3                            0x0000013aU
+#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY                    0x0000013bU
+#define _reg_PHY_SW_GRP_BYPASS_SHIFT                       0x0000013cU
+#define _reg_PHY_GRP_BYPASS_OVERRIDE                       0x0000013dU
+#define _reg_SC_PHY_MANUAL_UPDATE                          0x0000013eU
+#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE            0x0000013fU
+#define _reg_PHY_LP4_BOOT_DISABLE                          0x00000140U
+#define _reg_PHY_CSLVL_ENABLE                              0x00000141U
+#define _reg_PHY_CSLVL_CS_MAP                              0x00000142U
+#define _reg_PHY_CSLVL_START                               0x00000143U
+#define _reg_PHY_CSLVL_QTR                                 0x00000144U
+#define _reg_PHY_CSLVL_COARSE_CHK                          0x00000145U
+#define _reg_PHY_CSLVL_CAPTURE_CNT                         0x00000146U
+#define _reg_PHY_CSLVL_COARSE_DLY                          0x00000147U
+#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT                  0x00000148U
+#define _reg_PHY_CSLVL_DEBUG_MODE                          0x00000149U
+#define _reg_SC_PHY_CSLVL_DEBUG_CONT                       0x0000014aU
+#define _reg_SC_PHY_CSLVL_ERROR_CLR                        0x0000014bU
+#define _reg_PHY_CSLVL_OBS0                                0x0000014cU
+#define _reg_PHY_CSLVL_OBS1                                0x0000014dU
+#define _reg_PHY_CALVL_CS_MAP                              0x0000014eU
+#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT                0x0000014fU
+#define _reg_PHY_GRP_SHIFT_OBS_SELECT                      0x00000150U
+#define _reg_PHY_GRP_SLV_DLY_ENC_OBS                       0x00000151U
+#define _reg_PHY_GRP_SHIFT_OBS                             0x00000152U
+#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE              0x00000153U
+#define _reg_PHY_ADRCTL_SNAP_OBS_REGS                      0x00000154U
+#define _reg_PHY_DFI_PHYUPD_TYPE                           0x00000155U
+#define _reg_PHY_ADRCTL_LPDDR                              0x00000156U
+#define _reg_PHY_LP4_ACTIVE                                0x00000157U
+#define _reg_PHY_LPDDR3_CS                                 0x00000158U
+#define _reg_PHY_CALVL_RESULT_MASK                         0x00000159U
+#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES                  0x0000015aU
+#define _reg_PHY_SW_TXIO_CTRL_0                            0x0000015bU
+#define _reg_PHY_SW_TXIO_CTRL_1                            0x0000015cU
+#define _reg_PHY_SW_TXIO_CTRL_2                            0x0000015dU
+#define _reg_PHY_SW_TXIO_CTRL_3                            0x0000015eU
+#define _reg_PHY_MEMCLK_SW_TXIO_CTRL                       0x0000015fU
+#define _reg_PHY_CA_SW_TXPWR_CTRL                          0x00000160U
+#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL                      0x00000161U
+#define _reg_PHY_USER_DEF_REG_AC_0                         0x00000162U
+#define _reg_PHY_USER_DEF_REG_AC_1                         0x00000163U
+#define _reg_PHY_USER_DEF_REG_AC_2                         0x00000164U
+#define _reg_PHY_USER_DEF_REG_AC_3                         0x00000165U
+#define _reg_PHY_UPDATE_CLK_CAL_VALUES                     0x00000166U
+#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE                 0x00000167U
+#define _reg_PHY_PLL_CTRL                                  0x00000168U
+#define _reg_PHY_PLL_CTRL_TOP                              0x00000169U
+#define _reg_PHY_PLL_CTRL_CA                               0x0000016aU
+#define _reg_PHY_PLL_BYPASS                                0x0000016bU
+#define _reg_PHY_LOW_FREQ_SEL                              0x0000016cU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_0                        0x0000016dU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_1                        0x0000016eU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_2                        0x0000016fU
+#define _reg_PHY_PAD_VREF_CTRL_DQ_3                        0x00000170U
+#define _reg_PHY_PAD_VREF_CTRL_AC                          0x00000171U
+#define _reg_PHY_CSLVL_DLY_STEP                            0x00000172U
+#define _reg_PHY_SET_DFI_INPUT_0                           0x00000173U
+#define _reg_PHY_SET_DFI_INPUT_1                           0x00000174U
+#define _reg_PHY_SET_DFI_INPUT_2                           0x00000175U
+#define _reg_PHY_SET_DFI_INPUT_3                           0x00000176U
+#define _reg_PHY_GRP_SLAVE_DELAY_0                         0x00000177U
+#define _reg_PHY_GRP_SLAVE_DELAY_1                         0x00000178U
+#define _reg_PHY_GRP_SLAVE_DELAY_2                         0x00000179U
+#define _reg_PHY_GRP_SLAVE_DELAY_3                         0x0000017aU
+#define _reg_PHY_CS_ACS_ALLOCATION_0                       0x0000017bU
+#define _reg_PHY_CS_ACS_ALLOCATION_1                       0x0000017cU
+#define _reg_PHY_CS_ACS_ALLOCATION_2                       0x0000017dU
+#define _reg_PHY_CS_ACS_ALLOCATION_3                       0x0000017eU
+#define _reg_PHY_LP4_BOOT_PLL_CTRL                         0x0000017fU
+#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA                      0x00000180U
+#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL                     0x00000181U
+#define _reg_PHY_PLL_CTRL_OVERRIDE                         0x00000182U
+#define _reg_PHY_PLL_WAIT                                  0x00000183U
+#define _reg_PHY_PLL_WAIT_TOP                              0x00000184U
+#define _reg_PHY_PLL_OBS_0                                 0x00000185U
+#define _reg_PHY_PLL_OBS_1                                 0x00000186U
+#define _reg_PHY_PLL_OBS_2                                 0x00000187U
+#define _reg_PHY_PLL_OBS_3                                 0x00000188U
+#define _reg_PHY_PLL_OBS_4                                 0x00000189U
+#define _reg_PHY_PLL_TESTOUT_SEL                           0x0000018aU
+#define _reg_PHY_TCKSRE_WAIT                               0x0000018bU
+#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL                     0x0000018cU
+#define _reg_PHY_LP_WAKEUP                                 0x0000018dU
+#define _reg_PHY_LS_IDLE_EN                                0x0000018eU
+#define _reg_PHY_LP_CTRLUPD_CNTR_CFG                       0x0000018fU
+#define _reg_PHY_TDFI_PHY_WRDELAY                          0x00000190U
+#define _reg_PHY_PAD_FDBK_DRIVE                            0x00000191U
+#define _reg_PHY_PAD_DATA_DRIVE                            0x00000192U
+#define _reg_PHY_PAD_DQS_DRIVE                             0x00000193U
+#define _reg_PHY_PAD_ADDR_DRIVE                            0x00000194U
+#define _reg_PHY_PAD_CLK_DRIVE                             0x00000195U
+#define _reg_PHY_PAD_FDBK_TERM                             0x00000196U
+#define _reg_PHY_PAD_DATA_TERM                             0x00000197U
+#define _reg_PHY_PAD_DQS_TERM                              0x00000198U
+#define _reg_PHY_PAD_ADDR_TERM                             0x00000199U
+#define _reg_PHY_PAD_CLK_TERM                              0x0000019aU
+#define _reg_PHY_PAD_CKE_DRIVE                             0x0000019bU
+#define _reg_PHY_PAD_CKE_TERM                              0x0000019cU
+#define _reg_PHY_PAD_RST_DRIVE                             0x0000019dU
+#define _reg_PHY_PAD_RST_TERM                              0x0000019eU
+#define _reg_PHY_PAD_CS_DRIVE                              0x0000019fU
+#define _reg_PHY_PAD_CS_TERM                               0x000001a0U
+#define _reg_PHY_PAD_ODT_DRIVE                             0x000001a1U
+#define _reg_PHY_PAD_ODT_TERM                              0x000001a2U
+#define _reg_PHY_ADRCTL_RX_CAL                             0x000001a3U
+#define _reg_PHY_ADRCTL_LP3_RX_CAL                         0x000001a4U
+#define _reg_PHY_TST_CLK_PAD_CTRL                          0x000001a5U
+#define _reg_PHY_TST_CLK_PAD_CTRL2                         0x000001a6U
+#define _reg_PHY_CAL_MODE_0                                0x000001a7U
+#define _reg_PHY_CAL_CLEAR_0                               0x000001a8U
+#define _reg_PHY_CAL_START_0                               0x000001a9U
+#define _reg_PHY_CAL_INTERVAL_COUNT_0                      0x000001aaU
+#define _reg_PHY_CAL_SAMPLE_WAIT_0                         0x000001abU
+#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0                 0x000001acU
+#define _reg_PHY_CAL_CLK_SELECT_0                          0x000001adU
+#define _reg_PHY_CAL_RESULT_OBS_0                          0x000001aeU
+#define _reg_PHY_CAL_RESULT2_OBS_0                         0x000001afU
+#define _reg_PHY_CAL_CPTR_CNT_0                            0x000001b0U
+#define _reg_PHY_CAL_SETTLING_PRD_0                        0x000001b1U
+#define _reg_PHY_CAL_PU_FINE_ADJ_0                         0x000001b2U
+#define _reg_PHY_CAL_PD_FINE_ADJ_0                         0x000001b3U
+#define _reg_PHY_CAL_RCV_FINE_ADJ_0                        0x000001b4U
+#define _reg_PHY_CAL_DBG_CFG_0                             0x000001b5U
+#define _reg_SC_PHY_PAD_DBG_CONT_0                         0x000001b6U
+#define _reg_PHY_CAL_RESULT3_OBS_0                         0x000001b7U
+#define _reg_PHY_ADRCTL_PVT_MAP_0                          0x000001b8U
+#define _reg_PHY_CAL_SLOPE_ADJ_0                           0x000001b9U
+#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0                     0x000001baU
+#define _reg_PHY_CAL_TWO_PASS_CFG_0                        0x000001bbU
+#define _reg_PHY_CAL_SW_CAL_CFG_0                          0x000001bcU
+#define _reg_PHY_CAL_RANGE_MIN_0                           0x000001bdU
+#define _reg_PHY_CAL_RANGE_MAX_0                           0x000001beU
+#define _reg_PHY_PAD_ATB_CTRL                              0x000001bfU
+#define _reg_PHY_ADRCTL_MANUAL_UPDATE                      0x000001c0U
+#define _reg_PHY_AC_LPBK_ERR_CLEAR                         0x000001c1U
+#define _reg_PHY_AC_LPBK_OBS_SELECT                        0x000001c2U
+#define _reg_PHY_AC_LPBK_ENABLE                            0x000001c3U
+#define _reg_PHY_AC_LPBK_CONTROL                           0x000001c4U
+#define _reg_PHY_AC_PRBS_PATTERN_START                     0x000001c5U
+#define _reg_PHY_AC_PRBS_PATTERN_MASK                      0x000001c6U
+#define _reg_PHY_AC_LPBK_RESULT_OBS                        0x000001c7U
+#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT                    0x000001c8U
+#define _reg_PHY_AC_CLK_LPBK_ENABLE                        0x000001c9U
+#define _reg_PHY_AC_CLK_LPBK_CONTROL                       0x000001caU
+#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS                    0x000001cbU
+#define _reg_PHY_AC_PWR_RDC_DISABLE                        0x000001ccU
+#define _reg_PHY_DATA_BYTE_ORDER_SEL                       0x000001cdU
+#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH                  0x000001ceU
+#define _reg_PHY_LPDDR4_CONNECT                            0x000001cfU
+#define _reg_PHY_CALVL_DEVICE_MAP                          0x000001d0U
+#define _reg_PHY_ADR_DISABLE                               0x000001d1U
+#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL                   0x000001d2U
+#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE                   0x000001d3U
+#define _reg_PHY_DDL_AC_ENABLE                             0x000001d4U
+#define _reg_PHY_DDL_AC_MODE                               0x000001d5U
+#define _reg_PHY_PAD_BACKGROUND_CAL                        0x000001d6U
+#define _reg_PHY_INIT_UPDATE_CONFIG                        0x000001d7U
+#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC                0x000001d8U
+#define _reg_PHY_DLL_RST_EN                                0x000001d9U
+#define _reg_PHY_AC_INIT_COMPLETE_OBS                      0x000001daU
+#define _reg_PHY_DS_INIT_COMPLETE_OBS                      0x000001dbU
+#define _reg_PHY_UPDATE_MASK                               0x000001dcU
+#define _reg_PHY_PLL_SWITCH_CNT                            0x000001ddU
+#define _reg_PI_START                                      0x000001deU
+#define _reg_PI_DRAM_CLASS                                 0x000001dfU
+#define _reg_PI_VERSION                                    0x000001e0U
+#define _reg_PI_NORMAL_LVL_SEQ                             0x000001e1U
+#define _reg_PI_INIT_LVL_EN                                0x000001e2U
+#define _reg_PI_NOTCARE_PHYUPD                             0x000001e3U
+#define _reg_PI_ONBUS_MBIST                                0x000001e4U
+#define _reg_PI_TCMD_GAP                                   0x000001e5U
+#define _reg_PI_MASTER_ACK_DURATION_MIN                    0x000001e6U
+#define _reg_PI_DFI_VERSION                                0x000001e7U
+#define _reg_PI_TDFI_PHYMSTR_TYPE0                         0x000001e8U
+#define _reg_PI_TDFI_PHYMSTR_TYPE1                         0x000001e9U
+#define _reg_PI_TDFI_PHYMSTR_TYPE2                         0x000001eaU
+#define _reg_PI_TDFI_PHYMSTR_TYPE3                         0x000001ebU
+#define _reg_PI_DFI_PHYMSTR_TYPE                           0x000001ecU
+#define _reg_PI_DFI_PHYMSTR_CS_STATE_R                     0x000001edU
+#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R                    0x000001eeU
+#define _reg_PI_TDFI_PHYMSTR_MAX_F0                        0x000001efU
+#define _reg_PI_TDFI_PHYMSTR_RESP_F0                       0x000001f0U
+#define _reg_PI_TDFI_PHYMSTR_MAX_F1                        0x000001f1U
+#define _reg_PI_TDFI_PHYMSTR_RESP_F1                       0x000001f2U
+#define _reg_PI_TDFI_PHYMSTR_MAX_F2                        0x000001f3U
+#define _reg_PI_TDFI_PHYMSTR_RESP_F2                       0x000001f4U
+#define _reg_PI_TDFI_PHYUPD_RESP_F0                        0x000001f5U
+#define _reg_PI_TDFI_PHYUPD_TYPE0_F0                       0x000001f6U
+#define _reg_PI_TDFI_PHYUPD_TYPE1_F0                       0x000001f7U
+#define _reg_PI_TDFI_PHYUPD_TYPE2_F0                       0x000001f8U
+#define _reg_PI_TDFI_PHYUPD_TYPE3_F0                       0x000001f9U
+#define _reg_PI_TDFI_PHYUPD_RESP_F1                        0x000001faU
+#define _reg_PI_TDFI_PHYUPD_TYPE0_F1                       0x000001fbU
+#define _reg_PI_TDFI_PHYUPD_TYPE1_F1                       0x000001fcU
+#define _reg_PI_TDFI_PHYUPD_TYPE2_F1                       0x000001fdU
+#define _reg_PI_TDFI_PHYUPD_TYPE3_F1                       0x000001feU
+#define _reg_PI_TDFI_PHYUPD_RESP_F2                        0x000001ffU
+#define _reg_PI_TDFI_PHYUPD_TYPE0_F2                       0x00000200U
+#define _reg_PI_TDFI_PHYUPD_TYPE1_F2                       0x00000201U
+#define _reg_PI_TDFI_PHYUPD_TYPE2_F2                       0x00000202U
+#define _reg_PI_TDFI_PHYUPD_TYPE3_F2                       0x00000203U
+#define _reg_PI_CONTROL_ERROR_STATUS                       0x00000204U
+#define _reg_PI_EXIT_AFTER_INIT_CALVL                      0x00000205U
+#define _reg_PI_FREQ_MAP                                   0x00000206U
+#define _reg_PI_INIT_WORK_FREQ                             0x00000207U
+#define _reg_PI_INIT_DFS_CALVL_ONLY                        0x00000208U
+#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY                  0x00000209U
+#define _reg_PI_POWER_ON_SEQ_END_ARRAY                     0x0000020aU
+#define _reg_PI_SEQ1_PAT                                   0x0000020bU
+#define _reg_PI_SEQ1_PAT_MASK                              0x0000020cU
+#define _reg_PI_SEQ2_PAT                                   0x0000020dU
+#define _reg_PI_SEQ2_PAT_MASK                              0x0000020eU
+#define _reg_PI_SEQ3_PAT                                   0x0000020fU
+#define _reg_PI_SEQ3_PAT_MASK                              0x00000210U
+#define _reg_PI_SEQ4_PAT                                   0x00000211U
+#define _reg_PI_SEQ4_PAT_MASK                              0x00000212U
+#define _reg_PI_SEQ5_PAT                                   0x00000213U
+#define _reg_PI_SEQ5_PAT_MASK                              0x00000214U
+#define _reg_PI_SEQ6_PAT                                   0x00000215U
+#define _reg_PI_SEQ6_PAT_MASK                              0x00000216U
+#define _reg_PI_SEQ7_PAT                                   0x00000217U
+#define _reg_PI_SEQ7_PAT_MASK                              0x00000218U
+#define _reg_PI_SEQ8_PAT                                   0x00000219U
+#define _reg_PI_SEQ8_PAT_MASK                              0x0000021aU
+#define _reg_PI_WDT_DISABLE                                0x0000021bU
+#define _reg_PI_SW_RST_N                                   0x0000021cU
+#define _reg_RESERVED_R0                                   0x0000021dU
+#define _reg_PI_CS_MAP                                     0x0000021eU
+#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0                  0x0000021fU
+#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1                  0x00000220U
+#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2                  0x00000221U
+#define _reg_PI_TMRR                                       0x00000222U
+#define _reg_PI_WRLAT_F0                                   0x00000223U
+#define _reg_PI_ADDITIVE_LAT_F0                            0x00000224U
+#define _reg_PI_CASLAT_LIN_F0                              0x00000225U
+#define _reg_PI_WRLAT_F1                                   0x00000226U
+#define _reg_PI_ADDITIVE_LAT_F1                            0x00000227U
+#define _reg_PI_CASLAT_LIN_F1                              0x00000228U
+#define _reg_PI_WRLAT_F2                                   0x00000229U
+#define _reg_PI_ADDITIVE_LAT_F2                            0x0000022aU
+#define _reg_PI_CASLAT_LIN_F2                              0x0000022bU
+#define _reg_PI_PREAMBLE_SUPPORT                           0x0000022cU
+#define _reg_PI_AREFRESH                                   0x0000022dU
+#define _reg_PI_MCAREF_FORWARD_ONLY                        0x0000022eU
+#define _reg_PI_TRFC_F0                                    0x0000022fU
+#define _reg_PI_TREF_F0                                    0x00000230U
+#define _reg_PI_TRFC_F1                                    0x00000231U
+#define _reg_PI_TREF_F1                                    0x00000232U
+#define _reg_PI_TRFC_F2                                    0x00000233U
+#define _reg_PI_TREF_F2                                    0x00000234U
+#define _reg_RESERVED_H3VER2                               0x00000235U
+#define _reg_PI_TREF_INTERVAL                              0x00000236U
+#define _reg_PI_FREQ_CHANGE_REG_COPY                       0x00000237U
+#define _reg_PI_FREQ_SEL_FROM_REGIF                        0x00000238U
+#define _reg_PI_SWLVL_LOAD                                 0x00000239U
+#define _reg_PI_SWLVL_OP_DONE                              0x0000023aU
+#define _reg_PI_SW_WRLVL_RESP_0                            0x0000023bU
+#define _reg_PI_SW_WRLVL_RESP_1                            0x0000023cU
+#define _reg_PI_SW_WRLVL_RESP_2                            0x0000023dU
+#define _reg_PI_SW_WRLVL_RESP_3                            0x0000023eU
+#define _reg_PI_SW_RDLVL_RESP_0                            0x0000023fU
+#define _reg_PI_SW_RDLVL_RESP_1                            0x00000240U
+#define _reg_PI_SW_RDLVL_RESP_2                            0x00000241U
+#define _reg_PI_SW_RDLVL_RESP_3                            0x00000242U
+#define _reg_PI_SW_CALVL_RESP_0                            0x00000243U
+#define _reg_PI_SW_LEVELING_MODE                           0x00000244U
+#define _reg_PI_SWLVL_START                                0x00000245U
+#define _reg_PI_SWLVL_EXIT                                 0x00000246U
+#define _reg_PI_SWLVL_WR_SLICE_0                           0x00000247U
+#define _reg_PI_SWLVL_RD_SLICE_0                           0x00000248U
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0                  0x00000249U
+#define _reg_PI_SW_WDQLVL_RESP_0                           0x0000024aU
+#define _reg_PI_SWLVL_WR_SLICE_1                           0x0000024bU
+#define _reg_PI_SWLVL_RD_SLICE_1                           0x0000024cU
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1                  0x0000024dU
+#define _reg_PI_SW_WDQLVL_RESP_1                           0x0000024eU
+#define _reg_PI_SWLVL_WR_SLICE_2                           0x0000024fU
+#define _reg_PI_SWLVL_RD_SLICE_2                           0x00000250U
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2                  0x00000251U
+#define _reg_PI_SW_WDQLVL_RESP_2                           0x00000252U
+#define _reg_PI_SWLVL_WR_SLICE_3                           0x00000253U
+#define _reg_PI_SWLVL_RD_SLICE_3                           0x00000254U
+#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3                  0x00000255U
+#define _reg_PI_SW_WDQLVL_RESP_3                           0x00000256U
+#define _reg_PI_SW_WDQLVL_VREF                             0x00000257U
+#define _reg_PI_SWLVL_SM2_START                            0x00000258U
+#define _reg_PI_SWLVL_SM2_WR                               0x00000259U
+#define _reg_PI_SWLVL_SM2_RD                               0x0000025aU
+#define _reg_PI_SEQUENTIAL_LVL_REQ                         0x0000025bU
+#define _reg_PI_DFS_PERIOD_EN                              0x0000025cU
+#define _reg_PI_SRE_PERIOD_EN                              0x0000025dU
+#define _reg_PI_DFI40_POLARITY                             0x0000025eU
+#define _reg_PI_16BIT_DRAM_CONNECT                         0x0000025fU
+#define _reg_PI_TDFI_CTRL_DELAY_F0                         0x00000260U
+#define _reg_PI_TDFI_CTRL_DELAY_F1                         0x00000261U
+#define _reg_PI_TDFI_CTRL_DELAY_F2                         0x00000262U
+#define _reg_PI_WRLVL_REQ                                  0x00000263U
+#define _reg_PI_WRLVL_CS                                   0x00000264U
+#define _reg_PI_WLDQSEN                                    0x00000265U
+#define _reg_PI_WLMRD                                      0x00000266U
+#define _reg_PI_WRLVL_EN_F0                                0x00000267U
+#define _reg_PI_WRLVL_EN_F1                                0x00000268U
+#define _reg_PI_WRLVL_EN_F2                                0x00000269U
+#define _reg_PI_WRLVL_EN                                   0x0000026aU
+#define _reg_PI_WRLVL_INTERVAL                             0x0000026bU
+#define _reg_PI_WRLVL_PERIODIC                             0x0000026cU
+#define _reg_PI_WRLVL_ON_SREF_EXIT                         0x0000026dU
+#define _reg_PI_WRLVL_DISABLE_DFS                          0x0000026eU
+#define _reg_PI_WRLVL_RESP_MASK                            0x0000026fU
+#define _reg_PI_WRLVL_ROTATE                               0x00000270U
+#define _reg_PI_WRLVL_CS_MAP                               0x00000271U
+#define _reg_PI_WRLVL_ERROR_STATUS                         0x00000272U
+#define _reg_PI_TDFI_WRLVL_EN                              0x00000273U
+#define _reg_PI_TDFI_WRLVL_WW_F0                           0x00000274U
+#define _reg_PI_TDFI_WRLVL_WW_F1                           0x00000275U
+#define _reg_PI_TDFI_WRLVL_WW_F2                           0x00000276U
+#define _reg_PI_TDFI_WRLVL_WW                              0x00000277U
+#define _reg_PI_TDFI_WRLVL_RESP                            0x00000278U
+#define _reg_PI_TDFI_WRLVL_MAX                             0x00000279U
+#define _reg_PI_WRLVL_STROBE_NUM                           0x0000027aU
+#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ                    0x0000027bU
+#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR                    0x0000027cU
+#define _reg_PI_TODTL_2CMD_F0                              0x0000027dU
+#define _reg_PI_ODT_EN_F0                                  0x0000027eU
+#define _reg_PI_TODTL_2CMD_F1                              0x0000027fU
+#define _reg_PI_ODT_EN_F1                                  0x00000280U
+#define _reg_PI_TODTL_2CMD_F2                              0x00000281U
+#define _reg_PI_ODT_EN_F2                                  0x00000282U
+#define _reg_PI_TODTH_WR                                   0x00000283U
+#define _reg_PI_TODTH_RD                                   0x00000284U
+#define _reg_PI_ODT_RD_MAP_CS0                             0x00000285U
+#define _reg_PI_ODT_WR_MAP_CS0                             0x00000286U
+#define _reg_PI_ODT_RD_MAP_CS1                             0x00000287U
+#define _reg_PI_ODT_WR_MAP_CS1                             0x00000288U
+#define _reg_PI_ODT_RD_MAP_CS2                             0x00000289U
+#define _reg_PI_ODT_WR_MAP_CS2                             0x0000028aU
+#define _reg_PI_ODT_RD_MAP_CS3                             0x0000028bU
+#define _reg_PI_ODT_WR_MAP_CS3                             0x0000028cU
+#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD                    0x0000028dU
+#define _reg_PI_ODTLON_F0                                  0x0000028eU
+#define _reg_PI_TODTON_MIN_F0                              0x0000028fU
+#define _reg_PI_ODTLON_F1                                  0x00000290U
+#define _reg_PI_TODTON_MIN_F1                              0x00000291U
+#define _reg_PI_ODTLON_F2                                  0x00000292U
+#define _reg_PI_TODTON_MIN_F2                              0x00000293U
+#define _reg_PI_WR_TO_ODTH_F0                              0x00000294U
+#define _reg_PI_WR_TO_ODTH_F1                              0x00000295U
+#define _reg_PI_WR_TO_ODTH_F2                              0x00000296U
+#define _reg_PI_RD_TO_ODTH_F0                              0x00000297U
+#define _reg_PI_RD_TO_ODTH_F1                              0x00000298U
+#define _reg_PI_RD_TO_ODTH_F2                              0x00000299U
+#define _reg_PI_ADDRESS_MIRRORING                          0x0000029aU
+#define _reg_PI_RDLVL_REQ                                  0x0000029bU
+#define _reg_PI_RDLVL_GATE_REQ                             0x0000029cU
+#define _reg_PI_RDLVL_CS                                   0x0000029dU
+#define _reg_PI_RDLVL_PAT_0                                0x0000029eU
+#define _reg_PI_RDLVL_PAT_1                                0x0000029fU
+#define _reg_PI_RDLVL_PAT_2                                0x000002a0U
+#define _reg_PI_RDLVL_PAT_3                                0x000002a1U
+#define _reg_PI_RDLVL_PAT_4                                0x000002a2U
+#define _reg_PI_RDLVL_PAT_5                                0x000002a3U
+#define _reg_PI_RDLVL_PAT_6                                0x000002a4U
+#define _reg_PI_RDLVL_PAT_7                                0x000002a5U
+#define _reg_PI_RDLVL_SEQ_EN                               0x000002a6U
+#define _reg_PI_RDLVL_GATE_SEQ_EN                          0x000002a7U
+#define _reg_PI_RDLVL_PERIODIC                             0x000002a8U
+#define _reg_PI_RDLVL_ON_SREF_EXIT                         0x000002a9U
+#define _reg_PI_RDLVL_DISABLE_DFS                          0x000002aaU
+#define _reg_PI_RDLVL_GATE_PERIODIC                        0x000002abU
+#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT                    0x000002acU
+#define _reg_PI_RDLVL_GATE_DISABLE_DFS                     0x000002adU
+#define _reg_RESERVED_R1                                   0x000002aeU
+#define _reg_PI_RDLVL_ROTATE                               0x000002afU
+#define _reg_PI_RDLVL_GATE_ROTATE                          0x000002b0U
+#define _reg_PI_RDLVL_CS_MAP                               0x000002b1U
+#define _reg_PI_RDLVL_GATE_CS_MAP                          0x000002b2U
+#define _reg_PI_TDFI_RDLVL_RR                              0x000002b3U
+#define _reg_PI_TDFI_RDLVL_RESP                            0x000002b4U
+#define _reg_PI_RDLVL_RESP_MASK                            0x000002b5U
+#define _reg_PI_TDFI_RDLVL_EN                              0x000002b6U
+#define _reg_PI_RDLVL_EN_F0                                0x000002b7U
+#define _reg_PI_RDLVL_GATE_EN_F0                           0x000002b8U
+#define _reg_PI_RDLVL_EN_F1                                0x000002b9U
+#define _reg_PI_RDLVL_GATE_EN_F1                           0x000002baU
+#define _reg_PI_RDLVL_EN_F2                                0x000002bbU
+#define _reg_PI_RDLVL_GATE_EN_F2                           0x000002bcU
+#define _reg_PI_RDLVL_EN                                   0x000002bdU
+#define _reg_PI_RDLVL_GATE_EN                              0x000002beU
+#define _reg_PI_TDFI_RDLVL_MAX                             0x000002bfU
+#define _reg_PI_RDLVL_ERROR_STATUS                         0x000002c0U
+#define _reg_PI_RDLVL_INTERVAL                             0x000002c1U
+#define _reg_PI_RDLVL_GATE_INTERVAL                        0x000002c2U
+#define _reg_PI_RDLVL_PATTERN_START                        0x000002c3U
+#define _reg_PI_RDLVL_PATTERN_NUM                          0x000002c4U
+#define _reg_PI_RDLVL_STROBE_NUM                           0x000002c5U
+#define _reg_PI_RDLVL_GATE_STROBE_NUM                      0x000002c6U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_8                     0x000002c7U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_9                     0x000002c8U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_10                    0x000002c9U
+#define _reg_PI_LPDDR4_RDLVL_PATTERN_11                    0x000002caU
+#define _reg_PI_RD_PREAMBLE_TRAINING_EN                    0x000002cbU
+#define _reg_PI_REG_DIMM_ENABLE                            0x000002ccU
+#define _reg_PI_RDLAT_ADJ_F0                               0x000002cdU
+#define _reg_PI_RDLAT_ADJ_F1                               0x000002ceU
+#define _reg_PI_RDLAT_ADJ_F2                               0x000002cfU
+#define _reg_PI_TDFI_RDDATA_EN                             0x000002d0U
+#define _reg_PI_WRLAT_ADJ_F0                               0x000002d1U
+#define _reg_PI_WRLAT_ADJ_F1                               0x000002d2U
+#define _reg_PI_WRLAT_ADJ_F2                               0x000002d3U
+#define _reg_PI_TDFI_PHY_WRLAT                             0x000002d4U
+#define _reg_PI_TDFI_WRCSLAT_F0                            0x000002d5U
+#define _reg_PI_TDFI_WRCSLAT_F1                            0x000002d6U
+#define _reg_PI_TDFI_WRCSLAT_F2                            0x000002d7U
+#define _reg_PI_TDFI_RDCSLAT_F0                            0x000002d8U
+#define _reg_PI_TDFI_RDCSLAT_F1                            0x000002d9U
+#define _reg_PI_TDFI_RDCSLAT_F2                            0x000002daU
+#define _reg_PI_TDFI_PHY_WRDATA_F0                         0x000002dbU
+#define _reg_PI_TDFI_PHY_WRDATA_F1                         0x000002dcU
+#define _reg_PI_TDFI_PHY_WRDATA_F2                         0x000002ddU
+#define _reg_PI_TDFI_PHY_WRDATA                            0x000002deU
+#define _reg_PI_CALVL_REQ                                  0x000002dfU
+#define _reg_PI_CALVL_CS                                   0x000002e0U
+#define _reg_RESERVED_R2                                   0x000002e1U
+#define _reg_RESERVED_R3                                   0x000002e2U
+#define _reg_PI_CALVL_SEQ_EN                               0x000002e3U
+#define _reg_PI_CALVL_PERIODIC                             0x000002e4U
+#define _reg_PI_CALVL_ON_SREF_EXIT                         0x000002e5U
+#define _reg_PI_CALVL_DISABLE_DFS                          0x000002e6U
+#define _reg_PI_CALVL_ROTATE                               0x000002e7U
+#define _reg_PI_CALVL_CS_MAP                               0x000002e8U
+#define _reg_PI_TDFI_CALVL_EN                              0x000002e9U
+#define _reg_PI_TDFI_CALVL_CC_F0                           0x000002eaU
+#define _reg_PI_TDFI_CALVL_CAPTURE_F0                      0x000002ebU
+#define _reg_PI_TDFI_CALVL_CC_F1                           0x000002ecU
+#define _reg_PI_TDFI_CALVL_CAPTURE_F1                      0x000002edU
+#define _reg_PI_TDFI_CALVL_CC_F2                           0x000002eeU
+#define _reg_PI_TDFI_CALVL_CAPTURE_F2                      0x000002efU
+#define _reg_PI_TDFI_CALVL_RESP                            0x000002f0U
+#define _reg_PI_TDFI_CALVL_MAX                             0x000002f1U
+#define _reg_PI_CALVL_RESP_MASK                            0x000002f2U
+#define _reg_PI_CALVL_EN_F0                                0x000002f3U
+#define _reg_PI_CALVL_EN_F1                                0x000002f4U
+#define _reg_PI_CALVL_EN_F2                                0x000002f5U
+#define _reg_PI_CALVL_EN                                   0x000002f6U
+#define _reg_PI_CALVL_ERROR_STATUS                         0x000002f7U
+#define _reg_PI_CALVL_INTERVAL                             0x000002f8U
+#define _reg_PI_TCACKEL                                    0x000002f9U
+#define _reg_PI_TCAMRD                                     0x000002faU
+#define _reg_PI_TCACKEH                                    0x000002fbU
+#define _reg_PI_TMRZ_F0                                    0x000002fcU
+#define _reg_PI_TCAENT_F0                                  0x000002fdU
+#define _reg_PI_TMRZ_F1                                    0x000002feU
+#define _reg_PI_TCAENT_F1                                  0x000002ffU
+#define _reg_PI_TMRZ_F2                                    0x00000300U
+#define _reg_PI_TCAENT_F2                                  0x00000301U
+#define _reg_PI_TCAEXT                                     0x00000302U
+#define _reg_PI_CA_TRAIN_VREF_EN                           0x00000303U
+#define _reg_PI_TDFI_CACSCA_F0                             0x00000304U
+#define _reg_PI_TDFI_CASEL_F0                              0x00000305U
+#define _reg_PI_TVREF_SHORT_F0                             0x00000306U
+#define _reg_PI_TVREF_LONG_F0                              0x00000307U
+#define _reg_PI_TDFI_CACSCA_F1                             0x00000308U
+#define _reg_PI_TDFI_CASEL_F1                              0x00000309U
+#define _reg_PI_TVREF_SHORT_F1                             0x0000030aU
+#define _reg_PI_TVREF_LONG_F1                              0x0000030bU
+#define _reg_PI_TDFI_CACSCA_F2                             0x0000030cU
+#define _reg_PI_TDFI_CASEL_F2                              0x0000030dU
+#define _reg_PI_TVREF_SHORT_F2                             0x0000030eU
+#define _reg_PI_TVREF_LONG_F2                              0x0000030fU
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0          0x00000310U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0           0x00000311U
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1          0x00000312U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1           0x00000313U
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2          0x00000314U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2           0x00000315U
+#define _reg_PI_CALVL_VREF_INITIAL_START_POINT             0x00000316U
+#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT              0x00000317U
+#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE                0x00000318U
+#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE                 0x00000319U
+#define _reg_PI_CALVL_VREF_DELTA_F0                        0x0000031aU
+#define _reg_PI_CALVL_VREF_DELTA_F1                        0x0000031bU
+#define _reg_PI_CALVL_VREF_DELTA_F2                        0x0000031cU
+#define _reg_PI_CALVL_VREF_DELTA                           0x0000031dU
+#define _reg_PI_TDFI_INIT_START_MIN                        0x0000031eU
+#define _reg_PI_TDFI_INIT_COMPLETE_MIN                     0x0000031fU
+#define _reg_PI_TDFI_CALVL_STROBE_F0                       0x00000320U
+#define _reg_PI_TXP_F0                                     0x00000321U
+#define _reg_PI_TMRWCKEL_F0                                0x00000322U
+#define _reg_PI_TCKELCK_F0                                 0x00000323U
+#define _reg_PI_TDFI_CALVL_STROBE_F1                       0x00000324U
+#define _reg_PI_TXP_F1                                     0x00000325U
+#define _reg_PI_TMRWCKEL_F1                                0x00000326U
+#define _reg_PI_TCKELCK_F1                                 0x00000327U
+#define _reg_PI_TDFI_CALVL_STROBE_F2                       0x00000328U
+#define _reg_PI_TXP_F2                                     0x00000329U
+#define _reg_PI_TMRWCKEL_F2                                0x0000032aU
+#define _reg_PI_TCKELCK_F2                                 0x0000032bU
+#define _reg_PI_TCKCKEH                                    0x0000032cU
+#define _reg_PI_CALVL_STROBE_NUM                           0x0000032dU
+#define _reg_PI_SW_CA_TRAIN_VREF                           0x0000032eU
+#define _reg_PI_TDFI_INIT_START_F0                         0x0000032fU
+#define _reg_PI_TDFI_INIT_COMPLETE_F0                      0x00000330U
+#define _reg_PI_TDFI_INIT_START_F1                         0x00000331U
+#define _reg_PI_TDFI_INIT_COMPLETE_F1                      0x00000332U
+#define _reg_PI_TDFI_INIT_START_F2                         0x00000333U
+#define _reg_PI_TDFI_INIT_COMPLETE_F2                      0x00000334U
+#define _reg_PI_CLKDISABLE_2_INIT_START                    0x00000335U
+#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE          0x00000336U
+#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL              0x00000337U
+#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE            0x00000338U
+#define _reg_PI_TCKEHDQS_F0                                0x00000339U
+#define _reg_PI_TCKEHDQS_F1                                0x0000033aU
+#define _reg_PI_TCKEHDQS_F2                                0x0000033bU
+#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE                  0x0000033cU
+#define _reg_PI_WDQLVL_VREF_EN                             0x0000033dU
+#define _reg_PI_WDQLVL_BST_NUM                             0x0000033eU
+#define _reg_PI_TDFI_WDQLVL_WR_F0                          0x0000033fU
+#define _reg_PI_TDFI_WDQLVL_WR_F1                          0x00000340U
+#define _reg_PI_TDFI_WDQLVL_WR_F2                          0x00000341U
+#define _reg_PI_TDFI_WDQLVL_WR                             0x00000342U
+#define _reg_PI_TDFI_WDQLVL_RW                             0x00000343U
+#define _reg_PI_WDQLVL_RESP_MASK                           0x00000344U
+#define _reg_PI_WDQLVL_ROTATE                              0x00000345U
+#define _reg_PI_WDQLVL_CS_MAP                              0x00000346U
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0         0x00000347U
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0          0x00000348U
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1         0x00000349U
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1          0x0000034aU
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2         0x0000034bU
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2          0x0000034cU
+#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT            0x0000034dU
+#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT             0x0000034eU
+#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE               0x0000034fU
+#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE                0x00000350U
+#define _reg_PI_WDQLVL_VREF_DELTA_F0                       0x00000351U
+#define _reg_PI_WDQLVL_VREF_DELTA_F1                       0x00000352U
+#define _reg_PI_WDQLVL_VREF_DELTA_F2                       0x00000353U
+#define _reg_PI_WDQLVL_VREF_DELTA                          0x00000354U
+#define _reg_PI_WDQLVL_PERIODIC                            0x00000355U
+#define _reg_PI_WDQLVL_REQ                                 0x00000356U
+#define _reg_PI_WDQLVL_CS                                  0x00000357U
+#define _reg_PI_TDFI_WDQLVL_EN                             0x00000358U
+#define _reg_PI_TDFI_WDQLVL_RESP                           0x00000359U
+#define _reg_PI_TDFI_WDQLVL_MAX                            0x0000035aU
+#define _reg_PI_WDQLVL_INTERVAL                            0x0000035bU
+#define _reg_PI_WDQLVL_EN_F0                               0x0000035cU
+#define _reg_PI_WDQLVL_EN_F1                               0x0000035dU
+#define _reg_PI_WDQLVL_EN_F2                               0x0000035eU
+#define _reg_PI_WDQLVL_EN                                  0x0000035fU
+#define _reg_PI_WDQLVL_ON_SREF_EXIT                        0x00000360U
+#define _reg_PI_WDQLVL_DISABLE_DFS                         0x00000361U
+#define _reg_PI_WDQLVL_ERROR_STATUS                        0x00000362U
+#define _reg_PI_MR1_DATA_F0_0                              0x00000363U
+#define _reg_PI_MR2_DATA_F0_0                              0x00000364U
+#define _reg_PI_MR3_DATA_F0_0                              0x00000365U
+#define _reg_PI_MR11_DATA_F0_0                             0x00000366U
+#define _reg_PI_MR12_DATA_F0_0                             0x00000367U
+#define _reg_PI_MR14_DATA_F0_0                             0x00000368U
+#define _reg_PI_MR22_DATA_F0_0                             0x00000369U
+#define _reg_PI_MR1_DATA_F1_0                              0x0000036aU
+#define _reg_PI_MR2_DATA_F1_0                              0x0000036bU
+#define _reg_PI_MR3_DATA_F1_0                              0x0000036cU
+#define _reg_PI_MR11_DATA_F1_0                             0x0000036dU
+#define _reg_PI_MR12_DATA_F1_0                             0x0000036eU
+#define _reg_PI_MR14_DATA_F1_0                             0x0000036fU
+#define _reg_PI_MR22_DATA_F1_0                             0x00000370U
+#define _reg_PI_MR1_DATA_F2_0                              0x00000371U
+#define _reg_PI_MR2_DATA_F2_0                              0x00000372U
+#define _reg_PI_MR3_DATA_F2_0                              0x00000373U
+#define _reg_PI_MR11_DATA_F2_0                             0x00000374U
+#define _reg_PI_MR12_DATA_F2_0                             0x00000375U
+#define _reg_PI_MR14_DATA_F2_0                             0x00000376U
+#define _reg_PI_MR22_DATA_F2_0                             0x00000377U
+#define _reg_PI_MR13_DATA_0                                0x00000378U
+#define _reg_PI_MR1_DATA_F0_1                              0x00000379U
+#define _reg_PI_MR2_DATA_F0_1                              0x0000037aU
+#define _reg_PI_MR3_DATA_F0_1                              0x0000037bU
+#define _reg_PI_MR11_DATA_F0_1                             0x0000037cU
+#define _reg_PI_MR12_DATA_F0_1                             0x0000037dU
+#define _reg_PI_MR14_DATA_F0_1                             0x0000037eU
+#define _reg_PI_MR22_DATA_F0_1                             0x0000037fU
+#define _reg_PI_MR1_DATA_F1_1                              0x00000380U
+#define _reg_PI_MR2_DATA_F1_1                              0x00000381U
+#define _reg_PI_MR3_DATA_F1_1                              0x00000382U
+#define _reg_PI_MR11_DATA_F1_1                             0x00000383U
+#define _reg_PI_MR12_DATA_F1_1                             0x00000384U
+#define _reg_PI_MR14_DATA_F1_1                             0x00000385U
+#define _reg_PI_MR22_DATA_F1_1                             0x00000386U
+#define _reg_PI_MR1_DATA_F2_1                              0x00000387U
+#define _reg_PI_MR2_DATA_F2_1                              0x00000388U
+#define _reg_PI_MR3_DATA_F2_1                              0x00000389U
+#define _reg_PI_MR11_DATA_F2_1                             0x0000038aU
+#define _reg_PI_MR12_DATA_F2_1                             0x0000038bU
+#define _reg_PI_MR14_DATA_F2_1                             0x0000038cU
+#define _reg_PI_MR22_DATA_F2_1                             0x0000038dU
+#define _reg_PI_MR13_DATA_1                                0x0000038eU
+#define _reg_PI_MR1_DATA_F0_2                              0x0000038fU
+#define _reg_PI_MR2_DATA_F0_2                              0x00000390U
+#define _reg_PI_MR3_DATA_F0_2                              0x00000391U
+#define _reg_PI_MR11_DATA_F0_2                             0x00000392U
+#define _reg_PI_MR12_DATA_F0_2                             0x00000393U
+#define _reg_PI_MR14_DATA_F0_2                             0x00000394U
+#define _reg_PI_MR22_DATA_F0_2                             0x00000395U
+#define _reg_PI_MR1_DATA_F1_2                              0x00000396U
+#define _reg_PI_MR2_DATA_F1_2                              0x00000397U
+#define _reg_PI_MR3_DATA_F1_2                              0x00000398U
+#define _reg_PI_MR11_DATA_F1_2                             0x00000399U
+#define _reg_PI_MR12_DATA_F1_2                             0x0000039aU
+#define _reg_PI_MR14_DATA_F1_2                             0x0000039bU
+#define _reg_PI_MR22_DATA_F1_2                             0x0000039cU
+#define _reg_PI_MR1_DATA_F2_2                              0x0000039dU
+#define _reg_PI_MR2_DATA_F2_2                              0x0000039eU
+#define _reg_PI_MR3_DATA_F2_2                              0x0000039fU
+#define _reg_PI_MR11_DATA_F2_2                             0x000003a0U
+#define _reg_PI_MR12_DATA_F2_2                             0x000003a1U
+#define _reg_PI_MR14_DATA_F2_2                             0x000003a2U
+#define _reg_PI_MR22_DATA_F2_2                             0x000003a3U
+#define _reg_PI_MR13_DATA_2                                0x000003a4U
+#define _reg_PI_MR1_DATA_F0_3                              0x000003a5U
+#define _reg_PI_MR2_DATA_F0_3                              0x000003a6U
+#define _reg_PI_MR3_DATA_F0_3                              0x000003a7U
+#define _reg_PI_MR11_DATA_F0_3                             0x000003a8U
+#define _reg_PI_MR12_DATA_F0_3                             0x000003a9U
+#define _reg_PI_MR14_DATA_F0_3                             0x000003aaU
+#define _reg_PI_MR22_DATA_F0_3                             0x000003abU
+#define _reg_PI_MR1_DATA_F1_3                              0x000003acU
+#define _reg_PI_MR2_DATA_F1_3                              0x000003adU
+#define _reg_PI_MR3_DATA_F1_3                              0x000003aeU
+#define _reg_PI_MR11_DATA_F1_3                             0x000003afU
+#define _reg_PI_MR12_DATA_F1_3                             0x000003b0U
+#define _reg_PI_MR14_DATA_F1_3                             0x000003b1U
+#define _reg_PI_MR22_DATA_F1_3                             0x000003b2U
+#define _reg_PI_MR1_DATA_F2_3                              0x000003b3U
+#define _reg_PI_MR2_DATA_F2_3                              0x000003b4U
+#define _reg_PI_MR3_DATA_F2_3                              0x000003b5U
+#define _reg_PI_MR11_DATA_F2_3                             0x000003b6U
+#define _reg_PI_MR12_DATA_F2_3                             0x000003b7U
+#define _reg_PI_MR14_DATA_F2_3                             0x000003b8U
+#define _reg_PI_MR22_DATA_F2_3                             0x000003b9U
+#define _reg_PI_MR13_DATA_3                                0x000003baU
+#define _reg_PI_BANK_DIFF                                  0x000003bbU
+#define _reg_PI_ROW_DIFF                                   0x000003bcU
+#define _reg_PI_TFC_F0                                     0x000003bdU
+#define _reg_PI_TFC_F1                                     0x000003beU
+#define _reg_PI_TFC_F2                                     0x000003bfU
+#define _reg_PI_TCCD                                       0x000003c0U
+#define _reg_PI_TRTP_F0                                    0x000003c1U
+#define _reg_PI_TRP_F0                                     0x000003c2U
+#define _reg_PI_TRCD_F0                                    0x000003c3U
+#define _reg_PI_TWTR_F0                                    0x000003c4U
+#define _reg_PI_TWR_F0                                     0x000003c5U
+#define _reg_PI_TRAS_MAX_F0                                0x000003c6U
+#define _reg_PI_TRAS_MIN_F0                                0x000003c7U
+#define _reg_PI_TDQSCK_MAX_F0                              0x000003c8U
+#define _reg_PI_TCCDMW_F0                                  0x000003c9U
+#define _reg_PI_TSR_F0                                     0x000003caU
+#define _reg_PI_TMRD_F0                                    0x000003cbU
+#define _reg_PI_TMRW_F0                                    0x000003ccU
+#define _reg_PI_TMOD_F0                                    0x000003cdU
+#define _reg_PI_TRTP_F1                                    0x000003ceU
+#define _reg_PI_TRP_F1                                     0x000003cfU
+#define _reg_PI_TRCD_F1                                    0x000003d0U
+#define _reg_PI_TWTR_F1                                    0x000003d1U
+#define _reg_PI_TWR_F1                                     0x000003d2U
+#define _reg_PI_TRAS_MAX_F1                                0x000003d3U
+#define _reg_PI_TRAS_MIN_F1                                0x000003d4U
+#define _reg_PI_TDQSCK_MAX_F1                              0x000003d5U
+#define _reg_PI_TCCDMW_F1                                  0x000003d6U
+#define _reg_PI_TSR_F1                                     0x000003d7U
+#define _reg_PI_TMRD_F1                                    0x000003d8U
+#define _reg_PI_TMRW_F1                                    0x000003d9U
+#define _reg_PI_TMOD_F1                                    0x000003daU
+#define _reg_PI_TRTP_F2                                    0x000003dbU
+#define _reg_PI_TRP_F2                                     0x000003dcU
+#define _reg_PI_TRCD_F2                                    0x000003ddU
+#define _reg_PI_TWTR_F2                                    0x000003deU
+#define _reg_PI_TWR_F2                                     0x000003dfU
+#define _reg_PI_TRAS_MAX_F2                                0x000003e0U
+#define _reg_PI_TRAS_MIN_F2                                0x000003e1U
+#define _reg_PI_TDQSCK_MAX_F2                              0x000003e2U
+#define _reg_PI_TCCDMW_F2                                  0x000003e3U
+#define _reg_PI_TSR_F2                                     0x000003e4U
+#define _reg_PI_TMRD_F2                                    0x000003e5U
+#define _reg_PI_TMRW_F2                                    0x000003e6U
+#define _reg_PI_TMOD_F2                                    0x000003e7U
+#define _reg_RESERVED_R4                                   0x000003e8U
+#define _reg_RESERVED_R5                                   0x000003e9U
+#define _reg_RESERVED_R6                                   0x000003eaU
+#define _reg_RESERVED_R7                                   0x000003ebU
+#define _reg_RESERVED_R8                                   0x000003ecU
+#define _reg_RESERVED_R9                                   0x000003edU
+#define _reg_RESERVED_R10                                  0x000003eeU
+#define _reg_RESERVED_R11                                  0x000003efU
+#define _reg_RESERVED_R12                                  0x000003f0U
+#define _reg_RESERVED_R13                                  0x000003f1U
+#define _reg_RESERVED_R14                                  0x000003f2U
+#define _reg_RESERVED_R15                                  0x000003f3U
+#define _reg_RESERVED_R16                                  0x000003f4U
+#define _reg_RESERVED_R17                                  0x000003f5U
+#define _reg_RESERVED_R18                                  0x000003f6U
+#define _reg_RESERVED_R19                                  0x000003f7U
+#define _reg_RESERVED_R20                                  0x000003f8U
+#define _reg_RESERVED_R21                                  0x000003f9U
+#define _reg_RESERVED_R22                                  0x000003faU
+#define _reg_RESERVED_R23                                  0x000003fbU
+#define _reg_PI_INT_STATUS                                 0x000003fcU
+#define _reg_PI_INT_ACK                                    0x000003fdU
+#define _reg_PI_INT_MASK                                   0x000003feU
+#define _reg_PI_BIST_EXP_DATA_P0                           0x000003ffU
+#define _reg_PI_BIST_EXP_DATA_P1                           0x00000400U
+#define _reg_PI_BIST_EXP_DATA_P2                           0x00000401U
+#define _reg_PI_BIST_EXP_DATA_P3                           0x00000402U
+#define _reg_PI_BIST_FAIL_DATA_P0                          0x00000403U
+#define _reg_PI_BIST_FAIL_DATA_P1                          0x00000404U
+#define _reg_PI_BIST_FAIL_DATA_P2                          0x00000405U
+#define _reg_PI_BIST_FAIL_DATA_P3                          0x00000406U
+#define _reg_PI_BIST_FAIL_ADDR_P0                          0x00000407U
+#define _reg_PI_BIST_FAIL_ADDR_P1                          0x00000408U
+#define _reg_PI_BSTLEN                                     0x00000409U
+#define _reg_PI_LONG_COUNT_MASK                            0x0000040aU
+#define _reg_PI_CMD_SWAP_EN                                0x0000040bU
+#define _reg_PI_CKE_MUX_0                                  0x0000040cU
+#define _reg_PI_CKE_MUX_1                                  0x0000040dU
+#define _reg_PI_CKE_MUX_2                                  0x0000040eU
+#define _reg_PI_CKE_MUX_3                                  0x0000040fU
+#define _reg_PI_CS_MUX_0                                   0x00000410U
+#define _reg_PI_CS_MUX_1                                   0x00000411U
+#define _reg_PI_CS_MUX_2                                   0x00000412U
+#define _reg_PI_CS_MUX_3                                   0x00000413U
+#define _reg_PI_RAS_N_MUX                                  0x00000414U
+#define _reg_PI_CAS_N_MUX                                  0x00000415U
+#define _reg_PI_WE_N_MUX                                   0x00000416U
+#define _reg_PI_BANK_MUX_0                                 0x00000417U
+#define _reg_PI_BANK_MUX_1                                 0x00000418U
+#define _reg_PI_BANK_MUX_2                                 0x00000419U
+#define _reg_PI_ODT_MUX_0                                  0x0000041aU
+#define _reg_PI_ODT_MUX_1                                  0x0000041bU
+#define _reg_PI_ODT_MUX_2                                  0x0000041cU
+#define _reg_PI_ODT_MUX_3                                  0x0000041dU
+#define _reg_PI_RESET_N_MUX_0                              0x0000041eU
+#define _reg_PI_RESET_N_MUX_1                              0x0000041fU
+#define _reg_PI_RESET_N_MUX_2                              0x00000420U
+#define _reg_PI_RESET_N_MUX_3                              0x00000421U
+#define _reg_PI_DATA_BYTE_SWAP_EN                          0x00000422U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE0                      0x00000423U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE1                      0x00000424U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE2                      0x00000425U
+#define _reg_PI_DATA_BYTE_SWAP_SLICE3                      0x00000426U
+#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN                    0x00000427U
+#define _reg_PI_TDFI_CTRLUPD_MIN                           0x00000428U
+#define _reg_PI_TDFI_CTRLUPD_MAX_F0                        0x00000429U
+#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0                   0x0000042aU
+#define _reg_PI_TDFI_CTRLUPD_MAX_F1                        0x0000042bU
+#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1                   0x0000042cU
+#define _reg_PI_TDFI_CTRLUPD_MAX_F2                        0x0000042dU
+#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2                   0x0000042eU
+#define _reg_PI_UPDATE_ERROR_STATUS                        0x0000042fU
+#define _reg_PI_BIST_GO                                    0x00000430U
+#define _reg_PI_BIST_RESULT                                0x00000431U
+#define _reg_PI_ADDR_SPACE                                 0x00000432U
+#define _reg_PI_BIST_DATA_CHECK                            0x00000433U
+#define _reg_PI_BIST_ADDR_CHECK                            0x00000434U
+#define _reg_PI_BIST_START_ADDRESS_P0                      0x00000435U
+#define _reg_PI_BIST_START_ADDRESS_P1                      0x00000436U
+#define _reg_PI_BIST_DATA_MASK_P0                          0x00000437U
+#define _reg_PI_BIST_DATA_MASK_P1                          0x00000438U
+#define _reg_PI_BIST_ERR_COUNT                             0x00000439U
+#define _reg_PI_BIST_ERR_STOP                              0x0000043aU
+#define _reg_PI_BIST_ADDR_MASK_0_P0                        0x0000043bU
+#define _reg_PI_BIST_ADDR_MASK_0_P1                        0x0000043cU
+#define _reg_PI_BIST_ADDR_MASK_1_P0                        0x0000043dU
+#define _reg_PI_BIST_ADDR_MASK_1_P1                        0x0000043eU
+#define _reg_PI_BIST_ADDR_MASK_2_P0                        0x0000043fU
+#define _reg_PI_BIST_ADDR_MASK_2_P1                        0x00000440U
+#define _reg_PI_BIST_ADDR_MASK_3_P0                        0x00000441U
+#define _reg_PI_BIST_ADDR_MASK_3_P1                        0x00000442U
+#define _reg_PI_BIST_ADDR_MASK_4_P0                        0x00000443U
+#define _reg_PI_BIST_ADDR_MASK_4_P1                        0x00000444U
+#define _reg_PI_BIST_ADDR_MASK_5_P0                        0x00000445U
+#define _reg_PI_BIST_ADDR_MASK_5_P1                        0x00000446U
+#define _reg_PI_BIST_ADDR_MASK_6_P0                        0x00000447U
+#define _reg_PI_BIST_ADDR_MASK_6_P1                        0x00000448U
+#define _reg_PI_BIST_ADDR_MASK_7_P0                        0x00000449U
+#define _reg_PI_BIST_ADDR_MASK_7_P1                        0x0000044aU
+#define _reg_PI_BIST_ADDR_MASK_8_P0                        0x0000044bU
+#define _reg_PI_BIST_ADDR_MASK_8_P1                        0x0000044cU
+#define _reg_PI_BIST_ADDR_MASK_9_P0                        0x0000044dU
+#define _reg_PI_BIST_ADDR_MASK_9_P1                        0x0000044eU
+#define _reg_PI_BIST_MODE                                  0x0000044fU
+#define _reg_PI_BIST_ADDR_MODE                             0x00000450U
+#define _reg_PI_BIST_PAT_MODE                              0x00000451U
+#define _reg_PI_BIST_USER_PAT_P0                           0x00000452U
+#define _reg_PI_BIST_USER_PAT_P1                           0x00000453U
+#define _reg_PI_BIST_USER_PAT_P2                           0x00000454U
+#define _reg_PI_BIST_USER_PAT_P3                           0x00000455U
+#define _reg_PI_BIST_PAT_NUM                               0x00000456U
+#define _reg_PI_BIST_STAGE_0                               0x00000457U
+#define _reg_PI_BIST_STAGE_1                               0x00000458U
+#define _reg_PI_BIST_STAGE_2                               0x00000459U
+#define _reg_PI_BIST_STAGE_3                               0x0000045aU
+#define _reg_PI_BIST_STAGE_4                               0x0000045bU
+#define _reg_PI_BIST_STAGE_5                               0x0000045cU
+#define _reg_PI_BIST_STAGE_6                               0x0000045dU
+#define _reg_PI_BIST_STAGE_7                               0x0000045eU
+#define _reg_PI_COL_DIFF                                   0x0000045fU
+#define _reg_PI_SELF_REFRESH_EN                            0x00000460U
+#define _reg_PI_TXSR_F0                                    0x00000461U
+#define _reg_PI_TXSR_F1                                    0x00000462U
+#define _reg_PI_TXSR_F2                                    0x00000463U
+#define _reg_PI_MONITOR_SRC_SEL_0                          0x00000464U
+#define _reg_PI_MONITOR_CAP_SEL_0                          0x00000465U
+#define _reg_PI_MONITOR_0                                  0x00000466U
+#define _reg_PI_MONITOR_SRC_SEL_1                          0x00000467U
+#define _reg_PI_MONITOR_CAP_SEL_1                          0x00000468U
+#define _reg_PI_MONITOR_1                                  0x00000469U
+#define _reg_PI_MONITOR_SRC_SEL_2                          0x0000046aU
+#define _reg_PI_MONITOR_CAP_SEL_2                          0x0000046bU
+#define _reg_PI_MONITOR_2                                  0x0000046cU
+#define _reg_PI_MONITOR_SRC_SEL_3                          0x0000046dU
+#define _reg_PI_MONITOR_CAP_SEL_3                          0x0000046eU
+#define _reg_PI_MONITOR_3                                  0x0000046fU
+#define _reg_PI_MONITOR_SRC_SEL_4                          0x00000470U
+#define _reg_PI_MONITOR_CAP_SEL_4                          0x00000471U
+#define _reg_PI_MONITOR_4                                  0x00000472U
+#define _reg_PI_MONITOR_SRC_SEL_5                          0x00000473U
+#define _reg_PI_MONITOR_CAP_SEL_5                          0x00000474U
+#define _reg_PI_MONITOR_5                                  0x00000475U
+#define _reg_PI_MONITOR_SRC_SEL_6                          0x00000476U
+#define _reg_PI_MONITOR_CAP_SEL_6                          0x00000477U
+#define _reg_PI_MONITOR_6                                  0x00000478U
+#define _reg_PI_MONITOR_SRC_SEL_7                          0x00000479U
+#define _reg_PI_MONITOR_CAP_SEL_7                          0x0000047aU
+#define _reg_PI_MONITOR_7                                  0x0000047bU
+#define _reg_PI_MONITOR_STROBE                             0x0000047cU
+#define _reg_PI_DLL_LOCK                                   0x0000047dU
+#define _reg_PI_FREQ_NUMBER_STATUS                         0x0000047eU
+#define _reg_RESERVED_R24                                  0x0000047fU
+#define _reg_PI_PHYMSTR_TYPE                               0x00000480U
+#define _reg_PI_POWER_REDUC_EN                             0x00000481U
+#define _reg_RESERVED_R25                                  0x00000482U
+#define _reg_RESERVED_R26                                  0x00000483U
+#define _reg_RESERVED_R27                                  0x00000484U
+#define _reg_RESERVED_R28                                  0x00000485U
+#define _reg_RESERVED_R29                                  0x00000486U
+#define _reg_RESERVED_R30                                  0x00000487U
+#define _reg_RESERVED_R31                                  0x00000488U
+#define _reg_RESERVED_R32                                  0x00000489U
+#define _reg_RESERVED_R33                                  0x0000048aU
+#define _reg_RESERVED_R34                                  0x0000048bU
+#define _reg_RESERVED_R35                                  0x0000048cU
+#define _reg_RESERVED_R36                                  0x0000048dU
+#define _reg_RESERVED_R37                                  0x0000048eU
+#define _reg_RESERVED_R38                                  0x0000048fU
+#define _reg_RESERVED_R39                                  0x00000490U
+#define _reg_PI_WRLVL_MAX_STROBE_PEND                      0x00000491U
+#define _reg_PI_TSDO_F0                                    0x00000492U
+#define _reg_PI_TSDO_F1                                    0x00000493U
+#define _reg_PI_TSDO_F2                                    0x00000494U
+
+#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff)
+#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
+#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
+
+const static uint32_t DDR_REGDEF_TBL[4][1173] = {
+	{
+/*0000*/ 0xffffffffU,
+/*0001*/ 0xffffffffU,
+/*0002*/ 0x000b0400U,
+/*0003*/ 0xffffffffU,
+/*0004*/ 0xffffffffU,
+/*0005*/ 0x10010400U,
+/*0006*/ 0x18050400U,
+/*0007*/ 0x00050401U,
+/*0008*/ 0x08050401U,
+/*0009*/ 0x10050401U,
+/*000a*/ 0x18050401U,
+/*000b*/ 0x00050402U,
+/*000c*/ 0x08050402U,
+/*000d*/ 0x10050402U,
+/*000e*/ 0x18050402U,
+/*000f*/ 0x00040403U,
+/*0010*/ 0x08030403U,
+/*0011*/ 0x00180404U,
+/*0012*/ 0x18030404U,
+/*0013*/ 0x00180405U,
+/*0014*/ 0x18020405U,
+/*0015*/ 0x00010406U,
+/*0016*/ 0x08020406U,
+/*0017*/ 0x10010406U,
+/*0018*/ 0x18010406U,
+/*0019*/ 0x00020407U,
+/*001a*/ 0x08040407U,
+/*001b*/ 0x10040407U,
+/*001c*/ 0x18040407U,
+/*001d*/ 0x000a0408U,
+/*001e*/ 0x10040408U,
+/*001f*/ 0xffffffffU,
+/*0020*/ 0xffffffffU,
+/*0021*/ 0x18070408U,
+/*0022*/ 0xffffffffU,
+/*0023*/ 0xffffffffU,
+/*0024*/ 0xffffffffU,
+/*0025*/ 0xffffffffU,
+/*0026*/ 0xffffffffU,
+/*0027*/ 0xffffffffU,
+/*0028*/ 0x000a0409U,
+/*0029*/ 0x10040409U,
+/*002a*/ 0x18010409U,
+/*002b*/ 0x0001040aU,
+/*002c*/ 0x0802040aU,
+/*002d*/ 0x1009040aU,
+/*002e*/ 0x0009040bU,
+/*002f*/ 0x1002040bU,
+/*0030*/ 0x0020040cU,
+/*0031*/ 0xffffffffU,
+/*0032*/ 0x0001040dU,
+/*0033*/ 0xffffffffU,
+/*0034*/ 0xffffffffU,
+/*0035*/ 0xffffffffU,
+/*0036*/ 0xffffffffU,
+/*0037*/ 0x0020040eU,
+/*0038*/ 0x0020040fU,
+/*0039*/ 0x00200410U,
+/*003a*/ 0x00200411U,
+/*003b*/ 0x00030412U,
+/*003c*/ 0x08010412U,
+/*003d*/ 0x10030412U,
+/*003e*/ 0x18030412U,
+/*003f*/ 0x00040413U,
+/*0040*/ 0x08040413U,
+/*0041*/ 0x10040413U,
+/*0042*/ 0x18040413U,
+/*0043*/ 0x00010414U,
+/*0044*/ 0x08010414U,
+/*0045*/ 0x10060414U,
+/*0046*/ 0x18040414U,
+/*0047*/ 0xffffffffU,
+/*0048*/ 0x00060415U,
+/*0049*/ 0x08040415U,
+/*004a*/ 0x10060415U,
+/*004b*/ 0x18040415U,
+/*004c*/ 0x00020416U,
+/*004d*/ 0x08050416U,
+/*004e*/ 0x10080416U,
+/*004f*/ 0x00200417U,
+/*0050*/ 0x00060418U,
+/*0051*/ 0x08030418U,
+/*0052*/ 0x100b0418U,
+/*0053*/ 0x00040419U,
+/*0054*/ 0x08040419U,
+/*0055*/ 0x10040419U,
+/*0056*/ 0xffffffffU,
+/*0057*/ 0x18010419U,
+/*0058*/ 0x0009041aU,
+/*0059*/ 0x0020041bU,
+/*005a*/ 0x0020041cU,
+/*005b*/ 0x0020041dU,
+/*005c*/ 0x0020041eU,
+/*005d*/ 0x0010041fU,
+/*005e*/ 0x00200420U,
+/*005f*/ 0x00010421U,
+/*0060*/ 0x08060421U,
+/*0061*/ 0x10080421U,
+/*0062*/ 0x00200422U,
+/*0063*/ 0xffffffffU,
+/*0064*/ 0x000a0423U,
+/*0065*/ 0x10060423U,
+/*0066*/ 0x18070423U,
+/*0067*/ 0x00080424U,
+/*0068*/ 0x08080424U,
+/*0069*/ 0x100a0424U,
+/*006a*/ 0x00070425U,
+/*006b*/ 0x08080425U,
+/*006c*/ 0x10080425U,
+/*006d*/ 0x18030425U,
+/*006e*/ 0x000a0426U,
+/*006f*/ 0x100a0426U,
+/*0070*/ 0x00110427U,
+/*0071*/ 0x00090428U,
+/*0072*/ 0x10090428U,
+/*0073*/ 0x00100429U,
+/*0074*/ 0x100e0429U,
+/*0075*/ 0x000e042aU,
+/*0076*/ 0x100c042aU,
+/*0077*/ 0x000a042bU,
+/*0078*/ 0x100a042bU,
+/*0079*/ 0x0002042cU,
+/*007a*/ 0x0020042dU,
+/*007b*/ 0x000b042eU,
+/*007c*/ 0x100b042eU,
+/*007d*/ 0x0020042fU,
+/*007e*/ 0x00120430U,
+/*007f*/ 0x00200431U,
+/*0080*/ 0x00200432U,
+/*0081*/ 0xffffffffU,
+/*0082*/ 0xffffffffU,
+/*0083*/ 0x00010433U,
+/*0084*/ 0x08010433U,
+/*0085*/ 0x10080433U,
+/*0086*/ 0x000c0434U,
+/*0087*/ 0x100c0434U,
+/*0088*/ 0x000c0435U,
+/*0089*/ 0x100c0435U,
+/*008a*/ 0x000c0436U,
+/*008b*/ 0x100c0436U,
+/*008c*/ 0x000c0437U,
+/*008d*/ 0x100c0437U,
+/*008e*/ 0x000c0438U,
+/*008f*/ 0x100c0438U,
+/*0090*/ 0x000c0439U,
+/*0091*/ 0x100b0439U,
+/*0092*/ 0xffffffffU,
+/*0093*/ 0xffffffffU,
+/*0094*/ 0x000b043aU,
+/*0095*/ 0x100b043aU,
+/*0096*/ 0x000b043bU,
+/*0097*/ 0x100b043bU,
+/*0098*/ 0x000b043cU,
+/*0099*/ 0x100b043cU,
+/*009a*/ 0x000b043dU,
+/*009b*/ 0x100b043dU,
+/*009c*/ 0x000b043eU,
+/*009d*/ 0x100a043eU,
+/*009e*/ 0xffffffffU,
+/*009f*/ 0x000a043fU,
+/*00a0*/ 0x100a043fU,
+/*00a1*/ 0x000a0440U,
+/*00a2*/ 0x100a0440U,
+/*00a3*/ 0x000a0441U,
+/*00a4*/ 0x100a0441U,
+/*00a5*/ 0x000a0442U,
+/*00a6*/ 0x100a0442U,
+/*00a7*/ 0xffffffffU,
+/*00a8*/ 0x000a0443U,
+/*00a9*/ 0x100a0443U,
+/*00aa*/ 0x000a0444U,
+/*00ab*/ 0x100a0444U,
+/*00ac*/ 0x000a0445U,
+/*00ad*/ 0x100a0445U,
+/*00ae*/ 0x000a0446U,
+/*00af*/ 0x100a0446U,
+/*00b0*/ 0x000a0447U,
+/*00b1*/ 0x100a0447U,
+/*00b2*/ 0x000a0448U,
+/*00b3*/ 0x100a0448U,
+/*00b4*/ 0x000a0449U,
+/*00b5*/ 0x100a0449U,
+/*00b6*/ 0x000a044aU,
+/*00b7*/ 0x100a044aU,
+/*00b8*/ 0x000a044bU,
+/*00b9*/ 0x100a044bU,
+/*00ba*/ 0x000a044cU,
+/*00bb*/ 0x1004044cU,
+/*00bc*/ 0x1803044cU,
+/*00bd*/ 0x000a044dU,
+/*00be*/ 0x100a044dU,
+/*00bf*/ 0x0001044eU,
+/*00c0*/ 0x080a044eU,
+/*00c1*/ 0x1804044eU,
+/*00c2*/ 0x000b044fU,
+/*00c3*/ 0x100a044fU,
+/*00c4*/ 0xffffffffU,
+/*00c5*/ 0x00080450U,
+/*00c6*/ 0x08080450U,
+/*00c7*/ 0x10080450U,
+/*00c8*/ 0x18080450U,
+/*00c9*/ 0x00080451U,
+/*00ca*/ 0xffffffffU,
+/*00cb*/ 0x08080451U,
+/*00cc*/ 0x10010451U,
+/*00cd*/ 0x18080451U,
+/*00ce*/ 0x00080452U,
+/*00cf*/ 0x08020452U,
+/*00d0*/ 0x10020452U,
+/*00d1*/ 0x18040452U,
+/*00d2*/ 0x00040453U,
+/*00d3*/ 0xffffffffU,
+/*00d4*/ 0x08040453U,
+/*00d5*/ 0x100a0453U,
+/*00d6*/ 0x00060454U,
+/*00d7*/ 0x08080454U,
+/*00d8*/ 0xffffffffU,
+/*00d9*/ 0x10040454U,
+/*00da*/ 0x18040454U,
+/*00db*/ 0x00050455U,
+/*00dc*/ 0x08040455U,
+/*00dd*/ 0x10050455U,
+/*00de*/ 0x000a0456U,
+/*00df*/ 0x100a0456U,
+/*00e0*/ 0x00080457U,
+/*00e1*/ 0xffffffffU,
+/*00e2*/ 0x08040457U,
+/*00e3*/ 0xffffffffU,
+/*00e4*/ 0xffffffffU,
+/*00e5*/ 0x00050600U,
+/*00e6*/ 0x08050600U,
+/*00e7*/ 0x10050600U,
+/*00e8*/ 0x18050600U,
+/*00e9*/ 0x00050601U,
+/*00ea*/ 0x08050601U,
+/*00eb*/ 0x100b0601U,
+/*00ec*/ 0x00010602U,
+/*00ed*/ 0x08030602U,
+/*00ee*/ 0x00200603U,
+/*00ef*/ 0xffffffffU,
+/*00f0*/ 0x00030604U,
+/*00f1*/ 0x080a0604U,
+/*00f2*/ 0xffffffffU,
+/*00f3*/ 0xffffffffU,
+/*00f4*/ 0x18030604U,
+/*00f5*/ 0x00030605U,
+/*00f6*/ 0x08010605U,
+/*00f7*/ 0x10010605U,
+/*00f8*/ 0x18060605U,
+/*00f9*/ 0xffffffffU,
+/*00fa*/ 0xffffffffU,
+/*00fb*/ 0xffffffffU,
+/*00fc*/ 0x00020606U,
+/*00fd*/ 0x08030606U,
+/*00fe*/ 0x10010606U,
+/*00ff*/ 0x000f0607U,
+/*0100*/ 0x00200608U,
+/*0101*/ 0x00200609U,
+/*0102*/ 0x000b060aU,
+/*0103*/ 0x100b060aU,
+/*0104*/ 0x000b060bU,
+/*0105*/ 0xffffffffU,
+/*0106*/ 0xffffffffU,
+/*0107*/ 0x0018060cU,
+/*0108*/ 0x0018060dU,
+/*0109*/ 0x0018060eU,
+/*010a*/ 0x0018060fU,
+/*010b*/ 0x1804060fU,
+/*010c*/ 0x00050610U,
+/*010d*/ 0x08020610U,
+/*010e*/ 0x10040610U,
+/*010f*/ 0x18040610U,
+/*0110*/ 0x00010611U,
+/*0111*/ 0x08010611U,
+/*0112*/ 0x10010611U,
+/*0113*/ 0x18030611U,
+/*0114*/ 0x00200612U,
+/*0115*/ 0x00200613U,
+/*0116*/ 0x00010614U,
+/*0117*/ 0x08140614U,
+/*0118*/ 0x00140615U,
+/*0119*/ 0x00140616U,
+/*011a*/ 0x00140617U,
+/*011b*/ 0x00140618U,
+/*011c*/ 0x00140619U,
+/*011d*/ 0x0014061aU,
+/*011e*/ 0x0014061bU,
+/*011f*/ 0x0018061cU,
+/*0120*/ 0x000a061dU,
+/*0121*/ 0x1006061dU,
+/*0122*/ 0x1806061dU,
+/*0123*/ 0x0006061eU,
+/*0124*/ 0xffffffffU,
+/*0125*/ 0xffffffffU,
+/*0126*/ 0x0008061fU,
+/*0127*/ 0x080b061fU,
+/*0128*/ 0x000b0620U,
+/*0129*/ 0x100b0620U,
+/*012a*/ 0x000b0621U,
+/*012b*/ 0x100b0621U,
+/*012c*/ 0x000b0622U,
+/*012d*/ 0x10040622U,
+/*012e*/ 0x000a0623U,
+/*012f*/ 0x10060623U,
+/*0130*/ 0x18080623U,
+/*0131*/ 0xffffffffU,
+/*0132*/ 0x00040624U,
+/*0133*/ 0xffffffffU,
+/*0134*/ 0xffffffffU,
+/*0135*/ 0x00010700U,
+/*0136*/ 0x08020700U,
+/*0137*/ 0x10050700U,
+/*0138*/ 0x18050700U,
+/*0139*/ 0x00050701U,
+/*013a*/ 0x08050701U,
+/*013b*/ 0x100b0701U,
+/*013c*/ 0x00050702U,
+/*013d*/ 0x08010702U,
+/*013e*/ 0x10010702U,
+/*013f*/ 0xffffffffU,
+/*0140*/ 0x18010702U,
+/*0141*/ 0x00010703U,
+/*0142*/ 0x08040703U,
+/*0143*/ 0x100b0703U,
+/*0144*/ 0x000b0704U,
+/*0145*/ 0xffffffffU,
+/*0146*/ 0x10040704U,
+/*0147*/ 0x000b0705U,
+/*0148*/ 0x10040705U,
+/*0149*/ 0x18010705U,
+/*014a*/ 0x00010706U,
+/*014b*/ 0x08010706U,
+/*014c*/ 0x00200707U,
+/*014d*/ 0x00200708U,
+/*014e*/ 0x00080709U,
+/*014f*/ 0x080a0709U,
+/*0150*/ 0x18050709U,
+/*0151*/ 0x000a070aU,
+/*0152*/ 0x1003070aU,
+/*0153*/ 0x1803070aU,
+/*0154*/ 0x0001070bU,
+/*0155*/ 0x0802070bU,
+/*0156*/ 0x1001070bU,
+/*0157*/ 0x1801070bU,
+/*0158*/ 0x0001070cU,
+/*0159*/ 0x0802070cU,
+/*015a*/ 0xffffffffU,
+/*015b*/ 0xffffffffU,
+/*015c*/ 0xffffffffU,
+/*015d*/ 0xffffffffU,
+/*015e*/ 0xffffffffU,
+/*015f*/ 0xffffffffU,
+/*0160*/ 0xffffffffU,
+/*0161*/ 0xffffffffU,
+/*0162*/ 0xffffffffU,
+/*0163*/ 0xffffffffU,
+/*0164*/ 0xffffffffU,
+/*0165*/ 0xffffffffU,
+/*0166*/ 0x1001070cU,
+/*0167*/ 0x1801070cU,
+/*0168*/ 0x000d070dU,
+/*0169*/ 0xffffffffU,
+/*016a*/ 0xffffffffU,
+/*016b*/ 0x0005070eU,
+/*016c*/ 0x0001070fU,
+/*016d*/ 0x080e070fU,
+/*016e*/ 0x000e0710U,
+/*016f*/ 0x100e0710U,
+/*0170*/ 0x000e0711U,
+/*0171*/ 0x100e0711U,
+/*0172*/ 0x00040712U,
+/*0173*/ 0xffffffffU,
+/*0174*/ 0xffffffffU,
+/*0175*/ 0xffffffffU,
+/*0176*/ 0xffffffffU,
+/*0177*/ 0x080b0712U,
+/*0178*/ 0x000b0713U,
+/*0179*/ 0x100b0713U,
+/*017a*/ 0x000b0714U,
+/*017b*/ 0xffffffffU,
+/*017c*/ 0xffffffffU,
+/*017d*/ 0xffffffffU,
+/*017e*/ 0xffffffffU,
+/*017f*/ 0x000d0715U,
+/*0180*/ 0xffffffffU,
+/*0181*/ 0xffffffffU,
+/*0182*/ 0x10100715U,
+/*0183*/ 0x00080716U,
+/*0184*/ 0xffffffffU,
+/*0185*/ 0x08100716U,
+/*0186*/ 0x00100717U,
+/*0187*/ 0x10100717U,
+/*0188*/ 0x00100718U,
+/*0189*/ 0x10100718U,
+/*018a*/ 0x00030719U,
+/*018b*/ 0x08040719U,
+/*018c*/ 0x10010719U,
+/*018d*/ 0x18040719U,
+/*018e*/ 0xffffffffU,
+/*018f*/ 0xffffffffU,
+/*0190*/ 0x0001071aU,
+/*0191*/ 0x0812071aU,
+/*0192*/ 0x000a071bU,
+/*0193*/ 0x100c071bU,
+/*0194*/ 0x0012071cU,
+/*0195*/ 0x0014071dU,
+/*0196*/ 0x0012071eU,
+/*0197*/ 0x0011071fU,
+/*0198*/ 0x00110720U,
+/*0199*/ 0x00120721U,
+/*019a*/ 0x00120722U,
+/*019b*/ 0x00120723U,
+/*019c*/ 0x00120724U,
+/*019d*/ 0x00120725U,
+/*019e*/ 0x00120726U,
+/*019f*/ 0x00120727U,
+/*01a0*/ 0x00120728U,
+/*01a1*/ 0xffffffffU,
+/*01a2*/ 0xffffffffU,
+/*01a3*/ 0x00190729U,
+/*01a4*/ 0x0019072aU,
+/*01a5*/ 0x0020072bU,
+/*01a6*/ 0x0017072cU,
+/*01a7*/ 0x1808072cU,
+/*01a8*/ 0x0001072dU,
+/*01a9*/ 0x0801072dU,
+/*01aa*/ 0x0020072eU,
+/*01ab*/ 0x0008072fU,
+/*01ac*/ 0xffffffffU,
+/*01ad*/ 0x0803072fU,
+/*01ae*/ 0x00180730U,
+/*01af*/ 0x00180731U,
+/*01b0*/ 0xffffffffU,
+/*01b1*/ 0xffffffffU,
+/*01b2*/ 0xffffffffU,
+/*01b3*/ 0xffffffffU,
+/*01b4*/ 0xffffffffU,
+/*01b5*/ 0xffffffffU,
+/*01b6*/ 0xffffffffU,
+/*01b7*/ 0xffffffffU,
+/*01b8*/ 0xffffffffU,
+/*01b9*/ 0xffffffffU,
+/*01ba*/ 0xffffffffU,
+/*01bb*/ 0xffffffffU,
+/*01bc*/ 0xffffffffU,
+/*01bd*/ 0xffffffffU,
+/*01be*/ 0xffffffffU,
+/*01bf*/ 0x00100732U,
+/*01c0*/ 0x10010732U,
+/*01c1*/ 0x18010732U,
+/*01c2*/ 0x00050733U,
+/*01c3*/ 0x00200734U,
+/*01c4*/ 0x00090735U,
+/*01c5*/ 0xffffffffU,
+/*01c6*/ 0xffffffffU,
+/*01c7*/ 0x00200736U,
+/*01c8*/ 0x00040737U,
+/*01c9*/ 0x08100737U,
+/*01ca*/ 0x18060737U,
+/*01cb*/ 0x00100738U,
+/*01cc*/ 0xffffffffU,
+/*01cd*/ 0xffffffffU,
+/*01ce*/ 0xffffffffU,
+/*01cf*/ 0xffffffffU,
+/*01d0*/ 0xffffffffU,
+/*01d1*/ 0xffffffffU,
+/*01d2*/ 0xffffffffU,
+/*01d3*/ 0xffffffffU,
+/*01d4*/ 0x00200739U,
+/*01d5*/ 0x000b073aU,
+/*01d6*/ 0xffffffffU,
+/*01d7*/ 0xffffffffU,
+/*01d8*/ 0xffffffffU,
+/*01d9*/ 0xffffffffU,
+/*01da*/ 0xffffffffU,
+/*01db*/ 0xffffffffU,
+/*01dc*/ 0xffffffffU,
+/*01dd*/ 0xffffffffU,
+/*01de*/ 0x00010200U,
+/*01df*/ 0x08040200U,
+/*01e0*/ 0x10100200U,
+/*01e1*/ 0x00010201U,
+/*01e2*/ 0x08010201U,
+/*01e3*/ 0xffffffffU,
+/*01e4*/ 0xffffffffU,
+/*01e5*/ 0x10100201U,
+/*01e6*/ 0xffffffffU,
+/*01e7*/ 0xffffffffU,
+/*01e8*/ 0xffffffffU,
+/*01e9*/ 0xffffffffU,
+/*01ea*/ 0xffffffffU,
+/*01eb*/ 0xffffffffU,
+/*01ec*/ 0xffffffffU,
+/*01ed*/ 0xffffffffU,
+/*01ee*/ 0xffffffffU,
+/*01ef*/ 0x00200202U,
+/*01f0*/ 0x00100203U,
+/*01f1*/ 0x00200204U,
+/*01f2*/ 0x00100205U,
+/*01f3*/ 0x00200206U,
+/*01f4*/ 0x00100207U,
+/*01f5*/ 0x10100207U,
+/*01f6*/ 0x00200208U,
+/*01f7*/ 0x00200209U,
+/*01f8*/ 0x0020020aU,
+/*01f9*/ 0x0020020bU,
+/*01fa*/ 0x0010020cU,
+/*01fb*/ 0x0020020dU,
+/*01fc*/ 0x0020020eU,
+/*01fd*/ 0x0020020fU,
+/*01fe*/ 0x00200210U,
+/*01ff*/ 0x00100211U,
+/*0200*/ 0x00200212U,
+/*0201*/ 0x00200213U,
+/*0202*/ 0x00200214U,
+/*0203*/ 0x00200215U,
+/*0204*/ 0x00090216U,
+/*0205*/ 0x10010216U,
+/*0206*/ 0x00200217U,
+/*0207*/ 0x00050218U,
+/*0208*/ 0x08010218U,
+/*0209*/ 0x10080218U,
+/*020a*/ 0x18080218U,
+/*020b*/ 0x001c0219U,
+/*020c*/ 0x001c021aU,
+/*020d*/ 0x001c021bU,
+/*020e*/ 0x001c021cU,
+/*020f*/ 0x001c021dU,
+/*0210*/ 0x001c021eU,
+/*0211*/ 0x001c021fU,
+/*0212*/ 0x001c0220U,
+/*0213*/ 0x001c0221U,
+/*0214*/ 0x001c0222U,
+/*0215*/ 0x001c0223U,
+/*0216*/ 0x001c0224U,
+/*0217*/ 0x001c0225U,
+/*0218*/ 0x001c0226U,
+/*0219*/ 0x001c0227U,
+/*021a*/ 0x001c0228U,
+/*021b*/ 0x00010229U,
+/*021c*/ 0x08010229U,
+/*021d*/ 0x10010229U,
+/*021e*/ 0x18040229U,
+/*021f*/ 0x0008022aU,
+/*0220*/ 0x0808022aU,
+/*0221*/ 0x1008022aU,
+/*0222*/ 0x1804022aU,
+/*0223*/ 0x0006022bU,
+/*0224*/ 0xffffffffU,
+/*0225*/ 0x0807022bU,
+/*0226*/ 0x1006022bU,
+/*0227*/ 0xffffffffU,
+/*0228*/ 0x1807022bU,
+/*0229*/ 0x0006022cU,
+/*022a*/ 0xffffffffU,
+/*022b*/ 0x0807022cU,
+/*022c*/ 0x1002022cU,
+/*022d*/ 0x1801022cU,
+/*022e*/ 0xffffffffU,
+/*022f*/ 0x000a022dU,
+/*0230*/ 0x1010022dU,
+/*0231*/ 0x000a022eU,
+/*0232*/ 0x1010022eU,
+/*0233*/ 0x000a022fU,
+/*0234*/ 0x1010022fU,
+/*0235*/ 0xffffffffU,
+/*0236*/ 0x00100230U,
+/*0237*/ 0xffffffffU,
+/*0238*/ 0xffffffffU,
+/*0239*/ 0x10010230U,
+/*023a*/ 0x18010230U,
+/*023b*/ 0x00010231U,
+/*023c*/ 0x08010231U,
+/*023d*/ 0x10010231U,
+/*023e*/ 0x18010231U,
+/*023f*/ 0x00020232U,
+/*0240*/ 0x08020232U,
+/*0241*/ 0x10020232U,
+/*0242*/ 0x18020232U,
+/*0243*/ 0x00020233U,
+/*0244*/ 0x08030233U,
+/*0245*/ 0x10010233U,
+/*0246*/ 0x18010233U,
+/*0247*/ 0x00010234U,
+/*0248*/ 0x08010234U,
+/*0249*/ 0xffffffffU,
+/*024a*/ 0x10020234U,
+/*024b*/ 0x18010234U,
+/*024c*/ 0x00010235U,
+/*024d*/ 0xffffffffU,
+/*024e*/ 0x08020235U,
+/*024f*/ 0x10010235U,
+/*0250*/ 0x18010235U,
+/*0251*/ 0xffffffffU,
+/*0252*/ 0x00020236U,
+/*0253*/ 0x08010236U,
+/*0254*/ 0x10010236U,
+/*0255*/ 0xffffffffU,
+/*0256*/ 0x18020236U,
+/*0257*/ 0x00070237U,
+/*0258*/ 0x08010237U,
+/*0259*/ 0x10010237U,
+/*025a*/ 0x18010237U,
+/*025b*/ 0x00010238U,
+/*025c*/ 0x08010238U,
+/*025d*/ 0x10010238U,
+/*025e*/ 0xffffffffU,
+/*025f*/ 0x18010238U,
+/*0260*/ 0x00040239U,
+/*0261*/ 0x08040239U,
+/*0262*/ 0x10040239U,
+/*0263*/ 0x18010239U,
+/*0264*/ 0x0002023aU,
+/*0265*/ 0x0806023aU,
+/*0266*/ 0x1006023aU,
+/*0267*/ 0xffffffffU,
+/*0268*/ 0xffffffffU,
+/*0269*/ 0xffffffffU,
+/*026a*/ 0x1802023aU,
+/*026b*/ 0x0010023bU,
+/*026c*/ 0x1001023bU,
+/*026d*/ 0x1801023bU,
+/*026e*/ 0xffffffffU,
+/*026f*/ 0x0004023cU,
+/*0270*/ 0x0801023cU,
+/*0271*/ 0x1004023cU,
+/*0272*/ 0x1802023cU,
+/*0273*/ 0x0008023dU,
+/*0274*/ 0xffffffffU,
+/*0275*/ 0xffffffffU,
+/*0276*/ 0xffffffffU,
+/*0277*/ 0x080a023dU,
+/*0278*/ 0x0020023eU,
+/*0279*/ 0x0020023fU,
+/*027a*/ 0x00050240U,
+/*027b*/ 0x08010240U,
+/*027c*/ 0x10050240U,
+/*027d*/ 0x18080240U,
+/*027e*/ 0x00010241U,
+/*027f*/ 0x08080241U,
+/*0280*/ 0x10010241U,
+/*0281*/ 0x18080241U,
+/*0282*/ 0x00010242U,
+/*0283*/ 0x08040242U,
+/*0284*/ 0x10040242U,
+/*0285*/ 0x18040242U,
+/*0286*/ 0x00040243U,
+/*0287*/ 0x08040243U,
+/*0288*/ 0x10040243U,
+/*0289*/ 0x18040243U,
+/*028a*/ 0x00040244U,
+/*028b*/ 0x08040244U,
+/*028c*/ 0x10040244U,
+/*028d*/ 0x18010244U,
+/*028e*/ 0x00040245U,
+/*028f*/ 0x08040245U,
+/*0290*/ 0x10040245U,
+/*0291*/ 0x18040245U,
+/*0292*/ 0x00040246U,
+/*0293*/ 0x08040246U,
+/*0294*/ 0x10060246U,
+/*0295*/ 0x18060246U,
+/*0296*/ 0x00060247U,
+/*0297*/ 0x08060247U,
+/*0298*/ 0x10060247U,
+/*0299*/ 0x18060247U,
+/*029a*/ 0xffffffffU,
+/*029b*/ 0x00010248U,
+/*029c*/ 0x08010248U,
+/*029d*/ 0x10020248U,
+/*029e*/ 0xffffffffU,
+/*029f*/ 0xffffffffU,
+/*02a0*/ 0xffffffffU,
+/*02a1*/ 0xffffffffU,
+/*02a2*/ 0xffffffffU,
+/*02a3*/ 0xffffffffU,
+/*02a4*/ 0xffffffffU,
+/*02a5*/ 0xffffffffU,
+/*02a6*/ 0x18040248U,
+/*02a7*/ 0x00040249U,
+/*02a8*/ 0x08010249U,
+/*02a9*/ 0x10010249U,
+/*02aa*/ 0xffffffffU,
+/*02ab*/ 0x18010249U,
+/*02ac*/ 0x0001024aU,
+/*02ad*/ 0xffffffffU,
+/*02ae*/ 0x0801024aU,
+/*02af*/ 0x1001024aU,
+/*02b0*/ 0x1801024aU,
+/*02b1*/ 0x0004024bU,
+/*02b2*/ 0x0804024bU,
+/*02b3*/ 0x100a024bU,
+/*02b4*/ 0x0020024cU,
+/*02b5*/ 0x0004024dU,
+/*02b6*/ 0x0808024dU,
+/*02b7*/ 0xffffffffU,
+/*02b8*/ 0xffffffffU,
+/*02b9*/ 0xffffffffU,
+/*02ba*/ 0xffffffffU,
+/*02bb*/ 0xffffffffU,
+/*02bc*/ 0xffffffffU,
+/*02bd*/ 0x1002024dU,
+/*02be*/ 0x1802024dU,
+/*02bf*/ 0x0020024eU,
+/*02c0*/ 0x0002024fU,
+/*02c1*/ 0x0810024fU,
+/*02c2*/ 0x00100250U,
+/*02c3*/ 0x10040250U,
+/*02c4*/ 0x18040250U,
+/*02c5*/ 0x00050251U,
+/*02c6*/ 0x08050251U,
+/*02c7*/ 0xffffffffU,
+/*02c8*/ 0xffffffffU,
+/*02c9*/ 0xffffffffU,
+/*02ca*/ 0xffffffffU,
+/*02cb*/ 0x10010251U,
+/*02cc*/ 0x18010251U,
+/*02cd*/ 0x00070252U,
+/*02ce*/ 0x08070252U,
+/*02cf*/ 0x10070252U,
+/*02d0*/ 0x18070252U,
+/*02d1*/ 0x00070253U,
+/*02d2*/ 0x08070253U,
+/*02d3*/ 0x10070253U,
+/*02d4*/ 0x18070253U,
+/*02d5*/ 0x00070254U,
+/*02d6*/ 0x08070254U,
+/*02d7*/ 0x10070254U,
+/*02d8*/ 0xffffffffU,
+/*02d9*/ 0xffffffffU,
+/*02da*/ 0xffffffffU,
+/*02db*/ 0xffffffffU,
+/*02dc*/ 0xffffffffU,
+/*02dd*/ 0xffffffffU,
+/*02de*/ 0x18030254U,
+/*02df*/ 0x00010255U,
+/*02e0*/ 0x08020255U,
+/*02e1*/ 0x10010255U,
+/*02e2*/ 0x18040255U,
+/*02e3*/ 0x00020256U,
+/*02e4*/ 0x08010256U,
+/*02e5*/ 0x10010256U,
+/*02e6*/ 0xffffffffU,
+/*02e7*/ 0x18010256U,
+/*02e8*/ 0x00040257U,
+/*02e9*/ 0x08080257U,
+/*02ea*/ 0x100a0257U,
+/*02eb*/ 0x000a0258U,
+/*02ec*/ 0x100a0258U,
+/*02ed*/ 0x000a0259U,
+/*02ee*/ 0x100a0259U,
+/*02ef*/ 0x000a025aU,
+/*02f0*/ 0x0020025bU,
+/*02f1*/ 0x0020025cU,
+/*02f2*/ 0x0001025dU,
+/*02f3*/ 0xffffffffU,
+/*02f4*/ 0xffffffffU,
+/*02f5*/ 0xffffffffU,
+/*02f6*/ 0x0802025dU,
+/*02f7*/ 0x1002025dU,
+/*02f8*/ 0x0010025eU,
+/*02f9*/ 0x1005025eU,
+/*02fa*/ 0x1806025eU,
+/*02fb*/ 0x0005025fU,
+/*02fc*/ 0x0805025fU,
+/*02fd*/ 0x100e025fU,
+/*02fe*/ 0x00050260U,
+/*02ff*/ 0x080e0260U,
+/*0300*/ 0x18050260U,
+/*0301*/ 0x000e0261U,
+/*0302*/ 0x10050261U,
+/*0303*/ 0x18010261U,
+/*0304*/ 0x00050262U,
+/*0305*/ 0x08050262U,
+/*0306*/ 0x100a0262U,
+/*0307*/ 0x000a0263U,
+/*0308*/ 0x10050263U,
+/*0309*/ 0x18050263U,
+/*030a*/ 0x000a0264U,
+/*030b*/ 0x100a0264U,
+/*030c*/ 0x00050265U,
+/*030d*/ 0x08050265U,
+/*030e*/ 0x100a0265U,
+/*030f*/ 0x000a0266U,
+/*0310*/ 0xffffffffU,
+/*0311*/ 0xffffffffU,
+/*0312*/ 0xffffffffU,
+/*0313*/ 0xffffffffU,
+/*0314*/ 0xffffffffU,
+/*0315*/ 0xffffffffU,
+/*0316*/ 0x10070266U,
+/*0317*/ 0x18070266U,
+/*0318*/ 0x00040267U,
+/*0319*/ 0x08040267U,
+/*031a*/ 0xffffffffU,
+/*031b*/ 0xffffffffU,
+/*031c*/ 0xffffffffU,
+/*031d*/ 0x10040267U,
+/*031e*/ 0x18080267U,
+/*031f*/ 0x00080268U,
+/*0320*/ 0x08040268U,
+/*0321*/ 0xffffffffU,
+/*0322*/ 0xffffffffU,
+/*0323*/ 0xffffffffU,
+/*0324*/ 0x10040268U,
+/*0325*/ 0xffffffffU,
+/*0326*/ 0xffffffffU,
+/*0327*/ 0xffffffffU,
+/*0328*/ 0x18040268U,
+/*0329*/ 0xffffffffU,
+/*032a*/ 0xffffffffU,
+/*032b*/ 0xffffffffU,
+/*032c*/ 0x00040269U,
+/*032d*/ 0x08050269U,
+/*032e*/ 0x10070269U,
+/*032f*/ 0x18080269U,
+/*0330*/ 0x0010026aU,
+/*0331*/ 0x1008026aU,
+/*0332*/ 0x0010026bU,
+/*0333*/ 0x1008026bU,
+/*0334*/ 0x0010026cU,
+/*0335*/ 0x1008026cU,
+/*0336*/ 0x1808026cU,
+/*0337*/ 0x0001026dU,
+/*0338*/ 0x0801026dU,
+/*0339*/ 0x1006026dU,
+/*033a*/ 0x1806026dU,
+/*033b*/ 0x0006026eU,
+/*033c*/ 0xffffffffU,
+/*033d*/ 0x0801026eU,
+/*033e*/ 0x1003026eU,
+/*033f*/ 0xffffffffU,
+/*0340*/ 0xffffffffU,
+/*0341*/ 0xffffffffU,
+/*0342*/ 0x000a026fU,
+/*0343*/ 0x100a026fU,
+/*0344*/ 0x00040270U,
+/*0345*/ 0x08010270U,
+/*0346*/ 0x10040270U,
+/*0347*/ 0xffffffffU,
+/*0348*/ 0xffffffffU,
+/*0349*/ 0xffffffffU,
+/*034a*/ 0xffffffffU,
+/*034b*/ 0xffffffffU,
+/*034c*/ 0xffffffffU,
+/*034d*/ 0x18070270U,
+/*034e*/ 0x00070271U,
+/*034f*/ 0x08050271U,
+/*0350*/ 0x10050271U,
+/*0351*/ 0xffffffffU,
+/*0352*/ 0xffffffffU,
+/*0353*/ 0xffffffffU,
+/*0354*/ 0x18040271U,
+/*0355*/ 0x00010272U,
+/*0356*/ 0x08010272U,
+/*0357*/ 0x10020272U,
+/*0358*/ 0x18080272U,
+/*0359*/ 0x00200273U,
+/*035a*/ 0x00200274U,
+/*035b*/ 0x00100275U,
+/*035c*/ 0xffffffffU,
+/*035d*/ 0xffffffffU,
+/*035e*/ 0xffffffffU,
+/*035f*/ 0x10020275U,
+/*0360*/ 0x18010275U,
+/*0361*/ 0xffffffffU,
+/*0362*/ 0x00020276U,
+/*0363*/ 0x08080276U,
+/*0364*/ 0x10080276U,
+/*0365*/ 0x18080276U,
+/*0366*/ 0x00080277U,
+/*0367*/ 0x08080277U,
+/*0368*/ 0x10080277U,
+/*0369*/ 0xffffffffU,
+/*036a*/ 0x18080277U,
+/*036b*/ 0x00080278U,
+/*036c*/ 0x08080278U,
+/*036d*/ 0x10080278U,
+/*036e*/ 0x18080278U,
+/*036f*/ 0x00080279U,
+/*0370*/ 0xffffffffU,
+/*0371*/ 0x08080279U,
+/*0372*/ 0x10080279U,
+/*0373*/ 0x18080279U,
+/*0374*/ 0x0008027aU,
+/*0375*/ 0x0808027aU,
+/*0376*/ 0x1008027aU,
+/*0377*/ 0xffffffffU,
+/*0378*/ 0x1808027aU,
+/*0379*/ 0x0008027bU,
+/*037a*/ 0x0808027bU,
+/*037b*/ 0x1008027bU,
+/*037c*/ 0x1808027bU,
+/*037d*/ 0x0008027cU,
+/*037e*/ 0x0808027cU,
+/*037f*/ 0xffffffffU,
+/*0380*/ 0x1008027cU,
+/*0381*/ 0x1808027cU,
+/*0382*/ 0x0008027dU,
+/*0383*/ 0x0808027dU,
+/*0384*/ 0x1008027dU,
+/*0385*/ 0x1808027dU,
+/*0386*/ 0xffffffffU,
+/*0387*/ 0x0008027eU,
+/*0388*/ 0x0808027eU,
+/*0389*/ 0x1008027eU,
+/*038a*/ 0x1808027eU,
+/*038b*/ 0x0008027fU,
+/*038c*/ 0x0808027fU,
+/*038d*/ 0xffffffffU,
+/*038e*/ 0x1008027fU,
+/*038f*/ 0x1808027fU,
+/*0390*/ 0x00080280U,
+/*0391*/ 0x08080280U,
+/*0392*/ 0x10080280U,
+/*0393*/ 0x18080280U,
+/*0394*/ 0x00080281U,
+/*0395*/ 0xffffffffU,
+/*0396*/ 0x08080281U,
+/*0397*/ 0x10080281U,
+/*0398*/ 0x18080281U,
+/*0399*/ 0x00080282U,
+/*039a*/ 0x08080282U,
+/*039b*/ 0x10080282U,
+/*039c*/ 0xffffffffU,
+/*039d*/ 0x18080282U,
+/*039e*/ 0x00080283U,
+/*039f*/ 0x08080283U,
+/*03a0*/ 0x10080283U,
+/*03a1*/ 0x18080283U,
+/*03a2*/ 0x00080284U,
+/*03a3*/ 0xffffffffU,
+/*03a4*/ 0x08080284U,
+/*03a5*/ 0x10080284U,
+/*03a6*/ 0x18080284U,
+/*03a7*/ 0x00080285U,
+/*03a8*/ 0x08080285U,
+/*03a9*/ 0x10080285U,
+/*03aa*/ 0x18080285U,
+/*03ab*/ 0xffffffffU,
+/*03ac*/ 0x00080286U,
+/*03ad*/ 0x08080286U,
+/*03ae*/ 0x10080286U,
+/*03af*/ 0x18080286U,
+/*03b0*/ 0x00080287U,
+/*03b1*/ 0x08080287U,
+/*03b2*/ 0xffffffffU,
+/*03b3*/ 0x10080287U,
+/*03b4*/ 0x18080287U,
+/*03b5*/ 0x00080288U,
+/*03b6*/ 0x08080288U,
+/*03b7*/ 0x10080288U,
+/*03b8*/ 0x18080288U,
+/*03b9*/ 0xffffffffU,
+/*03ba*/ 0x00080289U,
+/*03bb*/ 0x08020289U,
+/*03bc*/ 0x10030289U,
+/*03bd*/ 0x000a028aU,
+/*03be*/ 0x100a028aU,
+/*03bf*/ 0x000a028bU,
+/*03c0*/ 0x1005028bU,
+/*03c1*/ 0x1804028bU,
+/*03c2*/ 0x0008028cU,
+/*03c3*/ 0x0808028cU,
+/*03c4*/ 0x1006028cU,
+/*03c5*/ 0x1806028cU,
+/*03c6*/ 0x0011028dU,
+/*03c7*/ 0x1808028dU,
+/*03c8*/ 0x0004028eU,
+/*03c9*/ 0x0806028eU,
+/*03ca*/ 0xffffffffU,
+/*03cb*/ 0x1006028eU,
+/*03cc*/ 0x1808028eU,
+/*03cd*/ 0xffffffffU,
+/*03ce*/ 0x0004028fU,
+/*03cf*/ 0x0808028fU,
+/*03d0*/ 0x1008028fU,
+/*03d1*/ 0x1806028fU,
+/*03d2*/ 0x00060290U,
+/*03d3*/ 0x08110290U,
+/*03d4*/ 0x00080291U,
+/*03d5*/ 0x08040291U,
+/*03d6*/ 0x10060291U,
+/*03d7*/ 0xffffffffU,
+/*03d8*/ 0x18060291U,
+/*03d9*/ 0x00080292U,
+/*03da*/ 0xffffffffU,
+/*03db*/ 0x08040292U,
+/*03dc*/ 0x10080292U,
+/*03dd*/ 0x18080292U,
+/*03de*/ 0x00060293U,
+/*03df*/ 0x08060293U,
+/*03e0*/ 0x00110294U,
+/*03e1*/ 0x18080294U,
+/*03e2*/ 0x00040295U,
+/*03e3*/ 0x08060295U,
+/*03e4*/ 0xffffffffU,
+/*03e5*/ 0x10060295U,
+/*03e6*/ 0x18080295U,
+/*03e7*/ 0xffffffffU,
+/*03e8*/ 0x00040296U,
+/*03e9*/ 0x08040296U,
+/*03ea*/ 0x10040296U,
+/*03eb*/ 0x18040296U,
+/*03ec*/ 0x00040297U,
+/*03ed*/ 0x08040297U,
+/*03ee*/ 0x10040297U,
+/*03ef*/ 0x18040297U,
+/*03f0*/ 0x00040298U,
+/*03f1*/ 0x08040298U,
+/*03f2*/ 0x10040298U,
+/*03f3*/ 0x18040298U,
+/*03f4*/ 0x00040299U,
+/*03f5*/ 0x08040299U,
+/*03f6*/ 0x10040299U,
+/*03f7*/ 0x18040299U,
+/*03f8*/ 0x0004029aU,
+/*03f9*/ 0x0804029aU,
+/*03fa*/ 0x1004029aU,
+/*03fb*/ 0x1804029aU,
+/*03fc*/ 0x0011029bU,
+/*03fd*/ 0x0010029cU,
+/*03fe*/ 0x0011029dU,
+/*03ff*/ 0x0020029eU,
+/*0400*/ 0x0020029fU,
+/*0401*/ 0x002002a0U,
+/*0402*/ 0x002002a1U,
+/*0403*/ 0x002002a2U,
+/*0404*/ 0x002002a3U,
+/*0405*/ 0x002002a4U,
+/*0406*/ 0x002002a5U,
+/*0407*/ 0x002002a6U,
+/*0408*/ 0x000202a7U,
+/*0409*/ 0x080502a7U,
+/*040a*/ 0x100502a7U,
+/*040b*/ 0xffffffffU,
+/*040c*/ 0xffffffffU,
+/*040d*/ 0xffffffffU,
+/*040e*/ 0xffffffffU,
+/*040f*/ 0xffffffffU,
+/*0410*/ 0xffffffffU,
+/*0411*/ 0xffffffffU,
+/*0412*/ 0xffffffffU,
+/*0413*/ 0xffffffffU,
+/*0414*/ 0xffffffffU,
+/*0415*/ 0xffffffffU,
+/*0416*/ 0xffffffffU,
+/*0417*/ 0xffffffffU,
+/*0418*/ 0xffffffffU,
+/*0419*/ 0xffffffffU,
+/*041a*/ 0xffffffffU,
+/*041b*/ 0xffffffffU,
+/*041c*/ 0xffffffffU,
+/*041d*/ 0xffffffffU,
+/*041e*/ 0xffffffffU,
+/*041f*/ 0xffffffffU,
+/*0420*/ 0xffffffffU,
+/*0421*/ 0xffffffffU,
+/*0422*/ 0xffffffffU,
+/*0423*/ 0xffffffffU,
+/*0424*/ 0xffffffffU,
+/*0425*/ 0xffffffffU,
+/*0426*/ 0xffffffffU,
+/*0427*/ 0x180102a7U,
+/*0428*/ 0x000402a8U,
+/*0429*/ 0x081002a8U,
+/*042a*/ 0x002002a9U,
+/*042b*/ 0x001002aaU,
+/*042c*/ 0x002002abU,
+/*042d*/ 0x001002acU,
+/*042e*/ 0x002002adU,
+/*042f*/ 0x000702aeU,
+/*0430*/ 0x080102aeU,
+/*0431*/ 0x100202aeU,
+/*0432*/ 0x180602aeU,
+/*0433*/ 0x000102afU,
+/*0434*/ 0x080102afU,
+/*0435*/ 0x002002b0U,
+/*0436*/ 0x000202b1U,
+/*0437*/ 0x002002b2U,
+/*0438*/ 0x002002b3U,
+/*0439*/ 0xffffffffU,
+/*043a*/ 0xffffffffU,
+/*043b*/ 0xffffffffU,
+/*043c*/ 0xffffffffU,
+/*043d*/ 0xffffffffU,
+/*043e*/ 0xffffffffU,
+/*043f*/ 0xffffffffU,
+/*0440*/ 0xffffffffU,
+/*0441*/ 0xffffffffU,
+/*0442*/ 0xffffffffU,
+/*0443*/ 0xffffffffU,
+/*0444*/ 0xffffffffU,
+/*0445*/ 0xffffffffU,
+/*0446*/ 0xffffffffU,
+/*0447*/ 0xffffffffU,
+/*0448*/ 0xffffffffU,
+/*0449*/ 0xffffffffU,
+/*044a*/ 0xffffffffU,
+/*044b*/ 0xffffffffU,
+/*044c*/ 0xffffffffU,
+/*044d*/ 0xffffffffU,
+/*044e*/ 0xffffffffU,
+/*044f*/ 0xffffffffU,
+/*0450*/ 0xffffffffU,
+/*0451*/ 0xffffffffU,
+/*0452*/ 0xffffffffU,
+/*0453*/ 0xffffffffU,
+/*0454*/ 0xffffffffU,
+/*0455*/ 0xffffffffU,
+/*0456*/ 0xffffffffU,
+/*0457*/ 0xffffffffU,
+/*0458*/ 0xffffffffU,
+/*0459*/ 0xffffffffU,
+/*045a*/ 0xffffffffU,
+/*045b*/ 0xffffffffU,
+/*045c*/ 0xffffffffU,
+/*045d*/ 0xffffffffU,
+/*045e*/ 0xffffffffU,
+/*045f*/ 0x000402b4U,
+/*0460*/ 0xffffffffU,
+/*0461*/ 0xffffffffU,
+/*0462*/ 0xffffffffU,
+/*0463*/ 0xffffffffU,
+/*0464*/ 0xffffffffU,
+/*0465*/ 0xffffffffU,
+/*0466*/ 0xffffffffU,
+/*0467*/ 0xffffffffU,
+/*0468*/ 0xffffffffU,
+/*0469*/ 0xffffffffU,
+/*046a*/ 0xffffffffU,
+/*046b*/ 0xffffffffU,
+/*046c*/ 0xffffffffU,
+/*046d*/ 0xffffffffU,
+/*046e*/ 0xffffffffU,
+/*046f*/ 0xffffffffU,
+/*0470*/ 0xffffffffU,
+/*0471*/ 0xffffffffU,
+/*0472*/ 0xffffffffU,
+/*0473*/ 0xffffffffU,
+/*0474*/ 0xffffffffU,
+/*0475*/ 0xffffffffU,
+/*0476*/ 0xffffffffU,
+/*0477*/ 0xffffffffU,
+/*0478*/ 0xffffffffU,
+/*0479*/ 0xffffffffU,
+/*047a*/ 0xffffffffU,
+/*047b*/ 0xffffffffU,
+/*047c*/ 0xffffffffU,
+/*047d*/ 0xffffffffU,
+/*047e*/ 0xffffffffU,
+/*047f*/ 0xffffffffU,
+/*0480*/ 0xffffffffU,
+/*0481*/ 0xffffffffU,
+/*0482*/ 0xffffffffU,
+/*0483*/ 0xffffffffU,
+/*0484*/ 0xffffffffU,
+/*0485*/ 0xffffffffU,
+/*0486*/ 0xffffffffU,
+/*0487*/ 0xffffffffU,
+/*0488*/ 0xffffffffU,
+/*0489*/ 0xffffffffU,
+/*048a*/ 0xffffffffU,
+/*048b*/ 0xffffffffU,
+/*048c*/ 0xffffffffU,
+/*048d*/ 0xffffffffU,
+/*048e*/ 0xffffffffU,
+/*048f*/ 0xffffffffU,
+/*0490*/ 0xffffffffU,
+/*0491*/ 0xffffffffU,
+/*0492*/ 0xffffffffU,
+/*0493*/ 0xffffffffU,
+/*0494*/ 0xffffffffU,
+	 },
+	{
+/*0000*/ 0x00200800U,
+/*0001*/ 0x00040801U,
+/*0002*/ 0x080b0801U,
+/*0003*/ 0xffffffffU,
+/*0004*/ 0xffffffffU,
+/*0005*/ 0x18010801U,
+/*0006*/ 0x00050802U,
+/*0007*/ 0x08050802U,
+/*0008*/ 0x10050802U,
+/*0009*/ 0x18050802U,
+/*000a*/ 0x00050803U,
+/*000b*/ 0x08050803U,
+/*000c*/ 0x10050803U,
+/*000d*/ 0x18050803U,
+/*000e*/ 0x00050804U,
+/*000f*/ 0x08040804U,
+/*0010*/ 0x10030804U,
+/*0011*/ 0x00180805U,
+/*0012*/ 0x18030805U,
+/*0013*/ 0x00180806U,
+/*0014*/ 0x18020806U,
+/*0015*/ 0x00010807U,
+/*0016*/ 0x08020807U,
+/*0017*/ 0x10010807U,
+/*0018*/ 0x18010807U,
+/*0019*/ 0x00020808U,
+/*001a*/ 0x08040808U,
+/*001b*/ 0x10040808U,
+/*001c*/ 0x18040808U,
+/*001d*/ 0x000a0809U,
+/*001e*/ 0x10040809U,
+/*001f*/ 0xffffffffU,
+/*0020*/ 0xffffffffU,
+/*0021*/ 0x18070809U,
+/*0022*/ 0xffffffffU,
+/*0023*/ 0xffffffffU,
+/*0024*/ 0xffffffffU,
+/*0025*/ 0xffffffffU,
+/*0026*/ 0xffffffffU,
+/*0027*/ 0xffffffffU,
+/*0028*/ 0x000a080aU,
+/*0029*/ 0x1005080aU,
+/*002a*/ 0x1801080aU,
+/*002b*/ 0x0001080bU,
+/*002c*/ 0x0802080bU,
+/*002d*/ 0x1009080bU,
+/*002e*/ 0x0009080cU,
+/*002f*/ 0x1002080cU,
+/*0030*/ 0x0020080dU,
+/*0031*/ 0xffffffffU,
+/*0032*/ 0x0001080eU,
+/*0033*/ 0xffffffffU,
+/*0034*/ 0xffffffffU,
+/*0035*/ 0xffffffffU,
+/*0036*/ 0xffffffffU,
+/*0037*/ 0x0020080fU,
+/*0038*/ 0x00200810U,
+/*0039*/ 0x00200811U,
+/*003a*/ 0x00200812U,
+/*003b*/ 0x00030813U,
+/*003c*/ 0x08010813U,
+/*003d*/ 0x10030813U,
+/*003e*/ 0x18030813U,
+/*003f*/ 0x00040814U,
+/*0040*/ 0x08040814U,
+/*0041*/ 0x10040814U,
+/*0042*/ 0x18040814U,
+/*0043*/ 0x00010815U,
+/*0044*/ 0x08010815U,
+/*0045*/ 0x10060815U,
+/*0046*/ 0x18040815U,
+/*0047*/ 0xffffffffU,
+/*0048*/ 0x00060816U,
+/*0049*/ 0x08040816U,
+/*004a*/ 0x10060816U,
+/*004b*/ 0x18040816U,
+/*004c*/ 0x00020817U,
+/*004d*/ 0x08050817U,
+/*004e*/ 0x10080817U,
+/*004f*/ 0x00200818U,
+/*0050*/ 0x00060819U,
+/*0051*/ 0x08030819U,
+/*0052*/ 0x100b0819U,
+/*0053*/ 0x0004081aU,
+/*0054*/ 0x0804081aU,
+/*0055*/ 0x1004081aU,
+/*0056*/ 0xffffffffU,
+/*0057*/ 0x1801081aU,
+/*0058*/ 0x0009081bU,
+/*0059*/ 0x0020081cU,
+/*005a*/ 0x0020081dU,
+/*005b*/ 0x0020081eU,
+/*005c*/ 0x0020081fU,
+/*005d*/ 0x00100820U,
+/*005e*/ 0xffffffffU,
+/*005f*/ 0x10010820U,
+/*0060*/ 0x18060820U,
+/*0061*/ 0x00080821U,
+/*0062*/ 0x00200822U,
+/*0063*/ 0xffffffffU,
+/*0064*/ 0x000a0823U,
+/*0065*/ 0x10060823U,
+/*0066*/ 0x18070823U,
+/*0067*/ 0x00080824U,
+/*0068*/ 0x08080824U,
+/*0069*/ 0x100a0824U,
+/*006a*/ 0x00070825U,
+/*006b*/ 0x08080825U,
+/*006c*/ 0x10080825U,
+/*006d*/ 0x18030825U,
+/*006e*/ 0x000a0826U,
+/*006f*/ 0x100a0826U,
+/*0070*/ 0x00110827U,
+/*0071*/ 0x00090828U,
+/*0072*/ 0x10090828U,
+/*0073*/ 0x00100829U,
+/*0074*/ 0x100e0829U,
+/*0075*/ 0x000e082aU,
+/*0076*/ 0x100c082aU,
+/*0077*/ 0x000a082bU,
+/*0078*/ 0x100a082bU,
+/*0079*/ 0x0002082cU,
+/*007a*/ 0x0020082dU,
+/*007b*/ 0x000b082eU,
+/*007c*/ 0x100b082eU,
+/*007d*/ 0x0020082fU,
+/*007e*/ 0x00120830U,
+/*007f*/ 0x00200831U,
+/*0080*/ 0x00200832U,
+/*0081*/ 0xffffffffU,
+/*0082*/ 0xffffffffU,
+/*0083*/ 0x00010833U,
+/*0084*/ 0x08010833U,
+/*0085*/ 0x10080833U,
+/*0086*/ 0x000c0834U,
+/*0087*/ 0x100c0834U,
+/*0088*/ 0x000c0835U,
+/*0089*/ 0x100c0835U,
+/*008a*/ 0x000c0836U,
+/*008b*/ 0x100c0836U,
+/*008c*/ 0x000c0837U,
+/*008d*/ 0x100c0837U,
+/*008e*/ 0x000c0838U,
+/*008f*/ 0x100c0838U,
+/*0090*/ 0x000c0839U,
+/*0091*/ 0x100b0839U,
+/*0092*/ 0xffffffffU,
+/*0093*/ 0xffffffffU,
+/*0094*/ 0x000b083aU,
+/*0095*/ 0x100b083aU,
+/*0096*/ 0x000b083bU,
+/*0097*/ 0x100b083bU,
+/*0098*/ 0x000b083cU,
+/*0099*/ 0x100b083cU,
+/*009a*/ 0x000b083dU,
+/*009b*/ 0x100b083dU,
+/*009c*/ 0x000b083eU,
+/*009d*/ 0x100a083eU,
+/*009e*/ 0xffffffffU,
+/*009f*/ 0x000a083fU,
+/*00a0*/ 0x100a083fU,
+/*00a1*/ 0x000a0840U,
+/*00a2*/ 0x100a0840U,
+/*00a3*/ 0x000a0841U,
+/*00a4*/ 0x100a0841U,
+/*00a5*/ 0x000a0842U,
+/*00a6*/ 0x100a0842U,
+/*00a7*/ 0x000a0843U,
+/*00a8*/ 0x100a0843U,
+/*00a9*/ 0x000a0844U,
+/*00aa*/ 0x100a0844U,
+/*00ab*/ 0x000a0845U,
+/*00ac*/ 0x100a0845U,
+/*00ad*/ 0x000a0846U,
+/*00ae*/ 0x100a0846U,
+/*00af*/ 0x000a0847U,
+/*00b0*/ 0x100a0847U,
+/*00b1*/ 0x000a0848U,
+/*00b2*/ 0x100a0848U,
+/*00b3*/ 0x000a0849U,
+/*00b4*/ 0x100a0849U,
+/*00b5*/ 0x000a084aU,
+/*00b6*/ 0x100a084aU,
+/*00b7*/ 0x000a084bU,
+/*00b8*/ 0x100a084bU,
+/*00b9*/ 0x000a084cU,
+/*00ba*/ 0x100a084cU,
+/*00bb*/ 0x0004084dU,
+/*00bc*/ 0x0803084dU,
+/*00bd*/ 0x100a084dU,
+/*00be*/ 0x000a084eU,
+/*00bf*/ 0x1001084eU,
+/*00c0*/ 0x000a084fU,
+/*00c1*/ 0x1004084fU,
+/*00c2*/ 0x000b0850U,
+/*00c3*/ 0x100a0850U,
+/*00c4*/ 0xffffffffU,
+/*00c5*/ 0x00080851U,
+/*00c6*/ 0x08080851U,
+/*00c7*/ 0x10080851U,
+/*00c8*/ 0x18080851U,
+/*00c9*/ 0x00080852U,
+/*00ca*/ 0xffffffffU,
+/*00cb*/ 0x08080852U,
+/*00cc*/ 0x10010852U,
+/*00cd*/ 0x18080852U,
+/*00ce*/ 0x00080853U,
+/*00cf*/ 0x08020853U,
+/*00d0*/ 0x10020853U,
+/*00d1*/ 0x18040853U,
+/*00d2*/ 0x00040854U,
+/*00d3*/ 0xffffffffU,
+/*00d4*/ 0x08040854U,
+/*00d5*/ 0x100a0854U,
+/*00d6*/ 0x00060855U,
+/*00d7*/ 0x08080855U,
+/*00d8*/ 0xffffffffU,
+/*00d9*/ 0x10040855U,
+/*00da*/ 0x18040855U,
+/*00db*/ 0x00050856U,
+/*00dc*/ 0x08040856U,
+/*00dd*/ 0x10050856U,
+/*00de*/ 0x000a0857U,
+/*00df*/ 0x100a0857U,
+/*00e0*/ 0x00080858U,
+/*00e1*/ 0xffffffffU,
+/*00e2*/ 0x08040858U,
+/*00e3*/ 0xffffffffU,
+/*00e4*/ 0xffffffffU,
+/*00e5*/ 0x00050a00U,
+/*00e6*/ 0x08050a00U,
+/*00e7*/ 0x10050a00U,
+/*00e8*/ 0x18050a00U,
+/*00e9*/ 0x00050a01U,
+/*00ea*/ 0x08050a01U,
+/*00eb*/ 0x100b0a01U,
+/*00ec*/ 0x00010a02U,
+/*00ed*/ 0x08030a02U,
+/*00ee*/ 0x00200a03U,
+/*00ef*/ 0xffffffffU,
+/*00f0*/ 0x00030a04U,
+/*00f1*/ 0x080a0a04U,
+/*00f2*/ 0xffffffffU,
+/*00f3*/ 0xffffffffU,
+/*00f4*/ 0x18030a04U,
+/*00f5*/ 0x00030a05U,
+/*00f6*/ 0x08010a05U,
+/*00f7*/ 0x10010a05U,
+/*00f8*/ 0x18060a05U,
+/*00f9*/ 0xffffffffU,
+/*00fa*/ 0xffffffffU,
+/*00fb*/ 0xffffffffU,
+/*00fc*/ 0x00020a06U,
+/*00fd*/ 0x08030a06U,
+/*00fe*/ 0x10010a06U,
+/*00ff*/ 0x000f0a07U,
+/*0100*/ 0x00200a08U,
+/*0101*/ 0x00200a09U,
+/*0102*/ 0x000b0a0aU,
+/*0103*/ 0x100b0a0aU,
+/*0104*/ 0x000b0a0bU,
+/*0105*/ 0xffffffffU,
+/*0106*/ 0xffffffffU,
+/*0107*/ 0x00180a0cU,
+/*0108*/ 0x00180a0dU,
+/*0109*/ 0x00180a0eU,
+/*010a*/ 0x00180a0fU,
+/*010b*/ 0x18040a0fU,
+/*010c*/ 0x00020a10U,
+/*010d*/ 0x08020a10U,
+/*010e*/ 0x10040a10U,
+/*010f*/ 0x18040a10U,
+/*0110*/ 0x00010a11U,
+/*0111*/ 0x08010a11U,
+/*0112*/ 0x10010a11U,
+/*0113*/ 0x18030a11U,
+/*0114*/ 0x00200a12U,
+/*0115*/ 0x00200a13U,
+/*0116*/ 0xffffffffU,
+/*0117*/ 0x00140a14U,
+/*0118*/ 0x00140a15U,
+/*0119*/ 0x00140a16U,
+/*011a*/ 0x00140a17U,
+/*011b*/ 0x00140a18U,
+/*011c*/ 0x00140a19U,
+/*011d*/ 0x00140a1aU,
+/*011e*/ 0x00140a1bU,
+/*011f*/ 0x001e0a1cU,
+/*0120*/ 0x000a0a1dU,
+/*0121*/ 0x10060a1dU,
+/*0122*/ 0x18060a1dU,
+/*0123*/ 0x00060a1eU,
+/*0124*/ 0xffffffffU,
+/*0125*/ 0x08060a1eU,
+/*0126*/ 0x00080a1fU,
+/*0127*/ 0x080b0a1fU,
+/*0128*/ 0x000b0a20U,
+/*0129*/ 0x100b0a20U,
+/*012a*/ 0x000b0a21U,
+/*012b*/ 0x100b0a21U,
+/*012c*/ 0x000b0a22U,
+/*012d*/ 0x10040a22U,
+/*012e*/ 0x000a0a23U,
+/*012f*/ 0x10060a23U,
+/*0130*/ 0x18080a23U,
+/*0131*/ 0xffffffffU,
+/*0132*/ 0x00040a24U,
+/*0133*/ 0xffffffffU,
+/*0134*/ 0xffffffffU,
+/*0135*/ 0x00010b80U,
+/*0136*/ 0x08020b80U,
+/*0137*/ 0x10050b80U,
+/*0138*/ 0x18050b80U,
+/*0139*/ 0x00050b81U,
+/*013a*/ 0x08050b81U,
+/*013b*/ 0x100b0b81U,
+/*013c*/ 0x00050b82U,
+/*013d*/ 0x08010b82U,
+/*013e*/ 0x10010b82U,
+/*013f*/ 0xffffffffU,
+/*0140*/ 0x18010b82U,
+/*0141*/ 0x00010b83U,
+/*0142*/ 0x08040b83U,
+/*0143*/ 0x100b0b83U,
+/*0144*/ 0x000b0b84U,
+/*0145*/ 0xffffffffU,
+/*0146*/ 0x10040b84U,
+/*0147*/ 0x000b0b85U,
+/*0148*/ 0x10040b85U,
+/*0149*/ 0x18010b85U,
+/*014a*/ 0x00010b86U,
+/*014b*/ 0x08010b86U,
+/*014c*/ 0x00200b87U,
+/*014d*/ 0x00200b88U,
+/*014e*/ 0x00080b89U,
+/*014f*/ 0x080a0b89U,
+/*0150*/ 0x18050b89U,
+/*0151*/ 0x000a0b8aU,
+/*0152*/ 0x10030b8aU,
+/*0153*/ 0x18030b8aU,
+/*0154*/ 0x00010b8bU,
+/*0155*/ 0x08020b8bU,
+/*0156*/ 0x10010b8bU,
+/*0157*/ 0x18010b8bU,
+/*0158*/ 0x00010b8cU,
+/*0159*/ 0x08030b8cU,
+/*015a*/ 0xffffffffU,
+/*015b*/ 0x10040b8cU,
+/*015c*/ 0x18040b8cU,
+/*015d*/ 0x00040b8dU,
+/*015e*/ 0x08040b8dU,
+/*015f*/ 0xffffffffU,
+/*0160*/ 0xffffffffU,
+/*0161*/ 0xffffffffU,
+/*0162*/ 0xffffffffU,
+/*0163*/ 0xffffffffU,
+/*0164*/ 0xffffffffU,
+/*0165*/ 0xffffffffU,
+/*0166*/ 0xffffffffU,
+/*0167*/ 0xffffffffU,
+/*0168*/ 0x000d0b8eU,
+/*0169*/ 0x100d0b8eU,
+/*016a*/ 0x000d0b8fU,
+/*016b*/ 0x00050b90U,
+/*016c*/ 0x00010b91U,
+/*016d*/ 0x080e0b91U,
+/*016e*/ 0x000e0b92U,
+/*016f*/ 0x100e0b92U,
+/*0170*/ 0x000e0b93U,
+/*0171*/ 0x100e0b93U,
+/*0172*/ 0x00040b94U,
+/*0173*/ 0x08040b94U,
+/*0174*/ 0x10040b94U,
+/*0175*/ 0x18040b94U,
+/*0176*/ 0x00040b95U,
+/*0177*/ 0x080b0b95U,
+/*0178*/ 0x000b0b96U,
+/*0179*/ 0x100b0b96U,
+/*017a*/ 0x000b0b97U,
+/*017b*/ 0xffffffffU,
+/*017c*/ 0xffffffffU,
+/*017d*/ 0xffffffffU,
+/*017e*/ 0xffffffffU,
+/*017f*/ 0x000d0b98U,
+/*0180*/ 0x100d0b98U,
+/*0181*/ 0x000d0b99U,
+/*0182*/ 0x10100b99U,
+/*0183*/ 0x10080b8dU,
+/*0184*/ 0x18080b8dU,
+/*0185*/ 0x00100b9aU,
+/*0186*/ 0x10100b9aU,
+/*0187*/ 0x00100b9bU,
+/*0188*/ 0x10100b9bU,
+/*0189*/ 0x00100b9cU,
+/*018a*/ 0x10030b9cU,
+/*018b*/ 0x18040b9cU,
+/*018c*/ 0x00010b9dU,
+/*018d*/ 0x08040b9dU,
+/*018e*/ 0xffffffffU,
+/*018f*/ 0xffffffffU,
+/*0190*/ 0x10010b9dU,
+/*0191*/ 0x00140b9eU,
+/*0192*/ 0x000a0b9fU,
+/*0193*/ 0x100c0b9fU,
+/*0194*/ 0x00120ba0U,
+/*0195*/ 0x00140ba1U,
+/*0196*/ 0x00120ba2U,
+/*0197*/ 0x00110ba3U,
+/*0198*/ 0x00110ba4U,
+/*0199*/ 0x00120ba5U,
+/*019a*/ 0x00120ba6U,
+/*019b*/ 0x00120ba7U,
+/*019c*/ 0x00120ba8U,
+/*019d*/ 0x00120ba9U,
+/*019e*/ 0x00120baaU,
+/*019f*/ 0x00120babU,
+/*01a0*/ 0x00120bacU,
+/*01a1*/ 0xffffffffU,
+/*01a2*/ 0xffffffffU,
+/*01a3*/ 0x00190badU,
+/*01a4*/ 0x00190baeU,
+/*01a5*/ 0x00200bafU,
+/*01a6*/ 0x00170bb0U,
+/*01a7*/ 0x18080bb0U,
+/*01a8*/ 0x00010bb1U,
+/*01a9*/ 0x08010bb1U,
+/*01aa*/ 0x00200bb2U,
+/*01ab*/ 0x00080bb3U,
+/*01ac*/ 0xffffffffU,
+/*01ad*/ 0x08030bb3U,
+/*01ae*/ 0x00180bb4U,
+/*01af*/ 0x00180bb5U,
+/*01b0*/ 0xffffffffU,
+/*01b1*/ 0xffffffffU,
+/*01b2*/ 0xffffffffU,
+/*01b3*/ 0xffffffffU,
+/*01b4*/ 0xffffffffU,
+/*01b5*/ 0xffffffffU,
+/*01b6*/ 0xffffffffU,
+/*01b7*/ 0xffffffffU,
+/*01b8*/ 0xffffffffU,
+/*01b9*/ 0xffffffffU,
+/*01ba*/ 0xffffffffU,
+/*01bb*/ 0xffffffffU,
+/*01bc*/ 0xffffffffU,
+/*01bd*/ 0xffffffffU,
+/*01be*/ 0xffffffffU,
+/*01bf*/ 0x00100bb6U,
+/*01c0*/ 0x10010bb6U,
+/*01c1*/ 0x18010bb6U,
+/*01c2*/ 0x00050bb7U,
+/*01c3*/ 0x00200bb8U,
+/*01c4*/ 0x00090bb9U,
+/*01c5*/ 0xffffffffU,
+/*01c6*/ 0xffffffffU,
+/*01c7*/ 0x00200bbaU,
+/*01c8*/ 0x00040bbbU,
+/*01c9*/ 0x08100bbbU,
+/*01ca*/ 0x18060bbbU,
+/*01cb*/ 0x00100bbcU,
+/*01cc*/ 0xffffffffU,
+/*01cd*/ 0x10080bbcU,
+/*01ce*/ 0xffffffffU,
+/*01cf*/ 0xffffffffU,
+/*01d0*/ 0xffffffffU,
+/*01d1*/ 0x18030bbcU,
+/*01d2*/ 0x00020bbdU,
+/*01d3*/ 0xffffffffU,
+/*01d4*/ 0x00200bbeU,
+/*01d5*/ 0x000b0bbfU,
+/*01d6*/ 0xffffffffU,
+/*01d7*/ 0xffffffffU,
+/*01d8*/ 0xffffffffU,
+/*01d9*/ 0x10020bbfU,
+/*01da*/ 0xffffffffU,
+/*01db*/ 0xffffffffU,
+/*01dc*/ 0xffffffffU,
+/*01dd*/ 0xffffffffU,
+/*01de*/ 0x00010200U,
+/*01df*/ 0x08040200U,
+/*01e0*/ 0x10100200U,
+/*01e1*/ 0x00010201U,
+/*01e2*/ 0x08010201U,
+/*01e3*/ 0xffffffffU,
+/*01e4*/ 0xffffffffU,
+/*01e5*/ 0x10100201U,
+/*01e6*/ 0xffffffffU,
+/*01e7*/ 0xffffffffU,
+/*01e8*/ 0xffffffffU,
+/*01e9*/ 0xffffffffU,
+/*01ea*/ 0xffffffffU,
+/*01eb*/ 0xffffffffU,
+/*01ec*/ 0xffffffffU,
+/*01ed*/ 0xffffffffU,
+/*01ee*/ 0xffffffffU,
+/*01ef*/ 0x00200202U,
+/*01f0*/ 0x00100203U,
+/*01f1*/ 0x00200204U,
+/*01f2*/ 0x00100205U,
+/*01f3*/ 0x00200206U,
+/*01f4*/ 0x00100207U,
+/*01f5*/ 0x10100207U,
+/*01f6*/ 0x00200208U,
+/*01f7*/ 0x00200209U,
+/*01f8*/ 0x0020020aU,
+/*01f9*/ 0x0020020bU,
+/*01fa*/ 0x0010020cU,
+/*01fb*/ 0x0020020dU,
+/*01fc*/ 0x0020020eU,
+/*01fd*/ 0x0020020fU,
+/*01fe*/ 0x00200210U,
+/*01ff*/ 0x00100211U,
+/*0200*/ 0x00200212U,
+/*0201*/ 0x00200213U,
+/*0202*/ 0x00200214U,
+/*0203*/ 0x00200215U,
+/*0204*/ 0x00090216U,
+/*0205*/ 0x10010216U,
+/*0206*/ 0x00200217U,
+/*0207*/ 0x00050218U,
+/*0208*/ 0x08010218U,
+/*0209*/ 0x10080218U,
+/*020a*/ 0x18080218U,
+/*020b*/ 0x001e0219U,
+/*020c*/ 0x001e021aU,
+/*020d*/ 0x001e021bU,
+/*020e*/ 0x001e021cU,
+/*020f*/ 0x001e021dU,
+/*0210*/ 0x001e021eU,
+/*0211*/ 0x001e021fU,
+/*0212*/ 0x001e0220U,
+/*0213*/ 0x001e0221U,
+/*0214*/ 0x001e0222U,
+/*0215*/ 0x001e0223U,
+/*0216*/ 0x001e0224U,
+/*0217*/ 0x001e0225U,
+/*0218*/ 0x001e0226U,
+/*0219*/ 0x001e0227U,
+/*021a*/ 0x001e0228U,
+/*021b*/ 0x00010229U,
+/*021c*/ 0x08010229U,
+/*021d*/ 0x10010229U,
+/*021e*/ 0x18040229U,
+/*021f*/ 0x0008022aU,
+/*0220*/ 0x0808022aU,
+/*0221*/ 0x1008022aU,
+/*0222*/ 0x1804022aU,
+/*0223*/ 0x0005022bU,
+/*0224*/ 0x0806022bU,
+/*0225*/ 0x1007022bU,
+/*0226*/ 0x1805022bU,
+/*0227*/ 0x0006022cU,
+/*0228*/ 0x0807022cU,
+/*0229*/ 0x1005022cU,
+/*022a*/ 0x1806022cU,
+/*022b*/ 0x0007022dU,
+/*022c*/ 0x0802022dU,
+/*022d*/ 0x1001022dU,
+/*022e*/ 0xffffffffU,
+/*022f*/ 0x000a022eU,
+/*0230*/ 0x1010022eU,
+/*0231*/ 0x000a022fU,
+/*0232*/ 0x1010022fU,
+/*0233*/ 0x000a0230U,
+/*0234*/ 0x10100230U,
+/*0235*/ 0xffffffffU,
+/*0236*/ 0x00100231U,
+/*0237*/ 0xffffffffU,
+/*0238*/ 0xffffffffU,
+/*0239*/ 0x10010231U,
+/*023a*/ 0x18010231U,
+/*023b*/ 0x00010232U,
+/*023c*/ 0x08010232U,
+/*023d*/ 0x10010232U,
+/*023e*/ 0x18010232U,
+/*023f*/ 0x00020233U,
+/*0240*/ 0x08020233U,
+/*0241*/ 0x10020233U,
+/*0242*/ 0x18020233U,
+/*0243*/ 0x00020234U,
+/*0244*/ 0x08030234U,
+/*0245*/ 0x10010234U,
+/*0246*/ 0x18010234U,
+/*0247*/ 0x00010235U,
+/*0248*/ 0x08010235U,
+/*0249*/ 0xffffffffU,
+/*024a*/ 0x10020235U,
+/*024b*/ 0x18010235U,
+/*024c*/ 0x00010236U,
+/*024d*/ 0xffffffffU,
+/*024e*/ 0x08020236U,
+/*024f*/ 0x10010236U,
+/*0250*/ 0x18010236U,
+/*0251*/ 0xffffffffU,
+/*0252*/ 0x00020237U,
+/*0253*/ 0x08010237U,
+/*0254*/ 0x10010237U,
+/*0255*/ 0xffffffffU,
+/*0256*/ 0x18020237U,
+/*0257*/ 0x00070238U,
+/*0258*/ 0x08010238U,
+/*0259*/ 0x10010238U,
+/*025a*/ 0x18010238U,
+/*025b*/ 0x00010239U,
+/*025c*/ 0x08010239U,
+/*025d*/ 0x10010239U,
+/*025e*/ 0xffffffffU,
+/*025f*/ 0x18010239U,
+/*0260*/ 0x0004023aU,
+/*0261*/ 0x0804023aU,
+/*0262*/ 0x1004023aU,
+/*0263*/ 0x1801023aU,
+/*0264*/ 0x0002023bU,
+/*0265*/ 0x0806023bU,
+/*0266*/ 0x1006023bU,
+/*0267*/ 0xffffffffU,
+/*0268*/ 0xffffffffU,
+/*0269*/ 0xffffffffU,
+/*026a*/ 0x1802023bU,
+/*026b*/ 0x0010023cU,
+/*026c*/ 0x1001023cU,
+/*026d*/ 0x1801023cU,
+/*026e*/ 0xffffffffU,
+/*026f*/ 0x0004023dU,
+/*0270*/ 0x0801023dU,
+/*0271*/ 0x1004023dU,
+/*0272*/ 0x1802023dU,
+/*0273*/ 0x0008023eU,
+/*0274*/ 0xffffffffU,
+/*0275*/ 0xffffffffU,
+/*0276*/ 0xffffffffU,
+/*0277*/ 0x080a023eU,
+/*0278*/ 0x0020023fU,
+/*0279*/ 0x00200240U,
+/*027a*/ 0x00050241U,
+/*027b*/ 0x08010241U,
+/*027c*/ 0x10050241U,
+/*027d*/ 0x18080241U,
+/*027e*/ 0x00010242U,
+/*027f*/ 0x08080242U,
+/*0280*/ 0x10010242U,
+/*0281*/ 0x18080242U,
+/*0282*/ 0x00010243U,
+/*0283*/ 0x08040243U,
+/*0284*/ 0x10040243U,
+/*0285*/ 0x18040243U,
+/*0286*/ 0x00040244U,
+/*0287*/ 0x08040244U,
+/*0288*/ 0x10040244U,
+/*0289*/ 0x18040244U,
+/*028a*/ 0x00040245U,
+/*028b*/ 0x08040245U,
+/*028c*/ 0x10040245U,
+/*028d*/ 0x18010245U,
+/*028e*/ 0x00040246U,
+/*028f*/ 0x08040246U,
+/*0290*/ 0x10040246U,
+/*0291*/ 0x18040246U,
+/*0292*/ 0x00040247U,
+/*0293*/ 0x08040247U,
+/*0294*/ 0x10060247U,
+/*0295*/ 0x18060247U,
+/*0296*/ 0x00060248U,
+/*0297*/ 0x08060248U,
+/*0298*/ 0x10060248U,
+/*0299*/ 0x18060248U,
+/*029a*/ 0x00040249U,
+/*029b*/ 0x08010249U,
+/*029c*/ 0x10010249U,
+/*029d*/ 0x18020249U,
+/*029e*/ 0xffffffffU,
+/*029f*/ 0xffffffffU,
+/*02a0*/ 0xffffffffU,
+/*02a1*/ 0xffffffffU,
+/*02a2*/ 0xffffffffU,
+/*02a3*/ 0xffffffffU,
+/*02a4*/ 0xffffffffU,
+/*02a5*/ 0xffffffffU,
+/*02a6*/ 0x0004024aU,
+/*02a7*/ 0x0804024aU,
+/*02a8*/ 0x1001024aU,
+/*02a9*/ 0x1801024aU,
+/*02aa*/ 0xffffffffU,
+/*02ab*/ 0x0001024bU,
+/*02ac*/ 0x0801024bU,
+/*02ad*/ 0xffffffffU,
+/*02ae*/ 0x1001024bU,
+/*02af*/ 0x1801024bU,
+/*02b0*/ 0x0001024cU,
+/*02b1*/ 0x0804024cU,
+/*02b2*/ 0x1004024cU,
+/*02b3*/ 0x000a024dU,
+/*02b4*/ 0x0020024eU,
+/*02b5*/ 0x0004024fU,
+/*02b6*/ 0x0808024fU,
+/*02b7*/ 0xffffffffU,
+/*02b8*/ 0xffffffffU,
+/*02b9*/ 0xffffffffU,
+/*02ba*/ 0xffffffffU,
+/*02bb*/ 0xffffffffU,
+/*02bc*/ 0xffffffffU,
+/*02bd*/ 0x1002024fU,
+/*02be*/ 0x1802024fU,
+/*02bf*/ 0x00200250U,
+/*02c0*/ 0x00020251U,
+/*02c1*/ 0x08100251U,
+/*02c2*/ 0x00100252U,
+/*02c3*/ 0x10040252U,
+/*02c4*/ 0x18040252U,
+/*02c5*/ 0x00050253U,
+/*02c6*/ 0x08050253U,
+/*02c7*/ 0xffffffffU,
+/*02c8*/ 0xffffffffU,
+/*02c9*/ 0xffffffffU,
+/*02ca*/ 0xffffffffU,
+/*02cb*/ 0x10010253U,
+/*02cc*/ 0x18010253U,
+/*02cd*/ 0x00080254U,
+/*02ce*/ 0x08080254U,
+/*02cf*/ 0x10080254U,
+/*02d0*/ 0x18080254U,
+/*02d1*/ 0x00080255U,
+/*02d2*/ 0x08080255U,
+/*02d3*/ 0x10080255U,
+/*02d4*/ 0x18080255U,
+/*02d5*/ 0x00080256U,
+/*02d6*/ 0x08080256U,
+/*02d7*/ 0x10080256U,
+/*02d8*/ 0xffffffffU,
+/*02d9*/ 0xffffffffU,
+/*02da*/ 0xffffffffU,
+/*02db*/ 0xffffffffU,
+/*02dc*/ 0xffffffffU,
+/*02dd*/ 0xffffffffU,
+/*02de*/ 0x18030256U,
+/*02df*/ 0x00010257U,
+/*02e0*/ 0x08020257U,
+/*02e1*/ 0x10010257U,
+/*02e2*/ 0x18040257U,
+/*02e3*/ 0x00020258U,
+/*02e4*/ 0x08010258U,
+/*02e5*/ 0x10010258U,
+/*02e6*/ 0xffffffffU,
+/*02e7*/ 0x18010258U,
+/*02e8*/ 0x00040259U,
+/*02e9*/ 0x08080259U,
+/*02ea*/ 0x100a0259U,
+/*02eb*/ 0x000a025aU,
+/*02ec*/ 0x100a025aU,
+/*02ed*/ 0x000a025bU,
+/*02ee*/ 0x100a025bU,
+/*02ef*/ 0x000a025cU,
+/*02f0*/ 0x0020025dU,
+/*02f1*/ 0x0020025eU,
+/*02f2*/ 0x0001025fU,
+/*02f3*/ 0xffffffffU,
+/*02f4*/ 0xffffffffU,
+/*02f5*/ 0xffffffffU,
+/*02f6*/ 0x0802025fU,
+/*02f7*/ 0x1002025fU,
+/*02f8*/ 0x00100260U,
+/*02f9*/ 0x10050260U,
+/*02fa*/ 0x18060260U,
+/*02fb*/ 0x00050261U,
+/*02fc*/ 0x08050261U,
+/*02fd*/ 0x100e0261U,
+/*02fe*/ 0x00050262U,
+/*02ff*/ 0x080e0262U,
+/*0300*/ 0x18050262U,
+/*0301*/ 0x000e0263U,
+/*0302*/ 0x10050263U,
+/*0303*/ 0x18010263U,
+/*0304*/ 0x00050264U,
+/*0305*/ 0x08050264U,
+/*0306*/ 0x100a0264U,
+/*0307*/ 0x000a0265U,
+/*0308*/ 0x10050265U,
+/*0309*/ 0x18050265U,
+/*030a*/ 0x000a0266U,
+/*030b*/ 0x100a0266U,
+/*030c*/ 0x00050267U,
+/*030d*/ 0x08050267U,
+/*030e*/ 0x100a0267U,
+/*030f*/ 0x000a0268U,
+/*0310*/ 0xffffffffU,
+/*0311*/ 0xffffffffU,
+/*0312*/ 0xffffffffU,
+/*0313*/ 0xffffffffU,
+/*0314*/ 0xffffffffU,
+/*0315*/ 0xffffffffU,
+/*0316*/ 0x10070268U,
+/*0317*/ 0x18070268U,
+/*0318*/ 0x00040269U,
+/*0319*/ 0x08040269U,
+/*031a*/ 0xffffffffU,
+/*031b*/ 0xffffffffU,
+/*031c*/ 0xffffffffU,
+/*031d*/ 0x10040269U,
+/*031e*/ 0x18080269U,
+/*031f*/ 0x0008026aU,
+/*0320*/ 0x0804026aU,
+/*0321*/ 0xffffffffU,
+/*0322*/ 0xffffffffU,
+/*0323*/ 0xffffffffU,
+/*0324*/ 0x1004026aU,
+/*0325*/ 0xffffffffU,
+/*0326*/ 0xffffffffU,
+/*0327*/ 0xffffffffU,
+/*0328*/ 0x1804026aU,
+/*0329*/ 0xffffffffU,
+/*032a*/ 0xffffffffU,
+/*032b*/ 0xffffffffU,
+/*032c*/ 0x0004026bU,
+/*032d*/ 0x0805026bU,
+/*032e*/ 0x1007026bU,
+/*032f*/ 0x1808026bU,
+/*0330*/ 0x0010026cU,
+/*0331*/ 0x1008026cU,
+/*0332*/ 0x0010026dU,
+/*0333*/ 0x1008026dU,
+/*0334*/ 0x0010026eU,
+/*0335*/ 0x1008026eU,
+/*0336*/ 0x1808026eU,
+/*0337*/ 0x0001026fU,
+/*0338*/ 0x0801026fU,
+/*0339*/ 0x1006026fU,
+/*033a*/ 0x1806026fU,
+/*033b*/ 0x00060270U,
+/*033c*/ 0xffffffffU,
+/*033d*/ 0x08010270U,
+/*033e*/ 0x10030270U,
+/*033f*/ 0xffffffffU,
+/*0340*/ 0xffffffffU,
+/*0341*/ 0xffffffffU,
+/*0342*/ 0x000a0271U,
+/*0343*/ 0x100a0271U,
+/*0344*/ 0x00040272U,
+/*0345*/ 0x08010272U,
+/*0346*/ 0x10040272U,
+/*0347*/ 0xffffffffU,
+/*0348*/ 0xffffffffU,
+/*0349*/ 0xffffffffU,
+/*034a*/ 0xffffffffU,
+/*034b*/ 0xffffffffU,
+/*034c*/ 0xffffffffU,
+/*034d*/ 0x18070272U,
+/*034e*/ 0x00070273U,
+/*034f*/ 0x08050273U,
+/*0350*/ 0x10050273U,
+/*0351*/ 0xffffffffU,
+/*0352*/ 0xffffffffU,
+/*0353*/ 0xffffffffU,
+/*0354*/ 0x18040273U,
+/*0355*/ 0x00010274U,
+/*0356*/ 0x08010274U,
+/*0357*/ 0x10020274U,
+/*0358*/ 0x18080274U,
+/*0359*/ 0x00200275U,
+/*035a*/ 0x00200276U,
+/*035b*/ 0x00100277U,
+/*035c*/ 0xffffffffU,
+/*035d*/ 0xffffffffU,
+/*035e*/ 0xffffffffU,
+/*035f*/ 0x10020277U,
+/*0360*/ 0x18010277U,
+/*0361*/ 0xffffffffU,
+/*0362*/ 0x00020278U,
+/*0363*/ 0x08100278U,
+/*0364*/ 0x00100279U,
+/*0365*/ 0x10100279U,
+/*0366*/ 0x0008027aU,
+/*0367*/ 0x0808027aU,
+/*0368*/ 0x1008027aU,
+/*0369*/ 0xffffffffU,
+/*036a*/ 0x0010027bU,
+/*036b*/ 0x1010027bU,
+/*036c*/ 0x0010027cU,
+/*036d*/ 0x1008027cU,
+/*036e*/ 0x1808027cU,
+/*036f*/ 0x0008027dU,
+/*0370*/ 0xffffffffU,
+/*0371*/ 0x0810027dU,
+/*0372*/ 0x0010027eU,
+/*0373*/ 0x1010027eU,
+/*0374*/ 0x0008027fU,
+/*0375*/ 0x0808027fU,
+/*0376*/ 0x1008027fU,
+/*0377*/ 0xffffffffU,
+/*0378*/ 0x1808027fU,
+/*0379*/ 0x00100280U,
+/*037a*/ 0x10100280U,
+/*037b*/ 0x00100281U,
+/*037c*/ 0x10080281U,
+/*037d*/ 0x18080281U,
+/*037e*/ 0x00080282U,
+/*037f*/ 0xffffffffU,
+/*0380*/ 0x08100282U,
+/*0381*/ 0x00100283U,
+/*0382*/ 0x10100283U,
+/*0383*/ 0x00080284U,
+/*0384*/ 0x08080284U,
+/*0385*/ 0x10080284U,
+/*0386*/ 0xffffffffU,
+/*0387*/ 0x00100285U,
+/*0388*/ 0x10100285U,
+/*0389*/ 0x00100286U,
+/*038a*/ 0x10080286U,
+/*038b*/ 0x18080286U,
+/*038c*/ 0x00080287U,
+/*038d*/ 0xffffffffU,
+/*038e*/ 0x08080287U,
+/*038f*/ 0x10100287U,
+/*0390*/ 0x00100288U,
+/*0391*/ 0x10100288U,
+/*0392*/ 0x00080289U,
+/*0393*/ 0x08080289U,
+/*0394*/ 0x10080289U,
+/*0395*/ 0xffffffffU,
+/*0396*/ 0x0010028aU,
+/*0397*/ 0x1010028aU,
+/*0398*/ 0x0010028bU,
+/*0399*/ 0x1008028bU,
+/*039a*/ 0x1808028bU,
+/*039b*/ 0x0008028cU,
+/*039c*/ 0xffffffffU,
+/*039d*/ 0x0810028cU,
+/*039e*/ 0x0010028dU,
+/*039f*/ 0x1010028dU,
+/*03a0*/ 0x0008028eU,
+/*03a1*/ 0x0808028eU,
+/*03a2*/ 0x1008028eU,
+/*03a3*/ 0xffffffffU,
+/*03a4*/ 0x1808028eU,
+/*03a5*/ 0x0010028fU,
+/*03a6*/ 0x1010028fU,
+/*03a7*/ 0x00100290U,
+/*03a8*/ 0x10080290U,
+/*03a9*/ 0x18080290U,
+/*03aa*/ 0x00080291U,
+/*03ab*/ 0xffffffffU,
+/*03ac*/ 0x08100291U,
+/*03ad*/ 0x00100292U,
+/*03ae*/ 0x10100292U,
+/*03af*/ 0x00080293U,
+/*03b0*/ 0x08080293U,
+/*03b1*/ 0x10080293U,
+/*03b2*/ 0xffffffffU,
+/*03b3*/ 0x00100294U,
+/*03b4*/ 0x10100294U,
+/*03b5*/ 0x00100295U,
+/*03b6*/ 0x10080295U,
+/*03b7*/ 0x18080295U,
+/*03b8*/ 0x00080296U,
+/*03b9*/ 0xffffffffU,
+/*03ba*/ 0x08080296U,
+/*03bb*/ 0x10020296U,
+/*03bc*/ 0x18030296U,
+/*03bd*/ 0x000a0297U,
+/*03be*/ 0x100a0297U,
+/*03bf*/ 0x000a0298U,
+/*03c0*/ 0x10050298U,
+/*03c1*/ 0x18040298U,
+/*03c2*/ 0x00080299U,
+/*03c3*/ 0x08080299U,
+/*03c4*/ 0x10060299U,
+/*03c5*/ 0x18060299U,
+/*03c6*/ 0x0011029aU,
+/*03c7*/ 0x1808029aU,
+/*03c8*/ 0x0004029bU,
+/*03c9*/ 0x0806029bU,
+/*03ca*/ 0xffffffffU,
+/*03cb*/ 0x1006029bU,
+/*03cc*/ 0x1808029bU,
+/*03cd*/ 0x0008029cU,
+/*03ce*/ 0x0804029cU,
+/*03cf*/ 0x1008029cU,
+/*03d0*/ 0x1808029cU,
+/*03d1*/ 0x0006029dU,
+/*03d2*/ 0x0806029dU,
+/*03d3*/ 0x0011029eU,
+/*03d4*/ 0x1808029eU,
+/*03d5*/ 0x0004029fU,
+/*03d6*/ 0x0806029fU,
+/*03d7*/ 0xffffffffU,
+/*03d8*/ 0x1006029fU,
+/*03d9*/ 0x1808029fU,
+/*03da*/ 0x000802a0U,
+/*03db*/ 0x080402a0U,
+/*03dc*/ 0x100802a0U,
+/*03dd*/ 0x180802a0U,
+/*03de*/ 0x000602a1U,
+/*03df*/ 0x080602a1U,
+/*03e0*/ 0x001102a2U,
+/*03e1*/ 0x180802a2U,
+/*03e2*/ 0x000402a3U,
+/*03e3*/ 0x080602a3U,
+/*03e4*/ 0xffffffffU,
+/*03e5*/ 0x100602a3U,
+/*03e6*/ 0x180802a3U,
+/*03e7*/ 0x000802a4U,
+/*03e8*/ 0x080402a4U,
+/*03e9*/ 0x100402a4U,
+/*03ea*/ 0x180402a4U,
+/*03eb*/ 0x000402a5U,
+/*03ec*/ 0x080402a5U,
+/*03ed*/ 0x100402a5U,
+/*03ee*/ 0x180402a5U,
+/*03ef*/ 0x000402a6U,
+/*03f0*/ 0x080402a6U,
+/*03f1*/ 0x100402a6U,
+/*03f2*/ 0x180402a6U,
+/*03f3*/ 0x000402a7U,
+/*03f4*/ 0x080402a7U,
+/*03f5*/ 0x100402a7U,
+/*03f6*/ 0x180402a7U,
+/*03f7*/ 0x000402a8U,
+/*03f8*/ 0x080402a8U,
+/*03f9*/ 0x100402a8U,
+/*03fa*/ 0x180402a8U,
+/*03fb*/ 0x000402a9U,
+/*03fc*/ 0x081202a9U,
+/*03fd*/ 0x001102aaU,
+/*03fe*/ 0x001202abU,
+/*03ff*/ 0x002002acU,
+/*0400*/ 0x002002adU,
+/*0401*/ 0x002002aeU,
+/*0402*/ 0x002002afU,
+/*0403*/ 0x002002b0U,
+/*0404*/ 0x002002b1U,
+/*0405*/ 0x002002b2U,
+/*0406*/ 0x002002b3U,
+/*0407*/ 0x002002b4U,
+/*0408*/ 0x000302b5U,
+/*0409*/ 0x080502b5U,
+/*040a*/ 0x100502b5U,
+/*040b*/ 0x180102b5U,
+/*040c*/ 0x000502b6U,
+/*040d*/ 0x080502b6U,
+/*040e*/ 0x100502b6U,
+/*040f*/ 0x180502b6U,
+/*0410*/ 0x000502b7U,
+/*0411*/ 0x080502b7U,
+/*0412*/ 0x100502b7U,
+/*0413*/ 0x180502b7U,
+/*0414*/ 0x000502b8U,
+/*0415*/ 0x080502b8U,
+/*0416*/ 0x100502b8U,
+/*0417*/ 0x180502b8U,
+/*0418*/ 0x000502b9U,
+/*0419*/ 0x080502b9U,
+/*041a*/ 0x100502b9U,
+/*041b*/ 0x180502b9U,
+/*041c*/ 0x000502baU,
+/*041d*/ 0x080502baU,
+/*041e*/ 0x100502baU,
+/*041f*/ 0x180502baU,
+/*0420*/ 0x000502bbU,
+/*0421*/ 0x080502bbU,
+/*0422*/ 0x100102bbU,
+/*0423*/ 0x180202bbU,
+/*0424*/ 0x000202bcU,
+/*0425*/ 0x080202bcU,
+/*0426*/ 0x100202bcU,
+/*0427*/ 0x180102bcU,
+/*0428*/ 0x000402bdU,
+/*0429*/ 0x081002bdU,
+/*042a*/ 0x002002beU,
+/*042b*/ 0x001002bfU,
+/*042c*/ 0x002002c0U,
+/*042d*/ 0x001002c1U,
+/*042e*/ 0x002002c2U,
+/*042f*/ 0x000702c3U,
+/*0430*/ 0x080102c3U,
+/*0431*/ 0x100202c3U,
+/*0432*/ 0x180602c3U,
+/*0433*/ 0x000102c4U,
+/*0434*/ 0x080102c4U,
+/*0435*/ 0x002002c5U,
+/*0436*/ 0x000302c6U,
+/*0437*/ 0x002002c7U,
+/*0438*/ 0x002002c8U,
+/*0439*/ 0xffffffffU,
+/*043a*/ 0xffffffffU,
+/*043b*/ 0xffffffffU,
+/*043c*/ 0xffffffffU,
+/*043d*/ 0xffffffffU,
+/*043e*/ 0xffffffffU,
+/*043f*/ 0xffffffffU,
+/*0440*/ 0xffffffffU,
+/*0441*/ 0xffffffffU,
+/*0442*/ 0xffffffffU,
+/*0443*/ 0xffffffffU,
+/*0444*/ 0xffffffffU,
+/*0445*/ 0xffffffffU,
+/*0446*/ 0xffffffffU,
+/*0447*/ 0xffffffffU,
+/*0448*/ 0xffffffffU,
+/*0449*/ 0xffffffffU,
+/*044a*/ 0xffffffffU,
+/*044b*/ 0xffffffffU,
+/*044c*/ 0xffffffffU,
+/*044d*/ 0xffffffffU,
+/*044e*/ 0xffffffffU,
+/*044f*/ 0xffffffffU,
+/*0450*/ 0xffffffffU,
+/*0451*/ 0xffffffffU,
+/*0452*/ 0xffffffffU,
+/*0453*/ 0xffffffffU,
+/*0454*/ 0xffffffffU,
+/*0455*/ 0xffffffffU,
+/*0456*/ 0xffffffffU,
+/*0457*/ 0xffffffffU,
+/*0458*/ 0xffffffffU,
+/*0459*/ 0xffffffffU,
+/*045a*/ 0xffffffffU,
+/*045b*/ 0xffffffffU,
+/*045c*/ 0xffffffffU,
+/*045d*/ 0xffffffffU,
+/*045e*/ 0xffffffffU,
+/*045f*/ 0x000402c9U,
+/*0460*/ 0xffffffffU,
+/*0461*/ 0xffffffffU,
+/*0462*/ 0xffffffffU,
+/*0463*/ 0xffffffffU,
+/*0464*/ 0xffffffffU,
+/*0465*/ 0xffffffffU,
+/*0466*/ 0xffffffffU,
+/*0467*/ 0xffffffffU,
+/*0468*/ 0xffffffffU,
+/*0469*/ 0xffffffffU,
+/*046a*/ 0xffffffffU,
+/*046b*/ 0xffffffffU,
+/*046c*/ 0xffffffffU,
+/*046d*/ 0xffffffffU,
+/*046e*/ 0xffffffffU,
+/*046f*/ 0xffffffffU,
+/*0470*/ 0xffffffffU,
+/*0471*/ 0xffffffffU,
+/*0472*/ 0xffffffffU,
+/*0473*/ 0xffffffffU,
+/*0474*/ 0xffffffffU,
+/*0475*/ 0xffffffffU,
+/*0476*/ 0xffffffffU,
+/*0477*/ 0xffffffffU,
+/*0478*/ 0xffffffffU,
+/*0479*/ 0xffffffffU,
+/*047a*/ 0xffffffffU,
+/*047b*/ 0xffffffffU,
+/*047c*/ 0xffffffffU,
+/*047d*/ 0xffffffffU,
+/*047e*/ 0xffffffffU,
+/*047f*/ 0xffffffffU,
+/*0480*/ 0xffffffffU,
+/*0481*/ 0xffffffffU,
+/*0482*/ 0xffffffffU,
+/*0483*/ 0xffffffffU,
+/*0484*/ 0xffffffffU,
+/*0485*/ 0xffffffffU,
+/*0486*/ 0xffffffffU,
+/*0487*/ 0xffffffffU,
+/*0488*/ 0xffffffffU,
+/*0489*/ 0xffffffffU,
+/*048a*/ 0xffffffffU,
+/*048b*/ 0xffffffffU,
+/*048c*/ 0xffffffffU,
+/*048d*/ 0xffffffffU,
+/*048e*/ 0xffffffffU,
+/*048f*/ 0xffffffffU,
+/*0490*/ 0xffffffffU,
+/*0491*/ 0xffffffffU,
+/*0492*/ 0xffffffffU,
+/*0493*/ 0xffffffffU,
+/*0494*/ 0xffffffffU,
+	 },
+	{
+/*0000*/ 0x00200400U,
+/*0001*/ 0x00040401U,
+/*0002*/ 0x080b0401U,
+/*0003*/ 0x000a0402U,
+/*0004*/ 0x10020402U,
+/*0005*/ 0x18010402U,
+/*0006*/ 0x00050403U,
+/*0007*/ 0x08050403U,
+/*0008*/ 0x10050403U,
+/*0009*/ 0x18050403U,
+/*000a*/ 0x00050404U,
+/*000b*/ 0x08050404U,
+/*000c*/ 0x10050404U,
+/*000d*/ 0x18050404U,
+/*000e*/ 0x00050405U,
+/*000f*/ 0x08040405U,
+/*0010*/ 0x10030405U,
+/*0011*/ 0x00180406U,
+/*0012*/ 0x18030406U,
+/*0013*/ 0x00180407U,
+/*0014*/ 0x18020407U,
+/*0015*/ 0x00010408U,
+/*0016*/ 0x08020408U,
+/*0017*/ 0x10010408U,
+/*0018*/ 0x18010408U,
+/*0019*/ 0x00020409U,
+/*001a*/ 0x08040409U,
+/*001b*/ 0x10040409U,
+/*001c*/ 0x18040409U,
+/*001d*/ 0xffffffffU,
+/*001e*/ 0x0004040aU,
+/*001f*/ 0xffffffffU,
+/*0020*/ 0xffffffffU,
+/*0021*/ 0x0809040aU,
+/*0022*/ 0x1801040aU,
+/*0023*/ 0x0020040bU,
+/*0024*/ 0x001c040cU,
+/*0025*/ 0x0001040dU,
+/*0026*/ 0x0807040dU,
+/*0027*/ 0x1009040dU,
+/*0028*/ 0x000a040eU,
+/*0029*/ 0x1005040eU,
+/*002a*/ 0x1801040eU,
+/*002b*/ 0x1001040fU,
+/*002c*/ 0x1802040fU,
+/*002d*/ 0x0009040fU,
+/*002e*/ 0x00090410U,
+/*002f*/ 0x10020410U,
+/*0030*/ 0x00200411U,
+/*0031*/ 0x00010412U,
+/*0032*/ 0x08020412U,
+/*0033*/ 0xffffffffU,
+/*0034*/ 0xffffffffU,
+/*0035*/ 0xffffffffU,
+/*0036*/ 0xffffffffU,
+/*0037*/ 0x00200413U,
+/*0038*/ 0x00200414U,
+/*0039*/ 0x00200415U,
+/*003a*/ 0x00200416U,
+/*003b*/ 0x00030417U,
+/*003c*/ 0x08010417U,
+/*003d*/ 0x10040417U,
+/*003e*/ 0x18030417U,
+/*003f*/ 0x00040418U,
+/*0040*/ 0x08040418U,
+/*0041*/ 0x10040418U,
+/*0042*/ 0x18040418U,
+/*0043*/ 0x00010419U,
+/*0044*/ 0x08010419U,
+/*0045*/ 0x10060419U,
+/*0046*/ 0x18040419U,
+/*0047*/ 0xffffffffU,
+/*0048*/ 0x0006041aU,
+/*0049*/ 0x0804041aU,
+/*004a*/ 0x1006041aU,
+/*004b*/ 0x1804041aU,
+/*004c*/ 0x0002041bU,
+/*004d*/ 0x0805041bU,
+/*004e*/ 0x1008041bU,
+/*004f*/ 0xffffffffU,
+/*0050*/ 0x1806041bU,
+/*0051*/ 0x0003041cU,
+/*0052*/ 0x080b041cU,
+/*0053*/ 0x1804041cU,
+/*0054*/ 0x0004041dU,
+/*0055*/ 0x0804041dU,
+/*0056*/ 0x1001041dU,
+/*0057*/ 0xffffffffU,
+/*0058*/ 0x0009041eU,
+/*0059*/ 0x0020041fU,
+/*005a*/ 0x00200420U,
+/*005b*/ 0x00200421U,
+/*005c*/ 0x00200422U,
+/*005d*/ 0x00100423U,
+/*005e*/ 0xffffffffU,
+/*005f*/ 0x10010423U,
+/*0060*/ 0x18060423U,
+/*0061*/ 0x00080424U,
+/*0062*/ 0x00200425U,
+/*0063*/ 0x00100426U,
+/*0064*/ 0x100a0426U,
+/*0065*/ 0x00060427U,
+/*0066*/ 0x08070427U,
+/*0067*/ 0x10080427U,
+/*0068*/ 0x18080427U,
+/*0069*/ 0x000a0428U,
+/*006a*/ 0x10070428U,
+/*006b*/ 0x18080428U,
+/*006c*/ 0x00080429U,
+/*006d*/ 0x08030429U,
+/*006e*/ 0x100a0429U,
+/*006f*/ 0x000a042aU,
+/*0070*/ 0x0011042bU,
+/*0071*/ 0x0009042cU,
+/*0072*/ 0x1009042cU,
+/*0073*/ 0x0010042dU,
+/*0074*/ 0x100e042dU,
+/*0075*/ 0x000e042eU,
+/*0076*/ 0x0012042fU,
+/*0077*/ 0x000a0430U,
+/*0078*/ 0x100a0430U,
+/*0079*/ 0x00020431U,
+/*007a*/ 0x00200432U,
+/*007b*/ 0x000b0433U,
+/*007c*/ 0x100b0433U,
+/*007d*/ 0x00200434U,
+/*007e*/ 0x00120435U,
+/*007f*/ 0x00200436U,
+/*0080*/ 0x00200437U,
+/*0081*/ 0x00080438U,
+/*0082*/ 0x08010438U,
+/*0083*/ 0x10010438U,
+/*0084*/ 0x18010438U,
+/*0085*/ 0x00080439U,
+/*0086*/ 0x080c0439U,
+/*0087*/ 0x000c043aU,
+/*0088*/ 0x100c043aU,
+/*0089*/ 0x000c043bU,
+/*008a*/ 0x100c043bU,
+/*008b*/ 0x000c043cU,
+/*008c*/ 0x100c043cU,
+/*008d*/ 0x000c043dU,
+/*008e*/ 0x100c043dU,
+/*008f*/ 0x000c043eU,
+/*0090*/ 0x100c043eU,
+/*0091*/ 0x000b043fU,
+/*0092*/ 0x1009043fU,
+/*0093*/ 0x00010440U,
+/*0094*/ 0x000b0441U,
+/*0095*/ 0x100b0441U,
+/*0096*/ 0x000b0442U,
+/*0097*/ 0x100b0442U,
+/*0098*/ 0x000b0443U,
+/*0099*/ 0x100b0443U,
+/*009a*/ 0x000b0444U,
+/*009b*/ 0x100b0444U,
+/*009c*/ 0x000b0445U,
+/*009d*/ 0x100a0445U,
+/*009e*/ 0x00020446U,
+/*009f*/ 0x080a0446U,
+/*00a0*/ 0x000a0447U,
+/*00a1*/ 0x100a0447U,
+/*00a2*/ 0x000a0448U,
+/*00a3*/ 0x100a0448U,
+/*00a4*/ 0x000a0449U,
+/*00a5*/ 0x100a0449U,
+/*00a6*/ 0x000a044aU,
+/*00a7*/ 0x100a044aU,
+/*00a8*/ 0x000a044bU,
+/*00a9*/ 0x100a044bU,
+/*00aa*/ 0x000a044cU,
+/*00ab*/ 0x100a044cU,
+/*00ac*/ 0x000a044dU,
+/*00ad*/ 0x100a044dU,
+/*00ae*/ 0x000a044eU,
+/*00af*/ 0x100a044eU,
+/*00b0*/ 0x000a044fU,
+/*00b1*/ 0x100a044fU,
+/*00b2*/ 0x000a0450U,
+/*00b3*/ 0x100a0450U,
+/*00b4*/ 0x000a0451U,
+/*00b5*/ 0x100a0451U,
+/*00b6*/ 0x000a0452U,
+/*00b7*/ 0x100a0452U,
+/*00b8*/ 0x000a0453U,
+/*00b9*/ 0x100a0453U,
+/*00ba*/ 0x000a0454U,
+/*00bb*/ 0x10040454U,
+/*00bc*/ 0x18030454U,
+/*00bd*/ 0x000a0455U,
+/*00be*/ 0x100a0455U,
+/*00bf*/ 0x00010456U,
+/*00c0*/ 0x080a0456U,
+/*00c1*/ 0x18040456U,
+/*00c2*/ 0x000b0457U,
+/*00c3*/ 0x100a0457U,
+/*00c4*/ 0x00030458U,
+/*00c5*/ 0x00080459U,
+/*00c6*/ 0x08080459U,
+/*00c7*/ 0x10080459U,
+/*00c8*/ 0x18080459U,
+/*00c9*/ 0x0008045aU,
+/*00ca*/ 0xffffffffU,
+/*00cb*/ 0x0808045aU,
+/*00cc*/ 0x1001045aU,
+/*00cd*/ 0x1808045aU,
+/*00ce*/ 0x0008045bU,
+/*00cf*/ 0x0802045bU,
+/*00d0*/ 0x1002045bU,
+/*00d1*/ 0x1805045bU,
+/*00d2*/ 0x0005045cU,
+/*00d3*/ 0xffffffffU,
+/*00d4*/ 0x0804045cU,
+/*00d5*/ 0x100a045cU,
+/*00d6*/ 0x0006045dU,
+/*00d7*/ 0x0808045dU,
+/*00d8*/ 0x1008045dU,
+/*00d9*/ 0x1804045dU,
+/*00da*/ 0x0004045eU,
+/*00db*/ 0x0805045eU,
+/*00dc*/ 0x1004045eU,
+/*00dd*/ 0x1805045eU,
+/*00de*/ 0x000a045fU,
+/*00df*/ 0x100a045fU,
+/*00e0*/ 0x00080460U,
+/*00e1*/ 0xffffffffU,
+/*00e2*/ 0x08040460U,
+/*00e3*/ 0xffffffffU,
+/*00e4*/ 0xffffffffU,
+/*00e5*/ 0x00050600U,
+/*00e6*/ 0x08050600U,
+/*00e7*/ 0x10050600U,
+/*00e8*/ 0x18050600U,
+/*00e9*/ 0x00050601U,
+/*00ea*/ 0x08050601U,
+/*00eb*/ 0x100b0601U,
+/*00ec*/ 0x00010602U,
+/*00ed*/ 0x08030602U,
+/*00ee*/ 0x00200603U,
+/*00ef*/ 0x00100604U,
+/*00f0*/ 0x10040604U,
+/*00f1*/ 0x000a0605U,
+/*00f2*/ 0x10090605U,
+/*00f3*/ 0x00080606U,
+/*00f4*/ 0x08030606U,
+/*00f5*/ 0x10030606U,
+/*00f6*/ 0x18010606U,
+/*00f7*/ 0x00010607U,
+/*00f8*/ 0x08070607U,
+/*00f9*/ 0x10070607U,
+/*00fa*/ 0x18050607U,
+/*00fb*/ 0x00010608U,
+/*00fc*/ 0x08020608U,
+/*00fd*/ 0x10030608U,
+/*00fe*/ 0x18010608U,
+/*00ff*/ 0x000f0609U,
+/*0100*/ 0x0020060aU,
+/*0101*/ 0x0020060bU,
+/*0102*/ 0x000b060cU,
+/*0103*/ 0x100b060cU,
+/*0104*/ 0x000b060dU,
+/*0105*/ 0x0018060eU,
+/*0106*/ 0x0018060fU,
+/*0107*/ 0xffffffffU,
+/*0108*/ 0xffffffffU,
+/*0109*/ 0xffffffffU,
+/*010a*/ 0xffffffffU,
+/*010b*/ 0xffffffffU,
+/*010c*/ 0x1802060fU,
+/*010d*/ 0x00020610U,
+/*010e*/ 0x08040610U,
+/*010f*/ 0x10040610U,
+/*0110*/ 0x18010610U,
+/*0111*/ 0x00010611U,
+/*0112*/ 0x08010611U,
+/*0113*/ 0x10030611U,
+/*0114*/ 0x00200612U,
+/*0115*/ 0x00200613U,
+/*0116*/ 0xffffffffU,
+/*0117*/ 0x00140614U,
+/*0118*/ 0x00140615U,
+/*0119*/ 0x00140616U,
+/*011a*/ 0x00140617U,
+/*011b*/ 0x00140618U,
+/*011c*/ 0x00140619U,
+/*011d*/ 0x0014061aU,
+/*011e*/ 0x0014061bU,
+/*011f*/ 0x0018061cU,
+/*0120*/ 0x000a061dU,
+/*0121*/ 0x1006061dU,
+/*0122*/ 0x1806061dU,
+/*0123*/ 0x0006061eU,
+/*0124*/ 0xffffffffU,
+/*0125*/ 0x0806061eU,
+/*0126*/ 0x0008061fU,
+/*0127*/ 0x080b061fU,
+/*0128*/ 0x000b0620U,
+/*0129*/ 0x100b0620U,
+/*012a*/ 0x000b0621U,
+/*012b*/ 0x100b0621U,
+/*012c*/ 0x000b0622U,
+/*012d*/ 0x10040622U,
+/*012e*/ 0x000a0623U,
+/*012f*/ 0x10060623U,
+/*0130*/ 0x18080623U,
+/*0131*/ 0x00080624U,
+/*0132*/ 0x08040624U,
+/*0133*/ 0x00020680U,
+/*0134*/ 0x00010681U,
+/*0135*/ 0x08010681U,
+/*0136*/ 0x10020681U,
+/*0137*/ 0x18050681U,
+/*0138*/ 0x00050682U,
+/*0139*/ 0x08050682U,
+/*013a*/ 0x10050682U,
+/*013b*/ 0x000b0683U,
+/*013c*/ 0x10050683U,
+/*013d*/ 0x18010683U,
+/*013e*/ 0x00010684U,
+/*013f*/ 0xffffffffU,
+/*0140*/ 0x08010684U,
+/*0141*/ 0x10010684U,
+/*0142*/ 0x18040684U,
+/*0143*/ 0x000b0685U,
+/*0144*/ 0x100b0685U,
+/*0145*/ 0x000b0686U,
+/*0146*/ 0x10040686U,
+/*0147*/ 0x000b0687U,
+/*0148*/ 0x10040687U,
+/*0149*/ 0x18010687U,
+/*014a*/ 0x00010688U,
+/*014b*/ 0x08010688U,
+/*014c*/ 0x00200689U,
+/*014d*/ 0x0020068aU,
+/*014e*/ 0x0008068bU,
+/*014f*/ 0x080a068bU,
+/*0150*/ 0x1805068bU,
+/*0151*/ 0x000a068cU,
+/*0152*/ 0x1003068cU,
+/*0153*/ 0x1803068cU,
+/*0154*/ 0x0001068dU,
+/*0155*/ 0x0802068dU,
+/*0156*/ 0x1001068dU,
+/*0157*/ 0x1801068dU,
+/*0158*/ 0x0001068eU,
+/*0159*/ 0x0802068eU,
+/*015a*/ 0x1001068eU,
+/*015b*/ 0x0004068fU,
+/*015c*/ 0x0804068fU,
+/*015d*/ 0x1004068fU,
+/*015e*/ 0x1804068fU,
+/*015f*/ 0x00010690U,
+/*0160*/ 0x08010690U,
+/*0161*/ 0x10010690U,
+/*0162*/ 0x00200691U,
+/*0163*/ 0x00200692U,
+/*0164*/ 0x00200693U,
+/*0165*/ 0x00200694U,
+/*0166*/ 0xffffffffU,
+/*0167*/ 0x1801068eU,
+/*0168*/ 0x000d0696U,
+/*0169*/ 0x100d0696U,
+/*016a*/ 0x000d0697U,
+/*016b*/ 0x00050698U,
+/*016c*/ 0x00010699U,
+/*016d*/ 0x080e0699U,
+/*016e*/ 0x000e069aU,
+/*016f*/ 0x100e069aU,
+/*0170*/ 0x000e069bU,
+/*0171*/ 0x100e069bU,
+/*0172*/ 0x0004069cU,
+/*0173*/ 0x0804069cU,
+/*0174*/ 0x1004069cU,
+/*0175*/ 0x1804069cU,
+/*0176*/ 0x0004069dU,
+/*0177*/ 0x080b069dU,
+/*0178*/ 0x000b069eU,
+/*0179*/ 0x100b069eU,
+/*017a*/ 0x000b069fU,
+/*017b*/ 0xffffffffU,
+/*017c*/ 0xffffffffU,
+/*017d*/ 0xffffffffU,
+/*017e*/ 0xffffffffU,
+/*017f*/ 0x000d06a0U,
+/*0180*/ 0x100d06a0U,
+/*0181*/ 0x000d06a1U,
+/*0182*/ 0x101006a1U,
+/*0183*/ 0x00080695U,
+/*0184*/ 0x08080695U,
+/*0185*/ 0x001006a2U,
+/*0186*/ 0x101006a2U,
+/*0187*/ 0x001006a3U,
+/*0188*/ 0x101006a3U,
+/*0189*/ 0x001006a4U,
+/*018a*/ 0x100306a4U,
+/*018b*/ 0x180406a4U,
+/*018c*/ 0x000106a5U,
+/*018d*/ 0x080806a5U,
+/*018e*/ 0x100106a5U,
+/*018f*/ 0x180506a5U,
+/*0190*/ 0x000106a6U,
+/*0191*/ 0x081406a6U,
+/*0192*/ 0x000a06a7U,
+/*0193*/ 0x100c06a7U,
+/*0194*/ 0x001206a8U,
+/*0195*/ 0x001406a9U,
+/*0196*/ 0x001206aaU,
+/*0197*/ 0x001106abU,
+/*0198*/ 0x001106acU,
+/*0199*/ 0x001206adU,
+/*019a*/ 0x001206aeU,
+/*019b*/ 0x001206afU,
+/*019c*/ 0x001206b0U,
+/*019d*/ 0x001206b1U,
+/*019e*/ 0x001206b2U,
+/*019f*/ 0x001206b3U,
+/*01a0*/ 0x001206b4U,
+/*01a1*/ 0x001206b5U,
+/*01a2*/ 0x001206b6U,
+/*01a3*/ 0x000e06b7U,
+/*01a4*/ 0x100d06b7U,
+/*01a5*/ 0x002006b8U,
+/*01a6*/ 0x001706b9U,
+/*01a7*/ 0x000906baU,
+/*01a8*/ 0x100106baU,
+/*01a9*/ 0x180106baU,
+/*01aa*/ 0x002006bbU,
+/*01ab*/ 0x000806bcU,
+/*01ac*/ 0x080306bcU,
+/*01ad*/ 0x100306bcU,
+/*01ae*/ 0x001806bdU,
+/*01af*/ 0x001806beU,
+/*01b0*/ 0x180706beU,
+/*01b1*/ 0x000506bfU,
+/*01b2*/ 0x080806bfU,
+/*01b3*/ 0x100806bfU,
+/*01b4*/ 0x180806bfU,
+/*01b5*/ 0x000106c0U,
+/*01b6*/ 0x080106c0U,
+/*01b7*/ 0x002006c1U,
+/*01b8*/ 0xffffffffU,
+/*01b9*/ 0xffffffffU,
+/*01ba*/ 0xffffffffU,
+/*01bb*/ 0xffffffffU,
+/*01bc*/ 0xffffffffU,
+/*01bd*/ 0xffffffffU,
+/*01be*/ 0xffffffffU,
+/*01bf*/ 0x001006c2U,
+/*01c0*/ 0x100106c2U,
+/*01c1*/ 0x180106c2U,
+/*01c2*/ 0x000206c3U,
+/*01c3*/ 0x080406c3U,
+/*01c4*/ 0x100906c3U,
+/*01c5*/ 0x000706c4U,
+/*01c6*/ 0x080406c4U,
+/*01c7*/ 0x002006c5U,
+/*01c8*/ 0x000106c6U,
+/*01c9*/ 0x080206c6U,
+/*01ca*/ 0x100606c6U,
+/*01cb*/ 0x001006c7U,
+/*01cc*/ 0x100106c7U,
+/*01cd*/ 0x002006c8U,
+/*01ce*/ 0x000806c9U,
+/*01cf*/ 0x080106c9U,
+/*01d0*/ 0x100506c9U,
+/*01d1*/ 0xffffffffU,
+/*01d2*/ 0x180206c9U,
+/*01d3*/ 0x000106caU,
+/*01d4*/ 0x002006cbU,
+/*01d5*/ 0x000b06ccU,
+/*01d6*/ 0x100106ccU,
+/*01d7*/ 0x180306ccU,
+/*01d8*/ 0x000806cdU,
+/*01d9*/ 0x080206cdU,
+/*01da*/ 0x100c06cdU,
+/*01db*/ 0x000406ceU,
+/*01dc*/ 0x080106ceU,
+/*01dd*/ 0xffffffffU,
+/*01de*/ 0x00010200U,
+/*01df*/ 0x08040200U,
+/*01e0*/ 0x10100200U,
+/*01e1*/ 0x00010201U,
+/*01e2*/ 0x08010201U,
+/*01e3*/ 0x10010201U,
+/*01e4*/ 0xffffffffU,
+/*01e5*/ 0x00100202U,
+/*01e6*/ 0x10080202U,
+/*01e7*/ 0xffffffffU,
+/*01e8*/ 0xffffffffU,
+/*01e9*/ 0xffffffffU,
+/*01ea*/ 0xffffffffU,
+/*01eb*/ 0xffffffffU,
+/*01ec*/ 0xffffffffU,
+/*01ed*/ 0xffffffffU,
+/*01ee*/ 0xffffffffU,
+/*01ef*/ 0x00200203U,
+/*01f0*/ 0x00100204U,
+/*01f1*/ 0x00200205U,
+/*01f2*/ 0x00100206U,
+/*01f3*/ 0x00200207U,
+/*01f4*/ 0x00100208U,
+/*01f5*/ 0x00140209U,
+/*01f6*/ 0x0020020aU,
+/*01f7*/ 0x0020020bU,
+/*01f8*/ 0x0020020cU,
+/*01f9*/ 0x0020020dU,
+/*01fa*/ 0x0014020eU,
+/*01fb*/ 0x0020020fU,
+/*01fc*/ 0x00200210U,
+/*01fd*/ 0x00200211U,
+/*01fe*/ 0x00200212U,
+/*01ff*/ 0x00140213U,
+/*0200*/ 0x00200214U,
+/*0201*/ 0x00200215U,
+/*0202*/ 0x00200216U,
+/*0203*/ 0x00200217U,
+/*0204*/ 0x00090218U,
+/*0205*/ 0x10010218U,
+/*0206*/ 0x00200219U,
+/*0207*/ 0x0005021aU,
+/*0208*/ 0x0801021aU,
+/*0209*/ 0x1008021aU,
+/*020a*/ 0x1808021aU,
+/*020b*/ 0x001c021bU,
+/*020c*/ 0x001c021cU,
+/*020d*/ 0x001c021dU,
+/*020e*/ 0x001c021eU,
+/*020f*/ 0x001c021fU,
+/*0210*/ 0x001c0220U,
+/*0211*/ 0x001c0221U,
+/*0212*/ 0x001c0222U,
+/*0213*/ 0x001c0223U,
+/*0214*/ 0x001c0224U,
+/*0215*/ 0x001c0225U,
+/*0216*/ 0x001c0226U,
+/*0217*/ 0x001c0227U,
+/*0218*/ 0x001c0228U,
+/*0219*/ 0x001c0229U,
+/*021a*/ 0x001c022aU,
+/*021b*/ 0x0001022bU,
+/*021c*/ 0x0801022bU,
+/*021d*/ 0x1001022bU,
+/*021e*/ 0x1804022bU,
+/*021f*/ 0x0008022cU,
+/*0220*/ 0x0808022cU,
+/*0221*/ 0x1008022cU,
+/*0222*/ 0x1804022cU,
+/*0223*/ 0x0007022dU,
+/*0224*/ 0xffffffffU,
+/*0225*/ 0x0807022dU,
+/*0226*/ 0x1007022dU,
+/*0227*/ 0xffffffffU,
+/*0228*/ 0x1807022dU,
+/*0229*/ 0x0007022eU,
+/*022a*/ 0xffffffffU,
+/*022b*/ 0x0807022eU,
+/*022c*/ 0x1002022eU,
+/*022d*/ 0x1801022eU,
+/*022e*/ 0x0001022fU,
+/*022f*/ 0x080a022fU,
+/*0230*/ 0x00140230U,
+/*0231*/ 0x000a0231U,
+/*0232*/ 0x00140232U,
+/*0233*/ 0x000a0233U,
+/*0234*/ 0x00140234U,
+/*0235*/ 0x18010234U,
+/*0236*/ 0x00100235U,
+/*0237*/ 0x10050235U,
+/*0238*/ 0x18010235U,
+/*0239*/ 0x00010236U,
+/*023a*/ 0x08010236U,
+/*023b*/ 0x10010236U,
+/*023c*/ 0x18010236U,
+/*023d*/ 0x00010237U,
+/*023e*/ 0x08010237U,
+/*023f*/ 0x10020237U,
+/*0240*/ 0x18020237U,
+/*0241*/ 0x00020238U,
+/*0242*/ 0x08020238U,
+/*0243*/ 0x10020238U,
+/*0244*/ 0x18030238U,
+/*0245*/ 0x00010239U,
+/*0246*/ 0x08010239U,
+/*0247*/ 0x10010239U,
+/*0248*/ 0x18010239U,
+/*0249*/ 0xffffffffU,
+/*024a*/ 0x0002023aU,
+/*024b*/ 0x0801023aU,
+/*024c*/ 0x1001023aU,
+/*024d*/ 0xffffffffU,
+/*024e*/ 0x1802023aU,
+/*024f*/ 0x0001023bU,
+/*0250*/ 0x0801023bU,
+/*0251*/ 0xffffffffU,
+/*0252*/ 0x1002023bU,
+/*0253*/ 0x1801023bU,
+/*0254*/ 0x0001023cU,
+/*0255*/ 0xffffffffU,
+/*0256*/ 0x0802023cU,
+/*0257*/ 0x1007023cU,
+/*0258*/ 0x1801023cU,
+/*0259*/ 0x0001023dU,
+/*025a*/ 0x0801023dU,
+/*025b*/ 0x1001023dU,
+/*025c*/ 0x1801023dU,
+/*025d*/ 0x0001023eU,
+/*025e*/ 0x0801023eU,
+/*025f*/ 0x1001023eU,
+/*0260*/ 0x1804023eU,
+/*0261*/ 0x0004023fU,
+/*0262*/ 0x0804023fU,
+/*0263*/ 0x1001023fU,
+/*0264*/ 0x1802023fU,
+/*0265*/ 0x00060240U,
+/*0266*/ 0x08060240U,
+/*0267*/ 0x10020240U,
+/*0268*/ 0x18020240U,
+/*0269*/ 0x00020241U,
+/*026a*/ 0xffffffffU,
+/*026b*/ 0x08100241U,
+/*026c*/ 0x18010241U,
+/*026d*/ 0x00010242U,
+/*026e*/ 0x08010242U,
+/*026f*/ 0x10040242U,
+/*0270*/ 0x18010242U,
+/*0271*/ 0x00040243U,
+/*0272*/ 0x08020243U,
+/*0273*/ 0x10080243U,
+/*0274*/ 0xffffffffU,
+/*0275*/ 0xffffffffU,
+/*0276*/ 0xffffffffU,
+/*0277*/ 0x000a0244U,
+/*0278*/ 0x00200245U,
+/*0279*/ 0x00200246U,
+/*027a*/ 0x00050247U,
+/*027b*/ 0x08010247U,
+/*027c*/ 0x10050247U,
+/*027d*/ 0x18080247U,
+/*027e*/ 0x00010248U,
+/*027f*/ 0x08080248U,
+/*0280*/ 0x10010248U,
+/*0281*/ 0x18080248U,
+/*0282*/ 0x00010249U,
+/*0283*/ 0x08040249U,
+/*0284*/ 0x10040249U,
+/*0285*/ 0x18040249U,
+/*0286*/ 0x0004024aU,
+/*0287*/ 0x0804024aU,
+/*0288*/ 0x1004024aU,
+/*0289*/ 0x1804024aU,
+/*028a*/ 0x0004024bU,
+/*028b*/ 0x0804024bU,
+/*028c*/ 0x1004024bU,
+/*028d*/ 0x1801024bU,
+/*028e*/ 0x0004024cU,
+/*028f*/ 0x0804024cU,
+/*0290*/ 0x1004024cU,
+/*0291*/ 0x1804024cU,
+/*0292*/ 0x0004024dU,
+/*0293*/ 0x0804024dU,
+/*0294*/ 0x1006024dU,
+/*0295*/ 0x1806024dU,
+/*0296*/ 0x0006024eU,
+/*0297*/ 0x0806024eU,
+/*0298*/ 0x1006024eU,
+/*0299*/ 0x1806024eU,
+/*029a*/ 0xffffffffU,
+/*029b*/ 0x0001024fU,
+/*029c*/ 0x0801024fU,
+/*029d*/ 0x1002024fU,
+/*029e*/ 0xffffffffU,
+/*029f*/ 0xffffffffU,
+/*02a0*/ 0xffffffffU,
+/*02a1*/ 0xffffffffU,
+/*02a2*/ 0xffffffffU,
+/*02a3*/ 0xffffffffU,
+/*02a4*/ 0xffffffffU,
+/*02a5*/ 0xffffffffU,
+/*02a6*/ 0x1804024fU,
+/*02a7*/ 0x00040250U,
+/*02a8*/ 0x08010250U,
+/*02a9*/ 0x10010250U,
+/*02aa*/ 0x18010250U,
+/*02ab*/ 0x00010251U,
+/*02ac*/ 0x08010251U,
+/*02ad*/ 0x10010251U,
+/*02ae*/ 0x18010251U,
+/*02af*/ 0x00010252U,
+/*02b0*/ 0x08010252U,
+/*02b1*/ 0x10040252U,
+/*02b2*/ 0x18040252U,
+/*02b3*/ 0x000a0253U,
+/*02b4*/ 0x00200254U,
+/*02b5*/ 0x00040255U,
+/*02b6*/ 0x08080255U,
+/*02b7*/ 0x10020255U,
+/*02b8*/ 0x18020255U,
+/*02b9*/ 0x00020256U,
+/*02ba*/ 0x08020256U,
+/*02bb*/ 0x10020256U,
+/*02bc*/ 0x18020256U,
+/*02bd*/ 0xffffffffU,
+/*02be*/ 0xffffffffU,
+/*02bf*/ 0x00200257U,
+/*02c0*/ 0x00020258U,
+/*02c1*/ 0x08100258U,
+/*02c2*/ 0x00100259U,
+/*02c3*/ 0x10040259U,
+/*02c4*/ 0x18040259U,
+/*02c5*/ 0x0005025aU,
+/*02c6*/ 0x0805025aU,
+/*02c7*/ 0x0020025bU,
+/*02c8*/ 0x0020025cU,
+/*02c9*/ 0x0020025dU,
+/*02ca*/ 0x0020025eU,
+/*02cb*/ 0x0001025fU,
+/*02cc*/ 0x0801025fU,
+/*02cd*/ 0x1007025fU,
+/*02ce*/ 0x1807025fU,
+/*02cf*/ 0x00070260U,
+/*02d0*/ 0x08070260U,
+/*02d1*/ 0x10070260U,
+/*02d2*/ 0x18070260U,
+/*02d3*/ 0x00070261U,
+/*02d4*/ 0x08070261U,
+/*02d5*/ 0x10070261U,
+/*02d6*/ 0x18070261U,
+/*02d7*/ 0x00070262U,
+/*02d8*/ 0x08070262U,
+/*02d9*/ 0x10070262U,
+/*02da*/ 0x18070262U,
+/*02db*/ 0x00030263U,
+/*02dc*/ 0x08030263U,
+/*02dd*/ 0x10030263U,
+/*02de*/ 0xffffffffU,
+/*02df*/ 0x18010263U,
+/*02e0*/ 0x00020264U,
+/*02e1*/ 0x08010264U,
+/*02e2*/ 0x10040264U,
+/*02e3*/ 0x18020264U,
+/*02e4*/ 0x00010265U,
+/*02e5*/ 0x08010265U,
+/*02e6*/ 0x10010265U,
+/*02e7*/ 0x18010265U,
+/*02e8*/ 0x00040266U,
+/*02e9*/ 0x08080266U,
+/*02ea*/ 0x100a0266U,
+/*02eb*/ 0x000a0267U,
+/*02ec*/ 0x100a0267U,
+/*02ed*/ 0x000a0268U,
+/*02ee*/ 0x100a0268U,
+/*02ef*/ 0x000a0269U,
+/*02f0*/ 0x0020026aU,
+/*02f1*/ 0x0020026bU,
+/*02f2*/ 0x0001026cU,
+/*02f3*/ 0x0802026cU,
+/*02f4*/ 0x1002026cU,
+/*02f5*/ 0x1802026cU,
+/*02f6*/ 0xffffffffU,
+/*02f7*/ 0x0002026dU,
+/*02f8*/ 0x0810026dU,
+/*02f9*/ 0x1805026dU,
+/*02fa*/ 0x0006026eU,
+/*02fb*/ 0x0805026eU,
+/*02fc*/ 0x1005026eU,
+/*02fd*/ 0x000e026fU,
+/*02fe*/ 0x1005026fU,
+/*02ff*/ 0x000e0270U,
+/*0300*/ 0x10050270U,
+/*0301*/ 0x000e0271U,
+/*0302*/ 0x10050271U,
+/*0303*/ 0x18010271U,
+/*0304*/ 0x00050272U,
+/*0305*/ 0x08050272U,
+/*0306*/ 0x100a0272U,
+/*0307*/ 0x000a0273U,
+/*0308*/ 0x10050273U,
+/*0309*/ 0x18050273U,
+/*030a*/ 0x000a0274U,
+/*030b*/ 0x100a0274U,
+/*030c*/ 0x00050275U,
+/*030d*/ 0x08050275U,
+/*030e*/ 0x100a0275U,
+/*030f*/ 0x000a0276U,
+/*0310*/ 0xffffffffU,
+/*0311*/ 0xffffffffU,
+/*0312*/ 0xffffffffU,
+/*0313*/ 0xffffffffU,
+/*0314*/ 0xffffffffU,
+/*0315*/ 0xffffffffU,
+/*0316*/ 0x10070276U,
+/*0317*/ 0x18070276U,
+/*0318*/ 0x00040277U,
+/*0319*/ 0x08040277U,
+/*031a*/ 0xffffffffU,
+/*031b*/ 0xffffffffU,
+/*031c*/ 0xffffffffU,
+/*031d*/ 0x10040277U,
+/*031e*/ 0x18080277U,
+/*031f*/ 0x00080278U,
+/*0320*/ 0x08040278U,
+/*0321*/ 0xffffffffU,
+/*0322*/ 0xffffffffU,
+/*0323*/ 0xffffffffU,
+/*0324*/ 0x10040278U,
+/*0325*/ 0xffffffffU,
+/*0326*/ 0xffffffffU,
+/*0327*/ 0xffffffffU,
+/*0328*/ 0x18040278U,
+/*0329*/ 0xffffffffU,
+/*032a*/ 0xffffffffU,
+/*032b*/ 0xffffffffU,
+/*032c*/ 0x00040279U,
+/*032d*/ 0x08050279U,
+/*032e*/ 0x10070279U,
+/*032f*/ 0x18080279U,
+/*0330*/ 0x0010027aU,
+/*0331*/ 0x1008027aU,
+/*0332*/ 0x0010027bU,
+/*0333*/ 0x1008027bU,
+/*0334*/ 0x0010027cU,
+/*0335*/ 0x1008027cU,
+/*0336*/ 0x1808027cU,
+/*0337*/ 0x0001027dU,
+/*0338*/ 0x0801027dU,
+/*0339*/ 0x1006027dU,
+/*033a*/ 0x1806027dU,
+/*033b*/ 0x0006027eU,
+/*033c*/ 0x0801027eU,
+/*033d*/ 0x1001027eU,
+/*033e*/ 0x1803027eU,
+/*033f*/ 0x000a027fU,
+/*0340*/ 0x100a027fU,
+/*0341*/ 0x000a0280U,
+/*0342*/ 0xffffffffU,
+/*0343*/ 0x100a0280U,
+/*0344*/ 0x00040281U,
+/*0345*/ 0x08010281U,
+/*0346*/ 0x10040281U,
+/*0347*/ 0xffffffffU,
+/*0348*/ 0xffffffffU,
+/*0349*/ 0xffffffffU,
+/*034a*/ 0xffffffffU,
+/*034b*/ 0xffffffffU,
+/*034c*/ 0xffffffffU,
+/*034d*/ 0x18070281U,
+/*034e*/ 0x00070282U,
+/*034f*/ 0x08050282U,
+/*0350*/ 0x10050282U,
+/*0351*/ 0xffffffffU,
+/*0352*/ 0xffffffffU,
+/*0353*/ 0xffffffffU,
+/*0354*/ 0x18040282U,
+/*0355*/ 0x00010283U,
+/*0356*/ 0x08010283U,
+/*0357*/ 0x10020283U,
+/*0358*/ 0x18080283U,
+/*0359*/ 0x00200284U,
+/*035a*/ 0x00200285U,
+/*035b*/ 0x00100286U,
+/*035c*/ 0x10020286U,
+/*035d*/ 0x18020286U,
+/*035e*/ 0x00020287U,
+/*035f*/ 0xffffffffU,
+/*0360*/ 0x08010287U,
+/*0361*/ 0x10010287U,
+/*0362*/ 0x18020287U,
+/*0363*/ 0x00080288U,
+/*0364*/ 0x08080288U,
+/*0365*/ 0x10080288U,
+/*0366*/ 0x18080288U,
+/*0367*/ 0x00080289U,
+/*0368*/ 0x08080289U,
+/*0369*/ 0xffffffffU,
+/*036a*/ 0x10080289U,
+/*036b*/ 0x18080289U,
+/*036c*/ 0x0008028aU,
+/*036d*/ 0x0808028aU,
+/*036e*/ 0x1008028aU,
+/*036f*/ 0x1808028aU,
+/*0370*/ 0xffffffffU,
+/*0371*/ 0x0008028bU,
+/*0372*/ 0x0808028bU,
+/*0373*/ 0x1008028bU,
+/*0374*/ 0x1808028bU,
+/*0375*/ 0x0008028cU,
+/*0376*/ 0x0808028cU,
+/*0377*/ 0xffffffffU,
+/*0378*/ 0x1008028cU,
+/*0379*/ 0x1808028cU,
+/*037a*/ 0x0008028dU,
+/*037b*/ 0x0808028dU,
+/*037c*/ 0x1008028dU,
+/*037d*/ 0x1808028dU,
+/*037e*/ 0x0008028eU,
+/*037f*/ 0xffffffffU,
+/*0380*/ 0x0808028eU,
+/*0381*/ 0x1008028eU,
+/*0382*/ 0x1808028eU,
+/*0383*/ 0x0008028fU,
+/*0384*/ 0x0808028fU,
+/*0385*/ 0x1008028fU,
+/*0386*/ 0xffffffffU,
+/*0387*/ 0x1808028fU,
+/*0388*/ 0x00080290U,
+/*0389*/ 0x08080290U,
+/*038a*/ 0x10080290U,
+/*038b*/ 0x18080290U,
+/*038c*/ 0x00080291U,
+/*038d*/ 0xffffffffU,
+/*038e*/ 0x08080291U,
+/*038f*/ 0x10080291U,
+/*0390*/ 0x18080291U,
+/*0391*/ 0x00080292U,
+/*0392*/ 0x08080292U,
+/*0393*/ 0x10080292U,
+/*0394*/ 0x18080292U,
+/*0395*/ 0xffffffffU,
+/*0396*/ 0x00080293U,
+/*0397*/ 0x08080293U,
+/*0398*/ 0x10080293U,
+/*0399*/ 0x18080293U,
+/*039a*/ 0x00080294U,
+/*039b*/ 0x08080294U,
+/*039c*/ 0xffffffffU,
+/*039d*/ 0x10080294U,
+/*039e*/ 0x18080294U,
+/*039f*/ 0x00080295U,
+/*03a0*/ 0x08080295U,
+/*03a1*/ 0x10080295U,
+/*03a2*/ 0x18080295U,
+/*03a3*/ 0xffffffffU,
+/*03a4*/ 0x00080296U,
+/*03a5*/ 0x08080296U,
+/*03a6*/ 0x10080296U,
+/*03a7*/ 0x18080296U,
+/*03a8*/ 0x00080297U,
+/*03a9*/ 0x08080297U,
+/*03aa*/ 0x10080297U,
+/*03ab*/ 0xffffffffU,
+/*03ac*/ 0x18080297U,
+/*03ad*/ 0x00080298U,
+/*03ae*/ 0x08080298U,
+/*03af*/ 0x10080298U,
+/*03b0*/ 0x18080298U,
+/*03b1*/ 0x00080299U,
+/*03b2*/ 0xffffffffU,
+/*03b3*/ 0x08080299U,
+/*03b4*/ 0x10080299U,
+/*03b5*/ 0x18080299U,
+/*03b6*/ 0x0008029aU,
+/*03b7*/ 0x0808029aU,
+/*03b8*/ 0x1008029aU,
+/*03b9*/ 0xffffffffU,
+/*03ba*/ 0x1808029aU,
+/*03bb*/ 0x0002029bU,
+/*03bc*/ 0x0803029bU,
+/*03bd*/ 0x100a029bU,
+/*03be*/ 0x000a029cU,
+/*03bf*/ 0x100a029cU,
+/*03c0*/ 0x0005029dU,
+/*03c1*/ 0x0808029dU,
+/*03c2*/ 0x1008029dU,
+/*03c3*/ 0x1808029dU,
+/*03c4*/ 0x0006029eU,
+/*03c5*/ 0x0806029eU,
+/*03c6*/ 0x0011029fU,
+/*03c7*/ 0x1808029fU,
+/*03c8*/ 0x000402a0U,
+/*03c9*/ 0x080602a0U,
+/*03ca*/ 0xffffffffU,
+/*03cb*/ 0x100602a0U,
+/*03cc*/ 0x180802a0U,
+/*03cd*/ 0xffffffffU,
+/*03ce*/ 0x000802a1U,
+/*03cf*/ 0x080802a1U,
+/*03d0*/ 0x100802a1U,
+/*03d1*/ 0x180602a1U,
+/*03d2*/ 0x000602a2U,
+/*03d3*/ 0x081102a2U,
+/*03d4*/ 0x000802a3U,
+/*03d5*/ 0x080402a3U,
+/*03d6*/ 0x100602a3U,
+/*03d7*/ 0xffffffffU,
+/*03d8*/ 0x180602a3U,
+/*03d9*/ 0x000802a4U,
+/*03da*/ 0xffffffffU,
+/*03db*/ 0x080802a4U,
+/*03dc*/ 0x100802a4U,
+/*03dd*/ 0x180802a4U,
+/*03de*/ 0x000602a5U,
+/*03df*/ 0x080602a5U,
+/*03e0*/ 0x001102a6U,
+/*03e1*/ 0x180802a6U,
+/*03e2*/ 0x000402a7U,
+/*03e3*/ 0x080602a7U,
+/*03e4*/ 0xffffffffU,
+/*03e5*/ 0x100602a7U,
+/*03e6*/ 0x180802a7U,
+/*03e7*/ 0xffffffffU,
+/*03e8*/ 0x000402a8U,
+/*03e9*/ 0x080402a8U,
+/*03ea*/ 0x100402a8U,
+/*03eb*/ 0x180402a8U,
+/*03ec*/ 0x000402a9U,
+/*03ed*/ 0x080402a9U,
+/*03ee*/ 0x100402a9U,
+/*03ef*/ 0x180402a9U,
+/*03f0*/ 0x000402aaU,
+/*03f1*/ 0x080402aaU,
+/*03f2*/ 0x100402aaU,
+/*03f3*/ 0x180402aaU,
+/*03f4*/ 0x000402abU,
+/*03f5*/ 0x080402abU,
+/*03f6*/ 0x100402abU,
+/*03f7*/ 0x180402abU,
+/*03f8*/ 0x000402acU,
+/*03f9*/ 0x080402acU,
+/*03fa*/ 0x100402acU,
+/*03fb*/ 0x180402acU,
+/*03fc*/ 0x001202adU,
+/*03fd*/ 0x001102aeU,
+/*03fe*/ 0x001202afU,
+/*03ff*/ 0x002002b0U,
+/*0400*/ 0x002002b1U,
+/*0401*/ 0x002002b2U,
+/*0402*/ 0x002002b3U,
+/*0403*/ 0x002002b4U,
+/*0404*/ 0x002002b5U,
+/*0405*/ 0x002002b6U,
+/*0406*/ 0x002002b7U,
+/*0407*/ 0x002002b8U,
+/*0408*/ 0x000202b9U,
+/*0409*/ 0x080502b9U,
+/*040a*/ 0x100502b9U,
+/*040b*/ 0x180102b9U,
+/*040c*/ 0x000402baU,
+/*040d*/ 0x080402baU,
+/*040e*/ 0x100402baU,
+/*040f*/ 0x180402baU,
+/*0410*/ 0x000402bbU,
+/*0411*/ 0x080402bbU,
+/*0412*/ 0x100402bbU,
+/*0413*/ 0x180402bbU,
+/*0414*/ 0xffffffffU,
+/*0415*/ 0xffffffffU,
+/*0416*/ 0xffffffffU,
+/*0417*/ 0xffffffffU,
+/*0418*/ 0xffffffffU,
+/*0419*/ 0xffffffffU,
+/*041a*/ 0x000402bcU,
+/*041b*/ 0x080402bcU,
+/*041c*/ 0x100402bcU,
+/*041d*/ 0x180402bcU,
+/*041e*/ 0x000402bdU,
+/*041f*/ 0x080402bdU,
+/*0420*/ 0x100402bdU,
+/*0421*/ 0x180402bdU,
+/*0422*/ 0x000102beU,
+/*0423*/ 0x080202beU,
+/*0424*/ 0x100202beU,
+/*0425*/ 0x180202beU,
+/*0426*/ 0x000202bfU,
+/*0427*/ 0x080102bfU,
+/*0428*/ 0x100402bfU,
+/*0429*/ 0x001002c0U,
+/*042a*/ 0x002002c1U,
+/*042b*/ 0x001002c2U,
+/*042c*/ 0x002002c3U,
+/*042d*/ 0x001002c4U,
+/*042e*/ 0x002002c5U,
+/*042f*/ 0x000702c6U,
+/*0430*/ 0x080102c6U,
+/*0431*/ 0x100202c6U,
+/*0432*/ 0x180602c6U,
+/*0433*/ 0x000102c7U,
+/*0434*/ 0x080102c7U,
+/*0435*/ 0x002002c8U,
+/*0436*/ 0x000202c9U,
+/*0437*/ 0x002002caU,
+/*0438*/ 0x002002cbU,
+/*0439*/ 0x000c02ccU,
+/*043a*/ 0x100c02ccU,
+/*043b*/ 0x002002cdU,
+/*043c*/ 0x000302ceU,
+/*043d*/ 0x002002cfU,
+/*043e*/ 0x000302d0U,
+/*043f*/ 0x002002d1U,
+/*0440*/ 0x000302d2U,
+/*0441*/ 0x002002d3U,
+/*0442*/ 0x000302d4U,
+/*0443*/ 0x002002d5U,
+/*0444*/ 0x000302d6U,
+/*0445*/ 0x002002d7U,
+/*0446*/ 0x000302d8U,
+/*0447*/ 0x002002d9U,
+/*0448*/ 0x000302daU,
+/*0449*/ 0x002002dbU,
+/*044a*/ 0x000302dcU,
+/*044b*/ 0x002002ddU,
+/*044c*/ 0x000302deU,
+/*044d*/ 0x002002dfU,
+/*044e*/ 0x000302e0U,
+/*044f*/ 0x080302e0U,
+/*0450*/ 0x100202e0U,
+/*0451*/ 0x180202e0U,
+/*0452*/ 0x002002e1U,
+/*0453*/ 0x002002e2U,
+/*0454*/ 0x002002e3U,
+/*0455*/ 0x002002e4U,
+/*0456*/ 0x000402e5U,
+/*0457*/ 0x001e02e6U,
+/*0458*/ 0x001e02e7U,
+/*0459*/ 0x001e02e8U,
+/*045a*/ 0x001e02e9U,
+/*045b*/ 0x001e02eaU,
+/*045c*/ 0x001e02ebU,
+/*045d*/ 0x001e02ecU,
+/*045e*/ 0x001e02edU,
+/*045f*/ 0x000402eeU,
+/*0460*/ 0xffffffffU,
+/*0461*/ 0xffffffffU,
+/*0462*/ 0xffffffffU,
+/*0463*/ 0xffffffffU,
+/*0464*/ 0x080402eeU,
+/*0465*/ 0x100102eeU,
+/*0466*/ 0x180802eeU,
+/*0467*/ 0x000402efU,
+/*0468*/ 0x080102efU,
+/*0469*/ 0x100802efU,
+/*046a*/ 0x180402efU,
+/*046b*/ 0x000102f0U,
+/*046c*/ 0x080802f0U,
+/*046d*/ 0x100402f0U,
+/*046e*/ 0x180102f0U,
+/*046f*/ 0x000802f1U,
+/*0470*/ 0x080402f1U,
+/*0471*/ 0x100102f1U,
+/*0472*/ 0x180802f1U,
+/*0473*/ 0x000402f2U,
+/*0474*/ 0x080102f2U,
+/*0475*/ 0x100802f2U,
+/*0476*/ 0x180402f2U,
+/*0477*/ 0x000102f3U,
+/*0478*/ 0x080802f3U,
+/*0479*/ 0x100402f3U,
+/*047a*/ 0x180102f3U,
+/*047b*/ 0x000802f4U,
+/*047c*/ 0x080802f4U,
+/*047d*/ 0x100102f4U,
+/*047e*/ 0x180502f4U,
+/*047f*/ 0xffffffffU,
+/*0480*/ 0xffffffffU,
+/*0481*/ 0xffffffffU,
+/*0482*/ 0xffffffffU,
+/*0483*/ 0xffffffffU,
+/*0484*/ 0xffffffffU,
+/*0485*/ 0xffffffffU,
+/*0486*/ 0xffffffffU,
+/*0487*/ 0xffffffffU,
+/*0488*/ 0xffffffffU,
+/*0489*/ 0xffffffffU,
+/*048a*/ 0xffffffffU,
+/*048b*/ 0xffffffffU,
+/*048c*/ 0xffffffffU,
+/*048d*/ 0xffffffffU,
+/*048e*/ 0xffffffffU,
+/*048f*/ 0xffffffffU,
+/*0490*/ 0xffffffffU,
+/*0491*/ 0xffffffffU,
+/*0492*/ 0xffffffffU,
+/*0493*/ 0xffffffffU,
+/*0494*/ 0xffffffffU,
+	 },
+	{
+/*0000*/ 0x00200800U,
+/*0001*/ 0x00040801U,
+/*0002*/ 0x080b0801U,
+/*0003*/ 0x000a0802U,
+/*0004*/ 0x10020802U,
+/*0005*/ 0x18010802U,
+/*0006*/ 0x00060803U,
+/*0007*/ 0x08060803U,
+/*0008*/ 0x10060803U,
+/*0009*/ 0x18060803U,
+/*000a*/ 0x00060804U,
+/*000b*/ 0x08060804U,
+/*000c*/ 0x10050804U,
+/*000d*/ 0x18060804U,
+/*000e*/ 0x00060805U,
+/*000f*/ 0x08040805U,
+/*0010*/ 0x10030805U,
+/*0011*/ 0x00180806U,
+/*0012*/ 0x18030806U,
+/*0013*/ 0x00180807U,
+/*0014*/ 0x18020807U,
+/*0015*/ 0x0801085eU,
+/*0016*/ 0x00020808U,
+/*0017*/ 0x08010808U,
+/*0018*/ 0x10010808U,
+/*0019*/ 0x18020808U,
+/*001a*/ 0x00050809U,
+/*001b*/ 0x08050809U,
+/*001c*/ 0x10040809U,
+/*001d*/ 0xffffffffU,
+/*001e*/ 0x18040809U,
+/*001f*/ 0x0002080aU,
+/*0020*/ 0x0805080aU,
+/*0021*/ 0x1009080aU,
+/*0022*/ 0x0001080bU,
+/*0023*/ 0x0020080cU,
+/*0024*/ 0x001c080dU,
+/*0025*/ 0x0001080eU,
+/*0026*/ 0x0807080eU,
+/*0027*/ 0x1009080eU,
+/*0028*/ 0x000a080fU,
+/*0029*/ 0x1005080fU,
+/*002a*/ 0x1801080fU,
+/*002b*/ 0x10010810U,
+/*002c*/ 0x18020810U,
+/*002d*/ 0x00090810U,
+/*002e*/ 0x00090811U,
+/*002f*/ 0x10020811U,
+/*0030*/ 0x00200812U,
+/*0031*/ 0x00010813U,
+/*0032*/ 0x08020813U,
+/*0033*/ 0x00200814U,
+/*0034*/ 0x00200815U,
+/*0035*/ 0x00200816U,
+/*0036*/ 0x00200817U,
+/*0037*/ 0xffffffffU,
+/*0038*/ 0xffffffffU,
+/*0039*/ 0xffffffffU,
+/*003a*/ 0xffffffffU,
+/*003b*/ 0x00030818U,
+/*003c*/ 0x08010818U,
+/*003d*/ 0x10040818U,
+/*003e*/ 0x18030818U,
+/*003f*/ 0x00040819U,
+/*0040*/ 0x08040819U,
+/*0041*/ 0x10040819U,
+/*0042*/ 0x18040819U,
+/*0043*/ 0x0001081aU,
+/*0044*/ 0x0801081aU,
+/*0045*/ 0x1006081aU,
+/*0046*/ 0x1804081aU,
+/*0047*/ 0x0008081bU,
+/*0048*/ 0x0806081bU,
+/*0049*/ 0x1004081bU,
+/*004a*/ 0x1806081bU,
+/*004b*/ 0x0004081cU,
+/*004c*/ 0x0802081cU,
+/*004d*/ 0x1005081cU,
+/*004e*/ 0x1808081cU,
+/*004f*/ 0xffffffffU,
+/*0050*/ 0x0006081dU,
+/*0051*/ 0x0803081dU,
+/*0052*/ 0x100b081dU,
+/*0053*/ 0x0004081eU,
+/*0054*/ 0x0804081eU,
+/*0055*/ 0x1004081eU,
+/*0056*/ 0x1801081eU,
+/*0057*/ 0xffffffffU,
+/*0058*/ 0x0009081fU,
+/*0059*/ 0x00200820U,
+/*005a*/ 0x00200821U,
+/*005b*/ 0x00200822U,
+/*005c*/ 0x00200823U,
+/*005d*/ 0x00100824U,
+/*005e*/ 0xffffffffU,
+/*005f*/ 0x10010824U,
+/*0060*/ 0x18060824U,
+/*0061*/ 0x00080825U,
+/*0062*/ 0x00200826U,
+/*0063*/ 0x00100827U,
+/*0064*/ 0x100b0827U,
+/*0065*/ 0x00070828U,
+/*0066*/ 0x08070828U,
+/*0067*/ 0x10090828U,
+/*0068*/ 0x00090829U,
+/*0069*/ 0x100b0829U,
+/*006a*/ 0x0007082aU,
+/*006b*/ 0x0808082aU,
+/*006c*/ 0x1009082aU,
+/*006d*/ 0x0003082bU,
+/*006e*/ 0x080a082bU,
+/*006f*/ 0x000a082cU,
+/*0070*/ 0x0011082dU,
+/*0071*/ 0x000a082eU,
+/*0072*/ 0x100a082eU,
+/*0073*/ 0x0010082fU,
+/*0074*/ 0x100e082fU,
+/*0075*/ 0x000e0830U,
+/*0076*/ 0x00120831U,
+/*0077*/ 0x000a0832U,
+/*0078*/ 0x100a0832U,
+/*0079*/ 0x00020833U,
+/*007a*/ 0x00200834U,
+/*007b*/ 0x000b0835U,
+/*007c*/ 0x100b0835U,
+/*007d*/ 0x00200836U,
+/*007e*/ 0x00130837U,
+/*007f*/ 0x00200838U,
+/*0080*/ 0x00200839U,
+/*0081*/ 0x0008083aU,
+/*0082*/ 0x0801083aU,
+/*0083*/ 0x1001083aU,
+/*0084*/ 0x1801083aU,
+/*0085*/ 0x0008083bU,
+/*0086*/ 0x080c083bU,
+/*0087*/ 0x000c083cU,
+/*0088*/ 0x100c083cU,
+/*0089*/ 0x000c083dU,
+/*008a*/ 0x100c083dU,
+/*008b*/ 0x000c083eU,
+/*008c*/ 0x100c083eU,
+/*008d*/ 0x000c083fU,
+/*008e*/ 0x100c083fU,
+/*008f*/ 0x000c0840U,
+/*0090*/ 0x100c0840U,
+/*0091*/ 0x000b0841U,
+/*0092*/ 0x10090841U,
+/*0093*/ 0x00010842U,
+/*0094*/ 0x000b0843U,
+/*0095*/ 0x100b0843U,
+/*0096*/ 0x000b0844U,
+/*0097*/ 0x100b0844U,
+/*0098*/ 0x000b0845U,
+/*0099*/ 0x100b0845U,
+/*009a*/ 0x000b0846U,
+/*009b*/ 0x100b0846U,
+/*009c*/ 0x000b0847U,
+/*009d*/ 0x100a0847U,
+/*009e*/ 0x00020848U,
+/*009f*/ 0x080a0848U,
+/*00a0*/ 0x000a0849U,
+/*00a1*/ 0x100a0849U,
+/*00a2*/ 0x000a084aU,
+/*00a3*/ 0x100a084aU,
+/*00a4*/ 0x000a084bU,
+/*00a5*/ 0x100a084bU,
+/*00a6*/ 0x000a084cU,
+/*00a7*/ 0x100a084cU,
+/*00a8*/ 0x000a084dU,
+/*00a9*/ 0x100a084dU,
+/*00aa*/ 0x000a084eU,
+/*00ab*/ 0x100a084eU,
+/*00ac*/ 0x000a084fU,
+/*00ad*/ 0x100a084fU,
+/*00ae*/ 0x000a0850U,
+/*00af*/ 0x100a0850U,
+/*00b0*/ 0x000a0851U,
+/*00b1*/ 0x100a0851U,
+/*00b2*/ 0x000a0852U,
+/*00b3*/ 0x100a0852U,
+/*00b4*/ 0x000a0853U,
+/*00b5*/ 0x100a0853U,
+/*00b6*/ 0x000a0854U,
+/*00b7*/ 0x100a0854U,
+/*00b8*/ 0x000a0855U,
+/*00b9*/ 0x100a0855U,
+/*00ba*/ 0x000a0856U,
+/*00bb*/ 0x10040856U,
+/*00bc*/ 0x18030856U,
+/*00bd*/ 0x000a0857U,
+/*00be*/ 0x100a0857U,
+/*00bf*/ 0x00010858U,
+/*00c0*/ 0x080a0858U,
+/*00c1*/ 0x18040858U,
+/*00c2*/ 0x000b0859U,
+/*00c3*/ 0x100a0859U,
+/*00c4*/ 0x0003085aU,
+/*00c5*/ 0x0008085bU,
+/*00c6*/ 0x0808085bU,
+/*00c7*/ 0x1008085bU,
+/*00c8*/ 0x1808085bU,
+/*00c9*/ 0x0008085cU,
+/*00ca*/ 0x0808085cU,
+/*00cb*/ 0x1008085cU,
+/*00cc*/ 0x1801085cU,
+/*00cd*/ 0x0008085dU,
+/*00ce*/ 0x0808085dU,
+/*00cf*/ 0x1002085dU,
+/*00d0*/ 0x1802085dU,
+/*00d1*/ 0x0005085eU,
+/*00d2*/ 0x1005085eU,
+/*00d3*/ 0x1805085eU,
+/*00d4*/ 0x0004085fU,
+/*00d5*/ 0x080b085fU,
+/*00d6*/ 0x1806085fU,
+/*00d7*/ 0x00080860U,
+/*00d8*/ 0x08080860U,
+/*00d9*/ 0x10040860U,
+/*00da*/ 0x18040860U,
+/*00db*/ 0x00060861U,
+/*00dc*/ 0x08040861U,
+/*00dd*/ 0x10050861U,
+/*00de*/ 0x000a0862U,
+/*00df*/ 0x100a0862U,
+/*00e0*/ 0x00080863U,
+/*00e1*/ 0x08010863U,
+/*00e2*/ 0x10040863U,
+/*00e3*/ 0x00020864U,
+/*00e4*/ 0x08030864U,
+/*00e5*/ 0x00050a00U,
+/*00e6*/ 0x08050a00U,
+/*00e7*/ 0x10050a00U,
+/*00e8*/ 0x18050a00U,
+/*00e9*/ 0x00050a01U,
+/*00ea*/ 0x08050a01U,
+/*00eb*/ 0x100b0a01U,
+/*00ec*/ 0x00010a02U,
+/*00ed*/ 0x08030a02U,
+/*00ee*/ 0x00200a03U,
+/*00ef*/ 0x00100a04U,
+/*00f0*/ 0x10040a04U,
+/*00f1*/ 0x000b0a05U,
+/*00f2*/ 0x10070a05U,
+/*00f3*/ 0x00090a06U,
+/*00f4*/ 0x10030a06U,
+/*00f5*/ 0x18030a06U,
+/*00f6*/ 0x00010a07U,
+/*00f7*/ 0x08010a07U,
+/*00f8*/ 0x10070a07U,
+/*00f9*/ 0x18070a07U,
+/*00fa*/ 0x00050a08U,
+/*00fb*/ 0x08010a08U,
+/*00fc*/ 0x10020a08U,
+/*00fd*/ 0x18030a08U,
+/*00fe*/ 0x00010a09U,
+/*00ff*/ 0x080f0a09U,
+/*0100*/ 0x00200a0aU,
+/*0101*/ 0x00200a0bU,
+/*0102*/ 0x000b0a0cU,
+/*0103*/ 0x100b0a0cU,
+/*0104*/ 0x000b0a0dU,
+/*0105*/ 0x00180a0eU,
+/*0106*/ 0x00180a0fU,
+/*0107*/ 0xffffffffU,
+/*0108*/ 0xffffffffU,
+/*0109*/ 0xffffffffU,
+/*010a*/ 0xffffffffU,
+/*010b*/ 0xffffffffU,
+/*010c*/ 0x18020a0fU,
+/*010d*/ 0x00020a10U,
+/*010e*/ 0x08040a10U,
+/*010f*/ 0x10040a10U,
+/*0110*/ 0x18010a10U,
+/*0111*/ 0x00010a11U,
+/*0112*/ 0x08010a11U,
+/*0113*/ 0x10030a11U,
+/*0114*/ 0x00200a12U,
+/*0115*/ 0x00200a13U,
+/*0116*/ 0xffffffffU,
+/*0117*/ 0x00140a14U,
+/*0118*/ 0x00140a15U,
+/*0119*/ 0x00140a16U,
+/*011a*/ 0x00140a17U,
+/*011b*/ 0x00140a18U,
+/*011c*/ 0x00140a19U,
+/*011d*/ 0x00140a1aU,
+/*011e*/ 0x00140a1bU,
+/*011f*/ 0x001e0a1cU,
+/*0120*/ 0x000a0a1dU,
+/*0121*/ 0x10060a1dU,
+/*0122*/ 0x18060a1dU,
+/*0123*/ 0x00060a1eU,
+/*0124*/ 0x08060a1eU,
+/*0125*/ 0x10060a1eU,
+/*0126*/ 0x00080a1fU,
+/*0127*/ 0x080b0a1fU,
+/*0128*/ 0x000b0a20U,
+/*0129*/ 0x100b0a20U,
+/*012a*/ 0x000b0a21U,
+/*012b*/ 0x100b0a21U,
+/*012c*/ 0x000b0a22U,
+/*012d*/ 0x10040a22U,
+/*012e*/ 0x000b0a23U,
+/*012f*/ 0x10060a23U,
+/*0130*/ 0x18080a23U,
+/*0131*/ 0x00080a24U,
+/*0132*/ 0x08040a24U,
+/*0133*/ 0x00020b80U,
+/*0134*/ 0x00010b81U,
+/*0135*/ 0x08010b81U,
+/*0136*/ 0x10020b81U,
+/*0137*/ 0x18050b81U,
+/*0138*/ 0x00050b82U,
+/*0139*/ 0x08050b82U,
+/*013a*/ 0x10050b82U,
+/*013b*/ 0x000b0b83U,
+/*013c*/ 0x10050b83U,
+/*013d*/ 0x18010b83U,
+/*013e*/ 0x00010b84U,
+/*013f*/ 0x08010b84U,
+/*0140*/ 0x10010b84U,
+/*0141*/ 0x18010b84U,
+/*0142*/ 0x00040b85U,
+/*0143*/ 0x080b0b85U,
+/*0144*/ 0x000b0b86U,
+/*0145*/ 0x100b0b86U,
+/*0146*/ 0x00040b87U,
+/*0147*/ 0x080b0b87U,
+/*0148*/ 0x18040b87U,
+/*0149*/ 0x00010b88U,
+/*014a*/ 0x08010b88U,
+/*014b*/ 0x10010b88U,
+/*014c*/ 0x00200b89U,
+/*014d*/ 0x00200b8aU,
+/*014e*/ 0x00080b8bU,
+/*014f*/ 0x080a0b8bU,
+/*0150*/ 0x18050b8bU,
+/*0151*/ 0x000b0b8cU,
+/*0152*/ 0x10030b8cU,
+/*0153*/ 0x18030b8cU,
+/*0154*/ 0x00010b8dU,
+/*0155*/ 0x08020b8dU,
+/*0156*/ 0x10010b8dU,
+/*0157*/ 0x18010b8dU,
+/*0158*/ 0x00010b8eU,
+/*0159*/ 0xffffffffU,
+/*015a*/ 0x08010b8eU,
+/*015b*/ 0x18040b8eU,
+/*015c*/ 0x00040b8fU,
+/*015d*/ 0x08040b8fU,
+/*015e*/ 0x10040b8fU,
+/*015f*/ 0x18010b8fU,
+/*0160*/ 0x00010b90U,
+/*0161*/ 0x08010b90U,
+/*0162*/ 0x00200b91U,
+/*0163*/ 0x00200b92U,
+/*0164*/ 0x00200b93U,
+/*0165*/ 0x00200b94U,
+/*0166*/ 0xffffffffU,
+/*0167*/ 0x10010b8eU,
+/*0168*/ 0x000d0b96U,
+/*0169*/ 0x100d0b96U,
+/*016a*/ 0x000d0b97U,
+/*016b*/ 0x00050b98U,
+/*016c*/ 0x00010b99U,
+/*016d*/ 0x080e0b99U,
+/*016e*/ 0x000e0b9aU,
+/*016f*/ 0x100e0b9aU,
+/*0170*/ 0x000e0b9bU,
+/*0171*/ 0x100e0b9bU,
+/*0172*/ 0x00040b9cU,
+/*0173*/ 0x08040b9cU,
+/*0174*/ 0x10040b9cU,
+/*0175*/ 0x18040b9cU,
+/*0176*/ 0x00040b9dU,
+/*0177*/ 0x080b0b9dU,
+/*0178*/ 0x000b0b9eU,
+/*0179*/ 0x100b0b9eU,
+/*017a*/ 0x000b0b9fU,
+/*017b*/ 0x00040ba0U,
+/*017c*/ 0x08040ba0U,
+/*017d*/ 0x10040ba0U,
+/*017e*/ 0x18040ba0U,
+/*017f*/ 0x000d0ba1U,
+/*0180*/ 0x100d0ba1U,
+/*0181*/ 0x000d0ba2U,
+/*0182*/ 0x10100ba2U,
+/*0183*/ 0x00080b95U,
+/*0184*/ 0x08080b95U,
+/*0185*/ 0x00100ba3U,
+/*0186*/ 0x10100ba3U,
+/*0187*/ 0x00100ba4U,
+/*0188*/ 0x10100ba4U,
+/*0189*/ 0x00100ba5U,
+/*018a*/ 0x10030ba5U,
+/*018b*/ 0x18040ba5U,
+/*018c*/ 0x00010ba6U,
+/*018d*/ 0x08080ba6U,
+/*018e*/ 0x10010ba6U,
+/*018f*/ 0x000a0ba7U,
+/*0190*/ 0x10010ba7U,
+/*0191*/ 0x00140ba8U,
+/*0192*/ 0x000b0ba9U,
+/*0193*/ 0x100c0ba9U,
+/*0194*/ 0x00120baaU,
+/*0195*/ 0x00140babU,
+/*0196*/ 0x00120bacU,
+/*0197*/ 0x00110badU,
+/*0198*/ 0x00110baeU,
+/*0199*/ 0x00120bafU,
+/*019a*/ 0x00120bb0U,
+/*019b*/ 0x00120bb1U,
+/*019c*/ 0x00120bb2U,
+/*019d*/ 0x00120bb3U,
+/*019e*/ 0x00120bb4U,
+/*019f*/ 0x00120bb5U,
+/*01a0*/ 0x00120bb6U,
+/*01a1*/ 0x00120bb7U,
+/*01a2*/ 0x00120bb8U,
+/*01a3*/ 0x000e0bb9U,
+/*01a4*/ 0x100d0bb9U,
+/*01a5*/ 0x00200bbaU,
+/*01a6*/ 0x00170bbbU,
+/*01a7*/ 0x000d0bbcU,
+/*01a8*/ 0x10010bbcU,
+/*01a9*/ 0x18010bbcU,
+/*01aa*/ 0x00200bbdU,
+/*01ab*/ 0x00080bbeU,
+/*01ac*/ 0x08030bbeU,
+/*01ad*/ 0x10030bbeU,
+/*01ae*/ 0x00180bbfU,
+/*01af*/ 0x00180bc0U,
+/*01b0*/ 0x18070bc0U,
+/*01b1*/ 0x00070bc1U,
+/*01b2*/ 0x08080bc1U,
+/*01b3*/ 0x10080bc1U,
+/*01b4*/ 0x18080bc1U,
+/*01b5*/ 0x00010bc2U,
+/*01b6*/ 0x08010bc2U,
+/*01b7*/ 0x00200bc3U,
+/*01b8*/ 0x00070bc4U,
+/*01b9*/ 0x08140bc4U,
+/*01ba*/ 0x00140bc5U,
+/*01bb*/ 0x00190bc6U,
+/*01bc*/ 0x00170bc7U,
+/*01bd*/ 0x00110bc8U,
+/*01be*/ 0x00110bc9U,
+/*01bf*/ 0x00100bcaU,
+/*01c0*/ 0x10010bcaU,
+/*01c1*/ 0x18010bcaU,
+/*01c2*/ 0x00020bcbU,
+/*01c3*/ 0x08040bcbU,
+/*01c4*/ 0x10090bcbU,
+/*01c5*/ 0x00070bccU,
+/*01c6*/ 0x08040bccU,
+/*01c7*/ 0x00200bcdU,
+/*01c8*/ 0x00010bceU,
+/*01c9*/ 0x08020bceU,
+/*01ca*/ 0x10060bceU,
+/*01cb*/ 0x00100bcfU,
+/*01cc*/ 0x10010bcfU,
+/*01cd*/ 0x00200bd0U,
+/*01ce*/ 0x00080bd1U,
+/*01cf*/ 0x08010bd1U,
+/*01d0*/ 0x10050bd1U,
+/*01d1*/ 0x18030bd1U,
+/*01d2*/ 0x00020bd2U,
+/*01d3*/ 0xffffffffU,
+/*01d4*/ 0x00200bd3U,
+/*01d5*/ 0x000b0bd4U,
+/*01d6*/ 0xffffffffU,
+/*01d7*/ 0x10030bd4U,
+/*01d8*/ 0x18080bd4U,
+/*01d9*/ 0x00020bd5U,
+/*01da*/ 0x080c0bd5U,
+/*01db*/ 0x18040bd5U,
+/*01dc*/ 0x00010bd6U,
+/*01dd*/ 0x08050bd6U,
+/*01de*/ 0x00010200U,
+/*01df*/ 0x08040200U,
+/*01e0*/ 0x10100200U,
+/*01e1*/ 0x00010201U,
+/*01e2*/ 0x08010201U,
+/*01e3*/ 0x10010201U,
+/*01e4*/ 0x18010201U,
+/*01e5*/ 0x00100202U,
+/*01e6*/ 0x10080202U,
+/*01e7*/ 0x18010202U,
+/*01e8*/ 0x00200203U,
+/*01e9*/ 0x00200204U,
+/*01ea*/ 0x00200205U,
+/*01eb*/ 0x00200206U,
+/*01ec*/ 0x00020207U,
+/*01ed*/ 0x08010207U,
+/*01ee*/ 0x10010207U,
+/*01ef*/ 0x00200208U,
+/*01f0*/ 0x00140209U,
+/*01f1*/ 0x0020020aU,
+/*01f2*/ 0x0014020bU,
+/*01f3*/ 0x0020020cU,
+/*01f4*/ 0x0014020dU,
+/*01f5*/ 0x0014020eU,
+/*01f6*/ 0x0020020fU,
+/*01f7*/ 0x00200210U,
+/*01f8*/ 0x00200211U,
+/*01f9*/ 0x00200212U,
+/*01fa*/ 0x00140213U,
+/*01fb*/ 0x00200214U,
+/*01fc*/ 0x00200215U,
+/*01fd*/ 0x00200216U,
+/*01fe*/ 0x00200217U,
+/*01ff*/ 0x00140218U,
+/*0200*/ 0x00200219U,
+/*0201*/ 0x0020021aU,
+/*0202*/ 0x0020021bU,
+/*0203*/ 0x0020021cU,
+/*0204*/ 0x0009021dU,
+/*0205*/ 0x1001021dU,
+/*0206*/ 0x0020021eU,
+/*0207*/ 0x0005021fU,
+/*0208*/ 0x0801021fU,
+/*0209*/ 0x1008021fU,
+/*020a*/ 0x1808021fU,
+/*020b*/ 0x001e0220U,
+/*020c*/ 0x001e0221U,
+/*020d*/ 0x001e0222U,
+/*020e*/ 0x001e0223U,
+/*020f*/ 0x001e0224U,
+/*0210*/ 0x001e0225U,
+/*0211*/ 0x001e0226U,
+/*0212*/ 0x001e0227U,
+/*0213*/ 0x001e0228U,
+/*0214*/ 0x001e0229U,
+/*0215*/ 0x001e022aU,
+/*0216*/ 0x001e022bU,
+/*0217*/ 0x001e022cU,
+/*0218*/ 0x001e022dU,
+/*0219*/ 0x001e022eU,
+/*021a*/ 0x001e022fU,
+/*021b*/ 0x00010230U,
+/*021c*/ 0x08010230U,
+/*021d*/ 0x10010230U,
+/*021e*/ 0x18040230U,
+/*021f*/ 0x00080231U,
+/*0220*/ 0x08080231U,
+/*0221*/ 0x10080231U,
+/*0222*/ 0x18040231U,
+/*0223*/ 0x00070232U,
+/*0224*/ 0x08060232U,
+/*0225*/ 0x10070232U,
+/*0226*/ 0x18070232U,
+/*0227*/ 0x00060233U,
+/*0228*/ 0x08070233U,
+/*0229*/ 0x10070233U,
+/*022a*/ 0x18060233U,
+/*022b*/ 0x00070234U,
+/*022c*/ 0x08020234U,
+/*022d*/ 0x10010234U,
+/*022e*/ 0x18010234U,
+/*022f*/ 0x000a0235U,
+/*0230*/ 0x00140236U,
+/*0231*/ 0x000a0237U,
+/*0232*/ 0x00140238U,
+/*0233*/ 0x000a0239U,
+/*0234*/ 0x0014023aU,
+/*0235*/ 0xffffffffU,
+/*0236*/ 0xffffffffU,
+/*0237*/ 0x0005023bU,
+/*0238*/ 0x0001023cU,
+/*0239*/ 0x1001023cU,
+/*023a*/ 0x1801023cU,
+/*023b*/ 0x0001023dU,
+/*023c*/ 0x0801023dU,
+/*023d*/ 0x1001023dU,
+/*023e*/ 0x1801023dU,
+/*023f*/ 0x0002023eU,
+/*0240*/ 0x0802023eU,
+/*0241*/ 0x1002023eU,
+/*0242*/ 0x1802023eU,
+/*0243*/ 0x0002023fU,
+/*0244*/ 0x0803023fU,
+/*0245*/ 0x1001023fU,
+/*0246*/ 0x1801023fU,
+/*0247*/ 0x00010240U,
+/*0248*/ 0x08010240U,
+/*0249*/ 0x10010240U,
+/*024a*/ 0x18020240U,
+/*024b*/ 0x00010241U,
+/*024c*/ 0x08010241U,
+/*024d*/ 0x10010241U,
+/*024e*/ 0x18020241U,
+/*024f*/ 0x00010242U,
+/*0250*/ 0x08010242U,
+/*0251*/ 0x10010242U,
+/*0252*/ 0x18020242U,
+/*0253*/ 0x00010243U,
+/*0254*/ 0x08010243U,
+/*0255*/ 0x10010243U,
+/*0256*/ 0x18020243U,
+/*0257*/ 0xffffffffU,
+/*0258*/ 0x00010244U,
+/*0259*/ 0x08010244U,
+/*025a*/ 0x10010244U,
+/*025b*/ 0x18010244U,
+/*025c*/ 0x00010245U,
+/*025d*/ 0x08010245U,
+/*025e*/ 0x10010245U,
+/*025f*/ 0x18010245U,
+/*0260*/ 0x00040246U,
+/*0261*/ 0x08040246U,
+/*0262*/ 0x10040246U,
+/*0263*/ 0x18010246U,
+/*0264*/ 0x00020247U,
+/*0265*/ 0x08060247U,
+/*0266*/ 0x10060247U,
+/*0267*/ 0x18020247U,
+/*0268*/ 0x00020248U,
+/*0269*/ 0x08020248U,
+/*026a*/ 0xffffffffU,
+/*026b*/ 0x10100248U,
+/*026c*/ 0x00010249U,
+/*026d*/ 0x08010249U,
+/*026e*/ 0x10010249U,
+/*026f*/ 0x18040249U,
+/*0270*/ 0x0001024aU,
+/*0271*/ 0x0804024aU,
+/*0272*/ 0x1003024aU,
+/*0273*/ 0x1808024aU,
+/*0274*/ 0x000a024bU,
+/*0275*/ 0x100a024bU,
+/*0276*/ 0x000a024cU,
+/*0277*/ 0xffffffffU,
+/*0278*/ 0x0020024dU,
+/*0279*/ 0x0020024eU,
+/*027a*/ 0x0005024fU,
+/*027b*/ 0x1801023aU,
+/*027c*/ 0x0805023cU,
+/*027d*/ 0x0808024fU,
+/*027e*/ 0x1001024fU,
+/*027f*/ 0x1808024fU,
+/*0280*/ 0x00010250U,
+/*0281*/ 0x08080250U,
+/*0282*/ 0x10010250U,
+/*0283*/ 0x18040250U,
+/*0284*/ 0x00040251U,
+/*0285*/ 0x08040251U,
+/*0286*/ 0x10040251U,
+/*0287*/ 0x18040251U,
+/*0288*/ 0x00040252U,
+/*0289*/ 0x08040252U,
+/*028a*/ 0x10040252U,
+/*028b*/ 0x18040252U,
+/*028c*/ 0x00040253U,
+/*028d*/ 0x08010253U,
+/*028e*/ 0x10040253U,
+/*028f*/ 0x18040253U,
+/*0290*/ 0x00040254U,
+/*0291*/ 0x08040254U,
+/*0292*/ 0x10040254U,
+/*0293*/ 0x18040254U,
+/*0294*/ 0x00060255U,
+/*0295*/ 0x08060255U,
+/*0296*/ 0x10060255U,
+/*0297*/ 0x18060255U,
+/*0298*/ 0x00060256U,
+/*0299*/ 0x08060256U,
+/*029a*/ 0x10040256U,
+/*029b*/ 0x18010256U,
+/*029c*/ 0x00010257U,
+/*029d*/ 0x08020257U,
+/*029e*/ 0x00200258U,
+/*029f*/ 0x00200259U,
+/*02a0*/ 0x0020025aU,
+/*02a1*/ 0x0020025bU,
+/*02a2*/ 0x0020025cU,
+/*02a3*/ 0x0020025dU,
+/*02a4*/ 0x0020025eU,
+/*02a5*/ 0x0020025fU,
+/*02a6*/ 0x00040260U,
+/*02a7*/ 0x08040260U,
+/*02a8*/ 0x10010260U,
+/*02a9*/ 0x18010260U,
+/*02aa*/ 0x00010261U,
+/*02ab*/ 0x08010261U,
+/*02ac*/ 0x10010261U,
+/*02ad*/ 0x18010261U,
+/*02ae*/ 0x00010262U,
+/*02af*/ 0x08010262U,
+/*02b0*/ 0x10010262U,
+/*02b1*/ 0x18040262U,
+/*02b2*/ 0x00040263U,
+/*02b3*/ 0x080a0263U,
+/*02b4*/ 0x00200264U,
+/*02b5*/ 0x00040265U,
+/*02b6*/ 0x08080265U,
+/*02b7*/ 0x10020265U,
+/*02b8*/ 0x18020265U,
+/*02b9*/ 0x00020266U,
+/*02ba*/ 0x08020266U,
+/*02bb*/ 0x10020266U,
+/*02bc*/ 0x18020266U,
+/*02bd*/ 0xffffffffU,
+/*02be*/ 0xffffffffU,
+/*02bf*/ 0x00200267U,
+/*02c0*/ 0x00030268U,
+/*02c1*/ 0x08100268U,
+/*02c2*/ 0x00100269U,
+/*02c3*/ 0x10040269U,
+/*02c4*/ 0x18040269U,
+/*02c5*/ 0x0005026aU,
+/*02c6*/ 0x0805026aU,
+/*02c7*/ 0xffffffffU,
+/*02c8*/ 0xffffffffU,
+/*02c9*/ 0xffffffffU,
+/*02ca*/ 0xffffffffU,
+/*02cb*/ 0x1001026aU,
+/*02cc*/ 0x1801026aU,
+/*02cd*/ 0x0008026bU,
+/*02ce*/ 0x0808026bU,
+/*02cf*/ 0x1008026bU,
+/*02d0*/ 0x1808026bU,
+/*02d1*/ 0x0008026cU,
+/*02d2*/ 0x0808026cU,
+/*02d3*/ 0x1008026cU,
+/*02d4*/ 0x1808026cU,
+/*02d5*/ 0x0008026dU,
+/*02d6*/ 0x0808026dU,
+/*02d7*/ 0x1008026dU,
+/*02d8*/ 0x1808026dU,
+/*02d9*/ 0x0008026eU,
+/*02da*/ 0x0808026eU,
+/*02db*/ 0x1003026eU,
+/*02dc*/ 0x1803026eU,
+/*02dd*/ 0x0003026fU,
+/*02de*/ 0xffffffffU,
+/*02df*/ 0x0801026fU,
+/*02e0*/ 0x1002026fU,
+/*02e1*/ 0x1801026fU,
+/*02e2*/ 0x00040270U,
+/*02e3*/ 0x08020270U,
+/*02e4*/ 0x10010270U,
+/*02e5*/ 0x18010270U,
+/*02e6*/ 0x00010271U,
+/*02e7*/ 0x08010271U,
+/*02e8*/ 0x10040271U,
+/*02e9*/ 0x18080271U,
+/*02ea*/ 0x000a0272U,
+/*02eb*/ 0x100a0272U,
+/*02ec*/ 0x000a0273U,
+/*02ed*/ 0x100a0273U,
+/*02ee*/ 0x000a0274U,
+/*02ef*/ 0x100a0274U,
+/*02f0*/ 0x00200275U,
+/*02f1*/ 0x00200276U,
+/*02f2*/ 0x00010277U,
+/*02f3*/ 0x08020277U,
+/*02f4*/ 0x10020277U,
+/*02f5*/ 0x18020277U,
+/*02f6*/ 0xffffffffU,
+/*02f7*/ 0x00020278U,
+/*02f8*/ 0x08100278U,
+/*02f9*/ 0x18050278U,
+/*02fa*/ 0x00060279U,
+/*02fb*/ 0x08050279U,
+/*02fc*/ 0x10050279U,
+/*02fd*/ 0x000e027aU,
+/*02fe*/ 0x1005027aU,
+/*02ff*/ 0x000e027bU,
+/*0300*/ 0x1005027bU,
+/*0301*/ 0x000e027cU,
+/*0302*/ 0x1005027cU,
+/*0303*/ 0x1801027cU,
+/*0304*/ 0x0005027dU,
+/*0305*/ 0x0805027dU,
+/*0306*/ 0x100a027dU,
+/*0307*/ 0x000a027eU,
+/*0308*/ 0x1005027eU,
+/*0309*/ 0x1805027eU,
+/*030a*/ 0x000a027fU,
+/*030b*/ 0x100a027fU,
+/*030c*/ 0x00050280U,
+/*030d*/ 0x08050280U,
+/*030e*/ 0x100a0280U,
+/*030f*/ 0x000a0281U,
+/*0310*/ 0x10070281U,
+/*0311*/ 0x18070281U,
+/*0312*/ 0x00070282U,
+/*0313*/ 0x08070282U,
+/*0314*/ 0x10070282U,
+/*0315*/ 0x18070282U,
+/*0316*/ 0xffffffffU,
+/*0317*/ 0xffffffffU,
+/*0318*/ 0x00040283U,
+/*0319*/ 0x08040283U,
+/*031a*/ 0x10040283U,
+/*031b*/ 0x18040283U,
+/*031c*/ 0x00040284U,
+/*031d*/ 0xffffffffU,
+/*031e*/ 0x08080284U,
+/*031f*/ 0x10080284U,
+/*0320*/ 0x18040284U,
+/*0321*/ 0x00050285U,
+/*0322*/ 0x08080285U,
+/*0323*/ 0x10050285U,
+/*0324*/ 0x18040285U,
+/*0325*/ 0x00050286U,
+/*0326*/ 0x08080286U,
+/*0327*/ 0x10050286U,
+/*0328*/ 0x18040286U,
+/*0329*/ 0x00050287U,
+/*032a*/ 0x08080287U,
+/*032b*/ 0x10050287U,
+/*032c*/ 0x18040287U,
+/*032d*/ 0x00050288U,
+/*032e*/ 0x08070288U,
+/*032f*/ 0x10080288U,
+/*0330*/ 0x00100289U,
+/*0331*/ 0x10080289U,
+/*0332*/ 0x0010028aU,
+/*0333*/ 0x1008028aU,
+/*0334*/ 0x0010028bU,
+/*0335*/ 0x1008028bU,
+/*0336*/ 0x1808028bU,
+/*0337*/ 0x0001028cU,
+/*0338*/ 0x0801028cU,
+/*0339*/ 0x1006028cU,
+/*033a*/ 0x1806028cU,
+/*033b*/ 0x0006028dU,
+/*033c*/ 0x0801028dU,
+/*033d*/ 0x1001028dU,
+/*033e*/ 0x1803028dU,
+/*033f*/ 0x000a028eU,
+/*0340*/ 0x100a028eU,
+/*0341*/ 0x000a028fU,
+/*0342*/ 0xffffffffU,
+/*0343*/ 0x100a028fU,
+/*0344*/ 0x00040290U,
+/*0345*/ 0x08010290U,
+/*0346*/ 0x10040290U,
+/*0347*/ 0x18070290U,
+/*0348*/ 0x00070291U,
+/*0349*/ 0x08070291U,
+/*034a*/ 0x10070291U,
+/*034b*/ 0x18070291U,
+/*034c*/ 0x00070292U,
+/*034d*/ 0xffffffffU,
+/*034e*/ 0xffffffffU,
+/*034f*/ 0x08050292U,
+/*0350*/ 0x10050292U,
+/*0351*/ 0x18040292U,
+/*0352*/ 0x00040293U,
+/*0353*/ 0x08040293U,
+/*0354*/ 0xffffffffU,
+/*0355*/ 0x10010293U,
+/*0356*/ 0x18010293U,
+/*0357*/ 0x00020294U,
+/*0358*/ 0x08080294U,
+/*0359*/ 0x00200295U,
+/*035a*/ 0x00200296U,
+/*035b*/ 0x00100297U,
+/*035c*/ 0x10020297U,
+/*035d*/ 0x18020297U,
+/*035e*/ 0x00020298U,
+/*035f*/ 0xffffffffU,
+/*0360*/ 0x08010298U,
+/*0361*/ 0x10010298U,
+/*0362*/ 0x18020298U,
+/*0363*/ 0x00100299U,
+/*0364*/ 0x10100299U,
+/*0365*/ 0x0010029aU,
+/*0366*/ 0x1008029aU,
+/*0367*/ 0x1808029aU,
+/*0368*/ 0x0008029bU,
+/*0369*/ 0x0808029bU,
+/*036a*/ 0x1010029bU,
+/*036b*/ 0x0010029cU,
+/*036c*/ 0x1010029cU,
+/*036d*/ 0x0008029dU,
+/*036e*/ 0x0808029dU,
+/*036f*/ 0x1008029dU,
+/*0370*/ 0x1808029dU,
+/*0371*/ 0x0010029eU,
+/*0372*/ 0x1010029eU,
+/*0373*/ 0x0010029fU,
+/*0374*/ 0x1008029fU,
+/*0375*/ 0x1808029fU,
+/*0376*/ 0x000802a0U,
+/*0377*/ 0x080802a0U,
+/*0378*/ 0x100802a0U,
+/*0379*/ 0x001002a1U,
+/*037a*/ 0x101002a1U,
+/*037b*/ 0x001002a2U,
+/*037c*/ 0x100802a2U,
+/*037d*/ 0x180802a2U,
+/*037e*/ 0x000802a3U,
+/*037f*/ 0x080802a3U,
+/*0380*/ 0x101002a3U,
+/*0381*/ 0x001002a4U,
+/*0382*/ 0x101002a4U,
+/*0383*/ 0x000802a5U,
+/*0384*/ 0x080802a5U,
+/*0385*/ 0x100802a5U,
+/*0386*/ 0x180802a5U,
+/*0387*/ 0x001002a6U,
+/*0388*/ 0x101002a6U,
+/*0389*/ 0x001002a7U,
+/*038a*/ 0x100802a7U,
+/*038b*/ 0x180802a7U,
+/*038c*/ 0x000802a8U,
+/*038d*/ 0x080802a8U,
+/*038e*/ 0x100802a8U,
+/*038f*/ 0x001002a9U,
+/*0390*/ 0x101002a9U,
+/*0391*/ 0x001002aaU,
+/*0392*/ 0x100802aaU,
+/*0393*/ 0x180802aaU,
+/*0394*/ 0x000802abU,
+/*0395*/ 0x080802abU,
+/*0396*/ 0x101002abU,
+/*0397*/ 0x001002acU,
+/*0398*/ 0x101002acU,
+/*0399*/ 0x000802adU,
+/*039a*/ 0x080802adU,
+/*039b*/ 0x100802adU,
+/*039c*/ 0x180802adU,
+/*039d*/ 0x001002aeU,
+/*039e*/ 0x101002aeU,
+/*039f*/ 0x001002afU,
+/*03a0*/ 0x100802afU,
+/*03a1*/ 0x180802afU,
+/*03a2*/ 0x000802b0U,
+/*03a3*/ 0x080802b0U,
+/*03a4*/ 0x100802b0U,
+/*03a5*/ 0x001002b1U,
+/*03a6*/ 0x101002b1U,
+/*03a7*/ 0x001002b2U,
+/*03a8*/ 0x100802b2U,
+/*03a9*/ 0x180802b2U,
+/*03aa*/ 0x000802b3U,
+/*03ab*/ 0x080802b3U,
+/*03ac*/ 0x101002b3U,
+/*03ad*/ 0x001002b4U,
+/*03ae*/ 0x101002b4U,
+/*03af*/ 0x000802b5U,
+/*03b0*/ 0x080802b5U,
+/*03b1*/ 0x100802b5U,
+/*03b2*/ 0x180802b5U,
+/*03b3*/ 0x001002b6U,
+/*03b4*/ 0x101002b6U,
+/*03b5*/ 0x001002b7U,
+/*03b6*/ 0x100802b7U,
+/*03b7*/ 0x180802b7U,
+/*03b8*/ 0x000802b8U,
+/*03b9*/ 0x080802b8U,
+/*03ba*/ 0x100802b8U,
+/*03bb*/ 0x180202b8U,
+/*03bc*/ 0x000302b9U,
+/*03bd*/ 0x080a02b9U,
+/*03be*/ 0x000a02baU,
+/*03bf*/ 0x100a02baU,
+/*03c0*/ 0x000502bbU,
+/*03c1*/ 0x080802bbU,
+/*03c2*/ 0x100802bbU,
+/*03c3*/ 0x180802bbU,
+/*03c4*/ 0x000602bcU,
+/*03c5*/ 0x080602bcU,
+/*03c6*/ 0x001102bdU,
+/*03c7*/ 0x180802bdU,
+/*03c8*/ 0x000402beU,
+/*03c9*/ 0x080602beU,
+/*03ca*/ 0x100802beU,
+/*03cb*/ 0x180802beU,
+/*03cc*/ 0x000802bfU,
+/*03cd*/ 0x080802bfU,
+/*03ce*/ 0x100802bfU,
+/*03cf*/ 0x180802bfU,
+/*03d0*/ 0x000802c0U,
+/*03d1*/ 0x080602c0U,
+/*03d2*/ 0x100602c0U,
+/*03d3*/ 0x001102c1U,
+/*03d4*/ 0x180802c1U,
+/*03d5*/ 0x000402c2U,
+/*03d6*/ 0x080602c2U,
+/*03d7*/ 0x100802c2U,
+/*03d8*/ 0x180802c2U,
+/*03d9*/ 0x000802c3U,
+/*03da*/ 0x080802c3U,
+/*03db*/ 0x100802c3U,
+/*03dc*/ 0x180802c3U,
+/*03dd*/ 0x000802c4U,
+/*03de*/ 0x080602c4U,
+/*03df*/ 0x100602c4U,
+/*03e0*/ 0x001102c5U,
+/*03e1*/ 0x180802c5U,
+/*03e2*/ 0x000402c6U,
+/*03e3*/ 0x080602c6U,
+/*03e4*/ 0x100802c6U,
+/*03e5*/ 0x180802c6U,
+/*03e6*/ 0x000802c7U,
+/*03e7*/ 0x080802c7U,
+/*03e8*/ 0x100402c7U,
+/*03e9*/ 0x180402c7U,
+/*03ea*/ 0x000402c8U,
+/*03eb*/ 0x080402c8U,
+/*03ec*/ 0x100402c8U,
+/*03ed*/ 0x180402c8U,
+/*03ee*/ 0x000402c9U,
+/*03ef*/ 0x080402c9U,
+/*03f0*/ 0x100402c9U,
+/*03f1*/ 0x180402c9U,
+/*03f2*/ 0x000402caU,
+/*03f3*/ 0x080402caU,
+/*03f4*/ 0x100402caU,
+/*03f5*/ 0x180402caU,
+/*03f6*/ 0x000402cbU,
+/*03f7*/ 0x080402cbU,
+/*03f8*/ 0x100402cbU,
+/*03f9*/ 0x180402cbU,
+/*03fa*/ 0x000402ccU,
+/*03fb*/ 0x080402ccU,
+/*03fc*/ 0x001702cdU,
+/*03fd*/ 0x001602ceU,
+/*03fe*/ 0x001702cfU,
+/*03ff*/ 0x002002d0U,
+/*0400*/ 0x002002d1U,
+/*0401*/ 0x002002d2U,
+/*0402*/ 0x002002d3U,
+/*0403*/ 0x002002d4U,
+/*0404*/ 0x002002d5U,
+/*0405*/ 0x002002d6U,
+/*0406*/ 0x002002d7U,
+/*0407*/ 0x002002d8U,
+/*0408*/ 0x000202d9U,
+/*0409*/ 0x080502d9U,
+/*040a*/ 0x100502d9U,
+/*040b*/ 0x180102d9U,
+/*040c*/ 0x000502daU,
+/*040d*/ 0x080502daU,
+/*040e*/ 0x100502daU,
+/*040f*/ 0x180502daU,
+/*0410*/ 0x000502dbU,
+/*0411*/ 0x080502dbU,
+/*0412*/ 0x100502dbU,
+/*0413*/ 0x180502dbU,
+/*0414*/ 0x000502dcU,
+/*0415*/ 0x080502dcU,
+/*0416*/ 0x100502dcU,
+/*0417*/ 0x180502dcU,
+/*0418*/ 0x000502ddU,
+/*0419*/ 0x080502ddU,
+/*041a*/ 0x100502ddU,
+/*041b*/ 0x180502ddU,
+/*041c*/ 0x000502deU,
+/*041d*/ 0x080502deU,
+/*041e*/ 0x100502deU,
+/*041f*/ 0x180502deU,
+/*0420*/ 0x000502dfU,
+/*0421*/ 0x080502dfU,
+/*0422*/ 0x100102dfU,
+/*0423*/ 0x180202dfU,
+/*0424*/ 0x000202e0U,
+/*0425*/ 0x080202e0U,
+/*0426*/ 0x100202e0U,
+/*0427*/ 0x180102e0U,
+/*0428*/ 0x000802e1U,
+/*0429*/ 0x081502e1U,
+/*042a*/ 0x002002e2U,
+/*042b*/ 0x001502e3U,
+/*042c*/ 0x002002e4U,
+/*042d*/ 0x001502e5U,
+/*042e*/ 0x002002e6U,
+/*042f*/ 0x000702e7U,
+/*0430*/ 0x080102e7U,
+/*0431*/ 0x100202e7U,
+/*0432*/ 0x180602e7U,
+/*0433*/ 0x000102e8U,
+/*0434*/ 0x080102e8U,
+/*0435*/ 0x002002e9U,
+/*0436*/ 0x000202eaU,
+/*0437*/ 0x002002ebU,
+/*0438*/ 0x002002ecU,
+/*0439*/ 0x000c02edU,
+/*043a*/ 0x100c02edU,
+/*043b*/ 0x002002eeU,
+/*043c*/ 0x000302efU,
+/*043d*/ 0x002002f0U,
+/*043e*/ 0x000302f1U,
+/*043f*/ 0x002002f2U,
+/*0440*/ 0x000302f3U,
+/*0441*/ 0x002002f4U,
+/*0442*/ 0x000302f5U,
+/*0443*/ 0x002002f6U,
+/*0444*/ 0x000302f7U,
+/*0445*/ 0x002002f8U,
+/*0446*/ 0x000302f9U,
+/*0447*/ 0x002002faU,
+/*0448*/ 0x000302fbU,
+/*0449*/ 0x002002fcU,
+/*044a*/ 0x000302fdU,
+/*044b*/ 0x002002feU,
+/*044c*/ 0x000302ffU,
+/*044d*/ 0x00200300U,
+/*044e*/ 0x00030301U,
+/*044f*/ 0x08030301U,
+/*0450*/ 0x10020301U,
+/*0451*/ 0x18020301U,
+/*0452*/ 0x00200302U,
+/*0453*/ 0x00200303U,
+/*0454*/ 0x00200304U,
+/*0455*/ 0x00200305U,
+/*0456*/ 0x00040306U,
+/*0457*/ 0x001e0307U,
+/*0458*/ 0x001e0308U,
+/*0459*/ 0x001e0309U,
+/*045a*/ 0x001e030aU,
+/*045b*/ 0x001e030bU,
+/*045c*/ 0x001e030cU,
+/*045d*/ 0x001e030dU,
+/*045e*/ 0x001e030eU,
+/*045f*/ 0x0004030fU,
+/*0460*/ 0x0801030fU,
+/*0461*/ 0x1010030fU,
+/*0462*/ 0x00100310U,
+/*0463*/ 0x10100310U,
+/*0464*/ 0x00040311U,
+/*0465*/ 0x08010311U,
+/*0466*/ 0x10080311U,
+/*0467*/ 0x18040311U,
+/*0468*/ 0x00010312U,
+/*0469*/ 0x08080312U,
+/*046a*/ 0x10040312U,
+/*046b*/ 0x18010312U,
+/*046c*/ 0x00080313U,
+/*046d*/ 0x08040313U,
+/*046e*/ 0x10010313U,
+/*046f*/ 0x18080313U,
+/*0470*/ 0x00040314U,
+/*0471*/ 0x08010314U,
+/*0472*/ 0x10080314U,
+/*0473*/ 0x18040314U,
+/*0474*/ 0x00010315U,
+/*0475*/ 0x08080315U,
+/*0476*/ 0x10040315U,
+/*0477*/ 0x18010315U,
+/*0478*/ 0x00080316U,
+/*0479*/ 0x08040316U,
+/*047a*/ 0x10010316U,
+/*047b*/ 0x18080316U,
+/*047c*/ 0x00080317U,
+/*047d*/ 0x00010318U,
+/*047e*/ 0x08050318U,
+/*047f*/ 0x10010318U,
+/*0480*/ 0x18020318U,
+/*0481*/ 0x00010319U,
+/*0482*/ 0x08010319U,
+/*0483*/ 0x10010319U,
+/*0484*/ 0x18010319U,
+/*0485*/ 0x0001031aU,
+/*0486*/ 0x0801031aU,
+/*0487*/ 0x1001031aU,
+/*0488*/ 0x1801031aU,
+/*0489*/ 0x0001031bU,
+/*048a*/ 0x0801031bU,
+/*048b*/ 0x1001031bU,
+/*048c*/ 0x1801031bU,
+/*048d*/ 0x0001031cU,
+/*048e*/ 0x0801031cU,
+/*048f*/ 0x1001031cU,
+/*0490*/ 0x1801031cU,
+/*0491*/ 0x0008031dU,
+/*0492*/ 0x0808031dU,
+/*0493*/ 0x1008031dU,
+/*0494*/ 0x1808031dU,
+	 }
+};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
new file mode 100644
index 0000000..39fc8a6
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_H3  0x0400
+#define DDR_PHY_ADR_V_REGSET_OFS_H3  0x0600
+#define DDR_PHY_ADR_I_REGSET_OFS_H3  0x0680
+#define DDR_PHY_ADR_G_REGSET_OFS_H3  0x0700
+#define DDR_PI_REGSET_OFS_H3         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80
+#define DDR_PI_REGSET_SIZE_H3        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_H3  88
+#define DDR_PHY_ADR_V_REGSET_NUM_H3  37
+#define DDR_PHY_ADR_I_REGSET_NUM_H3  37
+#define DDR_PHY_ADR_G_REGSET_NUM_H3  59
+#define DDR_PI_REGSET_NUM_H3         181
+
+static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = {
+/*0400*/ 0x000004f0,
+/*0401*/ 0x00000000,
+/*0402*/ 0x00000000,
+/*0403*/ 0x00000100,
+/*0404*/ 0x01003c0c,
+/*0405*/ 0x02003c0c,
+/*0406*/ 0x00010300,
+/*0407*/ 0x04000100,
+/*0408*/ 0x00000300,
+/*0409*/ 0x000700c0,
+/*040a*/ 0x00b00201,
+/*040b*/ 0x00000020,
+/*040c*/ 0x00000000,
+/*040d*/ 0x00000000,
+/*040e*/ 0x00000000,
+/*040f*/ 0x00000000,
+/*0410*/ 0x00000000,
+/*0411*/ 0x00000000,
+/*0412*/ 0x00000000,
+/*0413*/ 0x09000000,
+/*0414*/ 0x04080000,
+/*0415*/ 0x04080400,
+/*0416*/ 0x00000000,
+/*0417*/ 0x32103210,
+/*0418*/ 0x00800708,
+/*0419*/ 0x000f000c,
+/*041a*/ 0x00000100,
+/*041b*/ 0x55aa55aa,
+/*041c*/ 0x33cc33cc,
+/*041d*/ 0x0ff00ff0,
+/*041e*/ 0x0f0ff0f0,
+/*041f*/ 0x00008e38,
+/*0420*/ 0x76543210,
+/*0421*/ 0x00000001,
+/*0422*/ 0x00000000,
+/*0423*/ 0x00000000,
+/*0424*/ 0x00000000,
+/*0425*/ 0x00000000,
+/*0426*/ 0x00000000,
+/*0427*/ 0x00000000,
+/*0428*/ 0x00000000,
+/*0429*/ 0x00000000,
+/*042a*/ 0x00000000,
+/*042b*/ 0x00000000,
+/*042c*/ 0x00000000,
+/*042d*/ 0x00000000,
+/*042e*/ 0x00000000,
+/*042f*/ 0x00000000,
+/*0430*/ 0x00000000,
+/*0431*/ 0x00000000,
+/*0432*/ 0x00000000,
+/*0433*/ 0x00200000,
+/*0434*/ 0x08200820,
+/*0435*/ 0x08200820,
+/*0436*/ 0x08200820,
+/*0437*/ 0x08200820,
+/*0438*/ 0x08200820,
+/*0439*/ 0x00000820,
+/*043a*/ 0x03000300,
+/*043b*/ 0x03000300,
+/*043c*/ 0x03000300,
+/*043d*/ 0x03000300,
+/*043e*/ 0x00000300,
+/*043f*/ 0x00000000,
+/*0440*/ 0x00000000,
+/*0441*/ 0x00000000,
+/*0442*/ 0x00000000,
+/*0443*/ 0x00a000a0,
+/*0444*/ 0x00a000a0,
+/*0445*/ 0x00a000a0,
+/*0446*/ 0x00a000a0,
+/*0447*/ 0x00a000a0,
+/*0448*/ 0x00a000a0,
+/*0449*/ 0x00a000a0,
+/*044a*/ 0x00a000a0,
+/*044b*/ 0x00a000a0,
+/*044c*/ 0x01040109,
+/*044d*/ 0x00000200,
+/*044e*/ 0x01000000,
+/*044f*/ 0x00000200,
+/*0450*/ 0x4041a141,
+/*0451*/ 0xc00141a0,
+/*0452*/ 0x0e0100c0,
+/*0453*/ 0x0010000c,
+/*0454*/ 0x0c064208,
+/*0455*/ 0x000f0c18,
+/*0456*/ 0x00e00140,
+/*0457*/ 0x00000c20
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = {
+/*0600*/ 0x00000000,
+/*0601*/ 0x00000000,
+/*0602*/ 0x00000000,
+/*0603*/ 0x00000000,
+/*0604*/ 0x00000000,
+/*0605*/ 0x00000000,
+/*0606*/ 0x00000002,
+/*0607*/ 0x00000000,
+/*0608*/ 0x00000000,
+/*0609*/ 0x00000000,
+/*060a*/ 0x00400320,
+/*060b*/ 0x00000040,
+/*060c*/ 0x00dcba98,
+/*060d*/ 0x00000000,
+/*060e*/ 0x00dcba98,
+/*060f*/ 0x01000000,
+/*0610*/ 0x00020003,
+/*0611*/ 0x00000000,
+/*0612*/ 0x00000000,
+/*0613*/ 0x00000000,
+/*0614*/ 0x00002a01,
+/*0615*/ 0x00000015,
+/*0616*/ 0x00000015,
+/*0617*/ 0x0000002a,
+/*0618*/ 0x00000033,
+/*0619*/ 0x0000000c,
+/*061a*/ 0x0000000c,
+/*061b*/ 0x00000033,
+/*061c*/ 0x00418820,
+/*061d*/ 0x003f0000,
+/*061e*/ 0x0000003f,
+/*061f*/ 0x0002006e,
+/*0620*/ 0x02000200,
+/*0621*/ 0x02000200,
+/*0622*/ 0x00000200,
+/*0623*/ 0x42080010,
+/*0624*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = {
+/*0680*/ 0x04040404,
+/*0681*/ 0x00000404,
+/*0682*/ 0x00000000,
+/*0683*/ 0x00000000,
+/*0684*/ 0x00000000,
+/*0685*/ 0x00000000,
+/*0686*/ 0x00000002,
+/*0687*/ 0x00000000,
+/*0688*/ 0x00000000,
+/*0689*/ 0x00000000,
+/*068a*/ 0x00400320,
+/*068b*/ 0x00000040,
+/*068c*/ 0x00000000,
+/*068d*/ 0x00000000,
+/*068e*/ 0x00000000,
+/*068f*/ 0x01000000,
+/*0690*/ 0x00020003,
+/*0691*/ 0x00000000,
+/*0692*/ 0x00000000,
+/*0693*/ 0x00000000,
+/*0694*/ 0x00002a01,
+/*0695*/ 0x00000015,
+/*0696*/ 0x00000015,
+/*0697*/ 0x0000002a,
+/*0698*/ 0x00000033,
+/*0699*/ 0x0000000c,
+/*069a*/ 0x0000000c,
+/*069b*/ 0x00000033,
+/*069c*/ 0x00000000,
+/*069d*/ 0x00000000,
+/*069e*/ 0x00000000,
+/*069f*/ 0x0002006e,
+/*06a0*/ 0x02000200,
+/*06a1*/ 0x02000200,
+/*06a2*/ 0x00000200,
+/*06a3*/ 0x42080010,
+/*06a4*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = {
+/*0700*/ 0x00000001,
+/*0701*/ 0x00000000,
+/*0702*/ 0x00000005,
+/*0703*/ 0x04000f00,
+/*0704*/ 0x00020080,
+/*0705*/ 0x00020055,
+/*0706*/ 0x00000000,
+/*0707*/ 0x00000000,
+/*0708*/ 0x00000000,
+/*0709*/ 0x00000050,
+/*070a*/ 0x00000000,
+/*070b*/ 0x01010100,
+/*070c*/ 0x00000200,
+/*070d*/ 0x00001102,
+/*070e*/ 0x00000000,
+/*070f*/ 0x000f1f00,
+/*0710*/ 0x0f1f0f1f,
+/*0711*/ 0x0f1f0f1f,
+/*0712*/ 0x00020003,
+/*0713*/ 0x02000200,
+/*0714*/ 0x00000200,
+/*0715*/ 0x00001102,
+/*0716*/ 0x00000064,
+/*0717*/ 0x00000000,
+/*0718*/ 0x00000000,
+/*0719*/ 0x00000502,
+/*071a*/ 0x027f6e00,
+/*071b*/ 0x007f007f,
+/*071c*/ 0x00007f3c,
+/*071d*/ 0x00047f6e,
+/*071e*/ 0x0003154f,
+/*071f*/ 0x0001154f,
+/*0720*/ 0x0001154f,
+/*0721*/ 0x0001154f,
+/*0722*/ 0x0001154f,
+/*0723*/ 0x00003fee,
+/*0724*/ 0x0001154f,
+/*0725*/ 0x00003fee,
+/*0726*/ 0x0001154f,
+/*0727*/ 0x00007f3c,
+/*0728*/ 0x0001154f,
+/*0729*/ 0x00000000,
+/*072a*/ 0x00000000,
+/*072b*/ 0x00000000,
+/*072c*/ 0x65000000,
+/*072d*/ 0x00000000,
+/*072e*/ 0x00000000,
+/*072f*/ 0x00000201,
+/*0730*/ 0x00000000,
+/*0731*/ 0x00000000,
+/*0732*/ 0x00000000,
+/*0733*/ 0x00000000,
+/*0734*/ 0x00000000,
+/*0735*/ 0x00000000,
+/*0736*/ 0x00000000,
+/*0737*/ 0x00000000,
+/*0738*/ 0x00000000,
+/*0739*/ 0x00000000,
+/*073a*/ 0x00000000
+};
+
+static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = {
+/*0200*/ 0x00000b00,
+/*0201*/ 0x00000100,
+/*0202*/ 0x00000000,
+/*0203*/ 0x0000ffff,
+/*0204*/ 0x00000000,
+/*0205*/ 0x0000ffff,
+/*0206*/ 0x00000000,
+/*0207*/ 0x304cffff,
+/*0208*/ 0x00000200,
+/*0209*/ 0x00000200,
+/*020a*/ 0x00000200,
+/*020b*/ 0x00000200,
+/*020c*/ 0x0000304c,
+/*020d*/ 0x00000200,
+/*020e*/ 0x00000200,
+/*020f*/ 0x00000200,
+/*0210*/ 0x00000200,
+/*0211*/ 0x0000304c,
+/*0212*/ 0x00000200,
+/*0213*/ 0x00000200,
+/*0214*/ 0x00000200,
+/*0215*/ 0x00000200,
+/*0216*/ 0x00010000,
+/*0217*/ 0x00000003,
+/*0218*/ 0x01000001,
+/*0219*/ 0x00000000,
+/*021a*/ 0x00000000,
+/*021b*/ 0x00000000,
+/*021c*/ 0x00000000,
+/*021d*/ 0x00000000,
+/*021e*/ 0x00000000,
+/*021f*/ 0x00000000,
+/*0220*/ 0x00000000,
+/*0221*/ 0x00000000,
+/*0222*/ 0x00000000,
+/*0223*/ 0x00000000,
+/*0224*/ 0x00000000,
+/*0225*/ 0x00000000,
+/*0226*/ 0x00000000,
+/*0227*/ 0x00000000,
+/*0228*/ 0x00000000,
+/*0229*/ 0x0f000101,
+/*022a*/ 0x08492d25,
+/*022b*/ 0x500e0c04,
+/*022c*/ 0x0002500e,
+/*022d*/ 0x00460003,
+/*022e*/ 0x182600cf,
+/*022f*/ 0x182600cf,
+/*0230*/ 0x00000005,
+/*0231*/ 0x00000000,
+/*0232*/ 0x00000000,
+/*0233*/ 0x00000000,
+/*0234*/ 0x00000000,
+/*0235*/ 0x00000000,
+/*0236*/ 0x00000000,
+/*0237*/ 0x00000000,
+/*0238*/ 0x01000000,
+/*0239*/ 0x00040404,
+/*023a*/ 0x01280a00,
+/*023b*/ 0x00000000,
+/*023c*/ 0x000f0000,
+/*023d*/ 0x00001803,
+/*023e*/ 0x00000000,
+/*023f*/ 0x00000000,
+/*0240*/ 0x00060002,
+/*0241*/ 0x00010001,
+/*0242*/ 0x01000101,
+/*0243*/ 0x04020201,
+/*0244*/ 0x00080804,
+/*0245*/ 0x00000000,
+/*0246*/ 0x08030000,
+/*0247*/ 0x15150408,
+/*0248*/ 0x00000000,
+/*0249*/ 0x00000000,
+/*024a*/ 0x00000000,
+/*024b*/ 0x001e0f0f,
+/*024c*/ 0x00000000,
+/*024d*/ 0x01000300,
+/*024e*/ 0x00000000,
+/*024f*/ 0x00000000,
+/*0250*/ 0x01000000,
+/*0251*/ 0x00010101,
+/*0252*/ 0x000e0e0e,
+/*0253*/ 0x000c0c0c,
+/*0254*/ 0x02060601,
+/*0255*/ 0x00000000,
+/*0256*/ 0x00000003,
+/*0257*/ 0x00181703,
+/*0258*/ 0x00280006,
+/*0259*/ 0x00280016,
+/*025a*/ 0x00000016,
+/*025b*/ 0x00000000,
+/*025c*/ 0x00000000,
+/*025d*/ 0x00000000,
+/*025e*/ 0x140a0000,
+/*025f*/ 0x0005010a,
+/*0260*/ 0x03018d03,
+/*0261*/ 0x000a018d,
+/*0262*/ 0x00060100,
+/*0263*/ 0x01000006,
+/*0264*/ 0x018e018e,
+/*0265*/ 0x018e0100,
+/*0266*/ 0x1111018e,
+/*0267*/ 0x10010204,
+/*0268*/ 0x09090650,
+/*0269*/ 0x20110202,
+/*026a*/ 0x00201000,
+/*026b*/ 0x00201000,
+/*026c*/ 0x04041000,
+/*026d*/ 0x18020100,
+/*026e*/ 0x00010118,
+/*026f*/ 0x004b004a,
+/*0270*/ 0x050f0000,
+/*0271*/ 0x0c01021e,
+/*0272*/ 0x34000000,
+/*0273*/ 0x00000000,
+/*0274*/ 0x00000000,
+/*0275*/ 0x00000000,
+/*0276*/ 0x312ed400,
+/*0277*/ 0xd4111132,
+/*0278*/ 0x1132312e,
+/*0279*/ 0x312ed411,
+/*027a*/ 0x00111132,
+/*027b*/ 0x32312ed4,
+/*027c*/ 0x2ed41111,
+/*027d*/ 0x11113231,
+/*027e*/ 0x32312ed4,
+/*027f*/ 0xd4001111,
+/*0280*/ 0x1132312e,
+/*0281*/ 0x312ed411,
+/*0282*/ 0xd4111132,
+/*0283*/ 0x1132312e,
+/*0284*/ 0x2ed40011,
+/*0285*/ 0x11113231,
+/*0286*/ 0x32312ed4,
+/*0287*/ 0x2ed41111,
+/*0288*/ 0x11113231,
+/*0289*/ 0x00020000,
+/*028a*/ 0x018d018d,
+/*028b*/ 0x0c08018d,
+/*028c*/ 0x1f121d22,
+/*028d*/ 0x4301b344,
+/*028e*/ 0x10172006,
+/*028f*/ 0x121d220c,
+/*0290*/ 0x01b3441f,
+/*0291*/ 0x17200643,
+/*0292*/ 0x1d220c10,
+/*0293*/ 0x00001f12,
+/*0294*/ 0x4301b344,
+/*0295*/ 0x10172006,
+/*0296*/ 0x00020002,
+/*0297*/ 0x00020002,
+/*0298*/ 0x00020002,
+/*0299*/ 0x00020002,
+/*029a*/ 0x00020002,
+/*029b*/ 0x00000000,
+/*029c*/ 0x00000000,
+/*029d*/ 0x00000000,
+/*029e*/ 0x00000000,
+/*029f*/ 0x00000000,
+/*02a0*/ 0x00000000,
+/*02a1*/ 0x00000000,
+/*02a2*/ 0x00000000,
+/*02a3*/ 0x00000000,
+/*02a4*/ 0x00000000,
+/*02a5*/ 0x00000000,
+/*02a6*/ 0x00000000,
+/*02a7*/ 0x01000400,
+/*02a8*/ 0x00304c00,
+/*02a9*/ 0x0001e2f8,
+/*02aa*/ 0x0000304c,
+/*02ab*/ 0x0001e2f8,
+/*02ac*/ 0x0000304c,
+/*02ad*/ 0x0001e2f8,
+/*02ae*/ 0x08000000,
+/*02af*/ 0x00000100,
+/*02b0*/ 0x00000000,
+/*02b1*/ 0x00000000,
+/*02b2*/ 0x00000000,
+/*02b3*/ 0x00000000,
+/*02b4*/ 0x00000002
+};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
new file mode 100644
index 0000000..2e46401
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_H3VER2  0x0400
+#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2  0x0600
+#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2  0x0640
+#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2  0x0680
+#define DDR_PI_REGSET_OFS_H3VER2         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40
+#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40
+#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80
+#define DDR_PI_REGSET_SIZE_H3VER2        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_H3VER2  97
+#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2  37
+#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2  37
+#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2  79
+#define DDR_PI_REGSET_NUM_H3VER2         245
+
+static const uint32_t
+    DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = {
+/*0400*/ 0x76543210,
+/*0401*/ 0x0004f008,
+/*0402*/ 0x00020133,
+/*0403*/ 0x00000000,
+/*0404*/ 0x00000000,
+/*0405*/ 0x00010000,
+/*0406*/ 0x016e6e0e,
+/*0407*/ 0x026e6e0e,
+/*0408*/ 0x00010300,
+/*0409*/ 0x04000100,
+/*040a*/ 0x01000000,
+/*040b*/ 0x00000000,
+/*040c*/ 0x00000000,
+/*040d*/ 0x00000100,
+/*040e*/ 0x001700c0,
+/*040f*/ 0x020100b0,
+/*0410*/ 0x00030020,
+/*0411*/ 0x00000000,
+/*0412*/ 0x00000000,
+/*0413*/ 0x00000000,
+/*0414*/ 0x00000000,
+/*0415*/ 0x00000000,
+/*0416*/ 0x00000000,
+/*0417*/ 0x00000000,
+/*0418*/ 0x09000000,
+/*0419*/ 0x04080000,
+/*041a*/ 0x04080400,
+/*041b*/ 0x08000000,
+/*041c*/ 0x0c008007,
+/*041d*/ 0x00000f00,
+/*041e*/ 0x00000100,
+/*041f*/ 0x55aa55aa,
+/*0420*/ 0x33cc33cc,
+/*0421*/ 0x0ff00ff0,
+/*0422*/ 0x0f0ff0f0,
+/*0423*/ 0x00018e38,
+/*0424*/ 0x00000000,
+/*0425*/ 0x00000000,
+/*0426*/ 0x00000000,
+/*0427*/ 0x00000000,
+/*0428*/ 0x00000000,
+/*0429*/ 0x00000000,
+/*042a*/ 0x00000000,
+/*042b*/ 0x00000000,
+/*042c*/ 0x00000000,
+/*042d*/ 0x00000000,
+/*042e*/ 0x00000000,
+/*042f*/ 0x00000000,
+/*0430*/ 0x00000000,
+/*0431*/ 0x00000000,
+/*0432*/ 0x00000000,
+/*0433*/ 0x00000000,
+/*0434*/ 0x00000000,
+/*0435*/ 0x00000000,
+/*0436*/ 0x00000000,
+/*0437*/ 0x00000000,
+/*0438*/ 0x00000104,
+/*0439*/ 0x00082020,
+/*043a*/ 0x08200820,
+/*043b*/ 0x08200820,
+/*043c*/ 0x08200820,
+/*043d*/ 0x08200820,
+/*043e*/ 0x08200820,
+/*043f*/ 0x00000000,
+/*0440*/ 0x00000000,
+/*0441*/ 0x03000300,
+/*0442*/ 0x03000300,
+/*0443*/ 0x03000300,
+/*0444*/ 0x03000300,
+/*0445*/ 0x00000300,
+/*0446*/ 0x00000000,
+/*0447*/ 0x00000000,
+/*0448*/ 0x00000000,
+/*0449*/ 0x00000000,
+/*044a*/ 0x00000000,
+/*044b*/ 0x00a000a0,
+/*044c*/ 0x00a000a0,
+/*044d*/ 0x00a000a0,
+/*044e*/ 0x00a000a0,
+/*044f*/ 0x00a000a0,
+/*0450*/ 0x00a000a0,
+/*0451*/ 0x00a000a0,
+/*0452*/ 0x00a000a0,
+/*0453*/ 0x00a000a0,
+/*0454*/ 0x01040109,
+/*0455*/ 0x00000200,
+/*0456*/ 0x01000000,
+/*0457*/ 0x00000200,
+/*0458*/ 0x00000004,
+/*0459*/ 0x4041a141,
+/*045a*/ 0xc00141a0,
+/*045b*/ 0x0e0000c0,
+/*045c*/ 0x0010000c,
+/*045d*/ 0x063e4208,
+/*045e*/ 0x0f0c180c,
+/*045f*/ 0x00e00140,
+/*0460*/ 0x00000c20
+};
+
+static const uint32_t
+    DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = {
+/*0600*/ 0x00000000,
+/*0601*/ 0x00000000,
+/*0602*/ 0x00000000,
+/*0603*/ 0x00000000,
+/*0604*/ 0x00000000,
+/*0605*/ 0x00000000,
+/*0606*/ 0x00000000,
+/*0607*/ 0x00010000,
+/*0608*/ 0x00000200,
+/*0609*/ 0x00000000,
+/*060a*/ 0x00000000,
+/*060b*/ 0x00000000,
+/*060c*/ 0x00400320,
+/*060d*/ 0x00000040,
+/*060e*/ 0x00dcba98,
+/*060f*/ 0x03000000,
+/*0610*/ 0x00000200,
+/*0611*/ 0x00000000,
+/*0612*/ 0x00000000,
+/*0613*/ 0x00000000,
+/*0614*/ 0x0000002a,
+/*0615*/ 0x00000015,
+/*0616*/ 0x00000015,
+/*0617*/ 0x0000002a,
+/*0618*/ 0x00000033,
+/*0619*/ 0x0000000c,
+/*061a*/ 0x0000000c,
+/*061b*/ 0x00000033,
+/*061c*/ 0x00418820,
+/*061d*/ 0x003f0000,
+/*061e*/ 0x0000003f,
+/*061f*/ 0x0002c06e,
+/*0620*/ 0x02c002c0,
+/*0621*/ 0x02c002c0,
+/*0622*/ 0x000002c0,
+/*0623*/ 0x42080010,
+/*0624*/ 0x0000033e
+};
+
+static const uint32_t
+    DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = {
+/*0640*/ 0x00000000,
+/*0641*/ 0x00000000,
+/*0642*/ 0x00000000,
+/*0643*/ 0x00000000,
+/*0644*/ 0x00000000,
+/*0645*/ 0x00000000,
+/*0646*/ 0x00000000,
+/*0647*/ 0x00000000,
+/*0648*/ 0x00000000,
+/*0649*/ 0x00000000,
+/*064a*/ 0x00000000,
+/*064b*/ 0x00000000,
+/*064c*/ 0x00000000,
+/*064d*/ 0x00000000,
+/*064e*/ 0x00000000,
+/*064f*/ 0x00000000,
+/*0650*/ 0x00000000,
+/*0651*/ 0x00000000,
+/*0652*/ 0x00000000,
+/*0653*/ 0x00000000,
+/*0654*/ 0x00000000,
+/*0655*/ 0x00000000,
+/*0656*/ 0x00000000,
+/*0657*/ 0x00000000,
+/*0658*/ 0x00000000,
+/*0659*/ 0x00000000,
+/*065a*/ 0x00000000,
+/*065b*/ 0x00000000,
+/*065c*/ 0x00000000,
+/*065d*/ 0x00000000,
+/*065e*/ 0x00000000,
+/*065f*/ 0x00000000,
+/*0660*/ 0x00000000,
+/*0661*/ 0x00000000,
+/*0662*/ 0x00000000,
+/*0663*/ 0x00000000,
+/*0664*/ 0x00000000
+};
+
+static const uint32_t
+    DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = {
+/*0680*/ 0x00000000,
+/*0681*/ 0x00000100,
+/*0682*/ 0x00000000,
+/*0683*/ 0x00050000,
+/*0684*/ 0x0f000000,
+/*0685*/ 0x00800400,
+/*0686*/ 0x00020032,
+/*0687*/ 0x00020055,
+/*0688*/ 0x00000000,
+/*0689*/ 0x00000000,
+/*068a*/ 0x00000000,
+/*068b*/ 0x00000050,
+/*068c*/ 0x00000000,
+/*068d*/ 0x01010100,
+/*068e*/ 0x01000200,
+/*068f*/ 0x00000000,
+/*0690*/ 0x00010100,
+/*0691*/ 0x00000000,
+/*0692*/ 0x00000000,
+/*0693*/ 0x00000000,
+/*0694*/ 0x00000000,
+/*0695*/ 0x00005064,
+/*0696*/ 0x01421142,
+/*0697*/ 0x00000142,
+/*0698*/ 0x00000000,
+/*0699*/ 0x000f1100,
+/*069a*/ 0x0f110f11,
+/*069b*/ 0x09000f11,
+/*069c*/ 0x00000003,
+/*069d*/ 0x0002c000,
+/*069e*/ 0x02c002c0,
+/*069f*/ 0x000002c0,
+/*06a0*/ 0x01421142,
+/*06a1*/ 0x00000142,
+/*06a2*/ 0x00000000,
+/*06a3*/ 0x00000000,
+/*06a4*/ 0x05020000,
+/*06a5*/ 0x14000000,
+/*06a6*/ 0x027f6e00,
+/*06a7*/ 0x047f027f,
+/*06a8*/ 0x00027f6e,
+/*06a9*/ 0x00047f6e,
+/*06aa*/ 0x0003554f,
+/*06ab*/ 0x0001554f,
+/*06ac*/ 0x0001554f,
+/*06ad*/ 0x0001554f,
+/*06ae*/ 0x0001554f,
+/*06af*/ 0x00003fee,
+/*06b0*/ 0x0001554f,
+/*06b1*/ 0x00003fee,
+/*06b2*/ 0x0001554f,
+/*06b3*/ 0x00027f6e,
+/*06b4*/ 0x0001554f,
+/*06b5*/ 0x00004011,
+/*06b6*/ 0x00004410,
+/*06b7*/ 0x00000000,
+/*06b8*/ 0x00000000,
+/*06b9*/ 0x00000000,
+/*06ba*/ 0x00000065,
+/*06bb*/ 0x00000000,
+/*06bc*/ 0x00020201,
+/*06bd*/ 0x00000000,
+/*06be*/ 0x03000000,
+/*06bf*/ 0x00000008,
+/*06c0*/ 0x00000000,
+/*06c1*/ 0x00000000,
+/*06c2*/ 0x00000000,
+/*06c3*/ 0x00000000,
+/*06c4*/ 0x00000001,
+/*06c5*/ 0x00000000,
+/*06c6*/ 0x00000000,
+/*06c7*/ 0x00000000,
+/*06c8*/ 0x000000e4,
+/*06c9*/ 0x00010198,
+/*06ca*/ 0x00000000,
+/*06cb*/ 0x00000000,
+/*06cc*/ 0x07010000,
+/*06cd*/ 0x00000104,
+/*06ce*/ 0x00000000
+};
+
+static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = {
+/*0200*/ 0x00000b00,
+/*0201*/ 0x00000100,
+/*0202*/ 0x00640000,
+/*0203*/ 0x00000000,
+/*0204*/ 0x0000ffff,
+/*0205*/ 0x00000000,
+/*0206*/ 0x0000ffff,
+/*0207*/ 0x00000000,
+/*0208*/ 0x0000ffff,
+/*0209*/ 0x0000304c,
+/*020a*/ 0x00000200,
+/*020b*/ 0x00000200,
+/*020c*/ 0x00000200,
+/*020d*/ 0x00000200,
+/*020e*/ 0x0000304c,
+/*020f*/ 0x00000200,
+/*0210*/ 0x00000200,
+/*0211*/ 0x00000200,
+/*0212*/ 0x00000200,
+/*0213*/ 0x0000304c,
+/*0214*/ 0x00000200,
+/*0215*/ 0x00000200,
+/*0216*/ 0x00000200,
+/*0217*/ 0x00000200,
+/*0218*/ 0x00010000,
+/*0219*/ 0x00000003,
+/*021a*/ 0x01000001,
+/*021b*/ 0x00000000,
+/*021c*/ 0x00000000,
+/*021d*/ 0x00000000,
+/*021e*/ 0x00000000,
+/*021f*/ 0x00000000,
+/*0220*/ 0x00000000,
+/*0221*/ 0x00000000,
+/*0222*/ 0x00000000,
+/*0223*/ 0x00000000,
+/*0224*/ 0x00000000,
+/*0225*/ 0x00000000,
+/*0226*/ 0x00000000,
+/*0227*/ 0x00000000,
+/*0228*/ 0x00000000,
+/*0229*/ 0x00000000,
+/*022a*/ 0x00000000,
+/*022b*/ 0x0f000101,
+/*022c*/ 0x08492d25,
+/*022d*/ 0x500e0c04,
+/*022e*/ 0x0002500e,
+/*022f*/ 0x00000301,
+/*0230*/ 0x00000046,
+/*0231*/ 0x000000cf,
+/*0232*/ 0x00001826,
+/*0233*/ 0x000000cf,
+/*0234*/ 0x00001826,
+/*0235*/ 0x00000005,
+/*0236*/ 0x00000000,
+/*0237*/ 0x00000000,
+/*0238*/ 0x00000000,
+/*0239*/ 0x00000000,
+/*023a*/ 0x00000000,
+/*023b*/ 0x00000000,
+/*023c*/ 0x00000000,
+/*023d*/ 0x00000000,
+/*023e*/ 0x04010000,
+/*023f*/ 0x00000404,
+/*0240*/ 0x0101280a,
+/*0241*/ 0x00000000,
+/*0242*/ 0x00000000,
+/*0243*/ 0x0003000f,
+/*0244*/ 0x00000018,
+/*0245*/ 0x00000000,
+/*0246*/ 0x00000000,
+/*0247*/ 0x00060002,
+/*0248*/ 0x00010001,
+/*0249*/ 0x01000101,
+/*024a*/ 0x04020201,
+/*024b*/ 0x00080804,
+/*024c*/ 0x00000000,
+/*024d*/ 0x08030000,
+/*024e*/ 0x15150408,
+/*024f*/ 0x00000000,
+/*0250*/ 0x00000000,
+/*0251*/ 0x00000000,
+/*0252*/ 0x0f0f0000,
+/*0253*/ 0x0000001e,
+/*0254*/ 0x00000000,
+/*0255*/ 0x01000300,
+/*0256*/ 0x00000100,
+/*0257*/ 0x00000000,
+/*0258*/ 0x00000000,
+/*0259*/ 0x01000000,
+/*025a*/ 0x00000101,
+/*025b*/ 0x55555a5a,
+/*025c*/ 0x55555a5a,
+/*025d*/ 0x55555a5a,
+/*025e*/ 0x55555a5a,
+/*025f*/ 0x0e0e0001,
+/*0260*/ 0x0c0c000e,
+/*0261*/ 0x0601000c,
+/*0262*/ 0x17170106,
+/*0263*/ 0x00020202,
+/*0264*/ 0x03000000,
+/*0265*/ 0x00000000,
+/*0266*/ 0x00181703,
+/*0267*/ 0x00280006,
+/*0268*/ 0x00280016,
+/*0269*/ 0x00000016,
+/*026a*/ 0x00000000,
+/*026b*/ 0x00000000,
+/*026c*/ 0x00000000,
+/*026d*/ 0x0a000000,
+/*026e*/ 0x00010a14,
+/*026f*/ 0x00030005,
+/*0270*/ 0x0003018d,
+/*0271*/ 0x000a018d,
+/*0272*/ 0x00060100,
+/*0273*/ 0x01000006,
+/*0274*/ 0x018e018e,
+/*0275*/ 0x018e0100,
+/*0276*/ 0x1111018e,
+/*0277*/ 0x10010204,
+/*0278*/ 0x09090650,
+/*0279*/ 0xff110202,
+/*027a*/ 0x00ff1000,
+/*027b*/ 0x00ff1000,
+/*027c*/ 0x04041000,
+/*027d*/ 0x18020100,
+/*027e*/ 0x01010018,
+/*027f*/ 0x004a004a,
+/*0280*/ 0x004b004a,
+/*0281*/ 0x050f0000,
+/*0282*/ 0x0c01021e,
+/*0283*/ 0x34000000,
+/*0284*/ 0x00000000,
+/*0285*/ 0x00000000,
+/*0286*/ 0x00000000,
+/*0287*/ 0x00000000,
+/*0288*/ 0x36312ed4,
+/*0289*/ 0x2ed41111,
+/*028a*/ 0x11113631,
+/*028b*/ 0x36312ed4,
+/*028c*/ 0xd4001111,
+/*028d*/ 0x1136312e,
+/*028e*/ 0x312ed411,
+/*028f*/ 0xd4111136,
+/*0290*/ 0x1136312e,
+/*0291*/ 0x2ed40011,
+/*0292*/ 0x11113631,
+/*0293*/ 0x36312ed4,
+/*0294*/ 0x2ed41111,
+/*0295*/ 0x11113631,
+/*0296*/ 0x312ed400,
+/*0297*/ 0xd4111136,
+/*0298*/ 0x1136312e,
+/*0299*/ 0x312ed411,
+/*029a*/ 0x00111136,
+/*029b*/ 0x018d0200,
+/*029c*/ 0x018d018d,
+/*029d*/ 0x1d220c08,
+/*029e*/ 0x00001f12,
+/*029f*/ 0x4301b344,
+/*02a0*/ 0x10172006,
+/*02a1*/ 0x121d220c,
+/*02a2*/ 0x01b3441f,
+/*02a3*/ 0x17200643,
+/*02a4*/ 0x1d220c10,
+/*02a5*/ 0x00001f12,
+/*02a6*/ 0x4301b344,
+/*02a7*/ 0x10172006,
+/*02a8*/ 0x00020002,
+/*02a9*/ 0x00020002,
+/*02aa*/ 0x00020002,
+/*02ab*/ 0x00020002,
+/*02ac*/ 0x00020002,
+/*02ad*/ 0x00000000,
+/*02ae*/ 0x00000000,
+/*02af*/ 0x00000000,
+/*02b0*/ 0x00000000,
+/*02b1*/ 0x00000000,
+/*02b2*/ 0x00000000,
+/*02b3*/ 0x00000000,
+/*02b4*/ 0x00000000,
+/*02b5*/ 0x00000000,
+/*02b6*/ 0x00000000,
+/*02b7*/ 0x00000000,
+/*02b8*/ 0x00000000,
+/*02b9*/ 0x00000400,
+/*02ba*/ 0x05040302,
+/*02bb*/ 0x01000f0e,
+/*02bc*/ 0x07060504,
+/*02bd*/ 0x03020100,
+/*02be*/ 0x02010000,
+/*02bf*/ 0x00000103,
+/*02c0*/ 0x0000304c,
+/*02c1*/ 0x0001e2f8,
+/*02c2*/ 0x0000304c,
+/*02c3*/ 0x0001e2f8,
+/*02c4*/ 0x0000304c,
+/*02c5*/ 0x0001e2f8,
+/*02c6*/ 0x08000000,
+/*02c7*/ 0x00000100,
+/*02c8*/ 0x00000000,
+/*02c9*/ 0x00000000,
+/*02ca*/ 0x00000000,
+/*02cb*/ 0x00000000,
+/*02cc*/ 0x00010000,
+/*02cd*/ 0x00000000,
+/*02ce*/ 0x00000000,
+/*02cf*/ 0x00000000,
+/*02d0*/ 0x00000000,
+/*02d1*/ 0x00000000,
+/*02d2*/ 0x00000000,
+/*02d3*/ 0x00000000,
+/*02d4*/ 0x00000000,
+/*02d5*/ 0x00000000,
+/*02d6*/ 0x00000000,
+/*02d7*/ 0x00000000,
+/*02d8*/ 0x00000000,
+/*02d9*/ 0x00000000,
+/*02da*/ 0x00000000,
+/*02db*/ 0x00000000,
+/*02dc*/ 0x00000000,
+/*02dd*/ 0x00000000,
+/*02de*/ 0x00000000,
+/*02df*/ 0x00000000,
+/*02e0*/ 0x00000000,
+/*02e1*/ 0x00000000,
+/*02e2*/ 0x00000000,
+/*02e3*/ 0x00000000,
+/*02e4*/ 0x00000000,
+/*02e5*/ 0x00000000,
+/*02e6*/ 0x00000000,
+/*02e7*/ 0x00000000,
+/*02e8*/ 0x00000000,
+/*02e9*/ 0x00000000,
+/*02ea*/ 0x00000000,
+/*02eb*/ 0x00000000,
+/*02ec*/ 0x00000000,
+/*02ed*/ 0x00000000,
+/*02ee*/ 0x00000002,
+/*02ef*/ 0x00000000,
+/*02f0*/ 0x00000000,
+/*02f1*/ 0x00000000,
+/*02f2*/ 0x00000000,
+/*02f3*/ 0x00000000,
+/*02f4*/ 0x00000000
+};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
new file mode 100644
index 0000000..1762298
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
@@ -0,0 +1,467 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_M3  0x0800
+#define DDR_PHY_ADR_V_REGSET_OFS_M3  0x0a00
+#define DDR_PHY_ADR_I_REGSET_OFS_M3  0x0a80
+#define DDR_PHY_ADR_G_REGSET_OFS_M3  0x0b80
+#define DDR_PI_REGSET_OFS_M3         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80
+#define DDR_PI_REGSET_SIZE_M3        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_M3  89
+#define DDR_PHY_ADR_V_REGSET_NUM_M3  37
+#define DDR_PHY_ADR_I_REGSET_NUM_M3  37
+#define DDR_PHY_ADR_G_REGSET_NUM_M3  64
+#define DDR_PI_REGSET_NUM_M3         202
+
+static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = {
+/*0800*/ 0x76543210,
+/*0801*/ 0x0004f008,
+/*0802*/ 0x00000000,
+/*0803*/ 0x00000000,
+/*0804*/ 0x00010000,
+/*0805*/ 0x036e6e0e,
+/*0806*/ 0x026e6e0e,
+/*0807*/ 0x00010300,
+/*0808*/ 0x04000100,
+/*0809*/ 0x00000300,
+/*080a*/ 0x001700c0,
+/*080b*/ 0x00b00201,
+/*080c*/ 0x00030020,
+/*080d*/ 0x00000000,
+/*080e*/ 0x00000000,
+/*080f*/ 0x00000000,
+/*0810*/ 0x00000000,
+/*0811*/ 0x00000000,
+/*0812*/ 0x00000000,
+/*0813*/ 0x00000000,
+/*0814*/ 0x09000000,
+/*0815*/ 0x04080000,
+/*0816*/ 0x04080400,
+/*0817*/ 0x00000000,
+/*0818*/ 0x32103210,
+/*0819*/ 0x00800708,
+/*081a*/ 0x000f000c,
+/*081b*/ 0x00000100,
+/*081c*/ 0x55aa55aa,
+/*081d*/ 0x33cc33cc,
+/*081e*/ 0x0ff00ff0,
+/*081f*/ 0x0f0ff0f0,
+/*0820*/ 0x00018e38,
+/*0821*/ 0x00000000,
+/*0822*/ 0x00000000,
+/*0823*/ 0x00000000,
+/*0824*/ 0x00000000,
+/*0825*/ 0x00000000,
+/*0826*/ 0x00000000,
+/*0827*/ 0x00000000,
+/*0828*/ 0x00000000,
+/*0829*/ 0x00000000,
+/*082a*/ 0x00000000,
+/*082b*/ 0x00000000,
+/*082c*/ 0x00000000,
+/*082d*/ 0x00000000,
+/*082e*/ 0x00000000,
+/*082f*/ 0x00000000,
+/*0830*/ 0x00000000,
+/*0831*/ 0x00000000,
+/*0832*/ 0x00000000,
+/*0833*/ 0x00200000,
+/*0834*/ 0x08200820,
+/*0835*/ 0x08200820,
+/*0836*/ 0x08200820,
+/*0837*/ 0x08200820,
+/*0838*/ 0x08200820,
+/*0839*/ 0x00000820,
+/*083a*/ 0x03000300,
+/*083b*/ 0x03000300,
+/*083c*/ 0x03000300,
+/*083d*/ 0x03000300,
+/*083e*/ 0x00000300,
+/*083f*/ 0x00000000,
+/*0840*/ 0x00000000,
+/*0841*/ 0x00000000,
+/*0842*/ 0x00000000,
+/*0843*/ 0x00a00000,
+/*0844*/ 0x00a000a0,
+/*0845*/ 0x00a000a0,
+/*0846*/ 0x00a000a0,
+/*0847*/ 0x00a000a0,
+/*0848*/ 0x00a000a0,
+/*0849*/ 0x00a000a0,
+/*084a*/ 0x00a000a0,
+/*084b*/ 0x00a000a0,
+/*084c*/ 0x010900a0,
+/*084d*/ 0x02000104,
+/*084e*/ 0x00000000,
+/*084f*/ 0x00010000,
+/*0850*/ 0x00000200,
+/*0851*/ 0x4041a141,
+/*0852*/ 0xc00141a0,
+/*0853*/ 0x0e0100c0,
+/*0854*/ 0x0010000c,
+/*0855*/ 0x0c064208,
+/*0856*/ 0x000f0c18,
+/*0857*/ 0x00e00140,
+/*0858*/ 0x00000c20
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = {
+/*0a00*/ 0x00000000,
+/*0a01*/ 0x00000000,
+/*0a02*/ 0x00000000,
+/*0a03*/ 0x00000000,
+/*0a04*/ 0x00000000,
+/*0a05*/ 0x00000000,
+/*0a06*/ 0x00000002,
+/*0a07*/ 0x00000000,
+/*0a08*/ 0x00000000,
+/*0a09*/ 0x00000000,
+/*0a0a*/ 0x00400320,
+/*0a0b*/ 0x00000040,
+/*0a0c*/ 0x00dcba98,
+/*0a0d*/ 0x00000000,
+/*0a0e*/ 0x00dcba98,
+/*0a0f*/ 0x01000000,
+/*0a10*/ 0x00020003,
+/*0a11*/ 0x00000000,
+/*0a12*/ 0x00000000,
+/*0a13*/ 0x00000000,
+/*0a14*/ 0x0000002a,
+/*0a15*/ 0x00000015,
+/*0a16*/ 0x00000015,
+/*0a17*/ 0x0000002a,
+/*0a18*/ 0x00000033,
+/*0a19*/ 0x0000000c,
+/*0a1a*/ 0x0000000c,
+/*0a1b*/ 0x00000033,
+/*0a1c*/ 0x0a418820,
+/*0a1d*/ 0x003f0000,
+/*0a1e*/ 0x0000003f,
+/*0a1f*/ 0x0002c06e,
+/*0a20*/ 0x02c002c0,
+/*0a21*/ 0x02c002c0,
+/*0a22*/ 0x000002c0,
+/*0a23*/ 0x42080010,
+/*0a24*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = {
+/*0a80*/ 0x04040404,
+/*0a81*/ 0x00000404,
+/*0a82*/ 0x00000000,
+/*0a83*/ 0x00000000,
+/*0a84*/ 0x00000000,
+/*0a85*/ 0x00000000,
+/*0a86*/ 0x00000002,
+/*0a87*/ 0x00000000,
+/*0a88*/ 0x00000000,
+/*0a89*/ 0x00000000,
+/*0a8a*/ 0x00400320,
+/*0a8b*/ 0x00000040,
+/*0a8c*/ 0x00000000,
+/*0a8d*/ 0x00000000,
+/*0a8e*/ 0x00000000,
+/*0a8f*/ 0x01000000,
+/*0a90*/ 0x00020003,
+/*0a91*/ 0x00000000,
+/*0a92*/ 0x00000000,
+/*0a93*/ 0x00000000,
+/*0a94*/ 0x0000002a,
+/*0a95*/ 0x00000015,
+/*0a96*/ 0x00000015,
+/*0a97*/ 0x0000002a,
+/*0a98*/ 0x00000033,
+/*0a99*/ 0x0000000c,
+/*0a9a*/ 0x0000000c,
+/*0a9b*/ 0x00000033,
+/*0a9c*/ 0x00000000,
+/*0a9d*/ 0x00000000,
+/*0a9e*/ 0x00000000,
+/*0a9f*/ 0x0002c06e,
+/*0aa0*/ 0x02c002c0,
+/*0aa1*/ 0x02c002c0,
+/*0aa2*/ 0x000002c0,
+/*0aa3*/ 0x42080010,
+/*0aa4*/ 0x00000003
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = {
+/*0b80*/ 0x00000001,
+/*0b81*/ 0x00000000,
+/*0b82*/ 0x00000005,
+/*0b83*/ 0x04000f00,
+/*0b84*/ 0x00020080,
+/*0b85*/ 0x00020055,
+/*0b86*/ 0x00000000,
+/*0b87*/ 0x00000000,
+/*0b88*/ 0x00000000,
+/*0b89*/ 0x00000050,
+/*0b8a*/ 0x00000000,
+/*0b8b*/ 0x01010100,
+/*0b8c*/ 0x00000600,
+/*0b8d*/ 0x50640000,
+/*0b8e*/ 0x01421142,
+/*0b8f*/ 0x00000142,
+/*0b90*/ 0x00000000,
+/*0b91*/ 0x000f1600,
+/*0b92*/ 0x0f160f16,
+/*0b93*/ 0x0f160f16,
+/*0b94*/ 0x00000003,
+/*0b95*/ 0x0002c000,
+/*0b96*/ 0x02c002c0,
+/*0b97*/ 0x000002c0,
+/*0b98*/ 0x01421142,
+/*0b99*/ 0x00000142,
+/*0b9a*/ 0x00000000,
+/*0b9b*/ 0x00000000,
+/*0b9c*/ 0x05020000,
+/*0b9d*/ 0x00000000,
+/*0b9e*/ 0x00027f6e,
+/*0b9f*/ 0x047f027f,
+/*0ba0*/ 0x00027f6e,
+/*0ba1*/ 0x00047f6e,
+/*0ba2*/ 0x0003554f,
+/*0ba3*/ 0x0001554f,
+/*0ba4*/ 0x0001554f,
+/*0ba5*/ 0x0001554f,
+/*0ba6*/ 0x0001554f,
+/*0ba7*/ 0x00003fee,
+/*0ba8*/ 0x0001554f,
+/*0ba9*/ 0x00003fee,
+/*0baa*/ 0x0001554f,
+/*0bab*/ 0x00027f6e,
+/*0bac*/ 0x0001554f,
+/*0bad*/ 0x00000000,
+/*0bae*/ 0x00000000,
+/*0baf*/ 0x00000000,
+/*0bb0*/ 0x65000000,
+/*0bb1*/ 0x00000000,
+/*0bb2*/ 0x00000000,
+/*0bb3*/ 0x00000201,
+/*0bb4*/ 0x00000000,
+/*0bb5*/ 0x00000000,
+/*0bb6*/ 0x00000000,
+/*0bb7*/ 0x00000000,
+/*0bb8*/ 0x00000000,
+/*0bb9*/ 0x00000000,
+/*0bba*/ 0x00000000,
+/*0bbb*/ 0x00000000,
+/*0bbc*/ 0x06e40000,
+/*0bbd*/ 0x00000000,
+/*0bbe*/ 0x00000000,
+/*0bbf*/ 0x00010000
+};
+
+static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = {
+/*0200*/ 0x00000b00,
+/*0201*/ 0x00000100,
+/*0202*/ 0x00000000,
+/*0203*/ 0x0000ffff,
+/*0204*/ 0x00000000,
+/*0205*/ 0x0000ffff,
+/*0206*/ 0x00000000,
+/*0207*/ 0x304cffff,
+/*0208*/ 0x00000200,
+/*0209*/ 0x00000200,
+/*020a*/ 0x00000200,
+/*020b*/ 0x00000200,
+/*020c*/ 0x0000304c,
+/*020d*/ 0x00000200,
+/*020e*/ 0x00000200,
+/*020f*/ 0x00000200,
+/*0210*/ 0x00000200,
+/*0211*/ 0x0000304c,
+/*0212*/ 0x00000200,
+/*0213*/ 0x00000200,
+/*0214*/ 0x00000200,
+/*0215*/ 0x00000200,
+/*0216*/ 0x00010000,
+/*0217*/ 0x00000003,
+/*0218*/ 0x01000001,
+/*0219*/ 0x00000000,
+/*021a*/ 0x00000000,
+/*021b*/ 0x00000000,
+/*021c*/ 0x00000000,
+/*021d*/ 0x00000000,
+/*021e*/ 0x00000000,
+/*021f*/ 0x00000000,
+/*0220*/ 0x00000000,
+/*0221*/ 0x00000000,
+/*0222*/ 0x00000000,
+/*0223*/ 0x00000000,
+/*0224*/ 0x00000000,
+/*0225*/ 0x00000000,
+/*0226*/ 0x00000000,
+/*0227*/ 0x00000000,
+/*0228*/ 0x00000000,
+/*0229*/ 0x0f000101,
+/*022a*/ 0x08492d25,
+/*022b*/ 0x0e0c0004,
+/*022c*/ 0x000e5000,
+/*022d*/ 0x00000250,
+/*022e*/ 0x00460003,
+/*022f*/ 0x182600cf,
+/*0230*/ 0x182600cf,
+/*0231*/ 0x00000005,
+/*0232*/ 0x00000000,
+/*0233*/ 0x00000000,
+/*0234*/ 0x00000000,
+/*0235*/ 0x00000000,
+/*0236*/ 0x00000000,
+/*0237*/ 0x00000000,
+/*0238*/ 0x00000000,
+/*0239*/ 0x01000000,
+/*023a*/ 0x00040404,
+/*023b*/ 0x01280a00,
+/*023c*/ 0x00000000,
+/*023d*/ 0x000f0000,
+/*023e*/ 0x00001803,
+/*023f*/ 0x00000000,
+/*0240*/ 0x00000000,
+/*0241*/ 0x00060002,
+/*0242*/ 0x00010001,
+/*0243*/ 0x01000101,
+/*0244*/ 0x04020201,
+/*0245*/ 0x00080804,
+/*0246*/ 0x00000000,
+/*0247*/ 0x08030000,
+/*0248*/ 0x15150408,
+/*0249*/ 0x00000000,
+/*024a*/ 0x00000000,
+/*024b*/ 0x00000000,
+/*024c*/ 0x000f0f00,
+/*024d*/ 0x0000001e,
+/*024e*/ 0x00000000,
+/*024f*/ 0x01000300,
+/*0250*/ 0x00000000,
+/*0251*/ 0x00000000,
+/*0252*/ 0x01000000,
+/*0253*/ 0x00010101,
+/*0254*/ 0x000e0e0e,
+/*0255*/ 0x000c0c0c,
+/*0256*/ 0x02060601,
+/*0257*/ 0x00000000,
+/*0258*/ 0x00000003,
+/*0259*/ 0x00181703,
+/*025a*/ 0x00280006,
+/*025b*/ 0x00280016,
+/*025c*/ 0x00000016,
+/*025d*/ 0x00000000,
+/*025e*/ 0x00000000,
+/*025f*/ 0x00000000,
+/*0260*/ 0x140a0000,
+/*0261*/ 0x0005010a,
+/*0262*/ 0x03018d03,
+/*0263*/ 0x000a018d,
+/*0264*/ 0x00060100,
+/*0265*/ 0x01000006,
+/*0266*/ 0x018e018e,
+/*0267*/ 0x018e0100,
+/*0268*/ 0x1111018e,
+/*0269*/ 0x10010204,
+/*026a*/ 0x09090650,
+/*026b*/ 0x20110202,
+/*026c*/ 0x00201000,
+/*026d*/ 0x00201000,
+/*026e*/ 0x04041000,
+/*026f*/ 0x18020100,
+/*0270*/ 0x00010118,
+/*0271*/ 0x004b004a,
+/*0272*/ 0x050f0000,
+/*0273*/ 0x0c01021e,
+/*0274*/ 0x34000000,
+/*0275*/ 0x00000000,
+/*0276*/ 0x00000000,
+/*0277*/ 0x00000000,
+/*0278*/ 0x0000d400,
+/*0279*/ 0x0031002e,
+/*027a*/ 0x00111136,
+/*027b*/ 0x002e00d4,
+/*027c*/ 0x11360031,
+/*027d*/ 0x0000d411,
+/*027e*/ 0x0031002e,
+/*027f*/ 0x00111136,
+/*0280*/ 0x002e00d4,
+/*0281*/ 0x11360031,
+/*0282*/ 0x0000d411,
+/*0283*/ 0x0031002e,
+/*0284*/ 0x00111136,
+/*0285*/ 0x002e00d4,
+/*0286*/ 0x11360031,
+/*0287*/ 0x00d40011,
+/*0288*/ 0x0031002e,
+/*0289*/ 0x00111136,
+/*028a*/ 0x002e00d4,
+/*028b*/ 0x11360031,
+/*028c*/ 0x0000d411,
+/*028d*/ 0x0031002e,
+/*028e*/ 0x00111136,
+/*028f*/ 0x002e00d4,
+/*0290*/ 0x11360031,
+/*0291*/ 0x0000d411,
+/*0292*/ 0x0031002e,
+/*0293*/ 0x00111136,
+/*0294*/ 0x002e00d4,
+/*0295*/ 0x11360031,
+/*0296*/ 0x02000011,
+/*0297*/ 0x018d018d,
+/*0298*/ 0x0c08018d,
+/*0299*/ 0x1f121d22,
+/*029a*/ 0x4301b344,
+/*029b*/ 0x10172006,
+/*029c*/ 0x1d220c10,
+/*029d*/ 0x00001f12,
+/*029e*/ 0x4301b344,
+/*029f*/ 0x10172006,
+/*02a0*/ 0x1d220c10,
+/*02a1*/ 0x00001f12,
+/*02a2*/ 0x4301b344,
+/*02a3*/ 0x10172006,
+/*02a4*/ 0x02000210,
+/*02a5*/ 0x02000200,
+/*02a6*/ 0x02000200,
+/*02a7*/ 0x02000200,
+/*02a8*/ 0x02000200,
+/*02a9*/ 0x00000000,
+/*02aa*/ 0x00000000,
+/*02ab*/ 0x00000000,
+/*02ac*/ 0x00000000,
+/*02ad*/ 0x00000000,
+/*02ae*/ 0x00000000,
+/*02af*/ 0x00000000,
+/*02b0*/ 0x00000000,
+/*02b1*/ 0x00000000,
+/*02b2*/ 0x00000000,
+/*02b3*/ 0x00000000,
+/*02b4*/ 0x00000000,
+/*02b5*/ 0x00000400,
+/*02b6*/ 0x15141312,
+/*02b7*/ 0x11100f0e,
+/*02b8*/ 0x080b0c0d,
+/*02b9*/ 0x05040a09,
+/*02ba*/ 0x01000706,
+/*02bb*/ 0x00000302,
+/*02bc*/ 0x01030201,
+/*02bd*/ 0x00304c00,
+/*02be*/ 0x0001e2f8,
+/*02bf*/ 0x0000304c,
+/*02c0*/ 0x0001e2f8,
+/*02c1*/ 0x0000304c,
+/*02c2*/ 0x0001e2f8,
+/*02c3*/ 0x08000000,
+/*02c4*/ 0x00000100,
+/*02c5*/ 0x00000000,
+/*02c6*/ 0x00000000,
+/*02c7*/ 0x00000000,
+/*02c8*/ 0x00000000,
+/*02c9*/ 0x00000002
+};
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
new file mode 100644
index 0000000..f8ff0fd
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
@@ -0,0 +1,586 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define DDR_PHY_SLICE_REGSET_OFS_M3N  0x0800
+#define DDR_PHY_ADR_V_REGSET_OFS_M3N  0x0a00
+#define DDR_PHY_ADR_I_REGSET_OFS_M3N  0x0a80
+#define DDR_PHY_ADR_G_REGSET_OFS_M3N  0x0b80
+#define DDR_PI_REGSET_OFS_M3N         0x0200
+
+#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80
+#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80
+#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80
+#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80
+#define DDR_PI_REGSET_SIZE_M3N        0x100
+
+#define DDR_PHY_SLICE_REGSET_NUM_M3N  101
+#define DDR_PHY_ADR_V_REGSET_NUM_M3N  37
+#define DDR_PHY_ADR_I_REGSET_NUM_M3N  37
+#define DDR_PHY_ADR_G_REGSET_NUM_M3N  87
+#define DDR_PI_REGSET_NUM_M3N         286
+
+static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = {
+/*0800*/ 0x76543210,
+/*0801*/ 0x0004f008,
+/*0802*/ 0x00020200,
+/*0803*/ 0x00000000,
+/*0804*/ 0x00000000,
+/*0805*/ 0x00010000,
+/*0806*/ 0x036e6e0e,
+/*0807*/ 0x026e6e0e,
+/*0808*/ 0x00000103,
+/*0809*/ 0x00040001,
+/*080a*/ 0x00000103,
+/*080b*/ 0x00000001,
+/*080c*/ 0x00000000,
+/*080d*/ 0x00000000,
+/*080e*/ 0x00000100,
+/*080f*/ 0x001800c0,
+/*0810*/ 0x020100b0,
+/*0811*/ 0x00030020,
+/*0812*/ 0x00000000,
+/*0813*/ 0x00000000,
+/*0814*/ 0x0000aaaa,
+/*0815*/ 0x00005555,
+/*0816*/ 0x0000b5b5,
+/*0817*/ 0x00004a4a,
+/*0818*/ 0x00000000,
+/*0819*/ 0x09000000,
+/*081a*/ 0x04080000,
+/*081b*/ 0x08040000,
+/*081c*/ 0x00000004,
+/*081d*/ 0x00800710,
+/*081e*/ 0x000f000c,
+/*081f*/ 0x00000100,
+/*0820*/ 0x55aa55aa,
+/*0821*/ 0x33cc33cc,
+/*0822*/ 0x0ff00ff0,
+/*0823*/ 0x0f0ff0f0,
+/*0824*/ 0x00018e38,
+/*0825*/ 0x00000000,
+/*0826*/ 0x00000000,
+/*0827*/ 0x00000000,
+/*0828*/ 0x00000000,
+/*0829*/ 0x00000000,
+/*082a*/ 0x00000000,
+/*082b*/ 0x00000000,
+/*082c*/ 0x00000000,
+/*082d*/ 0x00000000,
+/*082e*/ 0x00000000,
+/*082f*/ 0x00000000,
+/*0830*/ 0x00000000,
+/*0831*/ 0x00000000,
+/*0832*/ 0x00000000,
+/*0833*/ 0x00000000,
+/*0834*/ 0x00000000,
+/*0835*/ 0x00000000,
+/*0836*/ 0x00000000,
+/*0837*/ 0x00000000,
+/*0838*/ 0x00000000,
+/*0839*/ 0x00000000,
+/*083a*/ 0x00000104,
+/*083b*/ 0x00082020,
+/*083c*/ 0x08200820,
+/*083d*/ 0x08200820,
+/*083e*/ 0x08200820,
+/*083f*/ 0x08200820,
+/*0840*/ 0x08200820,
+/*0841*/ 0x00000000,
+/*0842*/ 0x00000000,
+/*0843*/ 0x03000300,
+/*0844*/ 0x03000300,
+/*0845*/ 0x03000300,
+/*0846*/ 0x03000300,
+/*0847*/ 0x00000300,
+/*0848*/ 0x00000000,
+/*0849*/ 0x00000000,
+/*084a*/ 0x00000000,
+/*084b*/ 0x00000000,
+/*084c*/ 0x00000000,
+/*084d*/ 0x00a000a0,
+/*084e*/ 0x00a000a0,
+/*084f*/ 0x00a000a0,
+/*0850*/ 0x00a000a0,
+/*0851*/ 0x00a000a0,
+/*0852*/ 0x00a000a0,
+/*0853*/ 0x00a000a0,
+/*0854*/ 0x00a000a0,
+/*0855*/ 0x00a000a0,
+/*0856*/ 0x01040119,
+/*0857*/ 0x00000200,
+/*0858*/ 0x01000000,
+/*0859*/ 0x00000200,
+/*085a*/ 0x00000004,
+/*085b*/ 0x4041a141,
+/*085c*/ 0x0141c0a0,
+/*085d*/ 0x0000c0c0,
+/*085e*/ 0x0e0c000e,
+/*085f*/ 0x10001000,
+/*0860*/ 0x0c073e42,
+/*0861*/ 0x000f0c28,
+/*0862*/ 0x00e00140,
+/*0863*/ 0x000c0020,
+/*0864*/ 0x00000203
+};
+
+static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = {
+/*0a00*/ 0x00000000,
+/*0a01*/ 0x00000000,
+/*0a02*/ 0x00000000,
+/*0a03*/ 0x00000000,
+/*0a04*/ 0x00000000,
+/*0a05*/ 0x00000000,
+/*0a06*/ 0x00000000,
+/*0a07*/ 0x01000000,
+/*0a08*/ 0x00020000,
+/*0a09*/ 0x00000000,
+/*0a0a*/ 0x00000000,
+/*0a0b*/ 0x00000000,
+/*0a0c*/ 0x00400000,
+/*0a0d*/ 0x00000080,
+/*0a0e*/ 0x00dcba98,
+/*0a0f*/ 0x03000000,
+/*0a10*/ 0x00000200,
+/*0a11*/ 0x00000000,
+/*0a12*/ 0x00000000,
+/*0a13*/ 0x00000000,
+/*0a14*/ 0x0000002a,
+/*0a15*/ 0x00000015,
+/*0a16*/ 0x00000015,
+/*0a17*/ 0x0000002a,
+/*0a18*/ 0x00000033,
+/*0a19*/ 0x0000000c,
+/*0a1a*/ 0x0000000c,
+/*0a1b*/ 0x00000033,
+/*0a1c*/ 0x0a418820,
+/*0a1d*/ 0x003f0000,
+/*0a1e*/ 0x0000013f,
+/*0a1f*/ 0x0002c06e,
+/*0a20*/ 0x02c002c0,
+/*0a21*/ 0x02c002c0,
+/*0a22*/ 0x000002c0,
+/*0a23*/ 0x42080010,
+/*0a24*/ 0x0000033e
+};
+
+static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = {
+/*0a80*/ 0x00000000,
+/*0a81*/ 0x00000000,
+/*0a82*/ 0x00000000,
+/*0a83*/ 0x00000000,
+/*0a84*/ 0x00000000,
+/*0a85*/ 0x00000000,
+/*0a86*/ 0x00000000,
+/*0a87*/ 0x01000000,
+/*0a88*/ 0x00020000,
+/*0a89*/ 0x00000000,
+/*0a8a*/ 0x00000000,
+/*0a8b*/ 0x00000000,
+/*0a8c*/ 0x00400000,
+/*0a8d*/ 0x00000080,
+/*0a8e*/ 0x00000000,
+/*0a8f*/ 0x03000000,
+/*0a90*/ 0x00000200,
+/*0a91*/ 0x00000000,
+/*0a92*/ 0x00000000,
+/*0a93*/ 0x00000000,
+/*0a94*/ 0x0000002a,
+/*0a95*/ 0x00000015,
+/*0a96*/ 0x00000015,
+/*0a97*/ 0x0000002a,
+/*0a98*/ 0x00000033,
+/*0a99*/ 0x0000000c,
+/*0a9a*/ 0x0000000c,
+/*0a9b*/ 0x00000033,
+/*0a9c*/ 0x00000000,
+/*0a9d*/ 0x00000000,
+/*0a9e*/ 0x00000000,
+/*0a9f*/ 0x0002c06e,
+/*0aa0*/ 0x02c002c0,
+/*0aa1*/ 0x02c002c0,
+/*0aa2*/ 0x000002c0,
+/*0aa3*/ 0x42080010,
+/*0aa4*/ 0x0000033e
+};
+
+static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
+/*0b80*/ 0x00000000,
+/*0b81*/ 0x00000100,
+/*0b82*/ 0x00000000,
+/*0b83*/ 0x00050000,
+/*0b84*/ 0x00000000,
+/*0b85*/ 0x0004000f,
+/*0b86*/ 0x00280080,
+/*0b87*/ 0x02005502,
+/*0b88*/ 0x00000000,
+/*0b89*/ 0x00000000,
+/*0b8a*/ 0x00000000,
+/*0b8b*/ 0x00000050,
+/*0b8c*/ 0x00000000,
+/*0b8d*/ 0x01010100,
+/*0b8e*/ 0x00010000,
+/*0b8f*/ 0x00000000,
+/*0b90*/ 0x00000101,
+/*0b91*/ 0x00000000,
+/*0b92*/ 0x00000000,
+/*0b93*/ 0x00000000,
+/*0b94*/ 0x00000000,
+/*0b95*/ 0x00005064,
+/*0b96*/ 0x01421142,
+/*0b97*/ 0x00000142,
+/*0b98*/ 0x00000000,
+/*0b99*/ 0x000f1600,
+/*0b9a*/ 0x0f160f16,
+/*0b9b*/ 0x0f160f16,
+/*0b9c*/ 0x00000003,
+/*0b9d*/ 0x0002c000,
+/*0b9e*/ 0x02c002c0,
+/*0b9f*/ 0x000002c0,
+/*0ba0*/ 0x08040201,
+/*0ba1*/ 0x01421142,
+/*0ba2*/ 0x00000142,
+/*0ba3*/ 0x00000000,
+/*0ba4*/ 0x00000000,
+/*0ba5*/ 0x05030000,
+/*0ba6*/ 0x00010700,
+/*0ba7*/ 0x00000014,
+/*0ba8*/ 0x00027f6e,
+/*0ba9*/ 0x047f027f,
+/*0baa*/ 0x00027f6e,
+/*0bab*/ 0x00047f6e,
+/*0bac*/ 0x0003554f,
+/*0bad*/ 0x0001554f,
+/*0bae*/ 0x0001554f,
+/*0baf*/ 0x0001554f,
+/*0bb0*/ 0x0001554f,
+/*0bb1*/ 0x00003fee,
+/*0bb2*/ 0x0001554f,
+/*0bb3*/ 0x00003fee,
+/*0bb4*/ 0x0001554f,
+/*0bb5*/ 0x00027f6e,
+/*0bb6*/ 0x0001554f,
+/*0bb7*/ 0x00004011,
+/*0bb8*/ 0x00004410,
+/*0bb9*/ 0x00000000,
+/*0bba*/ 0x00000000,
+/*0bbb*/ 0x00000000,
+/*0bbc*/ 0x00000065,
+/*0bbd*/ 0x00000000,
+/*0bbe*/ 0x00040401,
+/*0bbf*/ 0x00000000,
+/*0bc0*/ 0x03000000,
+/*0bc1*/ 0x00000020,
+/*0bc2*/ 0x00000000,
+/*0bc3*/ 0x00000000,
+/*0bc4*/ 0x04102006,
+/*0bc5*/ 0x00041020,
+/*0bc6*/ 0x01c98c98,
+/*0bc7*/ 0x00400000,
+/*0bc8*/ 0x00000000,
+/*0bc9*/ 0x0001ffff,
+/*0bca*/ 0x00000000,
+/*0bcb*/ 0x00000000,
+/*0bcc*/ 0x00000001,
+/*0bcd*/ 0x00000000,
+/*0bce*/ 0x00000000,
+/*0bcf*/ 0x00000000,
+/*0bd0*/ 0x76543210,
+/*0bd1*/ 0x06010198,
+/*0bd2*/ 0x00000000,
+/*0bd3*/ 0x00000000,
+/*0bd4*/ 0x04070000,
+/*0bd5*/ 0x00000001,
+/*0bd6*/ 0x00000f00
+};
+
+static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = {
+/*0200*/ 0x00000b00,
+/*0201*/ 0x00000101,
+/*0202*/ 0x01640000,
+/*0203*/ 0x00000014,
+/*0204*/ 0x00000014,
+/*0205*/ 0x00000014,
+/*0206*/ 0x00000014,
+/*0207*/ 0x00000000,
+/*0208*/ 0x00000000,
+/*0209*/ 0x0000ffff,
+/*020a*/ 0x00000000,
+/*020b*/ 0x0000ffff,
+/*020c*/ 0x00000000,
+/*020d*/ 0x0000ffff,
+/*020e*/ 0x0000304c,
+/*020f*/ 0x00000200,
+/*0210*/ 0x00000200,
+/*0211*/ 0x00000200,
+/*0212*/ 0x00000200,
+/*0213*/ 0x0000304c,
+/*0214*/ 0x00000200,
+/*0215*/ 0x00000200,
+/*0216*/ 0x00000200,
+/*0217*/ 0x00000200,
+/*0218*/ 0x0000304c,
+/*0219*/ 0x00000200,
+/*021a*/ 0x00000200,
+/*021b*/ 0x00000200,
+/*021c*/ 0x00000200,
+/*021d*/ 0x00010000,
+/*021e*/ 0x00000003,
+/*021f*/ 0x01000001,
+/*0220*/ 0x00000000,
+/*0221*/ 0x00000000,
+/*0222*/ 0x00000000,
+/*0223*/ 0x00000000,
+/*0224*/ 0x00000000,
+/*0225*/ 0x00000000,
+/*0226*/ 0x00000000,
+/*0227*/ 0x00000000,
+/*0228*/ 0x00000000,
+/*0229*/ 0x00000000,
+/*022a*/ 0x00000000,
+/*022b*/ 0x00000000,
+/*022c*/ 0x00000000,
+/*022d*/ 0x00000000,
+/*022e*/ 0x00000000,
+/*022f*/ 0x00000000,
+/*0230*/ 0x0f000101,
+/*0231*/ 0x084d3129,
+/*0232*/ 0x0e0c0004,
+/*0233*/ 0x000e5000,
+/*0234*/ 0x01000250,
+/*0235*/ 0x00000003,
+/*0236*/ 0x00000046,
+/*0237*/ 0x000000cf,
+/*0238*/ 0x00001826,
+/*0239*/ 0x000000cf,
+/*023a*/ 0x00001826,
+/*023b*/ 0x00000000,
+/*023c*/ 0x00000000,
+/*023d*/ 0x00000000,
+/*023e*/ 0x00000000,
+/*023f*/ 0x00000000,
+/*0240*/ 0x00000000,
+/*0241*/ 0x00000000,
+/*0242*/ 0x00000000,
+/*0243*/ 0x00000000,
+/*0244*/ 0x00000000,
+/*0245*/ 0x01000000,
+/*0246*/ 0x00040404,
+/*0247*/ 0x01280a00,
+/*0248*/ 0x00000001,
+/*0249*/ 0x00000000,
+/*024a*/ 0x03000f00,
+/*024b*/ 0x00200020,
+/*024c*/ 0x00000020,
+/*024d*/ 0x00000000,
+/*024e*/ 0x00000000,
+/*024f*/ 0x00010002,
+/*0250*/ 0x01010001,
+/*0251*/ 0x02010100,
+/*0252*/ 0x08040402,
+/*0253*/ 0x00000008,
+/*0254*/ 0x00000000,
+/*0255*/ 0x04080803,
+/*0256*/ 0x00001515,
+/*0257*/ 0x00000000,
+/*0258*/ 0x000000aa,
+/*0259*/ 0x00000055,
+/*025a*/ 0x000000b5,
+/*025b*/ 0x0000004a,
+/*025c*/ 0x00000056,
+/*025d*/ 0x000000a9,
+/*025e*/ 0x000000a9,
+/*025f*/ 0x000000b5,
+/*0260*/ 0x00000000,
+/*0261*/ 0x00000000,
+/*0262*/ 0x0f000000,
+/*0263*/ 0x00001e0f,
+/*0264*/ 0x000007d0,
+/*0265*/ 0x01000300,
+/*0266*/ 0x00000100,
+/*0267*/ 0x00000000,
+/*0268*/ 0x00000000,
+/*0269*/ 0x01000000,
+/*026a*/ 0x00010101,
+/*026b*/ 0x000e0e0e,
+/*026c*/ 0x000c0c0c,
+/*026d*/ 0x01060601,
+/*026e*/ 0x04041717,
+/*026f*/ 0x00000004,
+/*0270*/ 0x00000300,
+/*0271*/ 0x17030000,
+/*0272*/ 0x00060018,
+/*0273*/ 0x00160028,
+/*0274*/ 0x00160028,
+/*0275*/ 0x00000000,
+/*0276*/ 0x00000000,
+/*0277*/ 0x00000000,
+/*0278*/ 0x0a000000,
+/*0279*/ 0x00010a14,
+/*027a*/ 0x00030005,
+/*027b*/ 0x0003018d,
+/*027c*/ 0x000a018d,
+/*027d*/ 0x00060100,
+/*027e*/ 0x01000006,
+/*027f*/ 0x018e018e,
+/*0280*/ 0x018e0100,
+/*0281*/ 0x1e1a018e,
+/*0282*/ 0x1e1a1e1a,
+/*0283*/ 0x01010204,
+/*0284*/ 0x06501001,
+/*0285*/ 0x090d0a07,
+/*0286*/ 0x090d0a07,
+/*0287*/ 0x0811180f,
+/*0288*/ 0x00ff1102,
+/*0289*/ 0x00ff1000,
+/*028a*/ 0x00ff1000,
+/*028b*/ 0x04041000,
+/*028c*/ 0x18020100,
+/*028d*/ 0x01010018,
+/*028e*/ 0x005f005f,
+/*028f*/ 0x005f005f,
+/*0290*/ 0x050f0000,
+/*0291*/ 0x051e051e,
+/*0292*/ 0x0c01021e,
+/*0293*/ 0x00000c0c,
+/*0294*/ 0x00003400,
+/*0295*/ 0x00000000,
+/*0296*/ 0x00000000,
+/*0297*/ 0x00000000,
+/*0298*/ 0x00000000,
+/*0299*/ 0x002e00d4,
+/*029a*/ 0x11360031,
+/*029b*/ 0x00d41611,
+/*029c*/ 0x0031002e,
+/*029d*/ 0x16111136,
+/*029e*/ 0x002e00d4,
+/*029f*/ 0x11360031,
+/*02a0*/ 0x00001611,
+/*02a1*/ 0x002e00d4,
+/*02a2*/ 0x11360031,
+/*02a3*/ 0x00d41611,
+/*02a4*/ 0x0031002e,
+/*02a5*/ 0x16111136,
+/*02a6*/ 0x002e00d4,
+/*02a7*/ 0x11360031,
+/*02a8*/ 0x00001611,
+/*02a9*/ 0x002e00d4,
+/*02aa*/ 0x11360031,
+/*02ab*/ 0x00d41611,
+/*02ac*/ 0x0031002e,
+/*02ad*/ 0x16111136,
+/*02ae*/ 0x002e00d4,
+/*02af*/ 0x11360031,
+/*02b0*/ 0x00001611,
+/*02b1*/ 0x002e00d4,
+/*02b2*/ 0x11360031,
+/*02b3*/ 0x00d41611,
+/*02b4*/ 0x0031002e,
+/*02b5*/ 0x16111136,
+/*02b6*/ 0x002e00d4,
+/*02b7*/ 0x11360031,
+/*02b8*/ 0x00001611,
+/*02b9*/ 0x00018d00,
+/*02ba*/ 0x018d018d,
+/*02bb*/ 0x1d220c08,
+/*02bc*/ 0x00001f12,
+/*02bd*/ 0x4301b344,
+/*02be*/ 0x17032006,
+/*02bf*/ 0x220c1010,
+/*02c0*/ 0x001f121d,
+/*02c1*/ 0x4301b344,
+/*02c2*/ 0x17062006,
+/*02c3*/ 0x220c1010,
+/*02c4*/ 0x001f121d,
+/*02c5*/ 0x4301b344,
+/*02c6*/ 0x17182006,
+/*02c7*/ 0x00021010,
+/*02c8*/ 0x00020002,
+/*02c9*/ 0x00020002,
+/*02ca*/ 0x00020002,
+/*02cb*/ 0x00020002,
+/*02cc*/ 0x00000002,
+/*02cd*/ 0x00000000,
+/*02ce*/ 0x00000000,
+/*02cf*/ 0x00000000,
+/*02d0*/ 0x00000000,
+/*02d1*/ 0x00000000,
+/*02d2*/ 0x00000000,
+/*02d3*/ 0x00000000,
+/*02d4*/ 0x00000000,
+/*02d5*/ 0x00000000,
+/*02d6*/ 0x00000000,
+/*02d7*/ 0x00000000,
+/*02d8*/ 0x00000000,
+/*02d9*/ 0x00000400,
+/*02da*/ 0x15141312,
+/*02db*/ 0x11100f0e,
+/*02dc*/ 0x080b0c0d,
+/*02dd*/ 0x05040a09,
+/*02de*/ 0x01000706,
+/*02df*/ 0x00000302,
+/*02e0*/ 0x01030201,
+/*02e1*/ 0x00304c08,
+/*02e2*/ 0x0001e2f8,
+/*02e3*/ 0x0000304c,
+/*02e4*/ 0x0001e2f8,
+/*02e5*/ 0x0000304c,
+/*02e6*/ 0x0001e2f8,
+/*02e7*/ 0x08000000,
+/*02e8*/ 0x00000100,
+/*02e9*/ 0x00000000,
+/*02ea*/ 0x00000000,
+/*02eb*/ 0x00000000,
+/*02ec*/ 0x00000000,
+/*02ed*/ 0x00010000,
+/*02ee*/ 0x00000000,
+/*02ef*/ 0x00000000,
+/*02f0*/ 0x00000000,
+/*02f1*/ 0x00000000,
+/*02f2*/ 0x00000000,
+/*02f3*/ 0x00000000,
+/*02f4*/ 0x00000000,
+/*02f5*/ 0x00000000,
+/*02f6*/ 0x00000000,
+/*02f7*/ 0x00000000,
+/*02f8*/ 0x00000000,
+/*02f9*/ 0x00000000,
+/*02fa*/ 0x00000000,
+/*02fb*/ 0x00000000,
+/*02fc*/ 0x00000000,
+/*02fd*/ 0x00000000,
+/*02fe*/ 0x00000000,
+/*02ff*/ 0x00000000,
+/*0300*/ 0x00000000,
+/*0301*/ 0x00000000,
+/*0302*/ 0x00000000,
+/*0303*/ 0x00000000,
+/*0304*/ 0x00000000,
+/*0305*/ 0x00000000,
+/*0306*/ 0x00000000,
+/*0307*/ 0x00000000,
+/*0308*/ 0x00000000,
+/*0309*/ 0x00000000,
+/*030a*/ 0x00000000,
+/*030b*/ 0x00000000,
+/*030c*/ 0x00000000,
+/*030d*/ 0x00000000,
+/*030e*/ 0x00000000,
+/*030f*/ 0x00050002,
+/*0310*/ 0x015c0057,
+/*0311*/ 0x01000100,
+/*0312*/ 0x01020001,
+/*0313*/ 0x00010300,
+/*0314*/ 0x05000104,
+/*0315*/ 0x01060001,
+/*0316*/ 0x00010700,
+/*0317*/ 0x00000000,
+/*0318*/ 0x00000000,
+/*0319*/ 0x00000001,
+/*031a*/ 0x00000000,
+/*031b*/ 0x00000000,
+/*031c*/ 0x00000000,
+/*031d*/ 0x20080101
+};
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
new file mode 100644
index 0000000..4bf6942
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <debug.h>
+#include "dram_sub_func.h"
+
+#define PRR				(0xFFF00044U)
+#define PRR_PRODUCT_MASK		(0x00007F00U)
+#define PRR_CUT_MASK			(0x000000FFU)
+#define PRR_PRODUCT_H3			(0x00004F00U)	/* R-Car H3  */
+#define PRR_PRODUCT_M3			(0x00005200U)	/* R-Car M3  */
+#define PRR_PRODUCT_M3N			(0x00005500U)	/* R-Car M3N */
+#define PRR_PRODUCT_E3			(0x00005700U)	/* R-Car E3  */
+#define PRR_PRODUCT_V3H			(0x00005600U)	/* R-Car V3H */
+
+#if RCAR_SYSTEM_SUSPEND
+#include "iic_dvfs.h"
+
+#define DRAM_BACKUP_GPIO_USE		(0)
+#if PMIC_ROHM_BD9571
+#define	PMIC_BKUP_MODE_CNT		(0x20U)
+#define	PMIC_QLLM_CNT			(0x27U)
+#define	BIT_BKUP_CTRL_OUT		((uint8_t)(1U << 4U))
+#define	BIT_QLLM_DDR0_EN		((uint8_t)(1U << 0U))
+#define	BIT_QLLM_DDR1_EN		((uint8_t)(1U << 1U))
+#endif
+
+#define	GPIO_OUTDT1			(0xE6051008U)
+#define GPIO_INDT1			(0xE605100CU)
+#define GPIO_OUTDT3			(0xE6053008U)
+#define GPIO_INDT3			(0xE605300CU)
+#define GPIO_OUTDT6			(0xE6055408U)
+#define GPIO_INDT6			(0xE605540CU)
+
+#if DRAM_BACKUP_GPIO_USE == 1
+#define GPIO_BKUP_REQB_SHIFT_SALVATOR	(9U)	/* GP1_9 (BKUP_REQB) */
+#define GPIO_BKUP_REQB_SHIFT_EBISU	(14U)	/* GP6_14(BKUP_REQB) */
+#define GPIO_BKUP_REQB_SHIFT_CONDOR	(1U)	/* GP3_1 (BKUP_REQB) */
+#endif
+#define GPIO_BKUP_TRG_SHIFT_SALVATOR	(8U)	/* GP1_8 (BKUP_TRG) */
+#define GPIO_BKUP_TRG_SHIFT_EBISU	(13U)	/* GP6_13(BKUP_TRG) */
+#define GPIO_BKUP_TRG_SHIFT_CONDOR	(0U)	/* GP3_0 (BKUP_TRG) */
+
+#define DRAM_BKUP_TRG_LOOP_CNT	(1000U)
+#endif
+
+void rcar_dram_get_boot_status(uint32_t * status)
+{
+#if RCAR_SYSTEM_SUSPEND
+	uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
+	uint32_t gpio = GPIO_INDT1;
+	uint32_t reg, product;
+
+	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+
+	if (product == PRR_PRODUCT_V3H) {
+		shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
+		gpio = GPIO_INDT3;
+	} else if (product == PRR_PRODUCT_E3) {
+		shift = GPIO_BKUP_TRG_SHIFT_EBISU;
+		gpio = GPIO_INDT6;
+	}
+
+	reg = mmio_read_32(gpio) & (1U << shift);
+	*status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD;
+#else
+	*status = DRAM_BOOT_STATUS_COLD;
+#endif
+}
+
+int32_t rcar_dram_update_boot_status(uint32_t status)
+{
+	int32_t ret = 0;
+#if RCAR_SYSTEM_SUSPEND
+#if PMIC_ROHM_BD9571
+#if DRAM_BACKUP_GPIO_USE == 0
+	uint8_t mode = 0U;
+#else
+	uint32_t reqb, outd;
+#endif
+	uint8_t qllm = 0;
+#endif
+	uint32_t i, product, trg, gpio;
+
+	product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+	if (product == PRR_PRODUCT_V3H) {
+#if DRAM_BACKUP_GPIO_USE == 1
+		reqb = GPIO_BKUP_REQB_SHIFT_CONDOR;
+		outd = GPIO_OUTDT3;
+#endif
+		trg = GPIO_BKUP_TRG_SHIFT_CONDOR;
+		gpio = GPIO_INDT3;
+	} else if (product == PRR_PRODUCT_E3) {
+#if DRAM_BACKUP_GPIO_USE == 1
+		reqb = GPIO_BKUP_REQB_SHIFT_EBISU;
+		outd = GPIO_OUTDT6;
+#endif
+		trg = GPIO_BKUP_TRG_SHIFT_EBISU;
+		gpio = GPIO_INDT6;
+	} else {
+#if DRAM_BACKUP_GPIO_USE == 1
+		reqb = GPIO_BKUP_REQB_SHIFT_SALVATOR;
+		outd = GPIO_OUTDT1;
+#endif
+		trg = GPIO_BKUP_TRG_SHIFT_SALVATOR;
+		gpio = GPIO_INDT1;
+	}
+
+	if (status != DRAM_BOOT_STATUS_WARM)
+		goto cold;
+
+#if DRAM_BACKUP_GPIO_USE==1
+	mmio_setbits_32(outd, 1U << reqb);
+#else
+
+#if PMIC_ROHM_BD9571
+	if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) {
+		ERROR("BKUP mode cnt READ ERROR.\n");
+		return DRAM_UPDATE_STATUS_ERR;
+	}
+
+	mode &= ~BIT_BKUP_CTRL_OUT;
+	if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) {
+		ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode);
+		return DRAM_UPDATE_STATUS_ERR;
+	}
+#endif
+#endif
+	for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) {
+		if (mmio_read_32(gpio) & (1U << trg))
+			continue;
+
+		goto cold;
+	}
+
+	ERROR("\nWarm booting Error...\n"
+	      " The potential of BKUP_TRG did not switch "
+	      "to Low.\n If you expect the operation of "
+	      "cold boot,\n check the board configuration"
+	      " (ex, Dip-SW) and/or the H/W failure.\n");
+
+	return DRAM_UPDATE_STATUS_ERR;
+
+cold:
+#if PMIC_ROHM_BD9571
+	if (ret)
+		return ret;
+
+	qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
+	if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) {
+		ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm);
+		ret = DRAM_UPDATE_STATUS_ERR;
+	}
+#endif
+#endif
+	return ret;
+}
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.h b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h
new file mode 100644
index 0000000..e083bfb
--- /dev/null
+++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DRAM_SUB_FUNC_H_
+#define DRAM_SUB_FUNC_H_
+
+#define DRAM_UPDATE_STATUS_ERR	(-1)
+#define DRAM_BOOT_STATUS_COLD	(0)
+#define DRAM_BOOT_STATUS_WARM	(1)
+
+int32_t rcar_dram_update_boot_status(uint32_t status);
+void rcar_dram_get_boot_status(uint32_t * status);
+
+#endif
diff --git a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
new file mode 100644
index 0000000..d75aa7c
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
@@ -0,0 +1,800 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <mmio.h>
+#include "pfc_init_e3.h"
+#include "rcar_def.h"
+
+/* GPIO base address */
+#define	GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
+#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
+#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
+#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
+#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
+#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
+#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
+#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
+#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
+#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
+#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
+#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
+#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
+#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
+#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
+#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
+#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
+#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
+#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
+#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
+#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
+#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
+#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
+#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
+#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
+#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
+#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
+#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
+#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
+#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
+#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
+#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
+#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
+#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
+#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
+
+/* Pin functon base address */
+#define	PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define	PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
+#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
+#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
+#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
+#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
+#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
+#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
+#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
+#define PFC_IOCTRL30		(PFC_BASE + 0x0380U)
+#define PFC_IOCTRL32		(PFC_BASE + 0x0388U)
+#define PFC_IOCTRL40		(PFC_BASE + 0x03C0U)
+#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
+#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
+#define	PFC_PUD0		(PFC_BASE + 0x0440U)
+#define	PFC_PUD1		(PFC_BASE + 0x0444U)
+#define	PFC_PUD2		(PFC_BASE + 0x0448U)
+#define	PFC_PUD3		(PFC_BASE + 0x044CU)
+#define	PFC_PUD4		(PFC_BASE + 0x0450U)
+#define	PFC_PUD5		(PFC_BASE + 0x0454U)
+#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
+#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
+
+#define GPSR0_SDA4		((uint32_t)1U << 17U)
+#define GPSR0_SCL4		((uint32_t)1U << 16U)
+#define	GPSR0_D15		((uint32_t)1U << 15U)
+#define	GPSR0_D14		((uint32_t)1U << 14U)
+#define	GPSR0_D13		((uint32_t)1U << 13U)
+#define	GPSR0_D12		((uint32_t)1U << 12U)
+#define	GPSR0_D11		((uint32_t)1U << 11U)
+#define	GPSR0_D10		((uint32_t)1U << 10U)
+#define	GPSR0_D9		((uint32_t)1U << 9U)
+#define	GPSR0_D8		((uint32_t)1U << 8U)
+#define	GPSR0_D7		((uint32_t)1U << 7U)
+#define	GPSR0_D6		((uint32_t)1U << 6U)
+#define	GPSR0_D5		((uint32_t)1U << 5U)
+#define	GPSR0_D4		((uint32_t)1U << 4U)
+#define	GPSR0_D3		((uint32_t)1U << 3U)
+#define	GPSR0_D2		((uint32_t)1U << 2U)
+#define	GPSR0_D1		((uint32_t)1U << 1U)
+#define	GPSR0_D0		((uint32_t)1U << 0U)
+#define	GPSR1_WE0		((uint32_t)1U << 22U)
+#define	GPSR1_CS0		((uint32_t)1U << 21U)
+#define	GPSR1_CLKOUT		((uint32_t)1U << 20U)
+#define	GPSR1_A19		((uint32_t)1U << 19U)
+#define	GPSR1_A18		((uint32_t)1U << 18U)
+#define	GPSR1_A17		((uint32_t)1U << 17U)
+#define	GPSR1_A16		((uint32_t)1U << 16U)
+#define	GPSR1_A15		((uint32_t)1U << 15U)
+#define	GPSR1_A14		((uint32_t)1U << 14U)
+#define	GPSR1_A13		((uint32_t)1U << 13U)
+#define	GPSR1_A12		((uint32_t)1U << 12U)
+#define	GPSR1_A11		((uint32_t)1U << 11U)
+#define	GPSR1_A10		((uint32_t)1U << 10U)
+#define	GPSR1_A9		((uint32_t)1U << 9U)
+#define	GPSR1_A8		((uint32_t)1U << 8U)
+#define	GPSR1_A7		((uint32_t)1U << 7U)
+#define	GPSR1_A6		((uint32_t)1U << 6U)
+#define	GPSR1_A5		((uint32_t)1U << 5U)
+#define	GPSR1_A4		((uint32_t)1U << 4U)
+#define	GPSR1_A3		((uint32_t)1U << 3U)
+#define	GPSR1_A2		((uint32_t)1U << 2U)
+#define	GPSR1_A1		((uint32_t)1U << 1U)
+#define	GPSR1_A0		((uint32_t)1U << 0U)
+#define	GPSR2_BIT27_REVERCED 	((uint32_t)1U << 27U)
+#define	GPSR2_BIT26_REVERCED 	((uint32_t)1U << 26U)
+#define	GPSR2_EX_WAIT0		((uint32_t)1U << 25U)
+#define	GPSR2_RD_WR		((uint32_t)1U << 24U)
+#define	GPSR2_RD		((uint32_t)1U << 23U)
+#define	GPSR2_BS		((uint32_t)1U << 22U)
+#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 21U)
+#define GPSR2_AVB_TXCREFCLK	((uint32_t)1U << 20U)
+#define	GPSR2_AVB_RD3		((uint32_t)1U << 19U)
+#define	GPSR2_AVB_RD2		((uint32_t)1U << 18U)
+#define	GPSR2_AVB_RD1		((uint32_t)1U << 17U)
+#define	GPSR2_AVB_RD0		((uint32_t)1U << 16U)
+#define	GPSR2_AVB_RXC		((uint32_t)1U << 15U)
+#define	GPSR2_AVB_RX_CTL	((uint32_t)1U << 14U)
+#define GPSR2_RPC_RESET		((uint32_t)1U << 13U)
+#define GPSR2_RPC_RPC_INT	((uint32_t)1U << 12U)
+#define GPSR2_QSPI1_SSL		((uint32_t)1U << 11U)
+#define GPSR2_QSPI1_IO3		((uint32_t)1U << 10U)
+#define GPSR2_QSPI1_IO2		((uint32_t)1U << 9U)
+#define GPSR2_QSPI1_MISO_IO1	((uint32_t)1U << 8U)
+#define GPSR2_QSPI1_MOSI_IO0	((uint32_t)1U << 7U)
+#define GPSR2_QSPI1_SPCLK	((uint32_t)1U << 6U)
+#define GPSR2_QSPI0_SSL		((uint32_t)1U << 5U)
+#define GPSR2_QSPI0_IO3		((uint32_t)1U << 4U)
+#define GPSR2_QSPI0_IO2		((uint32_t)1U << 3U)
+#define GPSR2_QSPI0_MISO_IO1	((uint32_t)1U << 2U)
+#define GPSR2_QSPI0_MOSI_IO0	((uint32_t)1U << 1U)
+#define GPSR2_QSPI0_SPCLK	((uint32_t)1U << 0U)
+#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
+#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
+#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
+#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
+#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
+#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
+#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
+#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
+#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
+#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
+#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
+#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
+#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
+#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
+#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
+#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
+#define	GPSR4_SD3_DS		((uint32_t)1U << 10U)
+#define	GPSR4_SD3_DAT7		((uint32_t)1U << 9U)
+#define	GPSR4_SD3_DAT6		((uint32_t)1U << 8U)
+#define	GPSR4_SD3_DAT5		((uint32_t)1U << 7U)
+#define	GPSR4_SD3_DAT4		((uint32_t)1U << 6U)
+#define	GPSR4_SD3_DAT3		((uint32_t)1U << 5U)
+#define	GPSR4_SD3_DAT2		((uint32_t)1U << 4U)
+#define	GPSR4_SD3_DAT1		((uint32_t)1U << 3U)
+#define	GPSR4_SD3_DAT0		((uint32_t)1U << 2U)
+#define	GPSR4_SD3_CMD		((uint32_t)1U << 1U)
+#define	GPSR4_SD3_CLK		((uint32_t)1U << 0U)
+#define	GPSR5_MLB_DAT		((uint32_t)1U << 19U)
+#define	GPSR5_MLB_SIG		((uint32_t)1U << 18U)
+#define	GPSR5_MLB_CLK		((uint32_t)1U << 17U)
+#define	GPSR5_SSI_SDATA9	((uint32_t)1U << 16U)
+#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 15U)
+#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 14U)
+#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 13U)
+#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 12U)
+#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 11U)
+#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 10U)
+#define	GPSR5_RX2_A		((uint32_t)1U << 9U)
+#define	GPSR5_TX2_A		((uint32_t)1U << 8U)
+#define	GPSR5_SCK2_A		((uint32_t)1U << 7U)
+#define	GPSR5_TX1		((uint32_t)1U << 6U)
+#define	GPSR5_RX1		((uint32_t)1U << 5U)
+#define	GPSR5_RTS0_TANS_A	((uint32_t)1U << 4U)
+#define	GPSR5_CTS0_A		((uint32_t)1U << 3U)
+#define	GPSR5_TX0_A		((uint32_t)1U << 2U)
+#define	GPSR5_RX0_A		((uint32_t)1U << 1U)
+#define	GPSR5_SCK0_A		((uint32_t)1U << 0U)
+#define	GPSR6_USB30_PWEN	((uint32_t)1U << 17U)
+#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
+#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
+#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
+#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
+#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
+#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
+#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
+#define	GPSR6_USB30_OVC		((uint32_t)1U << 9U)
+#define	GPSR6_AUDIO_CLKA	((uint32_t)1U << 8U)
+#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
+#define	GPSR6_SSI_WS349		((uint32_t)1U << 6U)
+#define	GPSR6_SSI_SCK349	((uint32_t)1U << 5U)
+#define	GPSR6_SSI_SDATA2	((uint32_t)1U << 4U)
+#define	GPSR6_SSI_SDATA1	((uint32_t)1U << 3U)
+#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
+#define	GPSR6_SSI_WS01239	((uint32_t)1U << 1U)
+#define	GPSR6_SSI_SCK01239	((uint32_t)1U << 0U)
+
+#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define IOCTRL30_MASK		(0x0007F000U)
+#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
+#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
+#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
+#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
+#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
+#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
+#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
+#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
+#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
+#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
+#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
+#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
+#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
+#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
+#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
+#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
+#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
+#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
+#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
+#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
+#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
+#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
+#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
+
+#define IOCTRL32_MASK		(0xFFFFFFFEU)
+#define POC2_VREF_33V		((uint32_t)1U << 0U)
+
+#define	MOD_SEL0_ADGB_A		((uint32_t)0U << 29U)
+#define	MOD_SEL0_ADGB_B		((uint32_t)1U << 29U)
+#define	MOD_SEL0_ADGB_C		((uint32_t)2U << 29U)
+#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 28U)
+#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 28U)
+#define	MOD_SEL0_FM_A		((uint32_t)0U << 26U)
+#define	MOD_SEL0_FM_B		((uint32_t)1U << 26U)
+#define	MOD_SEL0_FM_C		((uint32_t)2U << 26U)
+#define	MOD_SEL0_FSO_A		((uint32_t)0U << 25U)
+#define	MOD_SEL0_FSO_B		((uint32_t)1U << 25U)
+#define	MOD_SEL0_HSCIF0_A	((uint32_t)0U << 24U)
+#define	MOD_SEL0_HSCIF0_B	((uint32_t)1U << 24U)
+#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 23U)
+#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 23U)
+#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 22U)
+#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 22U)
+#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define	MOD_SEL0_I2C1_C		((uint32_t)2U << 20U)
+#define	MOD_SEL0_I2C1_D		((uint32_t)3U << 20U)
+#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 17U)
+#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 17U)
+#define	MOD_SEL0_I2C2_C		((uint32_t)2U << 17U)
+#define	MOD_SEL0_I2C2_D		((uint32_t)3U << 17U)
+#define	MOD_SEL0_I2C2_E		((uint32_t)4U << 17U)
+#define	MOD_SEL0_NDFC_A		((uint32_t)0U << 16U)
+#define	MOD_SEL0_NDFC_B		((uint32_t)1U << 16U)
+#define	MOD_SEL0_PWM0_A		((uint32_t)0U << 15U)
+#define	MOD_SEL0_PWM0_B		((uint32_t)1U << 15U)
+#define	MOD_SEL0_PWM1_A		((uint32_t)0U << 14U)
+#define	MOD_SEL0_PWM1_B		((uint32_t)1U << 14U)
+#define	MOD_SEL0_PWM2_A		((uint32_t)0U << 12U)
+#define	MOD_SEL0_PWM2_B		((uint32_t)1U << 12U)
+#define	MOD_SEL0_PWM2_C		((uint32_t)2U << 12U)
+#define	MOD_SEL0_PWM3_A		((uint32_t)0U << 10U)
+#define	MOD_SEL0_PWM3_B		((uint32_t)1U << 10U)
+#define	MOD_SEL0_PWM3_C		((uint32_t)2U << 10U)
+#define	MOD_SEL0_PWM4_A		((uint32_t)0U << 9U)
+#define	MOD_SEL0_PWM4_B		((uint32_t)1U << 9U)
+#define	MOD_SEL0_PWM5_A		((uint32_t)0U << 8U)
+#define	MOD_SEL0_PWM5_B		((uint32_t)1U << 8U)
+#define	MOD_SEL0_PWM6_A		((uint32_t)0U << 7U)
+#define	MOD_SEL0_PWM6_B		((uint32_t)1U << 7U)
+#define	MOD_SEL0_REMOCON_A	((uint32_t)0U << 5U)
+#define	MOD_SEL0_REMOCON_B	((uint32_t)1U << 5U)
+#define	MOD_SEL0_REMOCON_C	((uint32_t)2U << 5U)
+#define	MOD_SEL0_SCIF_A		((uint32_t)0U << 4U)
+#define	MOD_SEL0_SCIF_B		((uint32_t)1U << 4U)
+#define	MOD_SEL0_SCIF0_A	((uint32_t)0U << 3U)
+#define	MOD_SEL0_SCIF0_B	((uint32_t)1U << 3U)
+#define	MOD_SEL0_SCIF2_A	((uint32_t)0U << 2U)
+#define	MOD_SEL0_SCIF2_B	((uint32_t)1U << 2U)
+#define	MOD_SEL0_SPEED_PULSE_IF_A	((uint32_t)0U << 0U)
+#define	MOD_SEL0_SPEED_PULSE_IF_B	((uint32_t)1U << 0U)
+#define	MOD_SEL0_SPEED_PULSE_IF_C	((uint32_t)2U << 0U)
+#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 31U)
+#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 31U)
+#define	MOD_SEL1_SSI2_A		((uint32_t)0U << 30U)
+#define	MOD_SEL1_SSI2_B		((uint32_t)1U << 30U)
+#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 29U)
+#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 29U)
+#define MOD_SEL1_USB20_CH0_A	((uint32_t)0U << 28U)
+#define MOD_SEL1_USB20_CH0_B	((uint32_t)1U << 28U)
+#define	MOD_SEL1_DRIF2_A	((uint32_t)0U << 26U)
+#define	MOD_SEL1_DRIF2_B	((uint32_t)1U << 26U)
+#define	MOD_SEL1_DRIF3_A	((uint32_t)0U << 25U)
+#define	MOD_SEL1_DRIF3_B	((uint32_t)1U << 25U)
+#define	MOD_SEL1_HSCIF3_A	((uint32_t)0U << 22U)
+#define	MOD_SEL1_HSCIF3_B	((uint32_t)1U << 22U)
+#define	MOD_SEL1_HSCIF3_C	((uint32_t)2U << 22U)
+#define	MOD_SEL1_HSCIF3_D	((uint32_t)3U << 22U)
+#define	MOD_SEL1_HSCIF3_E	((uint32_t)4U << 22U)
+#define	MOD_SEL1_HSCIF4_A	((uint32_t)0U << 19U)
+#define	MOD_SEL1_HSCIF4_B	((uint32_t)1U << 19U)
+#define	MOD_SEL1_HSCIF4_C	((uint32_t)2U << 19U)
+#define	MOD_SEL1_HSCIF4_D	((uint32_t)3U << 19U)
+#define	MOD_SEL1_HSCIF4_E	((uint32_t)4U << 19U)
+#define	MOD_SEL1_I2C6_A		((uint32_t)0U << 18U)
+#define	MOD_SEL1_I2C6_B		((uint32_t)1U << 18U)
+#define	MOD_SEL1_I2C7_A		((uint32_t)0U << 17U)
+#define	MOD_SEL1_I2C7_B		((uint32_t)1U << 17U)
+#define	MOD_SEL1_MSIOF2_A	((uint32_t)0U << 16U)
+#define	MOD_SEL1_MSIOF2_B	((uint32_t)1U << 16U)
+#define	MOD_SEL1_MSIOF3_A	((uint32_t)0U << 15U)
+#define	MOD_SEL1_MSIOF3_B	((uint32_t)1U << 15U)
+#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define	MOD_SEL1_SCIF3_C	((uint32_t)2U << 13U)
+#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 11U)
+#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 11U)
+#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 11U)
+#define	MOD_SEL1_SCIF5_A	((uint32_t)0U << 9U)
+#define	MOD_SEL1_SCIF5_B	((uint32_t)1U << 9U)
+#define	MOD_SEL1_SCIF5_C	((uint32_t)2U << 9U)
+#define	MOD_SEL1_VIN4_A		((uint32_t)0U << 8U)
+#define	MOD_SEL1_VIN4_B		((uint32_t)1U << 8U)
+#define	MOD_SEL1_VIN5_A		((uint32_t)0U << 7U)
+#define	MOD_SEL1_VIN5_B		((uint32_t)1U << 7U)
+#define	MOD_SEL1_ADGC_A		((uint32_t)0U << 5U)
+#define	MOD_SEL1_ADGC_B		((uint32_t)1U << 5U)
+#define	MOD_SEL1_ADGC_C		((uint32_t)2U << 5U)
+#define	MOD_SEL1_SSI9_A		((uint32_t)0U << 4U)
+#define	MOD_SEL1_SSI9_B		((uint32_t)1U << 4U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data);
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t) addr, data);
+}
+
+void pfc_init_e3(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_ADGB_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_FM_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF0_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_NDFC_A
+		      | MOD_SEL0_PWM0_A
+		      | MOD_SEL0_PWM1_A
+		      | MOD_SEL0_PWM2_A
+		      | MOD_SEL0_PWM3_A
+		      | MOD_SEL0_PWM4_A
+		      | MOD_SEL0_PWM5_A
+		      | MOD_SEL0_PWM6_A
+		      | MOD_SEL0_REMOCON_A
+		      | MOD_SEL0_SCIF_A
+		      | MOD_SEL0_SCIF0_A
+		      | MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SSI2_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_USB20_CH0_B
+		      | MOD_SEL1_DRIF2_A
+		      | MOD_SEL1_DRIF3_A
+		      | MOD_SEL1_HSCIF3_A
+		      | MOD_SEL1_HSCIF4_A
+		      | MOD_SEL1_I2C6_A
+		      | MOD_SEL1_I2C7_A
+		      | MOD_SEL1_MSIOF2_A
+		      | MOD_SEL1_MSIOF3_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF5_A
+		      | MOD_SEL1_VIN4_A
+		      | MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)	/* QSPI1_MISO/IO1 */
+		      |IPSR_24_FUNC(0)	/* QSPI1_MOSI/IO0 */
+		      |IPSR_20_FUNC(0)	/* QSPI1_SPCLK */
+		      |IPSR_16_FUNC(0)	/* QSPI0_IO3 */
+		      |IPSR_12_FUNC(0)	/* QSPI0_IO2 */
+		      |IPSR_8_FUNC(0)	/* QSPI0_MISO/IO1 */
+		      |IPSR_4_FUNC(0)	/* QSPI0_MOSI/IO0 */
+		      |IPSR_0_FUNC(0));	/* QSPI0_SPCLK */
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0)	/* AVB_RD2 */
+		      |IPSR_24_FUNC(0)	/* AVB_RD1 */
+		      |IPSR_20_FUNC(0)	/* AVB_RD0 */
+		      |IPSR_16_FUNC(0)	/* RPC_RESET# */
+		      |IPSR_12_FUNC(0)	/* RPC_INT# */
+		      |IPSR_8_FUNC(0)	/* QSPI1_SSL */
+		      |IPSR_4_FUNC(0)	/* QSPI1_IO3 */
+		      |IPSR_0_FUNC(0));	/* QSPI1_IO2 */
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1)	/* IRQ0 */
+		      |IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(2)	/* AVB_LINK */
+		      |IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)	/* AVB_MDC */
+		      |IPSR_4_FUNC(0)	/* AVB_MDIO */
+		      |IPSR_0_FUNC(0));	/* AVB_TXCREFCLK */
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5)	/* DU_HSYNC */
+		      |IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(5)	/* DU_DG4 */
+		      |IPSR_8_FUNC(5)	/* DU_DOTCLKOUT0 */
+		      |IPSR_4_FUNC(5)	/* DU_DISP */
+		      |IPSR_0_FUNC(1));	/* IRQ1 */
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5)	/* DU_DB5 */
+		      |IPSR_24_FUNC(5)	/* DU_DB4 */
+		      |IPSR_20_FUNC(5)	/* DU_DB3 */
+		      |IPSR_16_FUNC(5)	/* DU_DB2 */
+		      |IPSR_12_FUNC(5)	/* DU_DG6 */
+		      |IPSR_8_FUNC(5)	/* DU_VSYNC */
+		      |IPSR_4_FUNC(5)	/* DU_DG5 */
+		      |IPSR_0_FUNC(5));	/* DU_DG7 */
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5)	/* DU_DR3 */
+		      |IPSR_24_FUNC(5)	/* DU_DB7 */
+		      |IPSR_20_FUNC(5)	/* DU_DR2 */
+		      |IPSR_16_FUNC(5)	/* DU_DR1 */
+		      |IPSR_12_FUNC(5)	/* DU_DR0 */
+		      |IPSR_8_FUNC(5)	/* DU_DB1 */
+		      |IPSR_4_FUNC(5)	/* DU_DB0 */
+		      |IPSR_0_FUNC(5));	/* DU_DB6 */
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5)	/* DU_DG1 */
+		      |IPSR_24_FUNC(5)	/* DU_DG0 */
+		      |IPSR_20_FUNC(5)	/* DU_DR7 */
+		      |IPSR_16_FUNC(2)	/* IRQ5 */
+		      |IPSR_12_FUNC(5)	/* DU_DR6 */
+		      |IPSR_8_FUNC(5)	/* DU_DR5 */
+		      |IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(5));	/* DU_DR4 */
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)	/* SD0_CLK */
+		      |IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(5)	/* DU_DOTCLKIN0 */
+		      |IPSR_16_FUNC(5)	/* DU_DG3 */
+		      |IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(5));	/* DU_DG2 */
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0)	/* SD1_DAT0 */
+		      |IPSR_24_FUNC(0)	/* SD1_CMD */
+		      |IPSR_20_FUNC(0)	/* SD1_CLK */
+		      |IPSR_16_FUNC(0)	/* SD0_DAT3 */
+		      |IPSR_12_FUNC(0)	/* SD0_DAT2 */
+		      |IPSR_8_FUNC(0)	/* SD0_DAT1 */
+		      |IPSR_4_FUNC(0)	/* SD0_DAT0 */
+		      |IPSR_0_FUNC(0));	/* SD0_CMD */
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)	/* SD3_DAT2 */
+		      |IPSR_24_FUNC(0)	/* SD3_DAT1 */
+		      |IPSR_20_FUNC(0)	/* SD3_DAT0 */
+		      |IPSR_16_FUNC(0)	/* SD3_CMD */
+		      |IPSR_12_FUNC(0)	/* SD3_CLK */
+		      |IPSR_8_FUNC(0)	/* SD1_DAT3 */
+		      |IPSR_4_FUNC(0)	/* SD1_DAT2 */
+		      |IPSR_0_FUNC(0));	/* SD1_DAT1 */
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)	/* SD0_WP */
+		      |IPSR_24_FUNC(0)	/* SD0_CD */
+		      |IPSR_20_FUNC(0)	/* SD3_DS */
+		      |IPSR_16_FUNC(0)	/* SD3_DAT7 */
+		      |IPSR_12_FUNC(0)	/* SD3_DAT6 */
+		      |IPSR_8_FUNC(0)	/* SD3_DAT5 */
+		      |IPSR_4_FUNC(0)	/* SD3_DAT4 */
+		      |IPSR_0_FUNC(0));	/* SD3_DAT3 */
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(2)	/* AUDIO_CLKOUT1_A */
+		      |IPSR_16_FUNC(2)	/* AUDIO_CLKOUT_A */
+		      |IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)	/* SD1_WP */
+		      |IPSR_0_FUNC(0));	/* SD1_CD */
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)	/* RX2_A */
+		      |IPSR_8_FUNC(0)	/* TX2_A */
+		      |IPSR_4_FUNC(2)	/* AUDIO_CLKB_A */
+		      |IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(2)	/* AUDIO_CLKC_A */
+		      |IPSR_4_FUNC(1)	/* HTX2_A */
+		      |IPSR_0_FUNC(1));	/* HRX2_A */
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3)	/* USB0_PWEN_B */
+		      |IPSR_24_FUNC(0)	/* SSI_SDATA4 */
+		      |IPSR_20_FUNC(0)	/* SSI_SDATA3 */
+		      |IPSR_16_FUNC(0)	/* SSI_WS349 */
+		      |IPSR_12_FUNC(0)	/* SSI_SCK349 */
+		      |IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)	/* SSI_SDATA1 */
+		      |IPSR_0_FUNC(0));	/* SSI_SDATA0 */
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)	/* USB30_OVC */
+		      |IPSR_24_FUNC(0)	/* USB30_PWEN */
+		      |IPSR_20_FUNC(0)	/* AUDIO_CLKA */
+		      |IPSR_16_FUNC(1)	/* HRTS2#_A */
+		      |IPSR_12_FUNC(1)	/* HCTS2#_A */
+		      |IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(3));	/* USB0_OVC_B */
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_SCL4
+		      | GPSR0_D15
+		      | GPSR0_D11
+		      | GPSR0_D10
+		      | GPSR0_D9
+		      | GPSR0_D8
+		      | GPSR0_D7
+		      | GPSR0_D6
+		      | GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0);
+	pfc_reg_write(PFC_GPSR1, GPSR1_WE0
+		      | GPSR1_CS0
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A11
+		      | GPSR1_A10
+		      | GPSR1_A9
+		      | GPSR1_A8
+		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
+		      | GPSR2_BIT26_REVERCED
+		      | GPSR2_RD
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_TXCREFCLK
+		      | GPSR2_AVB_RD3
+		      | GPSR2_AVB_RD2
+		      | GPSR2_AVB_RD1
+		      | GPSR2_AVB_RD0
+		      | GPSR2_AVB_RXC
+		      | GPSR2_AVB_RX_CTL
+		      | GPSR2_RPC_RESET
+		      | GPSR2_RPC_RPC_INT
+		      | GPSR2_QSPI1_SSL
+		      | GPSR2_QSPI1_IO3
+		      | GPSR2_QSPI1_IO2
+		      | GPSR2_QSPI1_MISO_IO1
+		      | GPSR2_QSPI1_MOSI_IO0
+		      | GPSR2_QSPI1_SPCLK
+		      | GPSR2_QSPI0_SSL
+		      | GPSR2_QSPI0_IO3
+		      | GPSR2_QSPI0_IO2
+		      | GPSR2_QSPI0_MISO_IO1
+		      | GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
+		      | GPSR3_SD1_CD
+		      | GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD1_CMD
+		      | GPSR3_SD1_CLK
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
+		      | GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT5
+		      | GPSR4_SD3_DAT4
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
+		      | GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
+		      | GPSR6_SSI_SDATA6
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_WS5
+		      | GPSR6_SSI_SCK5
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_USB30_OVC
+		      | GPSR6_AUDIO_CLKA
+		      | GPSR6_SSI_SDATA3
+		      | GPSR6_SSI_WS349
+		      | GPSR6_SSI_SCK349
+		      | GPSR6_SSI_SDATA1
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239);
+
+	/* initialize POC control */
+	reg = mmio_read_32(PFC_IOCTRL30);
+	reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
+	       | POC_SD1_DAT2_33V
+	       | POC_SD1_DAT1_33V
+	       | POC_SD1_DAT0_33V
+	       | POC_SD1_CMD_33V
+	       | POC_SD1_CLK_33V
+	       | POC_SD0_DAT3_33V
+	       | POC_SD0_DAT2_33V
+	       | POC_SD0_DAT1_33V
+	       | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+	pfc_reg_write(PFC_IOCTRL30, reg);
+	reg = mmio_read_32(PFC_IOCTRL32);
+	reg = (reg & IOCTRL32_MASK);
+	pfc_reg_write(PFC_IOCTRL32, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0xFDF80000U);
+	pfc_reg_write(PFC_PUD1, 0xCE298464U);
+	pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
+	pfc_reg_write(PFC_PUD3, 0x0000079FU);
+	pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
+	pfc_reg_write(PFC_PUD5, 0x40000000U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0xFFF00000U);
+	pfc_reg_write(PFC_PUEN1, 0x00000000U);
+	pfc_reg_write(PFC_PUEN2, 0x00000004U);
+	pfc_reg_write(PFC_PUEN3, 0x00000000U);
+	pfc_reg_write(PFC_PUEN4, 0x07800010U);
+	pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00020000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT0, 0x00000010U);
+	mmio_write_32(GPIO_OUTDT1, 0x00100000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT3, 0x00008000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00060000U);
+	mmio_write_32(GPIO_OUTDT6, 0x00000000U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000010U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x00100020U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x00008000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x00060000U);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00004000U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h
new file mode 100644
index 0000000..041a778
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_E3_H__
+#define PFC_INIT_E3_H__
+
+void pfc_init_e3(void);
+
+#endif /* PFC_INIT_E3_H__ */
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
new file mode 100644
index 0000000..1c38f06
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
@@ -0,0 +1,1374 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <mmio.h>
+
+
+/* GPIO base address */
+#define	GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
+#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
+#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
+#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
+#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
+#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
+#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
+#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
+#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
+#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
+#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
+#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
+#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
+#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
+#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
+#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
+#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
+#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
+#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
+#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
+#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
+#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
+#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
+#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
+#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
+#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
+#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
+#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
+#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
+#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
+#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
+#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
+#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
+#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
+#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
+#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
+#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
+#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
+#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
+#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
+#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
+#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
+#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
+#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
+#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
+#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
+#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
+#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
+#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
+#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
+#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
+#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
+
+/* Pin functon base address */
+#define	PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define	PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
+#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
+#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
+#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
+#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
+#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
+#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
+#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
+#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
+#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
+#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
+#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
+#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
+#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
+#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
+#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
+#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
+#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
+#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
+#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
+#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
+#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
+#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
+#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
+#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
+#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
+#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
+#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
+#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
+#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
+#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
+#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
+#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
+#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
+#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
+#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
+#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
+#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
+#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
+#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
+#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
+#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
+#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
+#define	PFC_PUD0		(PFC_BASE + 0x0440U)
+#define	PFC_PUD1		(PFC_BASE + 0x0444U)
+#define	PFC_PUD2		(PFC_BASE + 0x0448U)
+#define	PFC_PUD3		(PFC_BASE + 0x044CU)
+#define	PFC_PUD4		(PFC_BASE + 0x0450U)
+#define	PFC_PUD5		(PFC_BASE + 0x0454U)
+#define	PFC_PUD6		(PFC_BASE + 0x0458U)
+#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
+#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
+#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
+
+#define	GPSR0_D15		((uint32_t)1U << 15U)
+#define	GPSR0_D14		((uint32_t)1U << 14U)
+#define	GPSR0_D13		((uint32_t)1U << 13U)
+#define	GPSR0_D12		((uint32_t)1U << 12U)
+#define	GPSR0_D11		((uint32_t)1U << 11U)
+#define	GPSR0_D10		((uint32_t)1U << 10U)
+#define	GPSR0_D9		((uint32_t)1U << 9U)
+#define	GPSR0_D8		((uint32_t)1U << 8U)
+#define	GPSR0_D7		((uint32_t)1U << 7U)
+#define	GPSR0_D6		((uint32_t)1U << 6U)
+#define	GPSR0_D5		((uint32_t)1U << 5U)
+#define	GPSR0_D4		((uint32_t)1U << 4U)
+#define	GPSR0_D3		((uint32_t)1U << 3U)
+#define	GPSR0_D2		((uint32_t)1U << 2U)
+#define	GPSR0_D1		((uint32_t)1U << 1U)
+#define	GPSR0_D0		((uint32_t)1U << 0U)
+#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
+#define	GPSR1_WE1		((uint32_t)1U << 26U)
+#define	GPSR1_WE0		((uint32_t)1U << 25U)
+#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
+#define	GPSR1_RD		((uint32_t)1U << 23U)
+#define	GPSR1_BS		((uint32_t)1U << 22U)
+#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
+#define	GPSR1_CS0		((uint32_t)1U << 20U)
+#define	GPSR1_A19		((uint32_t)1U << 19U)
+#define	GPSR1_A18		((uint32_t)1U << 18U)
+#define	GPSR1_A17		((uint32_t)1U << 17U)
+#define	GPSR1_A16		((uint32_t)1U << 16U)
+#define	GPSR1_A15		((uint32_t)1U << 15U)
+#define	GPSR1_A14		((uint32_t)1U << 14U)
+#define	GPSR1_A13		((uint32_t)1U << 13U)
+#define	GPSR1_A12		((uint32_t)1U << 12U)
+#define	GPSR1_A11		((uint32_t)1U << 11U)
+#define	GPSR1_A10		((uint32_t)1U << 10U)
+#define	GPSR1_A9		((uint32_t)1U << 9U)
+#define	GPSR1_A8		((uint32_t)1U << 8U)
+#define	GPSR1_A7		((uint32_t)1U << 7U)
+#define	GPSR1_A6		((uint32_t)1U << 6U)
+#define	GPSR1_A5		((uint32_t)1U << 5U)
+#define	GPSR1_A4		((uint32_t)1U << 4U)
+#define	GPSR1_A3		((uint32_t)1U << 3U)
+#define	GPSR1_A2		((uint32_t)1U << 2U)
+#define	GPSR1_A1		((uint32_t)1U << 1U)
+#define	GPSR1_A0		((uint32_t)1U << 0U)
+#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
+#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
+#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
+#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
+#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
+#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
+#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
+#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
+#define	GPSR2_PWM0		((uint32_t)1U << 6U)
+#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
+#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
+#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
+#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
+#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
+#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
+#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
+#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
+#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
+#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
+#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
+#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
+#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
+#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
+#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
+#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
+#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
+#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
+#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
+#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
+#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
+#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
+#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
+#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
+#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
+#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
+#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
+#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
+#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
+#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
+#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
+#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
+#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
+#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
+#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
+#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
+#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
+#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
+#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
+#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
+#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
+#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
+#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
+#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
+#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
+#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
+#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
+#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
+#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
+#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
+#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
+#define	GPSR5_HTX0		((uint32_t)1U << 14U)
+#define	GPSR5_HRX0		((uint32_t)1U << 13U)
+#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
+#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
+#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
+#define	GPSR5_SCK2		((uint32_t)1U << 9U)
+#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
+#define	GPSR5_CTS1		((uint32_t)1U << 7U)
+#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
+#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
+#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
+#define	GPSR5_CTS0		((uint32_t)1U << 3U)
+#define	GPSR5_TX0		((uint32_t)1U << 2U)
+#define	GPSR5_RX0		((uint32_t)1U << 1U)
+#define	GPSR5_SCK0		((uint32_t)1U << 0U)
+#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
+#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
+#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
+#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
+#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
+#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
+#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
+#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
+#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
+#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
+#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
+#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
+#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
+#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
+#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
+#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
+#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
+#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
+#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
+#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
+#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
+#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
+#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
+#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
+#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
+#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
+#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
+#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
+#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
+#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
+#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
+#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
+#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
+#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
+#define	GPSR7_AVS2		((uint32_t)1U << 1U)
+#define	GPSR7_AVS1		((uint32_t)1U << 0U)
+
+#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
+#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
+#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
+#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
+#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
+#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
+#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
+#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
+#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
+#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
+#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
+#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
+#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
+#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
+#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
+#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
+#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
+#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
+#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
+#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
+#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
+#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
+#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
+#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
+#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
+#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
+#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
+#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
+#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
+#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
+
+#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define	DRVCTRL2_MASK		(0x88888888U)
+#define	DRVCTRL3_MASK		(0x88888888U)
+#define	DRVCTRL4_MASK		(0x88888888U)
+#define	DRVCTRL5_MASK		(0x88888888U)
+#define	DRVCTRL6_MASK		(0x88888888U)
+#define	DRVCTRL7_MASK		(0x88888888U)
+#define	DRVCTRL8_MASK		(0x88888888U)
+#define	DRVCTRL9_MASK		(0x88888888U)
+#define	DRVCTRL10_MASK		(0x88888888U)
+#define	DRVCTRL11_MASK		(0x888888CCU)
+#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define	DRVCTRL13_MASK		(0xCC888888U)
+#define	DRVCTRL14_MASK		(0x88888888U)
+#define	DRVCTRL15_MASK		(0x88888888U)
+#define	DRVCTRL16_MASK		(0x88888888U)
+#define	DRVCTRL17_MASK		(0x88888888U)
+#define	DRVCTRL18_MASK		(0x88888888U)
+#define	DRVCTRL19_MASK		(0x88888888U)
+#define	DRVCTRL20_MASK		(0x88888888U)
+#define	DRVCTRL21_MASK		(0x88888888U)
+#define	DRVCTRL22_MASK		(0x88888888U)
+#define	DRVCTRL23_MASK		(0x88888888U)
+#define	DRVCTRL24_MASK		(0x8888888FU)
+
+#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define	MOD_SEL0_I2C6_A		((uint32_t)0U << 20U)
+#define	MOD_SEL0_I2C6_B		((uint32_t)1U << 20U)
+#define	MOD_SEL0_I2C6_C		((uint32_t)2U << 20U)
+#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 19U)
+#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 19U)
+#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 18U)
+#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 18U)
+#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 17U)
+#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 17U)
+#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 15U)
+#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 15U)
+#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 15U)
+#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 15U)
+#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 14U)
+#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 14U)
+#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 13U)
+#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 13U)
+#define	MOD_SEL0_FSO_A		((uint32_t)0U << 12U)
+#define	MOD_SEL0_FSO_B		((uint32_t)1U << 12U)
+#define	MOD_SEL0_FM_A		((uint32_t)0U << 11U)
+#define	MOD_SEL0_FM_B		((uint32_t)1U << 11U)
+#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 10U)
+#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 10U)
+#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 9U)
+#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 9U)
+#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 8U)
+#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 8U)
+#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 6U)
+#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 6U)
+#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 6U)
+#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 4U)
+#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 4U)
+#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 4U)
+#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 3U)
+#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 3U)
+#define	MOD_SEL0_ADG_A		((uint32_t)0U << 1U)
+#define	MOD_SEL0_ADG_B		((uint32_t)1U << 1U)
+#define	MOD_SEL0_ADG_C		((uint32_t)2U << 1U)
+#define	MOD_SEL0_ADG_D		((uint32_t)3U << 1U)
+#define	MOD_SEL0_5LINE_A	((uint32_t)0U << 0U)
+#define	MOD_SEL0_5LINE_B	((uint32_t)1U << 0U)
+#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data);
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t) addr, data);
+}
+
+void pfc_init_h3_v1(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C6_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FM_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A | MOD_SEL0_5LINE_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A | MOD_SEL2_I2C_0_A | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(2)
+	       | DRVCTRL13_SD0_CMD(2)
+	       | DRVCTRL13_SD0_DAT0(2)
+	       | DRVCTRL13_SD0_DAT1(2)
+	       | DRVCTRL13_SD0_DAT2(2)
+	       | DRVCTRL13_SD0_DAT3(2));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(2)
+	       | DRVCTRL15_SD3_CMD(2)
+	       | DRVCTRL15_SD3_DAT0(2));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(2)
+	       | DRVCTRL16_SD3_DAT2(2)
+	       | DRVCTRL16_SD3_DAT3(2)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
new file mode 100644
index 0000000..844c1b9
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_H3_V1_H__
+#define PFC_INIT_H3_V1_H__
+
+void pfc_init_h3_v1(void);
+
+#endif /* PFC_INIT_H3_V1_H__ */
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
new file mode 100644
index 0000000..3ed0cd3
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
@@ -0,0 +1,1421 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <mmio.h>
+#include "pfc_init_h3_v2.h"
+#include "rcar_def.h"
+
+/* GPIO base address */
+#define	GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
+#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
+#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
+#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
+#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
+#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
+#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
+#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
+#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
+#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
+#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
+#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
+#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
+#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
+#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
+#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
+#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
+#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
+#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
+#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
+#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
+#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
+#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
+#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
+#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
+#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
+#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
+#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
+#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
+#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
+#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
+#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
+#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
+#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
+#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
+#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
+#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
+#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
+#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
+#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
+#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
+#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
+#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
+#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
+#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
+#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
+#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
+#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
+#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
+#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
+#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
+#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
+
+/* Pin functon base address */
+#define	PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define	PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
+#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
+#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
+#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
+#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
+#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
+#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
+#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
+#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
+#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
+#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
+#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
+#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
+#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
+#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
+#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
+#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
+#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
+#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
+#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
+#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
+#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
+#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
+#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
+#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
+#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
+#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
+#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
+#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
+#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
+#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
+#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
+#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
+#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
+#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
+#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
+#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
+#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
+#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
+#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
+#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
+#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
+#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
+#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
+#define	PFC_PUD0		(PFC_BASE + 0x0440U)
+#define	PFC_PUD1		(PFC_BASE + 0x0444U)
+#define	PFC_PUD2		(PFC_BASE + 0x0448U)
+#define	PFC_PUD3		(PFC_BASE + 0x044CU)
+#define	PFC_PUD4		(PFC_BASE + 0x0450U)
+#define	PFC_PUD5		(PFC_BASE + 0x0454U)
+#define	PFC_PUD6		(PFC_BASE + 0x0458U)
+#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
+#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
+#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
+
+#define	GPSR0_D15		((uint32_t)1U << 15U)
+#define	GPSR0_D14		((uint32_t)1U << 14U)
+#define	GPSR0_D13		((uint32_t)1U << 13U)
+#define	GPSR0_D12		((uint32_t)1U << 12U)
+#define	GPSR0_D11		((uint32_t)1U << 11U)
+#define	GPSR0_D10		((uint32_t)1U << 10U)
+#define	GPSR0_D9		((uint32_t)1U << 9U)
+#define	GPSR0_D8		((uint32_t)1U << 8U)
+#define	GPSR0_D7		((uint32_t)1U << 7U)
+#define	GPSR0_D6		((uint32_t)1U << 6U)
+#define	GPSR0_D5		((uint32_t)1U << 5U)
+#define	GPSR0_D4		((uint32_t)1U << 4U)
+#define	GPSR0_D3		((uint32_t)1U << 3U)
+#define	GPSR0_D2		((uint32_t)1U << 2U)
+#define	GPSR0_D1		((uint32_t)1U << 1U)
+#define	GPSR0_D0		((uint32_t)1U << 0U)
+#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
+#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
+#define	GPSR1_WE1		((uint32_t)1U << 26U)
+#define	GPSR1_WE0		((uint32_t)1U << 25U)
+#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
+#define	GPSR1_RD		((uint32_t)1U << 23U)
+#define	GPSR1_BS		((uint32_t)1U << 22U)
+#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
+#define	GPSR1_CS0		((uint32_t)1U << 20U)
+#define	GPSR1_A19		((uint32_t)1U << 19U)
+#define	GPSR1_A18		((uint32_t)1U << 18U)
+#define	GPSR1_A17		((uint32_t)1U << 17U)
+#define	GPSR1_A16		((uint32_t)1U << 16U)
+#define	GPSR1_A15		((uint32_t)1U << 15U)
+#define	GPSR1_A14		((uint32_t)1U << 14U)
+#define	GPSR1_A13		((uint32_t)1U << 13U)
+#define	GPSR1_A12		((uint32_t)1U << 12U)
+#define	GPSR1_A11		((uint32_t)1U << 11U)
+#define	GPSR1_A10		((uint32_t)1U << 10U)
+#define	GPSR1_A9		((uint32_t)1U << 9U)
+#define	GPSR1_A8		((uint32_t)1U << 8U)
+#define	GPSR1_A7		((uint32_t)1U << 7U)
+#define	GPSR1_A6		((uint32_t)1U << 6U)
+#define	GPSR1_A5		((uint32_t)1U << 5U)
+#define	GPSR1_A4		((uint32_t)1U << 4U)
+#define	GPSR1_A3		((uint32_t)1U << 3U)
+#define	GPSR1_A2		((uint32_t)1U << 2U)
+#define	GPSR1_A1		((uint32_t)1U << 1U)
+#define	GPSR1_A0		((uint32_t)1U << 0U)
+#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
+#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
+#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
+#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
+#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
+#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
+#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
+#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
+#define	GPSR2_PWM0		((uint32_t)1U << 6U)
+#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
+#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
+#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
+#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
+#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
+#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
+#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
+#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
+#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
+#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
+#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
+#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
+#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
+#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
+#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
+#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
+#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
+#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
+#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
+#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
+#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
+#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
+#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
+#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
+#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
+#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
+#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
+#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
+#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
+#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
+#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
+#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
+#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
+#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
+#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
+#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
+#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
+#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
+#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
+#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
+#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
+#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
+#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
+#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
+#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
+#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
+#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
+#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
+#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
+#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
+#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
+#define	GPSR5_HTX0		((uint32_t)1U << 14U)
+#define	GPSR5_HRX0		((uint32_t)1U << 13U)
+#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
+#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
+#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
+#define	GPSR5_SCK2		((uint32_t)1U << 9U)
+#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
+#define	GPSR5_CTS1		((uint32_t)1U << 7U)
+#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
+#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
+#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
+#define	GPSR5_CTS0		((uint32_t)1U << 3U)
+#define	GPSR5_TX0		((uint32_t)1U << 2U)
+#define	GPSR5_RX0		((uint32_t)1U << 1U)
+#define	GPSR5_SCK0		((uint32_t)1U << 0U)
+#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
+#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
+#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
+#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
+#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
+#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
+#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
+#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
+#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
+#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
+#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
+#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
+#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
+#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
+#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
+#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
+#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
+#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
+#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
+#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
+#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
+#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
+#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
+#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
+#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
+#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
+#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
+#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
+#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
+#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
+#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
+#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
+#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
+#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
+#define	GPSR7_AVS2		((uint32_t)1U << 1U)
+#define	GPSR7_AVS1		((uint32_t)1U << 0U)
+
+#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
+#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
+#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
+#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
+#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
+#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
+#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
+#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
+#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
+#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
+#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
+#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
+#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
+#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
+#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
+#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
+#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
+#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
+#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
+#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
+#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
+#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
+#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
+#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
+#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
+#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
+#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
+#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
+#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
+#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
+
+#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define	DRVCTRL2_MASK		(0x88888888U)
+#define	DRVCTRL3_MASK		(0x88888888U)
+#define	DRVCTRL4_MASK		(0x88888888U)
+#define	DRVCTRL5_MASK		(0x88888888U)
+#define	DRVCTRL6_MASK		(0x88888888U)
+#define	DRVCTRL7_MASK		(0x88888888U)
+#define	DRVCTRL8_MASK		(0x88888888U)
+#define	DRVCTRL9_MASK		(0x88888888U)
+#define	DRVCTRL10_MASK		(0x88888888U)
+#define	DRVCTRL11_MASK		(0x888888CCU)
+#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define	DRVCTRL13_MASK		(0xCC888888U)
+#define	DRVCTRL14_MASK		(0x88888888U)
+#define	DRVCTRL15_MASK		(0x88888888U)
+#define	DRVCTRL16_MASK		(0x88888888U)
+#define	DRVCTRL17_MASK		(0x88888888U)
+#define	DRVCTRL18_MASK		(0x88888888U)
+#define	DRVCTRL19_MASK		(0x88888888U)
+#define	DRVCTRL20_MASK		(0x88888888U)
+#define	DRVCTRL21_MASK		(0x88888888U)
+#define	DRVCTRL22_MASK		(0x88888888U)
+#define	DRVCTRL23_MASK		(0x88888888U)
+#define	DRVCTRL24_MASK		(0x8888888FU)
+
+#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE		(0xE6C50000U)
+#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA		(0x0000U)
+
+/* Realtime module stop control */
+#define	CPG_BASE		(0xE6150000U)
+#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
+#define CPG_RMSTPCR0		(CPG_BASE + 0x0110U)
+#define RMSTPCR0_RTDMAC		(0x00200000U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data);
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t) addr, data);
+}
+
+void pfc_init_h3_v2(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_FM_A
+		      | MOD_SEL2_SCIF5_A
+		      | MOD_SEL2_I2C6_A
+		      | MOD_SEL2_NDF_A
+		      | MOD_SEL2_SSI2_A
+		      | MOD_SEL2_SSI9_A
+		      | MOD_SEL2_TIMER_TMU2_A
+		      | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+		      | GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(7)
+	       | DRVCTRL13_SD0_CMD(7)
+	       | DRVCTRL13_SD0_DAT0(7)
+	       | DRVCTRL13_SD0_DAT1(7)
+	       | DRVCTRL13_SD0_DAT2(7)
+	       | DRVCTRL13_SD0_DAT3(7));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(7)
+	       | DRVCTRL15_SD3_CMD(7)
+	       | DRVCTRL15_SD3_DAT0(7));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+	       | DRVCTRL16_SD3_DAT2(7)
+	       | DRVCTRL16_SD3_DAT3(7)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
new file mode 100644
index 0000000..3f691f8
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_H3_V2_H__
+#define PFC_INIT_H3_V2_H__
+
+void pfc_init_h3_v2(void);
+
+#endif /* PFC_INIT_H3_V2_H__ */
diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
new file mode 100644
index 0000000..911ee8c
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -0,0 +1,1501 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <mmio.h>
+#include "pfc_init_m3.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+
+/* GPIO base address */
+#define	GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
+#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
+#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
+#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
+#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
+#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
+#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
+#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
+#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
+#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
+#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
+#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
+#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
+#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
+#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
+#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
+#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
+#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
+#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
+#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
+#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
+#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
+#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
+#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
+#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
+#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
+#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
+#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
+#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
+#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
+#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
+#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
+#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
+#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
+#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
+#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
+#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
+#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
+#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
+#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
+#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
+#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
+#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
+#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
+#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
+#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
+#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
+#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
+#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
+#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
+#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
+#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
+
+/* Pin functon base address */
+#define	PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define	PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
+#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
+#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
+#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
+#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
+#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
+#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
+#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
+#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
+#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
+#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
+#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
+#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
+#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
+#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
+#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
+#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
+#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
+#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
+#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
+#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
+#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
+#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
+#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
+#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
+#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
+#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
+#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
+#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
+#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
+#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
+#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
+#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
+#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
+#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
+#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
+#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
+#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
+#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
+#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
+#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
+#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
+#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
+#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
+#define	PFC_PUD0		(PFC_BASE + 0x0440U)
+#define	PFC_PUD1		(PFC_BASE + 0x0444U)
+#define	PFC_PUD2		(PFC_BASE + 0x0448U)
+#define	PFC_PUD3		(PFC_BASE + 0x044CU)
+#define	PFC_PUD4		(PFC_BASE + 0x0450U)
+#define	PFC_PUD5		(PFC_BASE + 0x0454U)
+#define	PFC_PUD6		(PFC_BASE + 0x0458U)
+#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
+#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
+#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
+
+#define	GPSR0_D15		((uint32_t)1U << 15U)
+#define	GPSR0_D14		((uint32_t)1U << 14U)
+#define	GPSR0_D13		((uint32_t)1U << 13U)
+#define	GPSR0_D12		((uint32_t)1U << 12U)
+#define	GPSR0_D11		((uint32_t)1U << 11U)
+#define	GPSR0_D10		((uint32_t)1U << 10U)
+#define	GPSR0_D9		((uint32_t)1U << 9U)
+#define	GPSR0_D8		((uint32_t)1U << 8U)
+#define	GPSR0_D7		((uint32_t)1U << 7U)
+#define	GPSR0_D6		((uint32_t)1U << 6U)
+#define	GPSR0_D5		((uint32_t)1U << 5U)
+#define	GPSR0_D4		((uint32_t)1U << 4U)
+#define	GPSR0_D3		((uint32_t)1U << 3U)
+#define	GPSR0_D2		((uint32_t)1U << 2U)
+#define	GPSR0_D1		((uint32_t)1U << 1U)
+#define	GPSR0_D0		((uint32_t)1U << 0U)
+#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
+#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
+#define	GPSR1_WE1		((uint32_t)1U << 26U)
+#define	GPSR1_WE0		((uint32_t)1U << 25U)
+#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
+#define	GPSR1_RD		((uint32_t)1U << 23U)
+#define	GPSR1_BS		((uint32_t)1U << 22U)
+#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
+#define	GPSR1_CS0		((uint32_t)1U << 20U)
+#define	GPSR1_A19		((uint32_t)1U << 19U)
+#define	GPSR1_A18		((uint32_t)1U << 18U)
+#define	GPSR1_A17		((uint32_t)1U << 17U)
+#define	GPSR1_A16		((uint32_t)1U << 16U)
+#define	GPSR1_A15		((uint32_t)1U << 15U)
+#define	GPSR1_A14		((uint32_t)1U << 14U)
+#define	GPSR1_A13		((uint32_t)1U << 13U)
+#define	GPSR1_A12		((uint32_t)1U << 12U)
+#define	GPSR1_A11		((uint32_t)1U << 11U)
+#define	GPSR1_A10		((uint32_t)1U << 10U)
+#define	GPSR1_A9		((uint32_t)1U << 9U)
+#define	GPSR1_A8		((uint32_t)1U << 8U)
+#define	GPSR1_A7		((uint32_t)1U << 7U)
+#define	GPSR1_A6		((uint32_t)1U << 6U)
+#define	GPSR1_A5		((uint32_t)1U << 5U)
+#define	GPSR1_A4		((uint32_t)1U << 4U)
+#define	GPSR1_A3		((uint32_t)1U << 3U)
+#define	GPSR1_A2		((uint32_t)1U << 2U)
+#define	GPSR1_A1		((uint32_t)1U << 1U)
+#define	GPSR1_A0		((uint32_t)1U << 0U)
+#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
+#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
+#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
+#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
+#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
+#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
+#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
+#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
+#define	GPSR2_PWM0		((uint32_t)1U << 6U)
+#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
+#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
+#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
+#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
+#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
+#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
+#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
+#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
+#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
+#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
+#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
+#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
+#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
+#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
+#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
+#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
+#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
+#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
+#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
+#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
+#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
+#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
+#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
+#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
+#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
+#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
+#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
+#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
+#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
+#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
+#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
+#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
+#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
+#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
+#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
+#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
+#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
+#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
+#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
+#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
+#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
+#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
+#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
+#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
+#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
+#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
+#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
+#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
+#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
+#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
+#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
+#define	GPSR5_HTX0		((uint32_t)1U << 14U)
+#define	GPSR5_HRX0		((uint32_t)1U << 13U)
+#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
+#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
+#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
+#define	GPSR5_SCK2		((uint32_t)1U << 9U)
+#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
+#define	GPSR5_CTS1		((uint32_t)1U << 7U)
+#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
+#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
+#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
+#define	GPSR5_CTS0		((uint32_t)1U << 3U)
+#define	GPSR5_TX0		((uint32_t)1U << 2U)
+#define	GPSR5_RX0		((uint32_t)1U << 1U)
+#define	GPSR5_SCK0		((uint32_t)1U << 0U)
+#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
+#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
+#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
+#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
+#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
+#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
+#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
+#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
+#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
+#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
+#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
+#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
+#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
+#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
+#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
+#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
+#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
+#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
+#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
+#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
+#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
+#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
+#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
+#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
+#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
+#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
+#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
+#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
+#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
+#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
+#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
+#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
+#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
+#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
+#define	GPSR7_AVS2		((uint32_t)1U << 1U)
+#define	GPSR7_AVS1		((uint32_t)1U << 0U)
+
+#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
+#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
+#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
+#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
+#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
+#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
+#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
+#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
+#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
+#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
+#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
+#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
+#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
+#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
+#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
+#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
+#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
+#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
+#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
+#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
+#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
+#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
+#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
+#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
+#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
+#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
+#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
+#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
+#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
+#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
+
+#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define	DRVCTRL2_MASK		(0x88888888U)
+#define	DRVCTRL3_MASK		(0x88888888U)
+#define	DRVCTRL4_MASK		(0x88888888U)
+#define	DRVCTRL5_MASK		(0x88888888U)
+#define	DRVCTRL6_MASK		(0x88888888U)
+#define	DRVCTRL7_MASK		(0x88888888U)
+#define	DRVCTRL8_MASK		(0x88888888U)
+#define	DRVCTRL9_MASK		(0x88888888U)
+#define	DRVCTRL10_MASK		(0x88888888U)
+#define	DRVCTRL11_MASK		(0x888888CCU)
+#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define	DRVCTRL13_MASK		(0xCC888888U)
+#define	DRVCTRL14_MASK		(0x88888888U)
+#define	DRVCTRL15_MASK		(0x88888888U)
+#define	DRVCTRL16_MASK		(0x88888888U)
+#define	DRVCTRL17_MASK		(0x88888888U)
+#define	DRVCTRL18_MASK		(0x88888888U)
+#define	DRVCTRL19_MASK		(0x88888888U)
+#define	DRVCTRL20_MASK		(0x88888888U)
+#define	DRVCTRL21_MASK		(0x88888888U)
+#define	DRVCTRL22_MASK		(0x88888888U)
+#define	DRVCTRL23_MASK		(0x88888888U)
+#define	DRVCTRL24_MASK		(0x8888888FU)
+
+#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+/* SCIF3 Registers for Dummy write */
+#define SCIF3_BASE		(0xE6C50000U)
+#define SCIF3_SCFCR		(SCIF3_BASE + 0x0018U)
+#define SCIF3_SCFDR		(SCIF3_BASE + 0x001CU)
+#define SCFCR_DATA		(0x0000U)
+
+/* Realtime module stop control */
+#define	CPG_BASE		(0xE6150000U)
+#define CPG_SCMSTPCR0		(CPG_BASE + 0x0B20U)
+#define CPG_MSTPSR0		(CPG_BASE + 0x0030U)
+#define SCMSTPCR0_RTDMAC	(0x00200000U)
+
+/* RT-DMAC Registers */
+#define RTDMAC_CH		(0U)	/* choose 0 to 15 */
+
+#define RTDMAC_BASE		(0xFFC10000U)
+#define RTDMAC_RDMOR		(RTDMAC_BASE + 0x0060U)
+#define RTDMAC_RDMCHCLR		(RTDMAC_BASE + 0x0080U)
+#define RTDMAC_RDMSAR(x)	(RTDMAC_BASE + 0x8000U + (0x80U * (x)))
+#define RTDMAC_RDMDAR(x)	(RTDMAC_BASE + 0x8004U + (0x80U * (x)))
+#define RTDMAC_RDMTCR(x)	(RTDMAC_BASE + 0x8008U + (0x80U * (x)))
+#define RTDMAC_RDMCHCR(x)	(RTDMAC_BASE + 0x800CU + (0x80U * (x)))
+#define RTDMAC_RDMCHCRB(x)	(RTDMAC_BASE + 0x801CU + (0x80U * (x)))
+#define RTDMAC_RDMDPBASE(x)	(RTDMAC_BASE + 0x8050U + (0x80U * (x)))
+#define RTDMAC_DESC_BASE	(RTDMAC_BASE + 0xA000U)
+#define RTDMAC_DESC_RDMSAR	(RTDMAC_DESC_BASE + 0x0000U)
+#define RTDMAC_DESC_RDMDAR	(RTDMAC_DESC_BASE + 0x0004U)
+#define RTDMAC_DESC_RDMTCR	(RTDMAC_DESC_BASE + 0x0008U)
+
+#define RDMOR_DME		(0x0001U)	/* DMA Master Enable */
+#define RDMCHCR_DPM_INFINITE	(0x30000000U)	/* Infinite repeat mode */
+#define RDMCHCR_RPT_TCR		(0x02000000U)	/* enable to update TCR */
+#define RDMCHCR_TS_2		(0x00000008U)	/* Word(2byte) units transfer */
+#define RDMCHCR_RS_AUTO		(0x00000400U)	/* Auto request */
+#define RDMCHCR_DE		(0x00000001U)	/* DMA Enable */
+#define RDMCHCRB_DRST		(0x00008000U)	/* Descriptor reset */
+#define RDMCHCRB_SLM_256	(0x00000080U)	/* once in 256 clock cycle */
+#define RDMDPBASE_SEL_EXT	(0x00000001U)	/* External memory use */
+
+static void StartRtDma0_Descriptor(void);
+static void pfc_reg_write(uint32_t addr, uint32_t data);
+
+static void StartRtDma0_Descriptor(void)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(RCAR_PRR);
+	reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	if (reg == (RCAR_PRODUCT_M3_CUT10)) {
+		/* Enable clock supply to RTDMAC. */
+		mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
+
+		/* Initialize ch0, Reset Descriptor */
+		mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t) 1U << RTDMAC_CH));
+		mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST);
+
+		/* Enable DMA */
+		mmio_write_16(RTDMAC_RDMOR, RDMOR_DME);
+
+		/* Set first transfer */
+		mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR);
+		mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR);
+		mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U);
+
+		/* Set descriptor */
+		mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U);
+		mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U);
+		mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U);
+		mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256);
+		mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE
+			      | RDMDPBASE_SEL_EXT);
+
+		/* Set transfer parameter, Start transfer */
+		mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
+			      | RDMCHCR_RPT_TCR
+			      | RDMCHCR_TS_2 | RDMCHCR_RS_AUTO | RDMCHCR_DE);
+	}
+}
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	uint32_t prr;
+
+	prr = mmio_read_32(RCAR_PRR);
+	prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+
+	mmio_write_32(PFC_PMMR, ~data);
+	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
+	}
+	mmio_write_32((uintptr_t) addr, data);
+	if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+		mmio_write_16(SCIF3_SCFCR, SCFCR_DATA);	/* Dummy write */
+	}
+}
+
+void pfc_init_m3(void)
+{
+	uint32_t reg;
+
+	/* Work around for PFC eratta */
+	StartRtDma0_Descriptor();
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_FM_A
+		      | MOD_SEL2_SCIF5_A
+		      | MOD_SEL2_I2C6_A
+		      | MOD_SEL2_NDF_A
+		      | MOD_SEL2_SSI2_A
+		      | MOD_SEL2_SSI9_A
+		      | MOD_SEL2_TIMER_TMU2_A
+		      | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+		      | GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(7)
+	       | DRVCTRL13_SD0_CMD(7)
+	       | DRVCTRL13_SD0_DAT0(7)
+	       | DRVCTRL13_SD0_DAT1(7)
+	       | DRVCTRL13_SD0_DAT2(7)
+	       | DRVCTRL13_SD0_DAT3(7));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(7)
+	       | DRVCTRL15_SD3_CMD(7)
+	       | DRVCTRL15_SD3_DAT0(7));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+	       | DRVCTRL16_SD3_DAT2(7)
+	       | DRVCTRL16_SD3_DAT3(7)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h
new file mode 100644
index 0000000..c6ee693
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_M3_H__
+#define PFC_INIT_M3_H__
+
+void pfc_init_m3(void);
+
+#endif /* PFC_INIT_M3_H__ */
diff --git a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
new file mode 100644
index 0000000..a2b6b34
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
@@ -0,0 +1,1409 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>		/* for uint32_t */
+#include <mmio.h>
+#include "pfc_init_m3n.h"
+#include "rcar_def.h"
+
+/* GPIO base address */
+#define	GPIO_BASE		(0xE6050000U)
+
+/* GPIO registers */
+#define	GPIO_IOINTSEL0		(GPIO_BASE + 0x0000U)
+#define	GPIO_INOUTSEL0		(GPIO_BASE + 0x0004U)
+#define	GPIO_OUTDT0		(GPIO_BASE + 0x0008U)
+#define	GPIO_INDT0		(GPIO_BASE + 0x000CU)
+#define	GPIO_INTDT0		(GPIO_BASE + 0x0010U)
+#define	GPIO_INTCLR0		(GPIO_BASE + 0x0014U)
+#define	GPIO_INTMSK0		(GPIO_BASE + 0x0018U)
+#define	GPIO_MSKCLR0		(GPIO_BASE + 0x001CU)
+#define	GPIO_POSNEG0		(GPIO_BASE + 0x0020U)
+#define	GPIO_EDGLEVEL0		(GPIO_BASE + 0x0024U)
+#define	GPIO_FILONOFF0		(GPIO_BASE + 0x0028U)
+#define	GPIO_INTMSKS0		(GPIO_BASE + 0x0038U)
+#define	GPIO_MSKCLRS0		(GPIO_BASE + 0x003CU)
+#define	GPIO_OUTDTSEL0		(GPIO_BASE + 0x0040U)
+#define	GPIO_OUTDTH0		(GPIO_BASE + 0x0044U)
+#define	GPIO_OUTDTL0		(GPIO_BASE + 0x0048U)
+#define	GPIO_BOTHEDGE0		(GPIO_BASE + 0x004CU)
+#define	GPIO_IOINTSEL1		(GPIO_BASE + 0x1000U)
+#define	GPIO_INOUTSEL1		(GPIO_BASE + 0x1004U)
+#define	GPIO_OUTDT1		(GPIO_BASE + 0x1008U)
+#define	GPIO_INDT1		(GPIO_BASE + 0x100CU)
+#define	GPIO_INTDT1		(GPIO_BASE + 0x1010U)
+#define	GPIO_INTCLR1		(GPIO_BASE + 0x1014U)
+#define	GPIO_INTMSK1		(GPIO_BASE + 0x1018U)
+#define	GPIO_MSKCLR1		(GPIO_BASE + 0x101CU)
+#define	GPIO_POSNEG1		(GPIO_BASE + 0x1020U)
+#define	GPIO_EDGLEVEL1		(GPIO_BASE + 0x1024U)
+#define	GPIO_FILONOFF1		(GPIO_BASE + 0x1028U)
+#define	GPIO_INTMSKS1		(GPIO_BASE + 0x1038U)
+#define	GPIO_MSKCLRS1		(GPIO_BASE + 0x103CU)
+#define	GPIO_OUTDTSEL1		(GPIO_BASE + 0x1040U)
+#define	GPIO_OUTDTH1		(GPIO_BASE + 0x1044U)
+#define	GPIO_OUTDTL1		(GPIO_BASE + 0x1048U)
+#define	GPIO_BOTHEDGE1		(GPIO_BASE + 0x104CU)
+#define	GPIO_IOINTSEL2		(GPIO_BASE + 0x2000U)
+#define	GPIO_INOUTSEL2		(GPIO_BASE + 0x2004U)
+#define	GPIO_OUTDT2		(GPIO_BASE + 0x2008U)
+#define	GPIO_INDT2		(GPIO_BASE + 0x200CU)
+#define	GPIO_INTDT2		(GPIO_BASE + 0x2010U)
+#define	GPIO_INTCLR2		(GPIO_BASE + 0x2014U)
+#define	GPIO_INTMSK2		(GPIO_BASE + 0x2018U)
+#define	GPIO_MSKCLR2		(GPIO_BASE + 0x201CU)
+#define	GPIO_POSNEG2		(GPIO_BASE + 0x2020U)
+#define	GPIO_EDGLEVEL2		(GPIO_BASE + 0x2024U)
+#define	GPIO_FILONOFF2		(GPIO_BASE + 0x2028U)
+#define	GPIO_INTMSKS2		(GPIO_BASE + 0x2038U)
+#define	GPIO_MSKCLRS2		(GPIO_BASE + 0x203CU)
+#define	GPIO_OUTDTSEL2		(GPIO_BASE + 0x2040U)
+#define	GPIO_OUTDTH2		(GPIO_BASE + 0x2044U)
+#define	GPIO_OUTDTL2		(GPIO_BASE + 0x2048U)
+#define	GPIO_BOTHEDGE2		(GPIO_BASE + 0x204CU)
+#define	GPIO_IOINTSEL3		(GPIO_BASE + 0x3000U)
+#define	GPIO_INOUTSEL3		(GPIO_BASE + 0x3004U)
+#define	GPIO_OUTDT3		(GPIO_BASE + 0x3008U)
+#define	GPIO_INDT3		(GPIO_BASE + 0x300CU)
+#define	GPIO_INTDT3		(GPIO_BASE + 0x3010U)
+#define	GPIO_INTCLR3		(GPIO_BASE + 0x3014U)
+#define	GPIO_INTMSK3		(GPIO_BASE + 0x3018U)
+#define	GPIO_MSKCLR3		(GPIO_BASE + 0x301CU)
+#define	GPIO_POSNEG3		(GPIO_BASE + 0x3020U)
+#define	GPIO_EDGLEVEL3		(GPIO_BASE + 0x3024U)
+#define	GPIO_FILONOFF3		(GPIO_BASE + 0x3028U)
+#define	GPIO_INTMSKS3		(GPIO_BASE + 0x3038U)
+#define	GPIO_MSKCLRS3		(GPIO_BASE + 0x303CU)
+#define	GPIO_OUTDTSEL3		(GPIO_BASE + 0x3040U)
+#define	GPIO_OUTDTH3		(GPIO_BASE + 0x3044U)
+#define	GPIO_OUTDTL3		(GPIO_BASE + 0x3048U)
+#define	GPIO_BOTHEDGE3		(GPIO_BASE + 0x304CU)
+#define	GPIO_IOINTSEL4		(GPIO_BASE + 0x4000U)
+#define	GPIO_INOUTSEL4		(GPIO_BASE + 0x4004U)
+#define	GPIO_OUTDT4		(GPIO_BASE + 0x4008U)
+#define	GPIO_INDT4		(GPIO_BASE + 0x400CU)
+#define	GPIO_INTDT4		(GPIO_BASE + 0x4010U)
+#define	GPIO_INTCLR4		(GPIO_BASE + 0x4014U)
+#define	GPIO_INTMSK4		(GPIO_BASE + 0x4018U)
+#define	GPIO_MSKCLR4		(GPIO_BASE + 0x401CU)
+#define	GPIO_POSNEG4		(GPIO_BASE + 0x4020U)
+#define	GPIO_EDGLEVEL4		(GPIO_BASE + 0x4024U)
+#define	GPIO_FILONOFF4		(GPIO_BASE + 0x4028U)
+#define	GPIO_INTMSKS4		(GPIO_BASE + 0x4038U)
+#define	GPIO_MSKCLRS4		(GPIO_BASE + 0x403CU)
+#define	GPIO_OUTDTSEL4		(GPIO_BASE + 0x4040U)
+#define	GPIO_OUTDTH4		(GPIO_BASE + 0x4044U)
+#define	GPIO_OUTDTL4		(GPIO_BASE + 0x4048U)
+#define	GPIO_BOTHEDGE4		(GPIO_BASE + 0x404CU)
+#define	GPIO_IOINTSEL5		(GPIO_BASE + 0x5000U)
+#define	GPIO_INOUTSEL5		(GPIO_BASE + 0x5004U)
+#define	GPIO_OUTDT5		(GPIO_BASE + 0x5008U)
+#define	GPIO_INDT5		(GPIO_BASE + 0x500CU)
+#define	GPIO_INTDT5		(GPIO_BASE + 0x5010U)
+#define	GPIO_INTCLR5		(GPIO_BASE + 0x5014U)
+#define	GPIO_INTMSK5		(GPIO_BASE + 0x5018U)
+#define	GPIO_MSKCLR5		(GPIO_BASE + 0x501CU)
+#define	GPIO_POSNEG5		(GPIO_BASE + 0x5020U)
+#define	GPIO_EDGLEVEL5		(GPIO_BASE + 0x5024U)
+#define	GPIO_FILONOFF5		(GPIO_BASE + 0x5028U)
+#define	GPIO_INTMSKS5		(GPIO_BASE + 0x5038U)
+#define	GPIO_MSKCLRS5		(GPIO_BASE + 0x503CU)
+#define	GPIO_OUTDTSEL5		(GPIO_BASE + 0x5040U)
+#define	GPIO_OUTDTH5		(GPIO_BASE + 0x5044U)
+#define	GPIO_OUTDTL5		(GPIO_BASE + 0x5048U)
+#define	GPIO_BOTHEDGE5		(GPIO_BASE + 0x504CU)
+#define	GPIO_IOINTSEL6		(GPIO_BASE + 0x5400U)
+#define	GPIO_INOUTSEL6		(GPIO_BASE + 0x5404U)
+#define	GPIO_OUTDT6		(GPIO_BASE + 0x5408U)
+#define	GPIO_INDT6		(GPIO_BASE + 0x540CU)
+#define	GPIO_INTDT6		(GPIO_BASE + 0x5410U)
+#define	GPIO_INTCLR6		(GPIO_BASE + 0x5414U)
+#define	GPIO_INTMSK6		(GPIO_BASE + 0x5418U)
+#define	GPIO_MSKCLR6		(GPIO_BASE + 0x541CU)
+#define	GPIO_POSNEG6		(GPIO_BASE + 0x5420U)
+#define	GPIO_EDGLEVEL6		(GPIO_BASE + 0x5424U)
+#define	GPIO_FILONOFF6		(GPIO_BASE + 0x5428U)
+#define	GPIO_INTMSKS6		(GPIO_BASE + 0x5438U)
+#define	GPIO_MSKCLRS6		(GPIO_BASE + 0x543CU)
+#define	GPIO_OUTDTSEL6		(GPIO_BASE + 0x5440U)
+#define	GPIO_OUTDTH6		(GPIO_BASE + 0x5444U)
+#define	GPIO_OUTDTL6		(GPIO_BASE + 0x5448U)
+#define	GPIO_BOTHEDGE6		(GPIO_BASE + 0x544CU)
+#define	GPIO_IOINTSEL7		(GPIO_BASE + 0x5800U)
+#define	GPIO_INOUTSEL7		(GPIO_BASE + 0x5804U)
+#define	GPIO_OUTDT7		(GPIO_BASE + 0x5808U)
+#define	GPIO_INDT7		(GPIO_BASE + 0x580CU)
+#define	GPIO_INTDT7		(GPIO_BASE + 0x5810U)
+#define	GPIO_INTCLR7		(GPIO_BASE + 0x5814U)
+#define	GPIO_INTMSK7		(GPIO_BASE + 0x5818U)
+#define	GPIO_MSKCLR7		(GPIO_BASE + 0x581CU)
+#define	GPIO_POSNEG7		(GPIO_BASE + 0x5820U)
+#define	GPIO_EDGLEVEL7		(GPIO_BASE + 0x5824U)
+#define	GPIO_FILONOFF7		(GPIO_BASE + 0x5828U)
+#define	GPIO_INTMSKS7		(GPIO_BASE + 0x5838U)
+#define	GPIO_MSKCLRS7		(GPIO_BASE + 0x583CU)
+#define	GPIO_OUTDTSEL7		(GPIO_BASE + 0x5840U)
+#define	GPIO_OUTDTH7		(GPIO_BASE + 0x5844U)
+#define	GPIO_OUTDTL7		(GPIO_BASE + 0x5848U)
+#define	GPIO_BOTHEDGE7		(GPIO_BASE + 0x584CU)
+
+/* Pin functon base address */
+#define	PFC_BASE		(0xE6060000U)
+
+/* Pin functon registers */
+#define	PFC_PMMR		(PFC_BASE + 0x0000U)
+#define PFC_GPSR0		(PFC_BASE + 0x0100U)
+#define PFC_GPSR1		(PFC_BASE + 0x0104U)
+#define PFC_GPSR2		(PFC_BASE + 0x0108U)
+#define PFC_GPSR3		(PFC_BASE + 0x010CU)
+#define PFC_GPSR4		(PFC_BASE + 0x0110U)
+#define	PFC_GPSR5		(PFC_BASE + 0x0114U)
+#define	PFC_GPSR6		(PFC_BASE + 0x0118U)
+#define	PFC_GPSR7		(PFC_BASE + 0x011CU)
+#define	PFC_IPSR0		(PFC_BASE + 0x0200U)
+#define	PFC_IPSR1		(PFC_BASE + 0x0204U)
+#define	PFC_IPSR2		(PFC_BASE + 0x0208U)
+#define	PFC_IPSR3		(PFC_BASE + 0x020CU)
+#define	PFC_IPSR4		(PFC_BASE + 0x0210U)
+#define	PFC_IPSR5		(PFC_BASE + 0x0214U)
+#define	PFC_IPSR6		(PFC_BASE + 0x0218U)
+#define	PFC_IPSR7		(PFC_BASE + 0x021CU)
+#define	PFC_IPSR8		(PFC_BASE + 0x0220U)
+#define	PFC_IPSR9		(PFC_BASE + 0x0224U)
+#define	PFC_IPSR10		(PFC_BASE + 0x0228U)
+#define	PFC_IPSR11		(PFC_BASE + 0x022CU)
+#define	PFC_IPSR12		(PFC_BASE + 0x0230U)
+#define	PFC_IPSR13		(PFC_BASE + 0x0234U)
+#define	PFC_IPSR14		(PFC_BASE + 0x0238U)
+#define	PFC_IPSR15		(PFC_BASE + 0x023CU)
+#define	PFC_IPSR16		(PFC_BASE + 0x0240U)
+#define	PFC_IPSR17		(PFC_BASE + 0x0244U)
+#define	PFC_IPSR18		(PFC_BASE + 0x0248U)
+#define PFC_DRVCTRL0		(PFC_BASE + 0x0300U)
+#define PFC_DRVCTRL1		(PFC_BASE + 0x0304U)
+#define PFC_DRVCTRL2		(PFC_BASE + 0x0308U)
+#define PFC_DRVCTRL3		(PFC_BASE + 0x030CU)
+#define PFC_DRVCTRL4		(PFC_BASE + 0x0310U)
+#define PFC_DRVCTRL5		(PFC_BASE + 0x0314U)
+#define PFC_DRVCTRL6		(PFC_BASE + 0x0318U)
+#define PFC_DRVCTRL7		(PFC_BASE + 0x031CU)
+#define PFC_DRVCTRL8		(PFC_BASE + 0x0320U)
+#define PFC_DRVCTRL9		(PFC_BASE + 0x0324U)
+#define PFC_DRVCTRL10		(PFC_BASE + 0x0328U)
+#define PFC_DRVCTRL11		(PFC_BASE + 0x032CU)
+#define PFC_DRVCTRL12		(PFC_BASE + 0x0330U)
+#define PFC_DRVCTRL13		(PFC_BASE + 0x0334U)
+#define PFC_DRVCTRL14		(PFC_BASE + 0x0338U)
+#define PFC_DRVCTRL15		(PFC_BASE + 0x033CU)
+#define PFC_DRVCTRL16		(PFC_BASE + 0x0340U)
+#define PFC_DRVCTRL17		(PFC_BASE + 0x0344U)
+#define PFC_DRVCTRL18		(PFC_BASE + 0x0348U)
+#define PFC_DRVCTRL19		(PFC_BASE + 0x034CU)
+#define PFC_DRVCTRL20		(PFC_BASE + 0x0350U)
+#define PFC_DRVCTRL21		(PFC_BASE + 0x0354U)
+#define PFC_DRVCTRL22		(PFC_BASE + 0x0358U)
+#define PFC_DRVCTRL23		(PFC_BASE + 0x035CU)
+#define PFC_DRVCTRL24		(PFC_BASE + 0x0360U)
+#define PFC_POCCTRL0		(PFC_BASE + 0x0380U)
+#define	PFC_TDSELCTRL0		(PFC_BASE + 0x03C0U)
+#define	PFC_IOCTRL		(PFC_BASE + 0x03E0U)
+#define	PFC_TSREG		(PFC_BASE + 0x03E4U)
+#define	PFC_PUEN0		(PFC_BASE + 0x0400U)
+#define	PFC_PUEN1		(PFC_BASE + 0x0404U)
+#define	PFC_PUEN2		(PFC_BASE + 0x0408U)
+#define	PFC_PUEN3		(PFC_BASE + 0x040CU)
+#define	PFC_PUEN4		(PFC_BASE + 0x0410U)
+#define	PFC_PUEN5		(PFC_BASE + 0x0414U)
+#define	PFC_PUEN6		(PFC_BASE + 0x0418U)
+#define	PFC_PUD0		(PFC_BASE + 0x0440U)
+#define	PFC_PUD1		(PFC_BASE + 0x0444U)
+#define	PFC_PUD2		(PFC_BASE + 0x0448U)
+#define	PFC_PUD3		(PFC_BASE + 0x044CU)
+#define	PFC_PUD4		(PFC_BASE + 0x0450U)
+#define	PFC_PUD5		(PFC_BASE + 0x0454U)
+#define	PFC_PUD6		(PFC_BASE + 0x0458U)
+#define	PFC_MOD_SEL0		(PFC_BASE + 0x0500U)
+#define	PFC_MOD_SEL1		(PFC_BASE + 0x0504U)
+#define	PFC_MOD_SEL2		(PFC_BASE + 0x0508U)
+
+#define	GPSR0_D15		((uint32_t)1U << 15U)
+#define	GPSR0_D14		((uint32_t)1U << 14U)
+#define	GPSR0_D13		((uint32_t)1U << 13U)
+#define	GPSR0_D12		((uint32_t)1U << 12U)
+#define	GPSR0_D11		((uint32_t)1U << 11U)
+#define	GPSR0_D10		((uint32_t)1U << 10U)
+#define	GPSR0_D9		((uint32_t)1U << 9U)
+#define	GPSR0_D8		((uint32_t)1U << 8U)
+#define	GPSR0_D7		((uint32_t)1U << 7U)
+#define	GPSR0_D6		((uint32_t)1U << 6U)
+#define	GPSR0_D5		((uint32_t)1U << 5U)
+#define	GPSR0_D4		((uint32_t)1U << 4U)
+#define	GPSR0_D3		((uint32_t)1U << 3U)
+#define	GPSR0_D2		((uint32_t)1U << 2U)
+#define	GPSR0_D1		((uint32_t)1U << 1U)
+#define	GPSR0_D0		((uint32_t)1U << 0U)
+#define	GPSR1_CLKOUT		((uint32_t)1U << 28U)
+#define	GPSR1_EX_WAIT0_A	((uint32_t)1U << 27U)
+#define	GPSR1_WE1		((uint32_t)1U << 26U)
+#define	GPSR1_WE0		((uint32_t)1U << 25U)
+#define	GPSR1_RD_WR		((uint32_t)1U << 24U)
+#define	GPSR1_RD		((uint32_t)1U << 23U)
+#define	GPSR1_BS		((uint32_t)1U << 22U)
+#define	GPSR1_CS1_A26		((uint32_t)1U << 21U)
+#define	GPSR1_CS0		((uint32_t)1U << 20U)
+#define	GPSR1_A19		((uint32_t)1U << 19U)
+#define	GPSR1_A18		((uint32_t)1U << 18U)
+#define	GPSR1_A17		((uint32_t)1U << 17U)
+#define	GPSR1_A16		((uint32_t)1U << 16U)
+#define	GPSR1_A15		((uint32_t)1U << 15U)
+#define	GPSR1_A14		((uint32_t)1U << 14U)
+#define	GPSR1_A13		((uint32_t)1U << 13U)
+#define	GPSR1_A12		((uint32_t)1U << 12U)
+#define	GPSR1_A11		((uint32_t)1U << 11U)
+#define	GPSR1_A10		((uint32_t)1U << 10U)
+#define	GPSR1_A9		((uint32_t)1U << 9U)
+#define	GPSR1_A8		((uint32_t)1U << 8U)
+#define	GPSR1_A7		((uint32_t)1U << 7U)
+#define	GPSR1_A6		((uint32_t)1U << 6U)
+#define	GPSR1_A5		((uint32_t)1U << 5U)
+#define	GPSR1_A4		((uint32_t)1U << 4U)
+#define	GPSR1_A3		((uint32_t)1U << 3U)
+#define	GPSR1_A2		((uint32_t)1U << 2U)
+#define	GPSR1_A1		((uint32_t)1U << 1U)
+#define	GPSR1_A0		((uint32_t)1U << 0U)
+#define	GPSR2_AVB_AVTP_CAPTURE_A	((uint32_t)1U << 14U)
+#define	GPSR2_AVB_AVTP_MATCH_A	((uint32_t)1U << 13U)
+#define	GPSR2_AVB_LINK		((uint32_t)1U << 12U)
+#define	GPSR2_AVB_PHY_INT	((uint32_t)1U << 11U)
+#define	GPSR2_AVB_MAGIC		((uint32_t)1U << 10U)
+#define	GPSR2_AVB_MDC		((uint32_t)1U << 9U)
+#define	GPSR2_PWM2_A		((uint32_t)1U << 8U)
+#define	GPSR2_PWM1_A		((uint32_t)1U << 7U)
+#define	GPSR2_PWM0		((uint32_t)1U << 6U)
+#define	GPSR2_IRQ5		((uint32_t)1U << 5U)
+#define	GPSR2_IRQ4		((uint32_t)1U << 4U)
+#define	GPSR2_IRQ3		((uint32_t)1U << 3U)
+#define	GPSR2_IRQ2		((uint32_t)1U << 2U)
+#define	GPSR2_IRQ1		((uint32_t)1U << 1U)
+#define	GPSR2_IRQ0		((uint32_t)1U << 0U)
+#define	GPSR3_SD1_WP		((uint32_t)1U << 15U)
+#define	GPSR3_SD1_CD		((uint32_t)1U << 14U)
+#define	GPSR3_SD0_WP		((uint32_t)1U << 13U)
+#define	GPSR3_SD0_CD		((uint32_t)1U << 12U)
+#define	GPSR3_SD1_DAT3		((uint32_t)1U << 11U)
+#define	GPSR3_SD1_DAT2		((uint32_t)1U << 10U)
+#define	GPSR3_SD1_DAT1		((uint32_t)1U << 9U)
+#define	GPSR3_SD1_DAT0		((uint32_t)1U << 8U)
+#define	GPSR3_SD1_CMD		((uint32_t)1U << 7U)
+#define	GPSR3_SD1_CLK		((uint32_t)1U << 6U)
+#define	GPSR3_SD0_DAT3		((uint32_t)1U << 5U)
+#define	GPSR3_SD0_DAT2		((uint32_t)1U << 4U)
+#define	GPSR3_SD0_DAT1		((uint32_t)1U << 3U)
+#define	GPSR3_SD0_DAT0		((uint32_t)1U << 2U)
+#define	GPSR3_SD0_CMD		((uint32_t)1U << 1U)
+#define	GPSR3_SD0_CLK		((uint32_t)1U << 0U)
+#define	GPSR4_SD3_DS		((uint32_t)1U << 17U)
+#define	GPSR4_SD3_DAT7		((uint32_t)1U << 16U)
+#define	GPSR4_SD3_DAT6		((uint32_t)1U << 15U)
+#define	GPSR4_SD3_DAT5		((uint32_t)1U << 14U)
+#define	GPSR4_SD3_DAT4		((uint32_t)1U << 13U)
+#define	GPSR4_SD3_DAT3		((uint32_t)1U << 12U)
+#define	GPSR4_SD3_DAT2		((uint32_t)1U << 11U)
+#define	GPSR4_SD3_DAT1		((uint32_t)1U << 10U)
+#define	GPSR4_SD3_DAT0		((uint32_t)1U << 9U)
+#define	GPSR4_SD3_CMD		((uint32_t)1U << 8U)
+#define	GPSR4_SD3_CLK		((uint32_t)1U << 7U)
+#define	GPSR4_SD2_DS		((uint32_t)1U << 6U)
+#define	GPSR4_SD2_DAT3		((uint32_t)1U << 5U)
+#define	GPSR4_SD2_DAT2		((uint32_t)1U << 4U)
+#define	GPSR4_SD2_DAT1		((uint32_t)1U << 3U)
+#define	GPSR4_SD2_DAT0		((uint32_t)1U << 2U)
+#define	GPSR4_SD2_CMD		((uint32_t)1U << 1U)
+#define	GPSR4_SD2_CLK		((uint32_t)1U << 0U)
+#define	GPSR5_MLB_DAT		((uint32_t)1U << 25U)
+#define	GPSR5_MLB_SIG		((uint32_t)1U << 24U)
+#define	GPSR5_MLB_CLK		((uint32_t)1U << 23U)
+#define	GPSR5_MSIOF0_RXD	((uint32_t)1U << 22U)
+#define	GPSR5_MSIOF0_SS2	((uint32_t)1U << 21U)
+#define	GPSR5_MSIOF0_TXD	((uint32_t)1U << 20U)
+#define	GPSR5_MSIOF0_SS1	((uint32_t)1U << 19U)
+#define	GPSR5_MSIOF0_SYNC	((uint32_t)1U << 18U)
+#define	GPSR5_MSIOF0_SCK	((uint32_t)1U << 17U)
+#define	GPSR5_HRTS0		((uint32_t)1U << 16U)
+#define	GPSR5_HCTS0		((uint32_t)1U << 15U)
+#define	GPSR5_HTX0		((uint32_t)1U << 14U)
+#define	GPSR5_HRX0		((uint32_t)1U << 13U)
+#define	GPSR5_HSCK0		((uint32_t)1U << 12U)
+#define	GPSR5_RX2_A		((uint32_t)1U << 11U)
+#define	GPSR5_TX2_A		((uint32_t)1U << 10U)
+#define	GPSR5_SCK2		((uint32_t)1U << 9U)
+#define	GPSR5_RTS1_TANS		((uint32_t)1U << 8U)
+#define	GPSR5_CTS1		((uint32_t)1U << 7U)
+#define	GPSR5_TX1_A		((uint32_t)1U << 6U)
+#define	GPSR5_RX1_A		((uint32_t)1U << 5U)
+#define	GPSR5_RTS0_TANS		((uint32_t)1U << 4U)
+#define	GPSR5_CTS0		((uint32_t)1U << 3U)
+#define	GPSR5_TX0		((uint32_t)1U << 2U)
+#define	GPSR5_RX0		((uint32_t)1U << 1U)
+#define	GPSR5_SCK0		((uint32_t)1U << 0U)
+#define	GPSR6_USB31_OVC		((uint32_t)1U << 31U)
+#define	GPSR6_USB31_PWEN	((uint32_t)1U << 30U)
+#define	GPSR6_USB30_OVC		((uint32_t)1U << 29U)
+#define	GPSR6_USB30_PWEN	((uint32_t)1U << 28U)
+#define	GPSR6_USB1_OVC		((uint32_t)1U << 27U)
+#define	GPSR6_USB1_PWEN		((uint32_t)1U << 26U)
+#define	GPSR6_USB0_OVC		((uint32_t)1U << 25U)
+#define	GPSR6_USB0_PWEN		((uint32_t)1U << 24U)
+#define	GPSR6_AUDIO_CLKB_B	((uint32_t)1U << 23U)
+#define	GPSR6_AUDIO_CLKA_A	((uint32_t)1U << 22U)
+#define	GPSR6_SSI_SDATA9_A	((uint32_t)1U << 21U)
+#define	GPSR6_SSI_SDATA8	((uint32_t)1U << 20U)
+#define	GPSR6_SSI_SDATA7	((uint32_t)1U << 19U)
+#define	GPSR6_SSI_WS78		((uint32_t)1U << 18U)
+#define	GPSR6_SSI_SCK78		((uint32_t)1U << 17U)
+#define	GPSR6_SSI_SDATA6	((uint32_t)1U << 16U)
+#define	GPSR6_SSI_WS6		((uint32_t)1U << 15U)
+#define	GPSR6_SSI_SCK6		((uint32_t)1U << 14U)
+#define	GPSR6_SSI_SDATA5	((uint32_t)1U << 13U)
+#define	GPSR6_SSI_WS5		((uint32_t)1U << 12U)
+#define	GPSR6_SSI_SCK5		((uint32_t)1U << 11U)
+#define	GPSR6_SSI_SDATA4	((uint32_t)1U << 10U)
+#define	GPSR6_SSI_WS4		((uint32_t)1U << 9U)
+#define	GPSR6_SSI_SCK4		((uint32_t)1U << 8U)
+#define	GPSR6_SSI_SDATA3	((uint32_t)1U << 7U)
+#define	GPSR6_SSI_WS34		((uint32_t)1U << 6U)
+#define	GPSR6_SSI_SCK34		((uint32_t)1U << 5U)
+#define	GPSR6_SSI_SDATA2_A	((uint32_t)1U << 4U)
+#define	GPSR6_SSI_SDATA1_A	((uint32_t)1U << 3U)
+#define	GPSR6_SSI_SDATA0	((uint32_t)1U << 2U)
+#define	GPSR6_SSI_WS0129	((uint32_t)1U << 1U)
+#define	GPSR6_SSI_SCK0129	((uint32_t)1U << 0U)
+#define	GPSR7_HDMI1_CEC		((uint32_t)1U << 3U)
+#define	GPSR7_HDMI0_CEC		((uint32_t)1U << 2U)
+#define	GPSR7_AVS2		((uint32_t)1U << 1U)
+#define	GPSR7_AVS1		((uint32_t)1U << 0U)
+
+#define	IPSR_28_FUNC(x)		((uint32_t)(x) << 28U)
+#define	IPSR_24_FUNC(x)		((uint32_t)(x) << 24U)
+#define	IPSR_20_FUNC(x)		((uint32_t)(x) << 20U)
+#define	IPSR_16_FUNC(x)		((uint32_t)(x) << 16U)
+#define	IPSR_12_FUNC(x)		((uint32_t)(x) << 12U)
+#define	IPSR_8_FUNC(x)		((uint32_t)(x) << 8U)
+#define	IPSR_4_FUNC(x)		((uint32_t)(x) << 4U)
+#define	IPSR_0_FUNC(x)		((uint32_t)(x) << 0U)
+
+#define	POC_SD3_DS_33V		((uint32_t)1U << 29U)
+#define	POC_SD3_DAT7_33V	((uint32_t)1U << 28U)
+#define	POC_SD3_DAT6_33V	((uint32_t)1U << 27U)
+#define	POC_SD3_DAT5_33V	((uint32_t)1U << 26U)
+#define	POC_SD3_DAT4_33V	((uint32_t)1U << 25U)
+#define	POC_SD3_DAT3_33V	((uint32_t)1U << 24U)
+#define	POC_SD3_DAT2_33V	((uint32_t)1U << 23U)
+#define	POC_SD3_DAT1_33V	((uint32_t)1U << 22U)
+#define	POC_SD3_DAT0_33V	((uint32_t)1U << 21U)
+#define	POC_SD3_CMD_33V		((uint32_t)1U << 20U)
+#define	POC_SD3_CLK_33V		((uint32_t)1U << 19U)
+#define	POC_SD2_DS_33V		((uint32_t)1U << 18U)
+#define	POC_SD2_DAT3_33V	((uint32_t)1U << 17U)
+#define	POC_SD2_DAT2_33V	((uint32_t)1U << 16U)
+#define	POC_SD2_DAT1_33V	((uint32_t)1U << 15U)
+#define	POC_SD2_DAT0_33V	((uint32_t)1U << 14U)
+#define	POC_SD2_CMD_33V		((uint32_t)1U << 13U)
+#define	POC_SD2_CLK_33V		((uint32_t)1U << 12U)
+#define	POC_SD1_DAT3_33V	((uint32_t)1U << 11U)
+#define	POC_SD1_DAT2_33V	((uint32_t)1U << 10U)
+#define	POC_SD1_DAT1_33V	((uint32_t)1U << 9U)
+#define	POC_SD1_DAT0_33V	((uint32_t)1U << 8U)
+#define	POC_SD1_CMD_33V		((uint32_t)1U << 7U)
+#define	POC_SD1_CLK_33V		((uint32_t)1U << 6U)
+#define	POC_SD0_DAT3_33V	((uint32_t)1U << 5U)
+#define	POC_SD0_DAT2_33V	((uint32_t)1U << 4U)
+#define	POC_SD0_DAT1_33V	((uint32_t)1U << 3U)
+#define	POC_SD0_DAT0_33V	((uint32_t)1U << 2U)
+#define	POC_SD0_CMD_33V		((uint32_t)1U << 1U)
+#define	POC_SD0_CLK_33V		((uint32_t)1U << 0U)
+
+#define	DRVCTRL0_MASK		(0xCCCCCCCCU)
+#define	DRVCTRL1_MASK		(0xCCCCCCC8U)
+#define	DRVCTRL2_MASK		(0x88888888U)
+#define	DRVCTRL3_MASK		(0x88888888U)
+#define	DRVCTRL4_MASK		(0x88888888U)
+#define	DRVCTRL5_MASK		(0x88888888U)
+#define	DRVCTRL6_MASK		(0x88888888U)
+#define	DRVCTRL7_MASK		(0x88888888U)
+#define	DRVCTRL8_MASK		(0x88888888U)
+#define	DRVCTRL9_MASK		(0x88888888U)
+#define	DRVCTRL10_MASK		(0x88888888U)
+#define	DRVCTRL11_MASK		(0x888888CCU)
+#define	DRVCTRL12_MASK		(0xCCCFFFCFU)
+#define	DRVCTRL13_MASK		(0xCC888888U)
+#define	DRVCTRL14_MASK		(0x88888888U)
+#define	DRVCTRL15_MASK		(0x88888888U)
+#define	DRVCTRL16_MASK		(0x88888888U)
+#define	DRVCTRL17_MASK		(0x88888888U)
+#define	DRVCTRL18_MASK		(0x88888888U)
+#define	DRVCTRL19_MASK		(0x88888888U)
+#define	DRVCTRL20_MASK		(0x88888888U)
+#define	DRVCTRL21_MASK		(0x88888888U)
+#define	DRVCTRL22_MASK		(0x88888888U)
+#define	DRVCTRL23_MASK		(0x88888888U)
+#define	DRVCTRL24_MASK		(0x8888888FU)
+
+#define	DRVCTRL0_QSPI0_SPCLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL0_QSPI0_MOSI_IO0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL0_QSPI0_MISO_IO1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL0_QSPI0_IO2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL0_QSPI0_IO3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL0_QSPI0_SSL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL0_QSPI1_SPCLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL0_QSPI1_MOSI_IO0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL1_QSPI1_MISO_IO1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL1_QSPI1_IO2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL1_QSPI1_IO3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL1_QSPI1_SS(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL1_RPC_INT(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL1_RPC_WP(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL1_RPC_RESET(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL1_AVB_RX_CTL(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL2_AVB_RXC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL2_AVB_RD0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL2_AVB_RD1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL2_AVB_RD2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL2_AVB_RD3(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL2_AVB_TX_CTL(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL2_AVB_TXC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL2_AVB_TD0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL3_AVB_TD1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL3_AVB_TD2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL3_AVB_TD3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL3_AVB_TXCREFCLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL3_AVB_MDIO(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL3_AVB_MDC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL3_AVB_MAGIC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL3_AVB_PHY_INT(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL4_AVB_LINK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL4_AVB_AVTP_MATCH(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL4_AVB_AVTP_CAPTURE(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL4_IRQ0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL4_IRQ1(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL4_IRQ2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL4_IRQ3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL4_IRQ4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL5_IRQ5(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL5_PWM0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL5_PWM1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL5_PWM2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL5_A0(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL5_A1(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL5_A2(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL5_A3(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL6_A4(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL6_A5(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL6_A6(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL6_A7(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL6_A8(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL6_A9(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL6_A10(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL6_A11(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL7_A12(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL7_A13(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL7_A14(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL7_A15(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL7_A16(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL7_A17(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL7_A18(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL7_A19(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL8_CLKOUT(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL8_CS0(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL8_CS1_A2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL8_BS(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL8_RD(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL8_RD_W(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL8_WE0(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL8_WE1(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL9_EX_WAIT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL9_PRESETOU(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL9_D0(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL9_D1(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL9_D2(x)		((uint32_t)(x) << 12U)
+#define	DRVCTRL9_D3(x)		((uint32_t)(x) << 8U)
+#define	DRVCTRL9_D4(x)		((uint32_t)(x) << 4U)
+#define	DRVCTRL9_D5(x)		((uint32_t)(x) << 0U)
+#define	DRVCTRL10_D6(x)		((uint32_t)(x) << 28U)
+#define	DRVCTRL10_D7(x)		((uint32_t)(x) << 24U)
+#define	DRVCTRL10_D8(x)		((uint32_t)(x) << 20U)
+#define	DRVCTRL10_D9(x)		((uint32_t)(x) << 16U)
+#define	DRVCTRL10_D10(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL10_D11(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL10_D12(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL10_D13(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL11_D14(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL11_D15(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL11_AVS1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL11_AVS2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL11_HDMI0_CEC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL11_HDMI1_CEC(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL11_DU_DOTCLKIN0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL11_DU_DOTCLKIN1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL12_DU_DOTCLKIN2(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL12_DU_DOTCLKIN3(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL12_DU_FSCLKST(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL12_DU_TMS(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_TDO(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL13_ASEBRK(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL13_SD0_CLK(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL13_SD0_CMD(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL13_SD0_DAT0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL13_SD0_DAT1(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL13_SD0_DAT2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL13_SD0_DAT3(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL14_SD1_CLK(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL14_SD1_CMD(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL14_SD1_DAT0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL14_SD1_DAT1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL14_SD1_DAT2(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL14_SD1_DAT3(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL14_SD2_CLK(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL14_SD2_CMD(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL15_SD2_DAT0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL15_SD2_DAT1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL15_SD2_DAT2(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL15_SD2_DAT3(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL15_SD2_DS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL15_SD3_CLK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL15_SD3_CMD(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL15_SD3_DAT0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL16_SD3_DAT1(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL16_SD3_DAT2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL16_SD3_DAT3(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL16_SD3_DAT4(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL16_SD3_DAT5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL16_SD3_DAT6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL16_SD3_DAT7(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL16_SD3_DS(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL17_SD0_CD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL17_SD0_WP(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL17_SD1_CD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL17_SD1_WP(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL17_SCK0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL17_RX0(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL17_TX0(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL17_CTS0(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL18_RTS0_TANS(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL18_RX1(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL18_TX1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL18_CTS1(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL18_RTS1_TANS(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL18_SCK2(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL18_TX2(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL18_RX2(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL19_HSCK0(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL19_HRX0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL19_HTX0(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL19_HCTS0(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL19_HRTS0(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL19_MSIOF0_SCK(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL19_MSIOF0_SYNC(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL19_MSIOF0_SS1(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL20_MSIOF0_TXD(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL20_MSIOF0_SS2(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL20_MSIOF0_RXD(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL20_MLB_CLK(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL20_MLB_SIG(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL20_MLB_DAT(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL20_MLB_REF(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL20_SSI_SCK0129(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL21_SSI_WS0129(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL21_SSI_SDATA0(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL21_SSI_SDATA1(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL21_SSI_SDATA2(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL21_SSI_SCK34(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL21_SSI_WS34(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL21_SSI_SDATA3(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL21_SSI_SCK4(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL22_SSI_WS4(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL22_SSI_SDATA4(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL22_SSI_SCK5(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL22_SSI_WS5(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL22_SSI_SDATA5(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL22_SSI_SCK6(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL22_SSI_WS6(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL22_SSI_SDATA6(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL23_SSI_SCK78(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL23_SSI_WS78(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL23_SSI_SDATA7(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL23_SSI_SDATA8(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL23_SSI_SDATA9(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL23_AUDIO_CLKA(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL23_AUDIO_CLKB(x)	((uint32_t)(x) << 4U)
+#define	DRVCTRL23_USB0_PWEN(x)	((uint32_t)(x) << 0U)
+#define	DRVCTRL24_USB0_OVC(x)	((uint32_t)(x) << 28U)
+#define	DRVCTRL24_USB1_PWEN(x)	((uint32_t)(x) << 24U)
+#define	DRVCTRL24_USB1_OVC(x)	((uint32_t)(x) << 20U)
+#define	DRVCTRL24_USB30_PWEN(x)	((uint32_t)(x) << 16U)
+#define	DRVCTRL24_USB30_OVC(x)	((uint32_t)(x) << 12U)
+#define	DRVCTRL24_USB31_PWEN(x)	((uint32_t)(x) << 8U)
+#define	DRVCTRL24_USB31_OVC(x)	((uint32_t)(x) << 4U)
+
+#define	MOD_SEL0_MSIOF3_A	((uint32_t)0U << 29U)
+#define	MOD_SEL0_MSIOF3_B	((uint32_t)1U << 29U)
+#define	MOD_SEL0_MSIOF3_C	((uint32_t)2U << 29U)
+#define	MOD_SEL0_MSIOF3_D	((uint32_t)3U << 29U)
+#define	MOD_SEL0_MSIOF3_E	((uint32_t)4U << 29U)
+#define	MOD_SEL0_MSIOF2_A	((uint32_t)0U << 27U)
+#define	MOD_SEL0_MSIOF2_B	((uint32_t)1U << 27U)
+#define	MOD_SEL0_MSIOF2_C	((uint32_t)2U << 27U)
+#define	MOD_SEL0_MSIOF2_D	((uint32_t)3U << 27U)
+#define	MOD_SEL0_MSIOF1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL0_MSIOF1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL0_MSIOF1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL0_MSIOF1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL0_MSIOF1_E	((uint32_t)4U << 24U)
+#define	MOD_SEL0_MSIOF1_F	((uint32_t)5U << 24U)
+#define	MOD_SEL0_MSIOF1_G	((uint32_t)6U << 24U)
+#define	MOD_SEL0_LBSC_A		((uint32_t)0U << 23U)
+#define	MOD_SEL0_LBSC_B		((uint32_t)1U << 23U)
+#define	MOD_SEL0_IEBUS_A	((uint32_t)0U << 22U)
+#define	MOD_SEL0_IEBUS_B	((uint32_t)1U << 22U)
+#define	MOD_SEL0_I2C2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL0_I2C2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL0_I2C1_A		((uint32_t)0U << 20U)
+#define	MOD_SEL0_I2C1_B		((uint32_t)1U << 20U)
+#define	MOD_SEL0_HSCIF4_A	((uint32_t)0U << 19U)
+#define	MOD_SEL0_HSCIF4_B	((uint32_t)1U << 19U)
+#define	MOD_SEL0_HSCIF3_A	((uint32_t)0U << 17U)
+#define	MOD_SEL0_HSCIF3_B	((uint32_t)1U << 17U)
+#define	MOD_SEL0_HSCIF3_C	((uint32_t)2U << 17U)
+#define	MOD_SEL0_HSCIF3_D	((uint32_t)3U << 17U)
+#define	MOD_SEL0_HSCIF1_A	((uint32_t)0U << 16U)
+#define	MOD_SEL0_HSCIF1_B	((uint32_t)1U << 16U)
+#define	MOD_SEL0_FSO_A		((uint32_t)0U << 15U)
+#define	MOD_SEL0_FSO_B		((uint32_t)1U << 15U)
+#define	MOD_SEL0_HSCIF2_A	((uint32_t)0U << 13U)
+#define	MOD_SEL0_HSCIF2_B	((uint32_t)1U << 13U)
+#define	MOD_SEL0_HSCIF2_C	((uint32_t)2U << 13U)
+#define	MOD_SEL0_ETHERAVB_A	((uint32_t)0U << 12U)
+#define	MOD_SEL0_ETHERAVB_B	((uint32_t)1U << 12U)
+#define	MOD_SEL0_DRIF3_A	((uint32_t)0U << 11U)
+#define	MOD_SEL0_DRIF3_B	((uint32_t)1U << 11U)
+#define	MOD_SEL0_DRIF2_A	((uint32_t)0U << 10U)
+#define	MOD_SEL0_DRIF2_B	((uint32_t)1U << 10U)
+#define	MOD_SEL0_DRIF1_A	((uint32_t)0U << 8U)
+#define	MOD_SEL0_DRIF1_B	((uint32_t)1U << 8U)
+#define	MOD_SEL0_DRIF1_C	((uint32_t)2U << 8U)
+#define	MOD_SEL0_DRIF0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL0_DRIF0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL0_DRIF0_C	((uint32_t)2U << 6U)
+#define	MOD_SEL0_CANFD0_A	((uint32_t)0U << 5U)
+#define	MOD_SEL0_CANFD0_B	((uint32_t)1U << 5U)
+#define	MOD_SEL0_ADG_A_A	((uint32_t)0U << 3U)
+#define	MOD_SEL0_ADG_A_B	((uint32_t)1U << 3U)
+#define	MOD_SEL0_ADG_A_C	((uint32_t)2U << 3U)
+#define	MOD_SEL1_TSIF1_A	((uint32_t)0U << 30U)
+#define	MOD_SEL1_TSIF1_B	((uint32_t)1U << 30U)
+#define	MOD_SEL1_TSIF1_C	((uint32_t)2U << 30U)
+#define	MOD_SEL1_TSIF1_D	((uint32_t)3U << 30U)
+#define	MOD_SEL1_TSIF0_A	((uint32_t)0U << 27U)
+#define	MOD_SEL1_TSIF0_B	((uint32_t)1U << 27U)
+#define	MOD_SEL1_TSIF0_C	((uint32_t)2U << 27U)
+#define	MOD_SEL1_TSIF0_D	((uint32_t)3U << 27U)
+#define	MOD_SEL1_TSIF0_E	((uint32_t)4U << 27U)
+#define	MOD_SEL1_TIMER_TMU_A	((uint32_t)0U << 26U)
+#define	MOD_SEL1_TIMER_TMU_B	((uint32_t)1U << 26U)
+#define	MOD_SEL1_SSP1_1_A	((uint32_t)0U << 24U)
+#define	MOD_SEL1_SSP1_1_B	((uint32_t)1U << 24U)
+#define	MOD_SEL1_SSP1_1_C	((uint32_t)2U << 24U)
+#define	MOD_SEL1_SSP1_1_D	((uint32_t)3U << 24U)
+#define	MOD_SEL1_SSP1_0_A	((uint32_t)0U << 21U)
+#define	MOD_SEL1_SSP1_0_B	((uint32_t)1U << 21U)
+#define	MOD_SEL1_SSP1_0_C	((uint32_t)2U << 21U)
+#define	MOD_SEL1_SSP1_0_D	((uint32_t)3U << 21U)
+#define	MOD_SEL1_SSP1_0_E	((uint32_t)4U << 21U)
+#define	MOD_SEL1_SSI_A		((uint32_t)0U << 20U)
+#define	MOD_SEL1_SSI_B		((uint32_t)1U << 20U)
+#define	MOD_SEL1_SPEED_PULSE_IF_A	((uint32_t)0U << 19U)
+#define	MOD_SEL1_SPEED_PULSE_IF_B	((uint32_t)1U << 19U)
+#define	MOD_SEL1_SIMCARD_A	((uint32_t)0U << 17U)
+#define	MOD_SEL1_SIMCARD_B	((uint32_t)1U << 17U)
+#define	MOD_SEL1_SIMCARD_C	((uint32_t)2U << 17U)
+#define	MOD_SEL1_SIMCARD_D	((uint32_t)3U << 17U)
+#define	MOD_SEL1_SDHI2_A	((uint32_t)0U << 16U)
+#define	MOD_SEL1_SDHI2_B	((uint32_t)1U << 16U)
+#define	MOD_SEL1_SCIF4_A	((uint32_t)0U << 14U)
+#define	MOD_SEL1_SCIF4_B	((uint32_t)1U << 14U)
+#define	MOD_SEL1_SCIF4_C	((uint32_t)2U << 14U)
+#define	MOD_SEL1_SCIF3_A	((uint32_t)0U << 13U)
+#define	MOD_SEL1_SCIF3_B	((uint32_t)1U << 13U)
+#define	MOD_SEL1_SCIF2_A	((uint32_t)0U << 12U)
+#define	MOD_SEL1_SCIF2_B	((uint32_t)1U << 12U)
+#define	MOD_SEL1_SCIF1_A	((uint32_t)0U << 11U)
+#define	MOD_SEL1_SCIF1_B	((uint32_t)1U << 11U)
+#define	MOD_SEL1_SCIF_A		((uint32_t)0U << 10U)
+#define	MOD_SEL1_SCIF_B		((uint32_t)1U << 10U)
+#define	MOD_SEL1_REMOCON_A	((uint32_t)0U << 9U)
+#define	MOD_SEL1_REMOCON_B	((uint32_t)1U << 9U)
+#define	MOD_SEL1_RCAN0_A	((uint32_t)0U << 6U)
+#define	MOD_SEL1_RCAN0_B	((uint32_t)1U << 6U)
+#define	MOD_SEL1_PWM6_A		((uint32_t)0U << 5U)
+#define	MOD_SEL1_PWM6_B		((uint32_t)1U << 5U)
+#define	MOD_SEL1_PWM5_A		((uint32_t)0U << 4U)
+#define	MOD_SEL1_PWM5_B		((uint32_t)1U << 4U)
+#define	MOD_SEL1_PWM4_A		((uint32_t)0U << 3U)
+#define	MOD_SEL1_PWM4_B		((uint32_t)1U << 3U)
+#define	MOD_SEL1_PWM3_A		((uint32_t)0U << 2U)
+#define	MOD_SEL1_PWM3_B		((uint32_t)1U << 2U)
+#define	MOD_SEL1_PWM2_A		((uint32_t)0U << 1U)
+#define	MOD_SEL1_PWM2_B		((uint32_t)1U << 1U)
+#define	MOD_SEL1_PWM1_A		((uint32_t)0U << 0U)
+#define	MOD_SEL1_PWM1_B		((uint32_t)1U << 0U)
+#define	MOD_SEL2_I2C_5_A	((uint32_t)0U << 31U)
+#define	MOD_SEL2_I2C_5_B	((uint32_t)1U << 31U)
+#define	MOD_SEL2_I2C_3_A	((uint32_t)0U << 30U)
+#define	MOD_SEL2_I2C_3_B	((uint32_t)1U << 30U)
+#define	MOD_SEL2_I2C_0_A	((uint32_t)0U << 29U)
+#define	MOD_SEL2_I2C_0_B	((uint32_t)1U << 29U)
+#define	MOD_SEL2_FM_A		((uint32_t)0U << 27U)
+#define	MOD_SEL2_FM_B		((uint32_t)1U << 27U)
+#define	MOD_SEL2_FM_C		((uint32_t)2U << 27U)
+#define	MOD_SEL2_FM_D		((uint32_t)3U << 27U)
+#define	MOD_SEL2_SCIF5_A	((uint32_t)0U << 26U)
+#define	MOD_SEL2_SCIF5_B	((uint32_t)1U << 26U)
+#define	MOD_SEL2_I2C6_A		((uint32_t)0U << 23U)
+#define	MOD_SEL2_I2C6_B		((uint32_t)1U << 23U)
+#define	MOD_SEL2_I2C6_C		((uint32_t)2U << 23U)
+#define	MOD_SEL2_NDF_A		((uint32_t)0U << 22U)
+#define	MOD_SEL2_NDF_B		((uint32_t)1U << 22U)
+#define	MOD_SEL2_SSI2_A		((uint32_t)0U << 21U)
+#define	MOD_SEL2_SSI2_B		((uint32_t)1U << 21U)
+#define	MOD_SEL2_SSI9_A		((uint32_t)0U << 20U)
+#define	MOD_SEL2_SSI9_B		((uint32_t)1U << 20U)
+#define	MOD_SEL2_TIMER_TMU2_A	((uint32_t)0U << 19U)
+#define	MOD_SEL2_TIMER_TMU2_B	((uint32_t)1U << 19U)
+#define	MOD_SEL2_ADG_B_A	((uint32_t)0U << 18U)
+#define	MOD_SEL2_ADG_B_B	((uint32_t)1U << 18U)
+#define	MOD_SEL2_ADG_C_A	((uint32_t)0U << 17U)
+#define	MOD_SEL2_ADG_C_B	((uint32_t)1U << 17U)
+#define	MOD_SEL2_VIN4_A		((uint32_t)0U << 0U)
+#define	MOD_SEL2_VIN4_B		((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data);
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+	mmio_write_32(PFC_PMMR, ~data);
+	mmio_write_32((uintptr_t) addr, data);
+}
+
+void pfc_init_m3n(void)
+{
+	uint32_t reg;
+
+	/* initialize module select */
+	pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
+		      | MOD_SEL0_MSIOF2_A
+		      | MOD_SEL0_MSIOF1_A
+		      | MOD_SEL0_LBSC_A
+		      | MOD_SEL0_IEBUS_A
+		      | MOD_SEL0_I2C2_A
+		      | MOD_SEL0_I2C1_A
+		      | MOD_SEL0_HSCIF4_A
+		      | MOD_SEL0_HSCIF3_A
+		      | MOD_SEL0_HSCIF1_A
+		      | MOD_SEL0_FSO_A
+		      | MOD_SEL0_HSCIF2_A
+		      | MOD_SEL0_ETHERAVB_A
+		      | MOD_SEL0_DRIF3_A
+		      | MOD_SEL0_DRIF2_A
+		      | MOD_SEL0_DRIF1_A
+		      | MOD_SEL0_DRIF0_A
+		      | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
+	pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
+		      | MOD_SEL1_TSIF0_A
+		      | MOD_SEL1_TIMER_TMU_A
+		      | MOD_SEL1_SSP1_1_A
+		      | MOD_SEL1_SSP1_0_A
+		      | MOD_SEL1_SSI_A
+		      | MOD_SEL1_SPEED_PULSE_IF_A
+		      | MOD_SEL1_SIMCARD_A
+		      | MOD_SEL1_SDHI2_A
+		      | MOD_SEL1_SCIF4_A
+		      | MOD_SEL1_SCIF3_A
+		      | MOD_SEL1_SCIF2_A
+		      | MOD_SEL1_SCIF1_A
+		      | MOD_SEL1_SCIF_A
+		      | MOD_SEL1_REMOCON_A
+		      | MOD_SEL1_RCAN0_A
+		      | MOD_SEL1_PWM6_A
+		      | MOD_SEL1_PWM5_A
+		      | MOD_SEL1_PWM4_A
+		      | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
+	pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
+		      | MOD_SEL2_I2C_3_A
+		      | MOD_SEL2_I2C_0_A
+		      | MOD_SEL2_FM_A
+		      | MOD_SEL2_SCIF5_A
+		      | MOD_SEL2_I2C6_A
+		      | MOD_SEL2_NDF_A
+		      | MOD_SEL2_SSI2_A
+		      | MOD_SEL2_SSI9_A
+		      | MOD_SEL2_TIMER_TMU2_A
+		      | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
+
+	/* initialize peripheral function select */
+	pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(3)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(3));
+	pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
+		      | IPSR_24_FUNC(6)
+		      | IPSR_20_FUNC(6)
+		      | IPSR_16_FUNC(6)
+		      | IPSR_12_FUNC(6)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(6)
+		      | IPSR_4_FUNC(6)
+		      | IPSR_0_FUNC(6));
+	pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(1)
+		      | IPSR_20_FUNC(1)
+		      | IPSR_16_FUNC(1)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(4)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(1));
+	pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(4)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(3)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(3)
+		      | IPSR_0_FUNC(8));
+	pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
+		      | IPSR_24_FUNC(0)
+		      | IPSR_20_FUNC(0)
+		      | IPSR_16_FUNC(0)
+		      | IPSR_12_FUNC(0)
+		      | IPSR_8_FUNC(0)
+		      | IPSR_4_FUNC(1)
+		      | IPSR_0_FUNC(0));
+	pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
+		      | IPSR_0_FUNC(0));
+
+	/* initialize GPIO/perihperal function select */
+	pfc_reg_write(PFC_GPSR0, GPSR0_D15
+		      | GPSR0_D14
+		      | GPSR0_D13
+		      | GPSR0_D12
+		      | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
+	pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
+		      | GPSR1_EX_WAIT0_A
+		      | GPSR1_A19
+		      | GPSR1_A18
+		      | GPSR1_A17
+		      | GPSR1_A16
+		      | GPSR1_A15
+		      | GPSR1_A14
+		      | GPSR1_A13
+		      | GPSR1_A12
+		      | GPSR1_A7
+		      | GPSR1_A6
+		      | GPSR1_A5
+		      | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
+	pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
+		      | GPSR2_AVB_AVTP_MATCH_A
+		      | GPSR2_AVB_LINK
+		      | GPSR2_AVB_PHY_INT
+		      | GPSR2_AVB_MDC
+		      | GPSR2_PWM2_A
+		      | GPSR2_PWM1_A
+		      | GPSR2_IRQ5
+		      | GPSR2_IRQ4
+		      | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
+	pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
+		      | GPSR3_SD0_CD
+		      | GPSR3_SD1_DAT3
+		      | GPSR3_SD1_DAT2
+		      | GPSR3_SD1_DAT1
+		      | GPSR3_SD1_DAT0
+		      | GPSR3_SD0_DAT3
+		      | GPSR3_SD0_DAT2
+		      | GPSR3_SD0_DAT1
+		      | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
+	pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
+		      | GPSR4_SD3_DAT6
+		      | GPSR4_SD3_DAT3
+		      | GPSR4_SD3_DAT2
+		      | GPSR4_SD3_DAT1
+		      | GPSR4_SD3_DAT0
+		      | GPSR4_SD3_CMD
+		      | GPSR4_SD3_CLK
+		      | GPSR4_SD2_DS
+		      | GPSR4_SD2_DAT3
+		      | GPSR4_SD2_DAT2
+		      | GPSR4_SD2_DAT1
+		      | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
+	pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
+		      | GPSR5_MSIOF0_SS1
+		      | GPSR5_MSIOF0_SYNC
+		      | GPSR5_HRTS0
+		      | GPSR5_HCTS0
+		      | GPSR5_HTX0
+		      | GPSR5_HRX0
+		      | GPSR5_HSCK0
+		      | GPSR5_RX2_A
+		      | GPSR5_TX2_A
+		      | GPSR5_SCK2
+		      | GPSR5_RTS1_TANS
+		      | GPSR5_CTS1
+		      | GPSR5_TX1_A
+		      | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
+	pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
+		      | GPSR6_USB30_PWEN
+		      | GPSR6_USB1_OVC
+		      | GPSR6_USB1_PWEN
+		      | GPSR6_USB0_OVC
+		      | GPSR6_USB0_PWEN
+		      | GPSR6_AUDIO_CLKB_B
+		      | GPSR6_AUDIO_CLKA_A
+		      | GPSR6_SSI_SDATA8
+		      | GPSR6_SSI_SDATA7
+		      | GPSR6_SSI_WS78
+		      | GPSR6_SSI_SCK78
+		      | GPSR6_SSI_WS6
+		      | GPSR6_SSI_SCK6
+		      | GPSR6_SSI_SDATA4
+		      | GPSR6_SSI_WS4
+		      | GPSR6_SSI_SCK4
+		      | GPSR6_SSI_SDATA1_A
+		      | GPSR6_SSI_SDATA0
+		      | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
+	pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
+		      | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
+
+	/* initialize POC control register */
+	pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
+		      | POC_SD3_DAT7_33V
+		      | POC_SD3_DAT6_33V
+		      | POC_SD3_DAT5_33V
+		      | POC_SD3_DAT4_33V
+		      | POC_SD3_DAT3_33V
+		      | POC_SD3_DAT2_33V
+		      | POC_SD3_DAT1_33V
+		      | POC_SD3_DAT0_33V
+		      | POC_SD3_CMD_33V
+		      | POC_SD3_CLK_33V
+		      | POC_SD0_DAT3_33V
+		      | POC_SD0_DAT2_33V
+		      | POC_SD0_DAT1_33V
+		      | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
+
+	/* initialize DRV control register */
+	reg = mmio_read_32(PFC_DRVCTRL0);
+	reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
+	       | DRVCTRL0_QSPI0_MOSI_IO0(3)
+	       | DRVCTRL0_QSPI0_MISO_IO1(3)
+	       | DRVCTRL0_QSPI0_IO2(3)
+	       | DRVCTRL0_QSPI0_IO3(3)
+	       | DRVCTRL0_QSPI0_SSL(3)
+	       | DRVCTRL0_QSPI1_SPCLK(3)
+	       | DRVCTRL0_QSPI1_MOSI_IO0(3));
+	pfc_reg_write(PFC_DRVCTRL0, reg);
+	reg = mmio_read_32(PFC_DRVCTRL1);
+	reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
+	       | DRVCTRL1_QSPI1_IO2(3)
+	       | DRVCTRL1_QSPI1_IO3(3)
+	       | DRVCTRL1_QSPI1_SS(3)
+	       | DRVCTRL1_RPC_INT(3)
+	       | DRVCTRL1_RPC_WP(3)
+	       | DRVCTRL1_RPC_RESET(3)
+	       | DRVCTRL1_AVB_RX_CTL(7));
+	pfc_reg_write(PFC_DRVCTRL1, reg);
+	reg = mmio_read_32(PFC_DRVCTRL2);
+	reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
+	       | DRVCTRL2_AVB_RD0(7)
+	       | DRVCTRL2_AVB_RD1(7)
+	       | DRVCTRL2_AVB_RD2(7)
+	       | DRVCTRL2_AVB_RD3(7)
+	       | DRVCTRL2_AVB_TX_CTL(3)
+	       | DRVCTRL2_AVB_TXC(3)
+	       | DRVCTRL2_AVB_TD0(3));
+	pfc_reg_write(PFC_DRVCTRL2, reg);
+	reg = mmio_read_32(PFC_DRVCTRL3);
+	reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
+	       | DRVCTRL3_AVB_TD2(3)
+	       | DRVCTRL3_AVB_TD3(3)
+	       | DRVCTRL3_AVB_TXCREFCLK(7)
+	       | DRVCTRL3_AVB_MDIO(7)
+	       | DRVCTRL3_AVB_MDC(7)
+	       | DRVCTRL3_AVB_MAGIC(7)
+	       | DRVCTRL3_AVB_PHY_INT(7));
+	pfc_reg_write(PFC_DRVCTRL3, reg);
+	reg = mmio_read_32(PFC_DRVCTRL4);
+	reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
+	       | DRVCTRL4_AVB_AVTP_MATCH(7)
+	       | DRVCTRL4_AVB_AVTP_CAPTURE(7)
+	       | DRVCTRL4_IRQ0(7)
+	       | DRVCTRL4_IRQ1(7)
+	       | DRVCTRL4_IRQ2(7)
+	       | DRVCTRL4_IRQ3(7)
+	       | DRVCTRL4_IRQ4(7));
+	pfc_reg_write(PFC_DRVCTRL4, reg);
+	reg = mmio_read_32(PFC_DRVCTRL5);
+	reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
+	       | DRVCTRL5_PWM0(7)
+	       | DRVCTRL5_PWM1(7)
+	       | DRVCTRL5_PWM2(7)
+	       | DRVCTRL5_A0(3)
+	       | DRVCTRL5_A1(3)
+	       | DRVCTRL5_A2(3)
+	       | DRVCTRL5_A3(3));
+	pfc_reg_write(PFC_DRVCTRL5, reg);
+	reg = mmio_read_32(PFC_DRVCTRL6);
+	reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
+	       | DRVCTRL6_A5(3)
+	       | DRVCTRL6_A6(3)
+	       | DRVCTRL6_A7(3)
+	       | DRVCTRL6_A8(7)
+	       | DRVCTRL6_A9(7)
+	       | DRVCTRL6_A10(7)
+	       | DRVCTRL6_A11(7));
+	pfc_reg_write(PFC_DRVCTRL6, reg);
+	reg = mmio_read_32(PFC_DRVCTRL7);
+	reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
+	       | DRVCTRL7_A13(3)
+	       | DRVCTRL7_A14(3)
+	       | DRVCTRL7_A15(3)
+	       | DRVCTRL7_A16(3)
+	       | DRVCTRL7_A17(3)
+	       | DRVCTRL7_A18(3)
+	       | DRVCTRL7_A19(3));
+	pfc_reg_write(PFC_DRVCTRL7, reg);
+	reg = mmio_read_32(PFC_DRVCTRL8);
+	reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
+	       | DRVCTRL8_CS0(7)
+	       | DRVCTRL8_CS1_A2(7)
+	       | DRVCTRL8_BS(7)
+	       | DRVCTRL8_RD(7)
+	       | DRVCTRL8_RD_W(7)
+	       | DRVCTRL8_WE0(7)
+	       | DRVCTRL8_WE1(7));
+	pfc_reg_write(PFC_DRVCTRL8, reg);
+	reg = mmio_read_32(PFC_DRVCTRL9);
+	reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
+	       | DRVCTRL9_PRESETOU(7)
+	       | DRVCTRL9_D0(7)
+	       | DRVCTRL9_D1(7)
+	       | DRVCTRL9_D2(7)
+	       | DRVCTRL9_D3(7)
+	       | DRVCTRL9_D4(7)
+	       | DRVCTRL9_D5(7));
+	pfc_reg_write(PFC_DRVCTRL9, reg);
+	reg = mmio_read_32(PFC_DRVCTRL10);
+	reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
+	       | DRVCTRL10_D7(7)
+	       | DRVCTRL10_D8(3)
+	       | DRVCTRL10_D9(3)
+	       | DRVCTRL10_D10(3)
+	       | DRVCTRL10_D11(3)
+	       | DRVCTRL10_D12(3)
+	       | DRVCTRL10_D13(3));
+	pfc_reg_write(PFC_DRVCTRL10, reg);
+	reg = mmio_read_32(PFC_DRVCTRL11);
+	reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
+	       | DRVCTRL11_D15(3)
+	       | DRVCTRL11_AVS1(7)
+	       | DRVCTRL11_AVS2(7)
+	       | DRVCTRL11_HDMI0_CEC(7)
+	       | DRVCTRL11_HDMI1_CEC(7)
+	       | DRVCTRL11_DU_DOTCLKIN0(3)
+	       | DRVCTRL11_DU_DOTCLKIN1(3));
+	pfc_reg_write(PFC_DRVCTRL11, reg);
+	reg = mmio_read_32(PFC_DRVCTRL12);
+	reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
+	       | DRVCTRL12_DU_DOTCLKIN3(3)
+	       | DRVCTRL12_DU_FSCLKST(3)
+	       | DRVCTRL12_DU_TMS(3));
+	pfc_reg_write(PFC_DRVCTRL12, reg);
+	reg = mmio_read_32(PFC_DRVCTRL13);
+	reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
+	       | DRVCTRL13_ASEBRK(3)
+	       | DRVCTRL13_SD0_CLK(7)
+	       | DRVCTRL13_SD0_CMD(7)
+	       | DRVCTRL13_SD0_DAT0(7)
+	       | DRVCTRL13_SD0_DAT1(7)
+	       | DRVCTRL13_SD0_DAT2(7)
+	       | DRVCTRL13_SD0_DAT3(7));
+	pfc_reg_write(PFC_DRVCTRL13, reg);
+	reg = mmio_read_32(PFC_DRVCTRL14);
+	reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
+	       | DRVCTRL14_SD1_CMD(7)
+	       | DRVCTRL14_SD1_DAT0(5)
+	       | DRVCTRL14_SD1_DAT1(5)
+	       | DRVCTRL14_SD1_DAT2(5)
+	       | DRVCTRL14_SD1_DAT3(5)
+	       | DRVCTRL14_SD2_CLK(5)
+	       | DRVCTRL14_SD2_CMD(5));
+	pfc_reg_write(PFC_DRVCTRL14, reg);
+	reg = mmio_read_32(PFC_DRVCTRL15);
+	reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
+	       | DRVCTRL15_SD2_DAT1(5)
+	       | DRVCTRL15_SD2_DAT2(5)
+	       | DRVCTRL15_SD2_DAT3(5)
+	       | DRVCTRL15_SD2_DS(5)
+	       | DRVCTRL15_SD3_CLK(7)
+	       | DRVCTRL15_SD3_CMD(7)
+	       | DRVCTRL15_SD3_DAT0(7));
+	pfc_reg_write(PFC_DRVCTRL15, reg);
+	reg = mmio_read_32(PFC_DRVCTRL16);
+	reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
+	       | DRVCTRL16_SD3_DAT2(7)
+	       | DRVCTRL16_SD3_DAT3(7)
+	       | DRVCTRL16_SD3_DAT4(7)
+	       | DRVCTRL16_SD3_DAT5(7)
+	       | DRVCTRL16_SD3_DAT6(7)
+	       | DRVCTRL16_SD3_DAT7(7)
+	       | DRVCTRL16_SD3_DS(7));
+	pfc_reg_write(PFC_DRVCTRL16, reg);
+	reg = mmio_read_32(PFC_DRVCTRL17);
+	reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
+	       | DRVCTRL17_SD0_WP(7)
+	       | DRVCTRL17_SD1_CD(7)
+	       | DRVCTRL17_SD1_WP(7)
+	       | DRVCTRL17_SCK0(7)
+	       | DRVCTRL17_RX0(7)
+	       | DRVCTRL17_TX0(7)
+	       | DRVCTRL17_CTS0(7));
+	pfc_reg_write(PFC_DRVCTRL17, reg);
+	reg = mmio_read_32(PFC_DRVCTRL18);
+	reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
+	       | DRVCTRL18_RX1(7)
+	       | DRVCTRL18_TX1(7)
+	       | DRVCTRL18_CTS1(7)
+	       | DRVCTRL18_RTS1_TANS(7)
+	       | DRVCTRL18_SCK2(7)
+	       | DRVCTRL18_TX2(7)
+	       | DRVCTRL18_RX2(7));
+	pfc_reg_write(PFC_DRVCTRL18, reg);
+	reg = mmio_read_32(PFC_DRVCTRL19);
+	reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
+	       | DRVCTRL19_HRX0(7)
+	       | DRVCTRL19_HTX0(7)
+	       | DRVCTRL19_HCTS0(7)
+	       | DRVCTRL19_HRTS0(7)
+	       | DRVCTRL19_MSIOF0_SCK(7)
+	       | DRVCTRL19_MSIOF0_SYNC(7)
+	       | DRVCTRL19_MSIOF0_SS1(7));
+	pfc_reg_write(PFC_DRVCTRL19, reg);
+	reg = mmio_read_32(PFC_DRVCTRL20);
+	reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
+	       | DRVCTRL20_MSIOF0_SS2(7)
+	       | DRVCTRL20_MSIOF0_RXD(7)
+	       | DRVCTRL20_MLB_CLK(7)
+	       | DRVCTRL20_MLB_SIG(7)
+	       | DRVCTRL20_MLB_DAT(7)
+	       | DRVCTRL20_MLB_REF(7)
+	       | DRVCTRL20_SSI_SCK0129(7));
+	pfc_reg_write(PFC_DRVCTRL20, reg);
+	reg = mmio_read_32(PFC_DRVCTRL21);
+	reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
+	       | DRVCTRL21_SSI_SDATA0(7)
+	       | DRVCTRL21_SSI_SDATA1(7)
+	       | DRVCTRL21_SSI_SDATA2(7)
+	       | DRVCTRL21_SSI_SCK34(7)
+	       | DRVCTRL21_SSI_WS34(7)
+	       | DRVCTRL21_SSI_SDATA3(7)
+	       | DRVCTRL21_SSI_SCK4(7));
+	pfc_reg_write(PFC_DRVCTRL21, reg);
+	reg = mmio_read_32(PFC_DRVCTRL22);
+	reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
+	       | DRVCTRL22_SSI_SDATA4(7)
+	       | DRVCTRL22_SSI_SCK5(7)
+	       | DRVCTRL22_SSI_WS5(7)
+	       | DRVCTRL22_SSI_SDATA5(7)
+	       | DRVCTRL22_SSI_SCK6(7)
+	       | DRVCTRL22_SSI_WS6(7)
+	       | DRVCTRL22_SSI_SDATA6(7));
+	pfc_reg_write(PFC_DRVCTRL22, reg);
+	reg = mmio_read_32(PFC_DRVCTRL23);
+	reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
+	       | DRVCTRL23_SSI_WS78(7)
+	       | DRVCTRL23_SSI_SDATA7(7)
+	       | DRVCTRL23_SSI_SDATA8(7)
+	       | DRVCTRL23_SSI_SDATA9(7)
+	       | DRVCTRL23_AUDIO_CLKA(7)
+	       | DRVCTRL23_AUDIO_CLKB(7)
+	       | DRVCTRL23_USB0_PWEN(7));
+	pfc_reg_write(PFC_DRVCTRL23, reg);
+	reg = mmio_read_32(PFC_DRVCTRL24);
+	reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
+	       | DRVCTRL24_USB1_PWEN(7)
+	       | DRVCTRL24_USB1_OVC(7)
+	       | DRVCTRL24_USB30_PWEN(7)
+	       | DRVCTRL24_USB30_OVC(7)
+	       | DRVCTRL24_USB31_PWEN(7)
+	       | DRVCTRL24_USB31_OVC(7));
+	pfc_reg_write(PFC_DRVCTRL24, reg);
+
+	/* initialize LSI pin pull-up/down control */
+	pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+	pfc_reg_write(PFC_PUD1, 0x00300FFEU);
+	pfc_reg_write(PFC_PUD2, 0x330001E6U);
+	pfc_reg_write(PFC_PUD3, 0x000002E0U);
+	pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+	pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+	pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+	/* initialize LSI pin pull-enable register */
+	pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+	pfc_reg_write(PFC_PUEN1, 0x00100234U);
+	pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+	pfc_reg_write(PFC_PUEN3, 0x00000200U);
+	pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+	pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+	pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+	/* initialize positive/negative logic select */
+	mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+	mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+	/* initialize general IO/interrupt switching */
+	mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+	mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+	/* initialize general output register */
+	mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+	mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+	mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
+	mmio_write_32(GPIO_OUTDT5, 0x00000006U);
+	mmio_write_32(GPIO_OUTDT6, 0x00003880U);
+
+	/* initialize general input/output switching */
+	mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
+	mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
+	mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
+	mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
+	mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
+	mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
+}
diff --git a/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h
new file mode 100644
index 0000000..9e08e58
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_M3N_H__
+#define PFC_INIT_M3N_H__
+
+void pfc_init_m3n(void);
+
+#endif /* PFC_INIT_M3N_H__ */
diff --git a/drivers/staging/renesas/rcar/pfc/pfc.mk b/drivers/staging/renesas/rcar/pfc/pfc.mk
new file mode 100644
index 0000000..40e4090
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/pfc.mk
@@ -0,0 +1,56 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_AUTO})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+
+else ifdef RCAR_LSI_CUT_COMPAT
+  ifeq (${RCAR_LSI},${RCAR_H3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_H3N})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3N})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_E3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
+  endif
+else
+  ifeq (${RCAR_LSI},${RCAR_H3})
+    ifeq (${LSI_CUT},10)
+      BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    else ifeq (${LSI_CUT},11)
+      BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
+    else
+#     LSI_CUT 20 or later
+      BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RCAR_H3N})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3N})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_E3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
+  endif
+endif
+
+BL2_SOURCES += drivers/staging/renesas/rcar/pfc/pfc_init.c
diff --git a/drivers/staging/renesas/rcar/pfc/pfc_init.c b/drivers/staging/renesas/rcar/pfc/pfc_init.c
new file mode 100644
index 0000000..fceff3d
--- /dev/null
+++ b/drivers/staging/renesas/rcar/pfc/pfc_init.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include <mmio.h>
+#include "rcar_def.h"
+#if RCAR_LSI == RCAR_AUTO
+#include "H3/pfc_init_h3_v1.h"
+#include "H3/pfc_init_h3_v2.h"
+#include "M3/pfc_init_m3.h"
+#include "M3N/pfc_init_m3n.h"
+#endif
+#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)	/* H3 */
+#include "H3/pfc_init_h3_v1.h"
+#include "H3/pfc_init_h3_v2.h"
+#endif
+#if RCAR_LSI == RCAR_M3		/* M3 */
+#include "M3/pfc_init_m3.h"
+#endif
+#if RCAR_LSI == RCAR_M3N	/* M3N */
+#include "M3N/pfc_init_m3n.h"
+#endif
+#if RCAR_LSI == RCAR_E3		/* E3 */
+#include "E3/pfc_init_e3.h"
+#endif
+
+ /* Product Register */
+#define PRR			(0xFFF00044U)
+#define PRR_PRODUCT_MASK	(0x00007F00U)
+#define PRR_CUT_MASK		(0x000000FFU)
+#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3 */
+#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3 */
+#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
+#define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3 */
+#define PRR_PRODUCT_10		(0x00U)
+#define PRR_PRODUCT_11		(0x01U)
+#define PRR_PRODUCT_20		(0x10U)
+
+#define PRR_PRODUCT_ERR(reg)	do{\
+				ERROR("LSI Product ID(PRR=0x%x) PFC "\
+				"initialize not supported.\n",reg);\
+				panic();\
+				}while(0)
+#define PRR_CUT_ERR(reg)	do{\
+				ERROR("LSI Cut ID(PRR=0x%x) PFC "\
+				"initialize not supported.\n",reg);\
+				panic();\
+				}while(0)
+
+void rcar_pfc_init(void)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(RCAR_PRR);
+#if RCAR_LSI == RCAR_AUTO
+	switch (reg & RCAR_PRODUCT_MASK) {
+	case RCAR_PRODUCT_H3:
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:	/* H3 Ver.1.0 */
+			pfc_init_h3_v1();
+			break;
+		case PRR_PRODUCT_11:	/* H3 Ver.1.1 */
+			pfc_init_h3_v1();
+			break;
+		default:	/* H3 Ver.2.0 or later */
+			pfc_init_h3_v2();
+			break;
+		}
+		break;
+	case RCAR_PRODUCT_M3:
+		pfc_init_m3();
+		break;
+	case RCAR_PRODUCT_M3N:
+		pfc_init_m3n();
+		break;
+	default:
+		PRR_PRODUCT_ERR(reg);
+		break;
+	}
+
+#elif RCAR_LSI_CUT_COMPAT
+	switch (reg & PRR_PRODUCT_MASK) {
+	case PRR_PRODUCT_H3:
+#if (RCAR_LSI != RCAR_H3) && (RCAR_LSI != RCAR_H3N)
+		PRR_PRODUCT_ERR(reg);
+#else
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:	/* H3 Ver.1.0 */
+			pfc_init_h3_v1();
+			break;
+		case PRR_PRODUCT_11:	/* H3 Ver.1.1 */
+			pfc_init_h3_v1();
+			break;
+		default:	/* H3 Ver.2.0 or later */
+			pfc_init_h3_v2();
+			break;
+		}
+#endif
+		break;
+	case PRR_PRODUCT_M3:
+#if RCAR_LSI != RCAR_M3
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_m3();
+#endif
+		break;
+	case PRR_PRODUCT_M3N:
+#if RCAR_LSI != RCAR_M3N
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_m3n();
+#endif
+		break;
+	case PRR_PRODUCT_E3:
+#if RCAR_LSI != RCAR_E3
+		PRR_PRODUCT_ERR(reg);
+#else
+		pfc_init_e3();
+#endif
+		break;
+	default:
+		PRR_PRODUCT_ERR(reg);
+		break;
+	}
+
+#else
+#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)	/* H3 */
+#if RCAR_LSI_CUT == RCAR_CUT_10
+	/* H3 Ver.1.0 */
+	if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10)
+	    != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_h3_v1();
+#elif RCAR_LSI_CUT == RCAR_CUT_11
+	/* H3 Ver.1.1 */
+	if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11)
+	    != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_h3_v1();
+#else
+	/* H3 Ver.2.0 or later */
+	if (PRR_PRODUCT_H3 != (reg & PRR_PRODUCT_MASK)) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_h3_v2();
+#endif
+#elif RCAR_LSI == RCAR_M3	/* M3 */
+	if ((PRR_PRODUCT_M3) != (reg & PRR_PRODUCT_MASK)) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_m3();
+#elif RCAR_LSI == RCAR_M3N	/* M3N */
+	if ((PRR_PRODUCT_M3N) != (reg & PRR_PRODUCT_MASK)) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_m3n();
+#elif RCAR_LSI == RCAR_E3	/* E3 */
+	if ((PRR_PRODUCT_E3) != (reg & PRR_PRODUCT_MASK)) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_e3();
+#else
+#error "Don't have PFC initialize routine(unknown)."
+#endif
+#endif
+}
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
new file mode 100644
index 0000000..efe0c75
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_e3_v10.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.02"
+
+#define QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
+#define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
+
+#define REF_ARS_ARBSTOPCYCLE_E3	(((SL_INIT_SSLOTCLK_E3) - 5U) << 16U)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_e3_v10_mstat390.h"
+#else
+#include "qos_init_e3_v10_mstat780.h"
+#endif
+
+#endif
+
+static void dbsc_setting(void)
+{
+	/* Register write enable */
+	io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+
+	/* BUFCAM settings */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+	io_write_32(DBSC_DBSCHCNT0, 0x000F0037);
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001);
+	io_write_32(DBSC_DBSCHRW0, 0x22421111);
+
+	/* DDR3 */
+	io_write_32(DBSC_SCFCTST2, 0x012F1123);
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+	io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+	io_write_32(DBSC_DBSCHQOS02, 0x00000000);
+	io_write_32(DBSC_DBSCHQOS03, 0x00000000);
+	io_write_32(DBSC_DBSCHQOS40, 0x00000300);
+	io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+	io_write_32(DBSC_DBSCHQOS42, 0x00000200);
+	io_write_32(DBSC_DBSCHQOS43, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS90, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS93, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS130, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS133, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+	io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+	io_write_32(DBSC_DBSCHQOS142, 0x00000080);
+	io_write_32(DBSC_DBSCHQOS143, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS150, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS151, 0x00000030);
+	io_write_32(DBSC_DBSCHQOS152, 0x00000020);
+	io_write_32(DBSC_DBSCHQOS153, 0x00000010);
+
+	/* Register write protect */
+	io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
+}
+
+void qos_init_e3_v10(void)
+{
+	dbsc_setting();
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_E3
+#error "Don't set DRAM Split 4ch(E3)"
+#else
+	ERROR("DRAM Split 4ch not supported.(E3)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RCAR_E3
+#error "Don't set DRAM Split 2ch(E3)"
+#else
+	ERROR("DRAM Split 2ch not supported.(E3)");
+	panic();
+#endif
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
+#endif
+
+	io_write_32(QOSCTRL_RAS, 0x00000020U);
+	io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+	io_write_32(QOSCTRL_DANT, 0x00100804U);
+	io_write_32(QOSCTRL_FSS, 0x0000000AU);
+	io_write_32(QOSCTRL_INSFC, 0x06330001U);
+	io_write_32(QOSCTRL_EARLYR, 0x00000000U);
+	io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	io_write_32(QOSCTRL_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+		    SL_INIT_SSLOTCLK_E3);
+	io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3);
+
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+		}
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(GPU_ACT_GRD, 0x00001234U);
+	io_write_32(GPU_ACT0, 0x00000000U);
+	io_write_32(GPU_ACT1, 0x00000000U);
+	io_write_32(GPU_ACT2, 0x00000000U);
+	io_write_32(GPU_ACT3, 0x00000000U);
+	io_write_32(GPU_ACT_GRD, 0x00000000U);
+
+	/* RT bus Leaf setting */
+	io_write_32(RT_ACT0, 0x00000000U);
+	io_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	io_write_32(CPU_ACT0, 0x00000003U);
+	io_write_32(CPU_ACT1, 0x00000003U);
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+	io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif
+}
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h
new file mode 100644
index 0000000..ab82e96
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_E3_V10__
+#define QOS_INIT_H_E3_V10__
+
+void qos_init_e3_v10(void);
+
+#endif /* QOS_INIT_H_E3_V10__ */
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
new file mode 100644
index 0000000..cf376a2
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008620000FFFFUL,
+	/* 0x0038, */ 0x001008620000FFFFUL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001415260000FFFFUL,
+	/* 0x0060, */ 0x001415260000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001414930000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08380000FFFFUL,
+	/* 0x00a8, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04110000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08380000FFFFUL,
+	/* 0x00c8, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04110000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001018580000FFFFUL,
+	/* 0x00f8, */ 0x000C04400000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001008580000FFFFUL,
+	/* 0x0118, */ 0x000C19660000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001008530000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00100C960000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x001008530000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0010042A0000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00101D8D0000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x001008530000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04020000FFFFUL,
+	/* 0x01f0, */ 0x000C04090000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04090000FFFFUL,
+	/* 0x0210, */ 0x000C04090000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C2A0000FFFFUL,
+	/* 0x0268, */ 0x001410040000FFFFUL,
+	/* 0x0270, */ 0x001404020000FFFFUL,
+	/* 0x0278, */ 0x000C08110000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFFFUL,
+	/* 0x0298, */ 0x001404020000FFFFUL,
+	/* 0x02a0, */ 0x000C04090000FFFFUL,
+	/* 0x02a8, */ 0x000C04090000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x000C04020000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04090000FFFFUL,
+	/* 0x02d8, */ 0x000C04090000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x000C04020000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04020000FFFFUL,
+	/* 0x0378, */ 0x000C04020000FFFFUL,
+	/* 0x0380, */ 0x000C04090000FFFFUL,
+	/* 0x0388, */ 0x000C04090000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005F03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060005FFFC01UL,
+	/* 0x01c8, */ 0x0021060005FFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021010005F79801UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021010005F79801UL,
+	/* 0x0218, */ 0x0011010005F79801UL,
+	/* 0x0220, */ 0x0011010005F79801UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010005F79801UL,
+	/* 0x0238, */ 0x0011010005F79801UL,
+	/* 0x0240, */ 0x0012010005F79801UL,
+	/* 0x0248, */ 0x0011010005F79801UL,
+	/* 0x0250, */ 0x0012010005F79801UL,
+	/* 0x0258, */ 0x0011010005F79801UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060005FFFC01UL,
+	/* 0x02f8, */ 0x0011060005FFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001005F03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060005FFFC01UL,
+	/* 0x0360, */ 0x0012060005FFFC01UL,
+	/* 0x0368, */ 0x0012001005F03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001005F03401UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
new file mode 100644
index 0000000..002a664
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001010C40000FFFFUL,
+	/* 0x0038, */ 0x001010C40000FFFFUL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00142A4B0000FFFFUL,
+	/* 0x0060, */ 0x00142A4B0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001429260000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C10700000FFFFUL,
+	/* 0x00a8, */ 0x000C08210000FFFFUL,
+	/* 0x00b0, */ 0x000C08210000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C10700000FFFFUL,
+	/* 0x00c8, */ 0x000C08210000FFFFUL,
+	/* 0x00d0, */ 0x000C08210000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x00102CAF0000FFFFUL,
+	/* 0x00f8, */ 0x000C087F0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100CAF0000FFFFUL,
+	/* 0x0118, */ 0x000C32CC0000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100CA50000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010152C0000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x00100CA50000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008530000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001037190000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x00100CA50000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04040000FFFFUL,
+	/* 0x01f0, */ 0x000C08110000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04110000FFFFUL,
+	/* 0x0210, */ 0x000C08110000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C18530000FFFFUL,
+	/* 0x0268, */ 0x00141C070000FFFFUL,
+	/* 0x0270, */ 0x001404040000FFFFUL,
+	/* 0x0278, */ 0x000C0C210000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x00141C070000FFFFUL,
+	/* 0x0298, */ 0x001404040000FFFFUL,
+	/* 0x02a0, */ 0x000C04110000FFFFUL,
+	/* 0x02a8, */ 0x000C04110000FFFFUL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x000C04040000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04110000FFFFUL,
+	/* 0x02d8, */ 0x000C04110000FFFFUL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x000C04040000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04040000FFFFUL,
+	/* 0x0378, */ 0x000C04040000FFFFUL,
+	/* 0x0380, */ 0x000C04110000FFFFUL,
+	/* 0x0388, */ 0x000C04110000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001002F03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060002FFFC01UL,
+	/* 0x01c8, */ 0x0021060002FFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021010002F3CC01UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021010002F3CC01UL,
+	/* 0x0218, */ 0x0011010002F3CC01UL,
+	/* 0x0220, */ 0x0011010002F3CC01UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010002F3CC01UL,
+	/* 0x0238, */ 0x0011010002F3CC01UL,
+	/* 0x0240, */ 0x0012010002F3CC01UL,
+	/* 0x0248, */ 0x0011010002F3CC01UL,
+	/* 0x0250, */ 0x0012010002F3CC01UL,
+	/* 0x0258, */ 0x0011010002F3CC01UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060002FFFC01UL,
+	/* 0x02f8, */ 0x0011060002FFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001002F03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060002FFFC01UL,
+	/* 0x0360, */ 0x0012060002FFFC01UL,
+	/* 0x0368, */ 0x0012001002F03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001002F03401UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
new file mode 100644
index 0000000..fd81187
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "qos_init_h3_v10.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.36"
+
+#define	RCAR_QOS_NONE			(3U)
+#define	RCAR_QOS_TYPE_DEFAULT		(0U)
+
+#define	RCAR_DRAM_SPLIT_LINEAR		(0U)
+#define	RCAR_DRAM_SPLIT_4CH		(1U)
+#define	RCAR_DRAM_SPLIT_2CH		(2U)
+#define	RCAR_DRAM_SPLIT_AUTO		(3U)
+
+#define	AXI_BASE			(0xE6784000U)
+#define	AXI_ADSPLCR0			(AXI_BASE + 0x0008U)
+#define	AXI_ADSPLCR1			(AXI_BASE + 0x000CU)
+#define	AXI_ADSPLCR2			(AXI_BASE + 0x0010U)
+#define	AXI_ADSPLCR3			(AXI_BASE + 0x0014U)
+#define	ADSPLCR0_ADRMODE_DEFAULT	((uint32_t)0U << 31U)
+#define	ADSPLCR0_ADRMODE_GEN2		((uint32_t)1U << 31U)
+#define	ADSPLCR0_SPLITSEL(x)		((uint32_t)(x) << 16U)
+#define	ADSPLCR0_AREA(x)		((uint32_t)(x) <<  8U)
+#define	ADSPLCR0_SWP			(0x0CU)
+
+#define	MSTAT_BASE			(0xE67E0000U)
+#define	MSTAT_FIX_QOS_BANK0		(MSTAT_BASE + 0x0000U)
+#define	MSTAT_FIX_QOS_BANK1		(MSTAT_BASE + 0x1000U)
+#define	MSTAT_BE_QOS_BANK0		(MSTAT_BASE + 0x2000U)
+#define	MSTAT_BE_QOS_BANK1		(MSTAT_BASE + 0x3000U)
+#define	MSTAT_SL_INIT			(MSTAT_BASE + 0x8000U)
+#define	MSTAT_REF_ARS			(MSTAT_BASE + 0x8004U)
+#define	MSTAT_STATQC			(MSTAT_BASE + 0x8008U)
+
+#define	RALLOC_BASE			(0xE67F0000U)
+#define	RALLOC_RAS			(RALLOC_BASE + 0x0000U)
+#define	RALLOC_FIXTH			(RALLOC_BASE + 0x0004U)
+#define	RALLOC_RAEN			(RALLOC_BASE + 0x0018U)
+#define	RALLOC_REGGD			(RALLOC_BASE + 0x0020U)
+#define	RALLOC_DANN			(RALLOC_BASE + 0x0030U)
+#define	RALLOC_DANT			(RALLOC_BASE + 0x0038U)
+#define	RALLOC_EC			(RALLOC_BASE + 0x003CU)
+#define	RALLOC_EMS			(RALLOC_BASE + 0x0040U)
+#define	RALLOC_INSFC			(RALLOC_BASE + 0x0050U)
+#define	RALLOC_BERR			(RALLOC_BASE + 0x0054U)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+static const mstat_slot_t mstat_fix[] = {
+	{0x0000U, 0x0000000000000000UL},
+	{0x0008U, 0x0000000000000000UL},
+	{0x0010U, 0x0000000000000000UL},
+	{0x0018U, 0x0000000000000000UL},
+	{0x0020U, 0x0000000000000000UL},
+	{0x0028U, 0x0000000000000000UL},
+	{0x0030U, 0x0000000000000000UL},
+	{0x0038U, 0x0000000000000000UL},
+	{0x0040U, 0x00140C050000FFFFUL},
+	{0x0048U, 0x0000000000000000UL},
+	{0x0050U, 0x0000000000000000UL},
+	{0x0058U, 0x001404030000FFFFUL},
+	{0x0060U, 0x001408060000FFFFUL},
+	{0x0068U, 0x0000000000000000UL},
+	{0x0070U, 0x0000000000000000UL},
+	{0x0078U, 0x0000000000000000UL},
+	{0x0080U, 0x0000000000000000UL},
+	{0x0088U, 0x00140C050000FFFFUL},
+	{0x0090U, 0x001408060000FFFFUL},
+	{0x0098U, 0x001404020000FFFFUL},
+	{0x00A0U, 0x0000000000000000UL},
+	{0x00A8U, 0x0000000000000000UL},
+	{0x00B0U, 0x0000000000000000UL},
+	{0x00B8U, 0x0000000000000000UL},
+	{0x00C0U, 0x0000000000000000UL},
+	{0x00C8U, 0x0000000000000000UL},
+	{0x00D0U, 0x0000000000000000UL},
+	{0x00D8U, 0x0000000000000000UL},
+	{0x00E0U, 0x0000000000000000UL},
+	{0x00E8U, 0x0000000000000000UL},
+	{0x00F0U, 0x0000000000000000UL},
+	{0x00F8U, 0x0000000000000000UL},
+	{0x0100U, 0x0000000000000000UL},
+	{0x0108U, 0x0000000000000000UL},
+	{0x0110U, 0x0000000000000000UL},
+	{0x0118U, 0x0000000000000000UL},
+	{0x0120U, 0x0000000000000000UL},
+	{0x0128U, 0x0000000000000000UL},
+	{0x0130U, 0x0000000000000000UL},
+	{0x0138U, 0x001004020000FFFFUL},
+	{0x0140U, 0x001004020000FFFFUL},
+	{0x0148U, 0x001004020000FFFFUL},
+	{0x0150U, 0x001008050000FFFFUL},
+	{0x0158U, 0x001008050000FFFFUL},
+	{0x0160U, 0x001008050000FFFFUL},
+	{0x0168U, 0x001008050000FFFFUL},
+	{0x0170U, 0x001008050000FFFFUL},
+	{0x0178U, 0x001004030000FFFFUL},
+	{0x0180U, 0x001004030000FFFFUL},
+	{0x0188U, 0x001004030000FFFFUL},
+	{0x0190U, 0x001014140000FFFFUL},
+	{0x0198U, 0x001014140000FFFFUL},
+	{0x01A0U, 0x001008060000FFFFUL},
+	{0x01A8U, 0x001008060000FFFFUL},
+	{0x01B0U, 0x001008060000FFFFUL},
+	{0x01B8U, 0x0000000000000000UL},
+	{0x01C0U, 0x0000000000000000UL},
+	{0x01C8U, 0x0000000000000000UL},
+	{0x01D0U, 0x0000000000000000UL},
+	{0x01D8U, 0x0000000000000000UL},
+	{0x01E0U, 0x0000000000000000UL},
+	{0x01E8U, 0x0000000000000000UL},
+	{0x01F0U, 0x0000000000000000UL},
+	{0x01F8U, 0x0000000000000000UL},
+	{0x0200U, 0x0000000000000000UL},
+	{0x0208U, 0x0000000000000000UL},
+	{0x0210U, 0x0000000000000000UL},
+	{0x0218U, 0x0000000000000000UL},
+	{0x0220U, 0x0000000000000000UL},
+	{0x0228U, 0x0000000000000000UL},
+	{0x0230U, 0x0000000000000000UL},
+	{0x0238U, 0x0000000000000000UL},
+	{0x0240U, 0x0000000000000000UL},
+	{0x0248U, 0x0000000000000000UL},
+	{0x0250U, 0x0000000000000000UL},
+	{0x0258U, 0x0000000000000000UL},
+	{0x0260U, 0x0000000000000000UL},
+	{0x0268U, 0x0000000000000000UL},
+	{0x0270U, 0x0000000000000000UL},
+	{0x0278U, 0x0000000000000000UL},
+	{0x0280U, 0x0000000000000000UL},
+	{0x0288U, 0x0000000000000000UL},
+	{0x0290U, 0x0000000000000000UL},
+	{0x0298U, 0x0000000000000000UL},
+	{0x02A0U, 0x0000000000000000UL},
+	{0x02A8U, 0x0000000000000000UL},
+	{0x02B0U, 0x0000000000000000UL},
+	{0x02B8U, 0x0000000000000000UL},
+	{0x02C0U, 0x0000000000000000UL},
+	{0x02C8U, 0x0000000000000000UL},
+	{0x02D0U, 0x0000000000000000UL},
+	{0x02D8U, 0x0000000000000000UL},
+	{0x02E0U, 0x0000000000000000UL},
+	{0x02E8U, 0x0000000000000000UL},
+	{0x02F0U, 0x0000000000000000UL},
+	{0x02F8U, 0x0000000000000000UL},
+	{0x0300U, 0x0000000000000000UL},
+	{0x0308U, 0x0000000000000000UL},
+	{0x0310U, 0x0000000000000000UL},
+	{0x0318U, 0x0000000000000000UL},
+	{0x0320U, 0x0000000000000000UL},
+	{0x0328U, 0x0000000000000000UL},
+	{0x0330U, 0x0000000000000000UL},
+	{0x0338U, 0x0000000000000000UL},
+};
+
+static const mstat_slot_t mstat_be[] = {
+	{0x0000U, 0x001000100C8FFC01UL},
+	{0x0008U, 0x001000100C8FFC01UL},
+	{0x0010U, 0x001000100C8FFC01UL},
+	{0x0018U, 0x001000100C8FFC01UL},
+	{0x0020U, 0x001000100C8FFC01UL},
+	{0x0028U, 0x001000100C8FFC01UL},
+	{0x0030U, 0x001000100C8FFC01UL},
+	{0x0038U, 0x001000100C8FFC01UL},
+	{0x0040U, 0x0000000000000000UL},
+	{0x0048U, 0x0000000000000000UL},
+	{0x0050U, 0x001000100C8FFC01UL},
+	{0x0058U, 0x0000000000000000UL},
+	{0x0060U, 0x0000000000000000UL},
+	{0x0068U, 0x001000100C8FFC01UL},
+	{0x0070U, 0x001000100C8FFC01UL},
+	{0x0078U, 0x001000100C8FFC01UL},
+	{0x0080U, 0x001000100C8FFC01UL},
+	{0x0088U, 0x0000000000000000UL},
+	{0x0090U, 0x0000000000000000UL},
+	{0x0098U, 0x0000000000000000UL},
+	{0x00A0U, 0x001000100C8FFC01UL},
+	{0x00A8U, 0x001000100C8FFC01UL},
+	{0x00B0U, 0x001000100C8FFC01UL},
+	{0x00B8U, 0x001000100C8FFC01UL},
+	{0x00C0U, 0x001000100C8FFC01UL},
+	{0x00C8U, 0x001000100C8FFC01UL},
+	{0x00D0U, 0x001000100C8FFC01UL},
+	{0x00D8U, 0x002000200C8FFC01UL},
+	{0x00E0U, 0x002000200C8FFC01UL},
+	{0x00E8U, 0x001000100C8FFC01UL},
+	{0x00F0U, 0x001000100C8FFC01UL},
+	{0x00F8U, 0x001000100C8FFC01UL},
+	{0x0100U, 0x0000000000000000UL},
+	{0x0108U, 0x002000200C8FFC01UL},
+	{0x0110U, 0x001000100C8FFC01UL},
+	{0x0118U, 0x001000100C8FFC01UL},
+	{0x0120U, 0x0000000000000000UL},
+	{0x0128U, 0x002000200C8FFC01UL},
+	{0x0130U, 0x001000100C8FFC01UL},
+	{0x0138U, 0x0000000000000000UL},
+	{0x0140U, 0x0000000000000000UL},
+	{0x0148U, 0x0000000000000000UL},
+	{0x0150U, 0x0000000000000000UL},
+	{0x0158U, 0x0000000000000000UL},
+	{0x0160U, 0x0000000000000000UL},
+	{0x0168U, 0x0000000000000000UL},
+	{0x0170U, 0x0000000000000000UL},
+	{0x0178U, 0x0000000000000000UL},
+	{0x0180U, 0x0000000000000000UL},
+	{0x0188U, 0x0000000000000000UL},
+	{0x0190U, 0x0000000000000000UL},
+	{0x0198U, 0x0000000000000000UL},
+	{0x01A0U, 0x0000000000000000UL},
+	{0x01A8U, 0x0000000000000000UL},
+	{0x01B0U, 0x0000000000000000UL},
+	{0x01B8U, 0x001000100C8FFC01UL},
+	{0x01C0U, 0x001000200C8FFC01UL},
+	{0x01C8U, 0x001000200C8FFC01UL},
+	{0x01D0U, 0x001000200C8FFC01UL},
+	{0x01D8U, 0x001000200C8FFC01UL},
+	{0x01E0U, 0x001000100C8FFC01UL},
+	{0x01E8U, 0x001000100C8FFC01UL},
+	{0x01F0U, 0x001000100C8FFC01UL},
+	{0x01F8U, 0x001000100C8FFC01UL},
+	{0x0200U, 0x001000100C8FFC01UL},
+	{0x0208U, 0x001000100C8FFC01UL},
+	{0x0210U, 0x001000100C8FFC01UL},
+	{0x0218U, 0x001000100C8FFC01UL},
+	{0x0220U, 0x001000100C8FFC01UL},
+	{0x0228U, 0x001000100C8FFC01UL},
+	{0x0230U, 0x001000100C8FFC01UL},
+	{0x0238U, 0x001000100C8FFC01UL},
+	{0x0240U, 0x001000100C8FFC01UL},
+	{0x0248U, 0x001000100C8FFC01UL},
+	{0x0250U, 0x001000100C8FFC01UL},
+	{0x0258U, 0x001000100C8FFC01UL},
+	{0x0260U, 0x001000100C8FFC01UL},
+	{0x0268U, 0x001000100C8FFC01UL},
+	{0x0270U, 0x001000100C8FFC01UL},
+	{0x0278U, 0x001000100C8FFC01UL},
+	{0x0280U, 0x001000100C8FFC01UL},
+	{0x0288U, 0x001000100C8FFC01UL},
+	{0x0290U, 0x001000100C8FFC01UL},
+	{0x0298U, 0x001000100C8FFC01UL},
+	{0x02A0U, 0x001000100C8FFC01UL},
+	{0x02A8U, 0x001000100C8FFC01UL},
+	{0x02B0U, 0x001000100C8FFC01UL},
+	{0x02B8U, 0x001000100C8FFC01UL},
+	{0x02C0U, 0x001000100C8FFC01UL},
+	{0x02C8U, 0x001000100C8FFC01UL},
+	{0x02D0U, 0x001000100C8FFC01UL},
+	{0x02D8U, 0x001000100C8FFC01UL},
+	{0x02E0U, 0x001000100C8FFC01UL},
+	{0x02E8U, 0x001000100C8FFC01UL},
+	{0x02F0U, 0x001000200C8FFC01UL},
+	{0x02F8U, 0x001000300C8FFC01UL},
+	{0x0300U, 0x0000000000000000UL},
+	{0x0308U, 0x001000200C8FFC01UL},
+	{0x0310U, 0x001000300C8FFC01UL},
+	{0x0318U, 0x0000000000000000UL},
+	{0x0320U, 0x001000200C8FFC01UL},
+	{0x0328U, 0x001000300C8FFC01UL},
+	{0x0330U, 0x001000200C8FFC01UL},
+	{0x0338U, 0x001000300C8FFC01UL},
+};
+#endif
+
+void qos_init_h3_v10(void)
+{
+	/* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+    (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 4ch\n");
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1BU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR1, 0x00000000U);
+	io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+	NOTICE("BL2: DRAM Split is 2ch\n");
+	io_write_32(AXI_ADSPLCR0, 0x00000000U);
+	io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1BU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR2, 0x00000000U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+	/* AR Cache setting */
+	io_write_32(0xE67D1000U, 0x00000100U);
+	io_write_32(0xE67D1008U, 0x00000100U);
+
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_RAS, 0x00000040U);
+	io_write_32(RALLOC_FIXTH, 0x000F0005U);
+	io_write_32(RALLOC_REGGD, 0x00000004U);
+	io_write_64(RALLOC_DANN, 0x0202000004040404UL);
+	io_write_32(RALLOC_DANT, 0x003C1110U);
+	io_write_32(RALLOC_EC, 0x00080001U);	/* need for H3 v1.* */
+	io_write_64(RALLOC_EMS, 0x0000000000000000UL);
+	io_write_32(RALLOC_INSFC, 0xC7840001U);
+	io_write_32(RALLOC_BERR, 0x00000000U);
+
+	/* MSTAT setting */
+	io_write_32(MSTAT_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
+	io_write_32(MSTAT_REF_ARS, 0x00330000U);
+
+	/* MSTAT SRAM setting */
+	for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+		io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
+			mstat_fix[i].value);
+		io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
+			mstat_fix[i].value);
+	}
+	for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+		io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
+			mstat_be[i].value);
+		io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
+			mstat_be[i].value);
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(0xFD820808U, 0x00001234U);
+	io_write_32(0xFD820800U, 0x0000003FU);
+	io_write_32(0xFD821800U, 0x0000003FU);
+	io_write_32(0xFD822800U, 0x0000003FU);
+	io_write_32(0xFD823800U, 0x0000003FU);
+	io_write_32(0xFD824800U, 0x0000003FU);
+	io_write_32(0xFD825800U, 0x0000003FU);
+	io_write_32(0xFD826800U, 0x0000003FU);
+	io_write_32(0xFD827800U, 0x0000003FU);
+
+	/* Resource Alloc start */
+	io_write_32(RALLOC_RAEN, 0x00000001U);
+
+	/* MSTAT start */
+	io_write_32(MSTAT_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_EC, 0x00080001U);	/* need for H3 v1.* */
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h
new file mode 100644
index 0000000..e55f774
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_H3_V10__
+#define QOS_INIT_H_H3_V10__
+
+void qos_init_h3_v10(void);
+
+#endif /* QOS_INIT_H_H3_V10__ */
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
new file mode 100644
index 0000000..1f65600
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
@@ -0,0 +1,607 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include <rcar_def.h>
+#include "../qos_common.h"
+#include "qos_init_h3_v11.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.37"
+
+#define	RCAR_QOS_NONE			(3U)
+#define	RCAR_QOS_TYPE_DEFAULT		(0U)
+
+#define	RCAR_DRAM_SPLIT_LINEAR		(0U)
+#define	RCAR_DRAM_SPLIT_4CH		(1U)
+#define	RCAR_DRAM_SPLIT_2CH		(2U)
+#define	RCAR_DRAM_SPLIT_AUTO		(3U)
+
+#define	RST_BASE			(0xE6160000U)
+#define	RST_MODEMR			(RST_BASE + 0x0060U)
+
+#define	RCAR_PWRSR8			(0xE6180340U)	/* A3VP_PWRSR0 */
+#define	RCAR_PWRONCR8			(0xE618034CU)	/* A3VP_PWRONCR */
+#define	RCAR_PWRSR9			(0xE6180380U)	/* A3VC_PWRSR0 */
+#define	RCAR_PWRONCR9			(0xE618038CU)	/* A3VC_PWRONCR */
+#define	RCAR_PWRSR10			(0xE61803C0U)	/* A2VC_PWRSR0 */
+#define	RCAR_PWRONCR10			(0xE61803CCU)	/* A2VC_PWRONCR */
+
+#define	DBSC_BASE			(0xE6790000U)
+#define DBSC_DBCAM0CNF0			(DBSC_BASE + 0x0900U)
+#define DBSC_DBCAM0CNF1			(DBSC_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2			(DBSC_BASE + 0x0908U)
+#define DBSC_DBCAM0CNF3			(DBSC_BASE + 0x090CU)
+#define DBSC_DBCAMDIS			(DBSC_BASE + 0x09fCU)
+#define DBSC_DBSCHCNT0			(DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHCNT1			(DBSC_BASE + 0x1004U)
+#define DBSC_DBSCHSZ0			(DBSC_BASE + 0x1010U)
+#define DBSC_DBSCHRW0			(DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHQOS_0_0		(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS_0_1		(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS_0_2		(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS_0_3		(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS_1_0		(DBSC_BASE + 0x1040U)
+#define DBSC_DBSCHQOS_1_1		(DBSC_BASE + 0x1044U)
+#define DBSC_DBSCHQOS_1_2		(DBSC_BASE + 0x1048U)
+#define DBSC_DBSCHQOS_1_3		(DBSC_BASE + 0x104CU)
+#define DBSC_DBSCHQOS_2_0		(DBSC_BASE + 0x1050U)
+#define DBSC_DBSCHQOS_2_1		(DBSC_BASE + 0x1054U)
+#define DBSC_DBSCHQOS_2_2		(DBSC_BASE + 0x1058U)
+#define DBSC_DBSCHQOS_2_3		(DBSC_BASE + 0x105CU)
+#define DBSC_DBSCHQOS_3_0		(DBSC_BASE + 0x1060U)
+#define DBSC_DBSCHQOS_3_1		(DBSC_BASE + 0x1064U)
+#define DBSC_DBSCHQOS_3_2		(DBSC_BASE + 0x1068U)
+#define DBSC_DBSCHQOS_3_3		(DBSC_BASE + 0x106CU)
+#define DBSC_DBSCHQOS_4_0		(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS_4_1		(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS_4_2		(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS_4_3		(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS_5_0		(DBSC_BASE + 0x1080U)
+#define DBSC_DBSCHQOS_5_1		(DBSC_BASE + 0x1084U)
+#define DBSC_DBSCHQOS_5_2		(DBSC_BASE + 0x1088U)
+#define DBSC_DBSCHQOS_5_3		(DBSC_BASE + 0x108CU)
+#define DBSC_DBSCHQOS_6_0		(DBSC_BASE + 0x1090U)
+#define DBSC_DBSCHQOS_6_1		(DBSC_BASE + 0x1094U)
+#define DBSC_DBSCHQOS_6_2		(DBSC_BASE + 0x1098U)
+#define DBSC_DBSCHQOS_6_3		(DBSC_BASE + 0x109CU)
+#define DBSC_DBSCHQOS_7_0		(DBSC_BASE + 0x10A0U)
+#define DBSC_DBSCHQOS_7_1		(DBSC_BASE + 0x10A4U)
+#define DBSC_DBSCHQOS_7_2		(DBSC_BASE + 0x10A8U)
+#define DBSC_DBSCHQOS_7_3		(DBSC_BASE + 0x10ACU)
+#define DBSC_DBSCHQOS_8_0		(DBSC_BASE + 0x10B0U)
+#define DBSC_DBSCHQOS_8_1		(DBSC_BASE + 0x10B4U)
+#define DBSC_DBSCHQOS_8_2		(DBSC_BASE + 0x10B8U)
+#define DBSC_DBSCHQOS_8_3		(DBSC_BASE + 0x10BCU)
+#define DBSC_DBSCHQOS_9_0		(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS_9_1		(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS_9_2		(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS_9_3		(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS_10_0		(DBSC_BASE + 0x10D0U)
+#define DBSC_DBSCHQOS_10_1		(DBSC_BASE + 0x10D4U)
+#define DBSC_DBSCHQOS_10_2		(DBSC_BASE + 0x10D8U)
+#define DBSC_DBSCHQOS_10_3		(DBSC_BASE + 0x10DCU)
+#define DBSC_DBSCHQOS_11_0		(DBSC_BASE + 0x10E0U)
+#define DBSC_DBSCHQOS_11_1		(DBSC_BASE + 0x10E4U)
+#define DBSC_DBSCHQOS_11_2		(DBSC_BASE + 0x10E8U)
+#define DBSC_DBSCHQOS_11_3		(DBSC_BASE + 0x10ECU)
+#define DBSC_DBSCHQOS_12_0		(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS_12_1		(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS_12_2		(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS_12_3		(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS_13_0		(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS_13_1		(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS_13_2		(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS_13_3		(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS_14_0		(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS_14_1		(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS_14_2		(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS_14_3		(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS_15_0		(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS_15_1		(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS_15_2		(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS_15_3		(DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST2			(DBSC_BASE + 0x170CU)
+
+#define	AXI_BASE			(0xE6784000U)
+#define	AXI_ADSPLCR0			(AXI_BASE + 0x0008U)
+#define	AXI_ADSPLCR1			(AXI_BASE + 0x000CU)
+#define	AXI_ADSPLCR2			(AXI_BASE + 0x0010U)
+#define	AXI_ADSPLCR3			(AXI_BASE + 0x0014U)
+#define	ADSPLCR0_ADRMODE_DEFAULT	((uint32_t)0U << 31U)
+#define	ADSPLCR0_ADRMODE_GEN2		((uint32_t)1U << 31U)
+#define	ADSPLCR0_SPLITSEL(x)		((uint32_t)(x) << 16U)
+#define	ADSPLCR0_AREA(x)		((uint32_t)(x) <<  8U)
+#define	ADSPLCR0_SWP			(0x0CU)
+
+#define	MSTAT_BASE			(0xE67E0000U)
+#define	MSTAT_FIX_QOS_BANK0		(MSTAT_BASE + 0x0000U)
+#define	MSTAT_FIX_QOS_BANK1		(MSTAT_BASE + 0x1000U)
+#define	MSTAT_BE_QOS_BANK0		(MSTAT_BASE + 0x2000U)
+#define	MSTAT_BE_QOS_BANK1		(MSTAT_BASE + 0x3000U)
+#define	MSTAT_SL_INIT			(MSTAT_BASE + 0x8000U)
+#define	MSTAT_REF_ARS			(MSTAT_BASE + 0x8004U)
+#define	MSTAT_STATQC			(MSTAT_BASE + 0x8008U)
+
+#define	RALLOC_BASE			(0xE67F0000U)
+#define	RALLOC_RAS			(RALLOC_BASE + 0x0000U)
+#define	RALLOC_FIXTH			(RALLOC_BASE + 0x0004U)
+#define	RALLOC_RAEN			(RALLOC_BASE + 0x0018U)
+#define	RALLOC_REGGD			(RALLOC_BASE + 0x0020U)
+#define	RALLOC_DANN			(RALLOC_BASE + 0x0030U)
+#define	RALLOC_DANT			(RALLOC_BASE + 0x0038U)
+#define	RALLOC_EC			(RALLOC_BASE + 0x003CU)
+#define	RALLOC_EMS			(RALLOC_BASE + 0x0040U)
+#define	RALLOC_INSFC			(RALLOC_BASE + 0x0050U)
+#define	RALLOC_BERR			(RALLOC_BASE + 0x0054U)
+#define	RALLOC_RACNT0			(RALLOC_BASE + 0x0080U)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+static const mstat_slot_t mstat_fix[] = {
+	{0x0000U, 0x0000000000000000UL},
+	{0x0008U, 0x0000000000000000UL},
+	{0x0010U, 0x0000000000000000UL},
+	{0x0018U, 0x0000000000000000UL},
+	{0x0020U, 0x0000000000000000UL},
+	{0x0028U, 0x0000000000000000UL},
+	{0x0030U, 0x001004030000FFFFUL},
+	{0x0038U, 0x001008060000FFFFUL},
+	{0x0040U, 0x001414090000FFFFUL},
+	{0x0048U, 0x0000000000000000UL},
+	{0x0050U, 0x001410010000FFFFUL},
+	{0x0058U, 0x00140C0C0000FFFFUL},
+	{0x0060U, 0x00140C0C0000FFFFUL},
+	{0x0068U, 0x0000000000000000UL},
+	{0x0070U, 0x001410010000FFFFUL},
+	{0x0078U, 0x001008060000FFFFUL},
+	{0x0080U, 0x001004020000FFFFUL},
+	{0x0088U, 0x001414090000FFFFUL},
+	{0x0090U, 0x00140C0C0000FFFFUL},
+	{0x0098U, 0x001408080000FFFFUL},
+	{0x00A0U, 0x000C08020000FFFFUL},
+	{0x00A8U, 0x000C04010000FFFFUL},
+	{0x00B0U, 0x000C04010000FFFFUL},
+	{0x00B8U, 0x0000000000000000UL},
+	{0x00C0U, 0x000C08020000FFFFUL},
+	{0x00C8U, 0x000C04010000FFFFUL},
+	{0x00D0U, 0x000C04010000FFFFUL},
+	{0x00D8U, 0x000C04030000FFFFUL},
+	{0x00E0U, 0x000C100F0000FFFFUL},
+	{0x00E8U, 0x0000000000000000UL},
+	{0x00F0U, 0x001010080000FFFFUL},
+	{0x00F8U, 0x001010080000FFFFUL},
+	{0x0100U, 0x0000000000000000UL},
+	{0x0108U, 0x000C04030000FFFFUL},
+	{0x0110U, 0x001010080000FFFFUL},
+	{0x0118U, 0x001010080000FFFFUL},
+	{0x0120U, 0x0000000000000000UL},
+	{0x0128U, 0x000C100E0000FFFFUL},
+	{0x0130U, 0x0000000000000000UL},
+	{0x0138U, 0x001008050000FFFFUL},
+	{0x0140U, 0x001008050000FFFFUL},
+	{0x0148U, 0x001008050000FFFFUL},
+	{0x0150U, 0x001008050000FFFFUL},
+	{0x0158U, 0x001008050000FFFFUL},
+	{0x0160U, 0x001008050000FFFFUL},
+	{0x0168U, 0x001008050000FFFFUL},
+	{0x0170U, 0x001008050000FFFFUL},
+	{0x0178U, 0x001004030000FFFFUL},
+	{0x0180U, 0x001004030000FFFFUL},
+	{0x0188U, 0x001004030000FFFFUL},
+	{0x0190U, 0x001014140000FFFFUL},
+	{0x0198U, 0x001014140000FFFFUL},
+	{0x01A0U, 0x001008050000FFFFUL},
+	{0x01A8U, 0x001008050000FFFFUL},
+	{0x01B0U, 0x001008050000FFFFUL},
+	{0x01B8U, 0x0000000000000000UL},
+	{0x01C0U, 0x0000000000000000UL},
+	{0x01C8U, 0x0000000000000000UL},
+	{0x01D0U, 0x0000000000000000UL},
+	{0x01D8U, 0x0000000000000000UL},
+	{0x01E0U, 0x0000000000000000UL},
+	{0x01E8U, 0x0000000000000000UL},
+	{0x01F0U, 0x0000000000000000UL},
+	{0x01F8U, 0x0000000000000000UL},
+	{0x0200U, 0x0000000000000000UL},
+	{0x0208U, 0x0000000000000000UL},
+	{0x0210U, 0x0000000000000000UL},
+	{0x0218U, 0x0000000000000000UL},
+	{0x0220U, 0x0000000000000000UL},
+	{0x0228U, 0x0000000000000000UL},
+	{0x0230U, 0x0000000000000000UL},
+	{0x0238U, 0x0000000000000000UL},
+	{0x0240U, 0x0000000000000000UL},
+	{0x0248U, 0x0000000000000000UL},
+	{0x0250U, 0x0000000000000000UL},
+	{0x0258U, 0x0000000000000000UL},
+	{0x0260U, 0x0000000000000000UL},
+	{0x0268U, 0x001408010000FFFFUL},
+	{0x0270U, 0x001404010000FFFFUL},
+	{0x0278U, 0x0000000000000000UL},
+	{0x0280U, 0x0000000000000000UL},
+	{0x0288U, 0x0000000000000000UL},
+	{0x0290U, 0x001408010000FFFFUL},
+	{0x0298U, 0x001404010000FFFFUL},
+	{0x02A0U, 0x000C04010000FFFFUL},
+	{0x02A8U, 0x000C04010000FFFFUL},
+	{0x02B0U, 0x001404010000FFFFUL},
+	{0x02B8U, 0x0000000000000000UL},
+	{0x02C0U, 0x0000000000000000UL},
+	{0x02C8U, 0x0000000000000000UL},
+	{0x02D0U, 0x000C04010000FFFFUL},
+	{0x02D8U, 0x000C04010000FFFFUL},
+	{0x02E0U, 0x001404010000FFFFUL},
+	{0x02E8U, 0x0000000000000000UL},
+	{0x02F0U, 0x0000000000000000UL},
+	{0x02F8U, 0x0000000000000000UL},
+	{0x0300U, 0x0000000000000000UL},
+	{0x0308U, 0x0000000000000000UL},
+	{0x0310U, 0x0000000000000000UL},
+	{0x0318U, 0x0000000000000000UL},
+	{0x0320U, 0x0000000000000000UL},
+	{0x0328U, 0x0000000000000000UL},
+	{0x0330U, 0x0000000000000000UL},
+	{0x0338U, 0x0000000000000000UL},
+};
+
+static const mstat_slot_t mstat_be[] = {
+	{0x0000U, 0x001200100C89C401UL},
+	{0x0008U, 0x001200100C89C401UL},
+	{0x0010U, 0x001200100C89C401UL},
+	{0x0018U, 0x001200100C89C401UL},
+	{0x0020U, 0x001100100C803401UL},
+	{0x0028U, 0x001100100C80FC01UL},
+	{0x0030U, 0x0000000000000000UL},
+	{0x0038U, 0x0000000000000000UL},
+	{0x0040U, 0x0000000000000000UL},
+	{0x0048U, 0x0000000000000000UL},
+	{0x0050U, 0x0000000000000000UL},
+	{0x0058U, 0x0000000000000000UL},
+	{0x0060U, 0x0000000000000000UL},
+	{0x0068U, 0x001100100C803401UL},
+	{0x0070U, 0x0000000000000000UL},
+	{0x0078U, 0x0000000000000000UL},
+	{0x0080U, 0x0000000000000000UL},
+	{0x0088U, 0x0000000000000000UL},
+	{0x0090U, 0x0000000000000000UL},
+	{0x0098U, 0x0000000000000000UL},
+	{0x00A0U, 0x0000000000000000UL},
+	{0x00A8U, 0x0000000000000000UL},
+	{0x00B0U, 0x0000000000000000UL},
+	{0x00B8U, 0x001100100C803401UL},
+	{0x00C0U, 0x0000000000000000UL},
+	{0x00C8U, 0x0000000000000000UL},
+	{0x00D0U, 0x0000000000000000UL},
+	{0x00D8U, 0x0000000000000000UL},
+	{0x00E0U, 0x0000000000000000UL},
+	{0x00E8U, 0x001100100C803401UL},
+	{0x00F0U, 0x0000000000000000UL},
+	{0x00F8U, 0x0000000000000000UL},
+	{0x0100U, 0x0000000000000000UL},
+	{0x0108U, 0x0000000000000000UL},
+	{0x0110U, 0x0000000000000000UL},
+	{0x0118U, 0x0000000000000000UL},
+	{0x0120U, 0x0000000000000000UL},
+	{0x0128U, 0x0000000000000000UL},
+	{0x0130U, 0x001100100C803401UL},
+	{0x0138U, 0x0000000000000000UL},
+	{0x0140U, 0x0000000000000000UL},
+	{0x0148U, 0x0000000000000000UL},
+	{0x0150U, 0x0000000000000000UL},
+	{0x0158U, 0x0000000000000000UL},
+	{0x0160U, 0x0000000000000000UL},
+	{0x0168U, 0x0000000000000000UL},
+	{0x0170U, 0x0000000000000000UL},
+	{0x0178U, 0x0000000000000000UL},
+	{0x0180U, 0x0000000000000000UL},
+	{0x0188U, 0x0000000000000000UL},
+	{0x0190U, 0x0000000000000000UL},
+	{0x0198U, 0x0000000000000000UL},
+	{0x01A0U, 0x0000000000000000UL},
+	{0x01A8U, 0x0000000000000000UL},
+	{0x01B0U, 0x0000000000000000UL},
+	{0x01B8U, 0x001100100C803401UL},
+	{0x01C0U, 0x001100800C8FFC01UL},
+	{0x01C8U, 0x001100800C8FFC01UL},
+	{0x01D0U, 0x001100800C8FFC01UL},
+	{0x01D8U, 0x001100800C8FFC01UL},
+	{0x01E0U, 0x001100100C80FC01UL},
+	{0x01E8U, 0x001200100C80FC01UL},
+	{0x01F0U, 0x001100100C80FC01UL},
+	{0x01F8U, 0x001100100C803401UL},
+	{0x0200U, 0x001100100C80FC01UL},
+	{0x0208U, 0x001200100C80FC01UL},
+	{0x0210U, 0x001100100C80FC01UL},
+	{0x0218U, 0x001100100C825801UL},
+	{0x0220U, 0x001100100C825801UL},
+	{0x0228U, 0x001100100C803401UL},
+	{0x0230U, 0x001100100C825801UL},
+	{0x0238U, 0x001100100C825801UL},
+	{0x0240U, 0x001200100C8BB801UL},
+	{0x0248U, 0x001100200C8FFC01UL},
+	{0x0250U, 0x001200100C8BB801UL},
+	{0x0258U, 0x001100200C8FFC01UL},
+	{0x0260U, 0x001100100C84E401UL},
+	{0x0268U, 0x0000000000000000UL},
+	{0x0270U, 0x0000000000000000UL},
+	{0x0278U, 0x001100100C81F401UL},
+	{0x0280U, 0x001100100C803401UL},
+	{0x0288U, 0x001100100C803401UL},
+	{0x0290U, 0x0000000000000000UL},
+	{0x0298U, 0x0000000000000000UL},
+	{0x02A0U, 0x0000000000000000UL},
+	{0x02A8U, 0x0000000000000000UL},
+	{0x02B0U, 0x0000000000000000UL},
+	{0x02B8U, 0x001100100C803401UL},
+	{0x02C0U, 0x001100100C803401UL},
+	{0x02C8U, 0x001100100C803401UL},
+	{0x02D0U, 0x0000000000000000UL},
+	{0x02D8U, 0x0000000000000000UL},
+	{0x02E0U, 0x0000000000000000UL},
+	{0x02E8U, 0x001100100C803401UL},
+	{0x02F0U, 0x001100300C8FFC01UL},
+	{0x02F8U, 0x001100500C8FFC01UL},
+	{0x0300U, 0x001100100C803401UL},
+	{0x0308U, 0x001100300C8FFC01UL},
+	{0x0310U, 0x001100500C8FFC01UL},
+	{0x0318U, 0x001200100C803401UL},
+	{0x0320U, 0x001100300C8FFC01UL},
+	{0x0328U, 0x001100500C8FFC01UL},
+	{0x0330U, 0x001100300C8FFC01UL},
+	{0x0338U, 0x001100500C8FFC01UL},
+};
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md = 0;
+
+	/* BUFCAM settings */
+	/* DBSC_DBCAM0CNF0 not set */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00044218);	/* dbcam0cnf1 */
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);	/* dbcam0cnf2 */
+	/* DBSC_DBCAM0CNF3 not set */
+	io_write_32(DBSC_DBSCHCNT0, 0x080F0037);	/* dbschcnt0 */
+	io_write_32(DBSC_DBSCHCNT1, 0x00001010);	/* dbschcnt1 */
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001);	/* dbschsz0 */
+	io_write_32(DBSC_DBSCHRW0, 0x22421111);	/* dbschrw0 */
+
+	md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
+
+	switch (md) {
+	case 0x0:
+		/* DDR3200 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x1:		/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
+		/* DDR2800 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x4:		/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
+		/* DDR2400 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	default:		/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000);
+	io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000);
+	io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000);
+	io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
+	/* DBSC_DBSCHQOS_1_0 not set */
+	/* DBSC_DBSCHQOS_1_1 not set */
+	/* DBSC_DBSCHQOS_1_2 not set */
+	/* DBSC_DBSCHQOS_1_3 not set */
+	/* DBSC_DBSCHQOS_2_0 not set */
+	/* DBSC_DBSCHQOS_2_1 not set */
+	/* DBSC_DBSCHQOS_2_2 not set */
+	/* DBSC_DBSCHQOS_2_3 not set */
+	/* DBSC_DBSCHQOS_3_0 not set */
+	/* DBSC_DBSCHQOS_3_1 not set */
+	/* DBSC_DBSCHQOS_3_2 not set */
+	/* DBSC_DBSCHQOS_3_3 not set */
+	io_write_32(DBSC_DBSCHQOS_4_0, 0x00000E00);
+	io_write_32(DBSC_DBSCHQOS_4_1, 0x00000DFF);
+	io_write_32(DBSC_DBSCHQOS_4_2, 0x00000400);
+	io_write_32(DBSC_DBSCHQOS_4_3, 0x00000200);
+	/* DBSC_DBSCHQOS_5_0 not set */
+	/* DBSC_DBSCHQOS_5_1 not set */
+	/* DBSC_DBSCHQOS_5_2 not set */
+	/* DBSC_DBSCHQOS_5_3 not set */
+	/* DBSC_DBSCHQOS_6_0 not set */
+	/* DBSC_DBSCHQOS_6_1 not set */
+	/* DBSC_DBSCHQOS_6_2 not set */
+	/* DBSC_DBSCHQOS_6_3 not set */
+	/* DBSC_DBSCHQOS_7_0 not set */
+	/* DBSC_DBSCHQOS_7_1 not set */
+	/* DBSC_DBSCHQOS_7_2 not set */
+	/* DBSC_DBSCHQOS_7_3 not set */
+	/* DBSC_DBSCHQOS_8_0 not set */
+	/* DBSC_DBSCHQOS_8_1 not set */
+	/* DBSC_DBSCHQOS_8_2 not set */
+	/* DBSC_DBSCHQOS_8_3 not set */
+	io_write_32(DBSC_DBSCHQOS_9_0, 0x00000C00);
+	io_write_32(DBSC_DBSCHQOS_9_1, 0x00000BFF);
+	io_write_32(DBSC_DBSCHQOS_9_2, 0x00000400);
+	io_write_32(DBSC_DBSCHQOS_9_3, 0x00000200);
+	/* DBSC_DBSCHQOS_10_0 not set */
+	/* DBSC_DBSCHQOS_10_1 not set */
+	/* DBSC_DBSCHQOS_10_2 not set */
+	/* DBSC_DBSCHQOS_10_3 not set */
+	/* DBSC_DBSCHQOS_11_0 not set */
+	/* DBSC_DBSCHQOS_11_1 not set */
+	/* DBSC_DBSCHQOS_11_2 not set */
+	/* DBSC_DBSCHQOS_11_3 not set */
+	/* DBSC_DBSCHQOS_12_0 not set */
+	/* DBSC_DBSCHQOS_12_1 not set */
+	/* DBSC_DBSCHQOS_12_2 not set */
+	/* DBSC_DBSCHQOS_12_3 not set */
+	io_write_32(DBSC_DBSCHQOS_13_0, 0x00000980);
+	io_write_32(DBSC_DBSCHQOS_13_1, 0x0000097F);
+	io_write_32(DBSC_DBSCHQOS_13_2, 0x00000300);
+	io_write_32(DBSC_DBSCHQOS_13_3, 0x00000180);
+	io_write_32(DBSC_DBSCHQOS_14_0, 0x00000800);
+	io_write_32(DBSC_DBSCHQOS_14_1, 0x000007FF);
+	io_write_32(DBSC_DBSCHQOS_14_2, 0x00000300);
+	io_write_32(DBSC_DBSCHQOS_14_3, 0x00000180);
+	io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0);
+	io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF);
+	io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0);
+	io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0);
+}
+
+void qos_init_h3_v11(void)
+{
+	dbsc_setting();
+
+	/* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+    (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 4ch\n");
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1BU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR1, 0x00000000U);
+	io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+	NOTICE("BL2: DRAM Split is 2ch\n");
+	io_write_32(AXI_ADSPLCR0, 0x00000000U);
+	io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1BU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR2, 0x00000000U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+	/* AR Cache setting */
+	io_write_32(0xE67D1000U, 0x00000100U);
+	io_write_32(0xE67D1008U, 0x00000100U);
+
+	/* Resource Alloc setting */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+	io_write_32(RALLOC_RAS, 0x00000020U);
+#else
+	io_write_32(RALLOC_RAS, 0x00000040U);
+#endif
+	io_write_32(RALLOC_FIXTH, 0x000F0005U);
+	io_write_32(RALLOC_REGGD, 0x00000000U);
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+	io_write_64(RALLOC_DANN, 0x0101010102020201UL);
+	io_write_32(RALLOC_DANT, 0x00181008U);
+#else
+	io_write_64(RALLOC_DANN, 0x0101000004040401UL);
+	io_write_32(RALLOC_DANT, 0x003C2010U);
+#endif
+	io_write_32(RALLOC_EC, 0x00080001U);	/* need for H3 v1.* */
+	io_write_64(RALLOC_EMS, 0x0000000000000000UL);
+	io_write_32(RALLOC_INSFC, 0xC7840001U);
+	io_write_32(RALLOC_BERR, 0x00000000U);
+	io_write_32(RALLOC_RACNT0, 0x00000000U);
+
+	/* MSTAT setting */
+	io_write_32(MSTAT_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
+	io_write_32(MSTAT_REF_ARS, 0x00330000U);
+
+	/* MSTAT SRAM setting */
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
+				    mstat_fix[i].value);
+			io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
+				    mstat_fix[i].value);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
+				    mstat_be[i].value);
+			io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
+				    mstat_be[i].value);
+		}
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(0xFD820808U, 0x00001234U);
+	io_write_32(0xFD820800U, 0x0000003FU);
+	io_write_32(0xFD821800U, 0x0000003FU);
+	io_write_32(0xFD822800U, 0x0000003FU);
+	io_write_32(0xFD823800U, 0x0000003FU);
+	io_write_32(0xFD824800U, 0x0000003FU);
+	io_write_32(0xFD825800U, 0x0000003FU);
+	io_write_32(0xFD826800U, 0x0000003FU);
+	io_write_32(0xFD827800U, 0x0000003FU);
+
+	/* VIO bus Leaf setting */
+	io_write_32(0xFEB89800, 0x00000001U);
+	io_write_32(0xFEB8A800, 0x00000001U);
+	io_write_32(0xFEB8B800, 0x00000001U);
+	io_write_32(0xFEB8C800, 0x00000001U);
+
+	/* HSC bus Leaf setting */
+	io_write_32(0xE6430800, 0x00000001U);
+	io_write_32(0xE6431800, 0x00000001U);
+	io_write_32(0xE6432800, 0x00000001U);
+	io_write_32(0xE6433800, 0x00000001U);
+
+	/* MP bus Leaf setting */
+	io_write_32(0xEC620800, 0x00000001U);
+	io_write_32(0xEC621800, 0x00000001U);
+
+	/* PERIE bus Leaf setting */
+	io_write_32(0xE7760800, 0x00000001U);
+	io_write_32(0xE7768800, 0x00000001U);
+
+	/* PERIW bus Leaf setting */
+	io_write_32(0xE6760800, 0x00000001U);
+	io_write_32(0xE6768800, 0x00000001U);
+
+	/* RT bus Leaf setting */
+	io_write_32(0xFFC50800, 0x00000001U);
+	io_write_32(0xFFC51800, 0x00000001U);
+
+	/* CCI bus Leaf setting */
+	{
+
+		uint32_t modemr = io_read_32(RCAR_MODEMR);
+
+		modemr &= MODEMR_BOOT_CPU_MASK;
+
+		if ((modemr == MODEMR_BOOT_CPU_CA57) ||
+		    (modemr == MODEMR_BOOT_CPU_CA53)) {
+			io_write_32(0xF1300800, 0x00000001U);
+			io_write_32(0xF1340800, 0x00000001U);
+			io_write_32(0xF1380800, 0x00000001U);
+			io_write_32(0xF13C0800, 0x00000001U);
+		}
+	}
+
+	/* Resource Alloc start */
+	io_write_32(RALLOC_RAEN, 0x00000001U);
+
+	/* MSTAT start */
+	io_write_32(MSTAT_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_EC, 0x00080001U);	/* need for H3 v1.* */
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.h
new file mode 100644
index 0000000..759e58b
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_H3_V11__
+#define QOS_INIT_H_H3_V11__
+
+void qos_init_h3_v11(void);
+
+#endif /* QOS_INIT_H_H3_V11__ */
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
new file mode 100644
index 0000000..6922360
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3_v20.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.19"
+
+#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+
+#define	QOSWT_WTEN_ENABLE				(0x1U)
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20	(SL_INIT_SSLOTCLK_H3_20 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
+#define WT_BASE_SUB_SLOT_NUM0			(12U)
+#define QOSWT_WTSET0_PERIOD0_H3_20		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
+#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#define QOSWT_WTSET1_PERIOD1_H3_20		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_20)-1U)
+#define QOSWT_WTSET1_SSLOT1				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET1_SLOTSLOT1			(WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v20_mstat195.h"
+#else
+#include "qos_init_h3_v20_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v20_qoswt195.h"
+#else
+#include "qos_init_h3_v20_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md = 0;
+
+	/* Register write enable */
+	io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+
+	/* BUFCAM settings */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218U);	/* dbcam0cnf1 */
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);	/* dbcam0cnf2 */
+	io_write_32(DBSC_DBCAM0CNF3, 0x00000000U);	/* dbcam0cnf3 */
+	io_write_32(DBSC_DBSCHCNT0, 0x000F0037U);	/* dbschcnt0 */
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001U);	/* dbschsz0 */
+	io_write_32(DBSC_DBSCHRW0, 0x22421111U);	/* dbschrw0 */
+
+	md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
+
+	switch (md) {
+	case 0x0:
+		/* DDR3200 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	case 0x1:		/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
+		/* DDR2800 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	case 0x4:		/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
+		/* DDR2400 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	default:		/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
+	io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
+	io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
+	io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
+	io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
+	io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
+	io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
+	io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
+	io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
+	io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
+	io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
+	io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
+	io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
+	io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
+	io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
+	io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
+	io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
+	io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
+	io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
+	io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
+
+	/* Register write protect */
+	io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
+}
+
+void qos_init_h3_v20(void)
+{
+	dbsc_setting();
+
+	/* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+    (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 4ch\n");
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1BU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR1, 0x00000000U);
+	io_write_32(AXI_ADSPLCR2, 0x00001054U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+	NOTICE("BL2: DRAM Split is 2ch\n");
+	io_write_32(AXI_ADSPLCR0, 0x00000000U);
+	io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1BU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR2, 0x00001004U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_RAS, 0x00000044U);
+	io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
+	io_write_32(QOSCTRL_DANT, 0x0020100AU);
+	io_write_32(QOSCTRL_INSFC, 0x06330001U);
+	io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	/* GPU Boost Mode */
+	io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+	io_write_32(QOSCTRL_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+		    SL_INIT_SSLOTCLK_H3_20);
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	io_write_32(QOSCTRL_REF_ARS,
+		    ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_20 << 16)));
+#else
+	io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+		}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+		for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+			io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+				    qoswt_fix[i]);
+			io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+				    qoswt_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+			io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+			io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+		}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(GPU_ACT0, 0x00000000U);
+	io_write_32(GPU_ACT1, 0x00000000U);
+	io_write_32(GPU_ACT2, 0x00000000U);
+	io_write_32(GPU_ACT3, 0x00000000U);
+	io_write_32(GPU_ACT4, 0x00000000U);
+	io_write_32(GPU_ACT5, 0x00000000U);
+	io_write_32(GPU_ACT6, 0x00000000U);
+	io_write_32(GPU_ACT7, 0x00000000U);
+
+	/* RT bus Leaf setting */
+	io_write_32(RT_ACT0, 0x00000000U);
+	io_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	io_write_32(CPU_ACT0, 0x00000003U);
+	io_write_32(CPU_ACT1, 0x00000003U);
+	io_write_32(CPU_ACT2, 0x00000003U);
+	io_write_32(CPU_ACT3, 0x00000003U);
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	io_write_32(QOSWT_WTREF,
+		    ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	io_write_32(QOSWT_WTSET0,
+		    ((QOSWT_WTSET0_PERIOD0_H3_20 << 16) |
+		     (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	io_write_32(QOSWT_WTSET1,
+		    ((QOSWT_WTSET1_PERIOD1_H3_20 << 16) |
+		     (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.h
new file mode 100644
index 0000000..59c1bdb
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_H3_V20__
+#define QOS_INIT_H_H3_V20__
+
+void qos_init_h3_v20(void);
+
+#endif /* QOS_INIT_H_H3_V20__ */
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h
new file mode 100644
index 0000000..3995df3
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat195.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000FFFFUL,
+	/* 0x0038, */ 0x001008070000FFFFUL,
+	/* 0x0040, */ 0x001424110000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x001410100000FFFFUL,
+	/* 0x0060, */ 0x0014100D0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x001008070000FFFFUL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001424110000FFFFUL,
+	/* 0x0090, */ 0x0014100D0000FFFFUL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C04020000FFFFUL,
+	/* 0x00a8, */ 0x000C04010000FFFFUL,
+	/* 0x00b0, */ 0x000C04010000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C04020000FFFFUL,
+	/* 0x00c8, */ 0x000C04010000FFFFUL,
+	/* 0x00d0, */ 0x000C04010000FFFFUL,
+	/* 0x00d8, */ 0x001024090000FFFFUL,
+	/* 0x00e0, */ 0x00100C090000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001024090000FFFFUL,
+	/* 0x00f8, */ 0x000C08070000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100C090000FFFFUL,
+	/* 0x0118, */ 0x000C10100000FFFFUL,
+	/* 0x0120, */ 0x000C10100000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100C0B0000FFFFUL,
+	/* 0x0140, */ 0x00100C0B0000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010100D0000FFFFUL,
+	/* 0x0158, */ 0x0010100D0000FFFFUL,
+	/* 0x0160, */ 0x00100C0B0000FFFFUL,
+	/* 0x0168, */ 0x00100C0B0000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008060000FFFFUL,
+	/* 0x0180, */ 0x001008060000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00102C2C0000FFFFUL,
+	/* 0x0198, */ 0x00102C2C0000FFFFUL,
+	/* 0x01a0, */ 0x00100C0B0000FFFFUL,
+	/* 0x01a8, */ 0x00100C0B0000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFFFUL,
+	/* 0x0268, */ 0x001408010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C04010000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x001408010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x001408010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x001200200BDFFC01UL,
+	/* 0x0008, */ 0x001200200BDFFC01UL,
+	/* 0x0010, */ 0x001200200BDFFC01UL,
+	/* 0x0018, */ 0x001200200BDFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100700BDFFC01UL,
+	/* 0x01c8, */ 0x002100700BDFFC01UL,
+	/* 0x01d0, */ 0x002100700BDFFC01UL,
+	/* 0x01d8, */ 0x002100700BDFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x002100200BDFFC01UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x002100200BDFFC01UL,
+	/* 0x0218, */ 0x001100200BDFFC01UL,
+	/* 0x0220, */ 0x001100200BDFFC01UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001100200BDFFC01UL,
+	/* 0x0238, */ 0x001100200BDFFC01UL,
+	/* 0x0240, */ 0x001200200BDFFC01UL,
+	/* 0x0248, */ 0x001100200BDFFC01UL,
+	/* 0x0250, */ 0x001200200BDFFC01UL,
+	/* 0x0258, */ 0x001100200BDFFC01UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001100400BDFFC01UL,
+	/* 0x02f8, */ 0x001100600BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x001100400BDFFC01UL,
+	/* 0x0310, */ 0x001100600BDFFC01UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x001100400BDFFC01UL,
+	/* 0x0328, */ 0x001100600BDFFC01UL,
+	/* 0x0330, */ 0x001100400BDFFC01UL,
+	/* 0x0338, */ 0x001100600BDFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x001200100BD0FC01UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h
new file mode 100644
index 0000000..770c022
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_mstat390.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000FFFFUL,
+	/* 0x0038, */ 0x0010100D0000FFFFUL,
+	/* 0x0040, */ 0x001444210000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x0014201F0000FFFFUL,
+	/* 0x0060, */ 0x00141C190000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x0010100D0000FFFFUL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001444210000FFFFUL,
+	/* 0x0090, */ 0x00141C190000FFFFUL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08040000FFFFUL,
+	/* 0x00a8, */ 0x000C04020000FFFFUL,
+	/* 0x00b0, */ 0x000C04020000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08040000FFFFUL,
+	/* 0x00c8, */ 0x000C04020000FFFFUL,
+	/* 0x00d0, */ 0x000C04020000FFFFUL,
+	/* 0x00d8, */ 0x001044110000FFFFUL,
+	/* 0x00e0, */ 0x001014110000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001044110000FFFFUL,
+	/* 0x00f8, */ 0x000C100D0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001014110000FFFFUL,
+	/* 0x0118, */ 0x000C20200000FFFFUL,
+	/* 0x0120, */ 0x000C20200000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001018150000FFFFUL,
+	/* 0x0140, */ 0x001018150000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101C190000FFFFUL,
+	/* 0x0158, */ 0x00101C190000FFFFUL,
+	/* 0x0160, */ 0x001018150000FFFFUL,
+	/* 0x0168, */ 0x001018150000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100C0B0000FFFFUL,
+	/* 0x0180, */ 0x00100C0B0000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001058570000FFFFUL,
+	/* 0x0198, */ 0x001058570000FFFFUL,
+	/* 0x01a0, */ 0x001018150000FFFFUL,
+	/* 0x01a8, */ 0x001018150000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFFFUL,
+	/* 0x0268, */ 0x001410010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C08020000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x00140C010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x00140C010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0012003005EFFC01UL,
+	/* 0x0008, */ 0x0012003005EFFC01UL,
+	/* 0x0010, */ 0x0012003005EFFC01UL,
+	/* 0x0018, */ 0x0012003005EFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100D005EFFC01UL,
+	/* 0x01c8, */ 0x002100D005EFFC01UL,
+	/* 0x01d0, */ 0x002100D005EFFC01UL,
+	/* 0x01d8, */ 0x002100D005EFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021003005EFFC01UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021003005EFFC01UL,
+	/* 0x0218, */ 0x0011003005EFFC01UL,
+	/* 0x0220, */ 0x0011003005EFFC01UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011003005EFFC01UL,
+	/* 0x0238, */ 0x0011003005EFFC01UL,
+	/* 0x0240, */ 0x0012003005EFFC01UL,
+	/* 0x0248, */ 0x0011003005EFFC01UL,
+	/* 0x0250, */ 0x0012003005EFFC01UL,
+	/* 0x0258, */ 0x0011003005EFFC01UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011007005EFFC01UL,
+	/* 0x02f8, */ 0x001100B005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0011007005EFFC01UL,
+	/* 0x0310, */ 0x001100B005EFFC01UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0011007005EFFC01UL,
+	/* 0x0328, */ 0x001100B005EFFC01UL,
+	/* 0x0330, */ 0x0011007005EFFC01UL,
+	/* 0x0338, */ 0x001100B005EFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0012001005E0FC01UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h
new file mode 100644
index 0000000..82e4b01
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt195.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000C010UL,
+	/* 0x0038, */ 0x001008070000C010UL,
+	/* 0x0040, */ 0x001424110000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001410100000C010UL,
+	/* 0x0060, */ 0x0014100D0000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x001008070000C010UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001424110000FFF0UL,
+	/* 0x0090, */ 0x0014100D0000C010UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFF0UL,
+	/* 0x0268, */ 0x001408010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04010000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h
new file mode 100644
index 0000000..f3e7360
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20_qoswt390.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000C010UL,
+	/* 0x0038, */ 0x0010100D0000C010UL,
+	/* 0x0040, */ 0x001444210000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0014201F0000C010UL,
+	/* 0x0060, */ 0x00141C190000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0010100D0000C010UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001444210000FFF0UL,
+	/* 0x0090, */ 0x00141C190000C010UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFF0UL,
+	/* 0x0268, */ 0x001410010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C08020000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
new file mode 100644
index 0000000..5986a39
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3_v30.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.07"
+
+#define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
+
+#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+
+#define	QOSWT_WTEN_ENABLE				(0x1U)
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30	(SL_INIT_SSLOTCLK_H3_30 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
+#define WT_BASE_SUB_SLOT_NUM0			(12U)
+#define QOSWT_WTSET0_PERIOD0_H3_30		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3_30)-1U)
+#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#define QOSWT_WTSET1_PERIOD1_H3_30		(QOSWT_WTSET0_PERIOD0_H3_30)
+#define QOSWT_WTSET1_SSLOT1				(QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SLOTSLOT1			(QOSWT_WTSET0_SLOTSLOT0)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v30_mstat195.h"
+#else
+#include "qos_init_h3_v30_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3_v30_qoswt195.h"
+#else
+#include "qos_init_h3_v30_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md = 0;
+
+	/* Register write enable */
+	io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+
+	/* BUFCAM settings */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218U);	/* dbcam0cnf1 */
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);	/* dbcam0cnf2 */
+	io_write_32(DBSC_DBCAM0CNF3, 0x00000000U);	/* dbcam0cnf3 */
+	io_write_32(DBSC_DBSCHCNT0, 0x000F0037U);	/* dbschcnt0 */
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001U);	/* dbschsz0 */
+	io_write_32(DBSC_DBSCHRW0, 0x22421111U);	/* dbschrw0 */
+
+	md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
+
+	switch (md) {
+	case 0x0:
+		/* DDR3200 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	case 0x1:		/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
+		/* DDR2800 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	case 0x4:		/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
+		/* DDR2400 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	default:		/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
+	io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
+	io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
+	io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
+	io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
+	io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
+	io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
+	io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
+	io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
+	io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
+	io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
+	io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
+	io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
+	io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
+	io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
+	io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
+	io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
+	io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
+	io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
+	io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
+
+	/* Register write protect */
+	io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
+}
+
+void qos_init_h3_v30(void)
+{
+	unsigned int split_area;
+	dbsc_setting();
+
+#if RCAR_DRAM_LPDDR4_MEMCONF == 0	/* 1GB */
+	split_area = 0x1BU;
+#else /* default 2GB */
+	split_area = 0x1CU;
+#endif
+
+	/* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
+    (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 4ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(split_area)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR1, 0x00000000U);
+	io_write_32(AXI_ADSPLCR2, 0x00001054U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
+	NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(split_area)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR2, 0x00001004U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_RAS, 0x00000044U);
+	io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
+	io_write_32(QOSCTRL_DANT, 0x0020100AU);
+	io_write_32(QOSCTRL_FSS, 0x0000000AU);
+	io_write_32(QOSCTRL_INSFC, 0x06330001U);
+	io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	/* GPU Boost Mode */
+	io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+	io_write_32(QOSCTRL_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+		    SL_INIT_SSLOTCLK_H3_30);
+	io_write_32(QOSCTRL_REF_ARS,
+		    ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
+
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+		}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+		for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+			io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+				    qoswt_fix[i]);
+			io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+				    qoswt_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+			io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+			io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+		}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+	}
+
+	/* AXI setting */
+	io_write_32(AXI_MMCR, 0x00010008U);
+	io_write_32(AXI_TR3CR, 0x00010000U);
+	io_write_32(AXI_TR4CR, 0x00010000U);
+
+	/* 3DG bus Leaf setting */
+
+	/* RT bus Leaf setting */
+	io_write_32(RT_ACT0, 0x00000000U);
+	io_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	io_write_32(CPU_ACT0, 0x00000003U);
+	io_write_32(CPU_ACT1, 0x00000003U);
+	io_write_32(CPU_ACT2, 0x00000003U);
+	io_write_32(CPU_ACT3, 0x00000003U);
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	io_write_32(QOSWT_WTREF,
+		    ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	io_write_32(QOSWT_WTSET0,
+		    ((QOSWT_WTSET0_PERIOD0_H3_30 << 16) |
+		     (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	io_write_32(QOSWT_WTSET1,
+		    ((QOSWT_WTSET1_PERIOD1_H3_30 << 16) |
+		     (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.h
new file mode 100644
index 0000000..5441f55
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_H3_V30__
+#define QOS_INIT_H_H3_V30__
+
+void qos_init_h3_v30(void);
+
+#endif /* QOS_INIT_H_H3_V20__ */
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
new file mode 100644
index 0000000..daa4076
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000FFFFUL,
+	/* 0x0038, */ 0x001008070000FFFFUL,
+	/* 0x0040, */ 0x001410070000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x0014100D0000FFFFUL,
+	/* 0x0060, */ 0x0014100D0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x001008070000FFFFUL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFFFUL,
+	/* 0x0090, */ 0x0014100D0000FFFFUL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C04020000FFFFUL,
+	/* 0x00a8, */ 0x000C04010000FFFFUL,
+	/* 0x00b0, */ 0x000C04010000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C04020000FFFFUL,
+	/* 0x00c8, */ 0x000C04010000FFFFUL,
+	/* 0x00d0, */ 0x000C04010000FFFFUL,
+	/* 0x00d8, */ 0x001024090000FFFFUL,
+	/* 0x00e0, */ 0x00100C090000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001024090000FFFFUL,
+	/* 0x00f8, */ 0x000C08080000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100C090000FFFFUL,
+	/* 0x0118, */ 0x000C18180000FFFFUL,
+	/* 0x0120, */ 0x000C18180000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100C0B0000FFFFUL,
+	/* 0x0140, */ 0x00100C0B0000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010100D0000FFFFUL,
+	/* 0x0158, */ 0x0010100D0000FFFFUL,
+	/* 0x0160, */ 0x00100C0B0000FFFFUL,
+	/* 0x0168, */ 0x00100C0B0000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008060000FFFFUL,
+	/* 0x0180, */ 0x001008060000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00102C2C0000FFFFUL,
+	/* 0x0198, */ 0x00102C2C0000FFFFUL,
+	/* 0x01a0, */ 0x00100C0B0000FFFFUL,
+	/* 0x01a8, */ 0x00100C0B0000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFFFUL,
+	/* 0x0268, */ 0x001408010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C04010000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x001408010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x001408010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x001200600BDFFC01UL,
+	/* 0x0008, */ 0x001200600BDFFC01UL,
+	/* 0x0010, */ 0x001200600BDFFC01UL,
+	/* 0x0018, */ 0x001200600BDFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100600BDFFC01UL,
+	/* 0x01c8, */ 0x002100600BDFFC01UL,
+	/* 0x01d0, */ 0x002100600BDFFC01UL,
+	/* 0x01d8, */ 0x002100600BDFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x002100100BDF2401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x002100100BDF2401UL,
+	/* 0x0218, */ 0x001100100BDF2401UL,
+	/* 0x0220, */ 0x001100100BDF2401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001100100BDF2401UL,
+	/* 0x0238, */ 0x001100100BDF2401UL,
+	/* 0x0240, */ 0x001200100BDF2401UL,
+	/* 0x0248, */ 0x001100100BDF2401UL,
+	/* 0x0250, */ 0x001200100BDF2401UL,
+	/* 0x0258, */ 0x001100100BDF2401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001100600BDFFC01UL,
+	/* 0x02f8, */ 0x001100600BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x001100600BDFFC01UL,
+	/* 0x0310, */ 0x001100600BDFFC01UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x001100600BDFFC01UL,
+	/* 0x0328, */ 0x001100600BDFFC01UL,
+	/* 0x0330, */ 0x001100600BDFFC01UL,
+	/* 0x0338, */ 0x001100600BDFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x001200100BD0FC01UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
new file mode 100644
index 0000000..f72165c
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000FFFFUL,
+	/* 0x0038, */ 0x0010100D0000FFFFUL,
+	/* 0x0040, */ 0x00141C0E0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001408010000FFFFUL,
+	/* 0x0058, */ 0x00141C190000FFFFUL,
+	/* 0x0060, */ 0x00141C190000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001408010000FFFFUL,
+	/* 0x0078, */ 0x0010100D0000FFFFUL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFFFUL,
+	/* 0x0090, */ 0x00141C190000FFFFUL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08040000FFFFUL,
+	/* 0x00a8, */ 0x000C04020000FFFFUL,
+	/* 0x00b0, */ 0x000C04020000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08040000FFFFUL,
+	/* 0x00c8, */ 0x000C04020000FFFFUL,
+	/* 0x00d0, */ 0x000C04020000FFFFUL,
+	/* 0x00d8, */ 0x001044110000FFFFUL,
+	/* 0x00e0, */ 0x001014110000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001044110000FFFFUL,
+	/* 0x00f8, */ 0x000C10100000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001014110000FFFFUL,
+	/* 0x0118, */ 0x000C302F0000FFFFUL,
+	/* 0x0120, */ 0x000C302F0000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001018150000FFFFUL,
+	/* 0x0140, */ 0x001018150000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101C190000FFFFUL,
+	/* 0x0158, */ 0x00101C190000FFFFUL,
+	/* 0x0160, */ 0x001018150000FFFFUL,
+	/* 0x0168, */ 0x001018150000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100C0B0000FFFFUL,
+	/* 0x0180, */ 0x00100C0B0000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001058570000FFFFUL,
+	/* 0x0198, */ 0x001058570000FFFFUL,
+	/* 0x01a0, */ 0x001018150000FFFFUL,
+	/* 0x01a8, */ 0x001018150000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFFFUL,
+	/* 0x0268, */ 0x001410010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C08020000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x00140C010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x00140C010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0012006005EFFC01UL,
+	/* 0x0008, */ 0x0012006005EFFC01UL,
+	/* 0x0010, */ 0x0012006005EFFC01UL,
+	/* 0x0018, */ 0x0012006005EFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021006005EFFC01UL,
+	/* 0x01c8, */ 0x0021006005EFFC01UL,
+	/* 0x01d0, */ 0x0021006005EFFC01UL,
+	/* 0x01d8, */ 0x0021006005EFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021001005E79401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021001005E79401UL,
+	/* 0x0218, */ 0x0011001005E79401UL,
+	/* 0x0220, */ 0x0011001005E79401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011001005E79401UL,
+	/* 0x0238, */ 0x0011001005E79401UL,
+	/* 0x0240, */ 0x0012001005E79401UL,
+	/* 0x0248, */ 0x0011001005E79401UL,
+	/* 0x0250, */ 0x0012001005E79401UL,
+	/* 0x0258, */ 0x0011001005E79401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011006005EFFC01UL,
+	/* 0x02f8, */ 0x0011006005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0011006005EFFC01UL,
+	/* 0x0310, */ 0x0011006005EFFC01UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0011006005EFFC01UL,
+	/* 0x0328, */ 0x0011006005EFFC01UL,
+	/* 0x0330, */ 0x0011006005EFFC01UL,
+	/* 0x0338, */ 0x0011006005EFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0012001005E0FC01UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h
new file mode 100644
index 0000000..b0c11cc
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt195.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000C010UL,
+	/* 0x0038, */ 0x001008070000C010UL,
+	/* 0x0040, */ 0x001410070000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0014100D0000C010UL,
+	/* 0x0060, */ 0x0014100D0000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x001008070000C010UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFF0UL,
+	/* 0x0090, */ 0x0014100D0000C010UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFF0UL,
+	/* 0x0268, */ 0x001408010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04010000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h
new file mode 100644
index 0000000..a1e4c72
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_qoswt390.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000C010UL,
+	/* 0x0038, */ 0x0010100D0000C010UL,
+	/* 0x0040, */ 0x00141C0E0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00141C190000C010UL,
+	/* 0x0060, */ 0x00141C190000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0010100D0000C010UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFF0UL,
+	/* 0x0090, */ 0x00141C190000C010UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFF0UL,
+	/* 0x0268, */ 0x001410010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C08020000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
new file mode 100644
index 0000000..58c3716
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_h3n_v30.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.03"
+
+#define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
+
+#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+
+#define	QOSWT_WTEN_ENABLE				(0x1U)
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N	(SL_INIT_SSLOTCLK_H3N - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
+#define WT_BASE_SUB_SLOT_NUM0			(12U)
+#define QOSWT_WTSET0_PERIOD0_H3N		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3N)-1U)
+#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#define QOSWT_WTSET1_PERIOD1_H3N		(QOSWT_WTSET0_PERIOD0_H3N)
+#define QOSWT_WTSET1_SSLOT1				(QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SLOTSLOT1			(QOSWT_WTSET0_SLOTSLOT0)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3n_v30_mstat195.h"
+#else
+#include "qos_init_h3n_v30_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_h3n_v30_qoswt195.h"
+#else
+#include "qos_init_h3n_v30_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md = 0;
+
+	/* Register write enable */
+	io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+
+	/* BUFCAM settings */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218U);	/* dbcam0cnf1 */
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);	/* dbcam0cnf2 */
+	io_write_32(DBSC_DBCAM0CNF3, 0x00000000U);	/* dbcam0cnf3 */
+	io_write_32(DBSC_DBSCHCNT0, 0x000F0037U);	/* dbschcnt0 */
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001U);	/* dbschsz0 */
+	io_write_32(DBSC_DBSCHRW0, 0x22421111U);	/* dbschrw0 */
+
+	md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
+
+	switch (md) {
+	case 0x0:
+		/* DDR3200 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	case 0x1:		/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
+		/* DDR2800 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	case 0x4:		/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
+		/* DDR2400 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	default:		/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123U);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
+	io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
+	io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
+	io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
+	io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
+	io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
+	io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
+	io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
+	io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
+	io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
+	io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
+	io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
+	io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
+	io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
+	io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
+	io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
+	io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
+	io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
+	io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
+	io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
+	io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
+	io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
+
+	/* Register write protect */
+	io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
+}
+
+void qos_init_h3n_v30(void)
+{
+	unsigned int split_area;
+	dbsc_setting();
+
+	/* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
+	split_area = 0x1CU;
+
+	/* DRAM Split Address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
+#if RCAR_LSI == RCAR_H3N
+#error "Don't set DRAM Split 4ch(H3N)"
+#else
+	ERROR("DRAM Split 4ch not supported.(H3N)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+    (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(split_area)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR2, 0x00001004U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+	NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_RAS, 0x00000044U);
+	io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+	io_write_32(QOSCTRL_DANT, 0x0020100AU);
+	io_write_32(QOSCTRL_FSS, 0x0000000AU);
+	io_write_32(QOSCTRL_INSFC, 0x06330001U);
+	io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	/* GPU Boost Mode */
+	io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+	io_write_32(QOSCTRL_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+		    SL_INIT_SSLOTCLK_H3N);
+	io_write_32(QOSCTRL_REF_ARS,
+		    ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
+
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+		}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+		for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+			io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+				    qoswt_fix[i]);
+			io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+				    qoswt_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+			io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+			io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+		}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+	}
+
+	/* AXI setting */
+	io_write_32(AXI_MMCR, 0x00010008U);
+	io_write_32(AXI_TR3CR, 0x00010000U);
+	io_write_32(AXI_TR4CR, 0x00010000U);
+
+	/* 3DG bus Leaf setting */
+	io_write_32(GPU_ACT_GRD, 0x00001234U);
+	io_write_32(GPU_ACT0, 0x00000000U);
+	io_write_32(GPU_ACT1, 0x00000000U);
+	io_write_32(GPU_ACT2, 0x00000000U);
+	io_write_32(GPU_ACT3, 0x00000000U);
+	io_write_32(GPU_ACT_GRD, 0x00000000U);
+
+	/* RT bus Leaf setting */
+	io_write_32(RT_ACT0, 0x00000000U);
+	io_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	io_write_32(CPU_ACT0, 0x00000003U);
+	io_write_32(CPU_ACT1, 0x00000003U);
+	io_write_32(CPU_ACT2, 0x00000003U);
+	io_write_32(CPU_ACT3, 0x00000003U);
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	io_write_32(QOSWT_WTREF,
+		    ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	io_write_32(QOSWT_WTSET0,
+		    ((QOSWT_WTSET0_PERIOD0_H3N << 16) |
+		     (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	io_write_32(QOSWT_WTSET1,
+		    ((QOSWT_WTSET1_PERIOD1_H3N << 16) |
+		     (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.h
new file mode 100644
index 0000000..73fe694
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_H3N_V30__
+#define QOS_INIT_H_H3N_V30__
+
+void qos_init_h3n_v30(void);
+
+#endif /* QOS_INIT_H_H3N_V30__ */
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
new file mode 100644
index 0000000..b73e90b
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000FFFFUL,
+	/* 0x0038, */ 0x001008070000FFFFUL,
+	/* 0x0040, */ 0x001410070000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x0014100D0000FFFFUL,
+	/* 0x0060, */ 0x0014100D0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C04020000FFFFUL,
+	/* 0x00a8, */ 0x000C04010000FFFFUL,
+	/* 0x00b0, */ 0x000C04010000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C04020000FFFFUL,
+	/* 0x00c8, */ 0x000C04010000FFFFUL,
+	/* 0x00d0, */ 0x000C04010000FFFFUL,
+	/* 0x00d8, */ 0x001024090000FFFFUL,
+	/* 0x00e0, */ 0x00100C090000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001024090000FFFFUL,
+	/* 0x00f8, */ 0x000C08080000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100C090000FFFFUL,
+	/* 0x0118, */ 0x000C18180000FFFFUL,
+	/* 0x0120, */ 0x000C18180000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100C0B0000FFFFUL,
+	/* 0x0140, */ 0x00100C0B0000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010100D0000FFFFUL,
+	/* 0x0158, */ 0x0010100D0000FFFFUL,
+	/* 0x0160, */ 0x00100C0B0000FFFFUL,
+	/* 0x0168, */ 0x00100C0B0000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008060000FFFFUL,
+	/* 0x0180, */ 0x001008060000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00102C2C0000FFFFUL,
+	/* 0x0198, */ 0x00102C2C0000FFFFUL,
+	/* 0x01a0, */ 0x00100C0B0000FFFFUL,
+	/* 0x01a8, */ 0x00100C0B0000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFFFUL,
+	/* 0x0268, */ 0x001408010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C04010000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x001408010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x001408010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x001200600BDFFC01UL,
+	/* 0x0008, */ 0x001200600BDFFC01UL,
+	/* 0x0010, */ 0x001200600BDFFC01UL,
+	/* 0x0018, */ 0x001200600BDFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100600BDFFC01UL,
+	/* 0x01c8, */ 0x002100600BDFFC01UL,
+	/* 0x01d0, */ 0x002100600BDFFC01UL,
+	/* 0x01d8, */ 0x002100600BDFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x002100100BDF2401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x002100100BDF2401UL,
+	/* 0x0218, */ 0x001100100BDF2401UL,
+	/* 0x0220, */ 0x001100100BDF2401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001100100BDF2401UL,
+	/* 0x0238, */ 0x001100100BDF2401UL,
+	/* 0x0240, */ 0x001200100BDF2401UL,
+	/* 0x0248, */ 0x001100100BDF2401UL,
+	/* 0x0250, */ 0x001200100BDF2401UL,
+	/* 0x0258, */ 0x001100100BDF2401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001100600BDFFC01UL,
+	/* 0x02f8, */ 0x001100600BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x001100600BDFFC01UL,
+	/* 0x0310, */ 0x001100600BDFFC01UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x001100600BDFFC01UL,
+	/* 0x0328, */ 0x001100600BDFFC01UL,
+	/* 0x0330, */ 0x001100600BDFFC01UL,
+	/* 0x0338, */ 0x001100600BDFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x001200100BD0FC01UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
new file mode 100644
index 0000000..1b7c383
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000FFFFUL,
+	/* 0x0038, */ 0x0010100D0000FFFFUL,
+	/* 0x0040, */ 0x00141C0E0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001408010000FFFFUL,
+	/* 0x0058, */ 0x00141C190000FFFFUL,
+	/* 0x0060, */ 0x00141C190000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001408010000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08040000FFFFUL,
+	/* 0x00a8, */ 0x000C04020000FFFFUL,
+	/* 0x00b0, */ 0x000C04020000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08040000FFFFUL,
+	/* 0x00c8, */ 0x000C04020000FFFFUL,
+	/* 0x00d0, */ 0x000C04020000FFFFUL,
+	/* 0x00d8, */ 0x001044110000FFFFUL,
+	/* 0x00e0, */ 0x001014110000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001044110000FFFFUL,
+	/* 0x00f8, */ 0x000C10100000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001014110000FFFFUL,
+	/* 0x0118, */ 0x000C302F0000FFFFUL,
+	/* 0x0120, */ 0x000C302F0000FFFFUL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001018150000FFFFUL,
+	/* 0x0140, */ 0x001018150000FFFFUL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101C190000FFFFUL,
+	/* 0x0158, */ 0x00101C190000FFFFUL,
+	/* 0x0160, */ 0x001018150000FFFFUL,
+	/* 0x0168, */ 0x001018150000FFFFUL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100C0B0000FFFFUL,
+	/* 0x0180, */ 0x00100C0B0000FFFFUL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001058570000FFFFUL,
+	/* 0x0198, */ 0x001058570000FFFFUL,
+	/* 0x01a0, */ 0x001018150000FFFFUL,
+	/* 0x01a8, */ 0x001018150000FFFFUL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFFFUL,
+	/* 0x0268, */ 0x001410010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C08020000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x00140C010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x00140C010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0012006005EFFC01UL,
+	/* 0x0008, */ 0x0012006005EFFC01UL,
+	/* 0x0010, */ 0x0012006005EFFC01UL,
+	/* 0x0018, */ 0x0012006005EFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E0FC01UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021006005EFFC01UL,
+	/* 0x01c8, */ 0x0021006005EFFC01UL,
+	/* 0x01d0, */ 0x0021006005EFFC01UL,
+	/* 0x01d8, */ 0x0021006005EFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021001005E79401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021001005E79401UL,
+	/* 0x0218, */ 0x0011001005E79401UL,
+	/* 0x0220, */ 0x0011001005E79401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011001005E79401UL,
+	/* 0x0238, */ 0x0011001005E79401UL,
+	/* 0x0240, */ 0x0012001005E79401UL,
+	/* 0x0248, */ 0x0011001005E79401UL,
+	/* 0x0250, */ 0x0012001005E79401UL,
+	/* 0x0258, */ 0x0011001005E79401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011006005EFFC01UL,
+	/* 0x02f8, */ 0x0011006005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0011006005EFFC01UL,
+	/* 0x0310, */ 0x0011006005EFFC01UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0011006005EFFC01UL,
+	/* 0x0328, */ 0x0011006005EFFC01UL,
+	/* 0x0330, */ 0x0011006005EFFC01UL,
+	/* 0x0338, */ 0x0011006005EFFC01UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0012001005E0FC01UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h
new file mode 100644
index 0000000..affd013
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt195.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000C010UL,
+	/* 0x0038, */ 0x001008070000C010UL,
+	/* 0x0040, */ 0x001410070000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0014100D0000C010UL,
+	/* 0x0060, */ 0x0014100D0000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001410070000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFF0UL,
+	/* 0x0268, */ 0x001408010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04010000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h
new file mode 100644
index 0000000..1c48d28
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_qoswt390.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000C010UL,
+	/* 0x0038, */ 0x0010100D0000C010UL,
+	/* 0x0040, */ 0x00141C0E0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00141C190000C010UL,
+	/* 0x0060, */ 0x00141C190000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x00141C0E0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFF0UL,
+	/* 0x0268, */ 0x001410010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C08020000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
new file mode 100644
index 0000000..a0d1e14
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "qos_init_m3_v10.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.19"
+
+#define	RCAR_QOS_NONE			(3U)
+#define	RCAR_QOS_TYPE_DEFAULT		(0U)
+
+#define	RCAR_DRAM_SPLIT_LINEAR		(0U)
+#define	RCAR_DRAM_SPLIT_4CH		(1U)
+#define	RCAR_DRAM_SPLIT_2CH		(2U)
+#define	RCAR_DRAM_SPLIT_AUTO		(3U)
+
+#define	RST_BASE			(0xE6160000U)
+#define	RST_MODEMR			(RST_BASE + 0x0060U)
+
+#define	DBSC_BASE			(0xE6790000U)
+#define DBSC_DBCAM0CNF0			(DBSC_BASE + 0x0900U)
+#define DBSC_DBCAM0CNF1			(DBSC_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2			(DBSC_BASE + 0x0908U)
+#define DBSC_DBCAM0CNF3			(DBSC_BASE + 0x090CU)
+#define DBSC_DBCAMDIS			(DBSC_BASE + 0x09fCU)
+#define DBSC_DBSCHCNT0			(DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHCNT1			(DBSC_BASE + 0x1004U)
+#define DBSC_DBSCHSZ0			(DBSC_BASE + 0x1010U)
+#define DBSC_DBSCHRW0			(DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHQOS_0_0		(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS_0_1		(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS_0_2		(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS_0_3		(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS_1_0		(DBSC_BASE + 0x1040U)
+#define DBSC_DBSCHQOS_1_1		(DBSC_BASE + 0x1044U)
+#define DBSC_DBSCHQOS_1_2		(DBSC_BASE + 0x1048U)
+#define DBSC_DBSCHQOS_1_3		(DBSC_BASE + 0x104CU)
+#define DBSC_DBSCHQOS_2_0		(DBSC_BASE + 0x1050U)
+#define DBSC_DBSCHQOS_2_1		(DBSC_BASE + 0x1054U)
+#define DBSC_DBSCHQOS_2_2		(DBSC_BASE + 0x1058U)
+#define DBSC_DBSCHQOS_2_3		(DBSC_BASE + 0x105CU)
+#define DBSC_DBSCHQOS_3_0		(DBSC_BASE + 0x1060U)
+#define DBSC_DBSCHQOS_3_1		(DBSC_BASE + 0x1064U)
+#define DBSC_DBSCHQOS_3_2		(DBSC_BASE + 0x1068U)
+#define DBSC_DBSCHQOS_3_3		(DBSC_BASE + 0x106CU)
+#define DBSC_DBSCHQOS_4_0		(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS_4_1		(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS_4_2		(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS_4_3		(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS_5_0		(DBSC_BASE + 0x1080U)
+#define DBSC_DBSCHQOS_5_1		(DBSC_BASE + 0x1084U)
+#define DBSC_DBSCHQOS_5_2		(DBSC_BASE + 0x1088U)
+#define DBSC_DBSCHQOS_5_3		(DBSC_BASE + 0x108CU)
+#define DBSC_DBSCHQOS_6_0		(DBSC_BASE + 0x1090U)
+#define DBSC_DBSCHQOS_6_1		(DBSC_BASE + 0x1094U)
+#define DBSC_DBSCHQOS_6_2		(DBSC_BASE + 0x1098U)
+#define DBSC_DBSCHQOS_6_3		(DBSC_BASE + 0x109CU)
+#define DBSC_DBSCHQOS_7_0		(DBSC_BASE + 0x10A0U)
+#define DBSC_DBSCHQOS_7_1		(DBSC_BASE + 0x10A4U)
+#define DBSC_DBSCHQOS_7_2		(DBSC_BASE + 0x10A8U)
+#define DBSC_DBSCHQOS_7_3		(DBSC_BASE + 0x10ACU)
+#define DBSC_DBSCHQOS_8_0		(DBSC_BASE + 0x10B0U)
+#define DBSC_DBSCHQOS_8_1		(DBSC_BASE + 0x10B4U)
+#define DBSC_DBSCHQOS_8_2		(DBSC_BASE + 0x10B8U)
+#define DBSC_DBSCHQOS_8_3		(DBSC_BASE + 0x10BCU)
+#define DBSC_DBSCHQOS_9_0		(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS_9_1		(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS_9_2		(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS_9_3		(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS_10_0		(DBSC_BASE + 0x10D0U)
+#define DBSC_DBSCHQOS_10_1		(DBSC_BASE + 0x10D4U)
+#define DBSC_DBSCHQOS_10_2		(DBSC_BASE + 0x10D8U)
+#define DBSC_DBSCHQOS_10_3		(DBSC_BASE + 0x10DCU)
+#define DBSC_DBSCHQOS_11_0		(DBSC_BASE + 0x10E0U)
+#define DBSC_DBSCHQOS_11_1		(DBSC_BASE + 0x10E4U)
+#define DBSC_DBSCHQOS_11_2		(DBSC_BASE + 0x10E8U)
+#define DBSC_DBSCHQOS_11_3		(DBSC_BASE + 0x10ECU)
+#define DBSC_DBSCHQOS_12_0		(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS_12_1		(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS_12_2		(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS_12_3		(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS_13_0		(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS_13_1		(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS_13_2		(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS_13_3		(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS_14_0		(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS_14_1		(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS_14_2		(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS_14_3		(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS_15_0		(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS_15_1		(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS_15_2		(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS_15_3		(DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST2			(DBSC_BASE + 0x170CU)
+
+#define	AXI_BASE			(0xE6784000U)
+#define	AXI_ADSPLCR0			(AXI_BASE + 0x0008U)
+#define	AXI_ADSPLCR1			(AXI_BASE + 0x000CU)
+#define	AXI_ADSPLCR2			(AXI_BASE + 0x0010U)
+#define	AXI_ADSPLCR3			(AXI_BASE + 0x0014U)
+#define	ADSPLCR0_ADRMODE_DEFAULT	((uint32_t)0U << 31U)
+#define	ADSPLCR0_ADRMODE_GEN2		((uint32_t)1U << 31U)
+#define	ADSPLCR0_SPLITSEL(x)		((uint32_t)(x) << 16U)
+#define	ADSPLCR0_AREA(x)		((uint32_t)(x) <<  8U)
+#define	ADSPLCR0_SWP			(0x0CU)
+
+#define	MSTAT_BASE			(0xE67E0000U)
+#define	MSTAT_FIX_QOS_BANK0		(MSTAT_BASE + 0x0000U)
+#define	MSTAT_FIX_QOS_BANK1		(MSTAT_BASE + 0x1000U)
+#define	MSTAT_BE_QOS_BANK0		(MSTAT_BASE + 0x2000U)
+#define	MSTAT_BE_QOS_BANK1		(MSTAT_BASE + 0x3000U)
+#define	MSTAT_SL_INIT			(MSTAT_BASE + 0x8000U)
+#define	MSTAT_REF_ARS			(MSTAT_BASE + 0x8004U)
+#define	MSTAT_STATQC			(MSTAT_BASE + 0x8008U)
+
+#define	RALLOC_BASE			(0xE67F0000U)
+#define	RALLOC_RAS			(RALLOC_BASE + 0x0000U)
+#define	RALLOC_FIXTH			(RALLOC_BASE + 0x0004U)
+#define	RALLOC_RAEN			(RALLOC_BASE + 0x0018U)
+#define	RALLOC_REGGD			(RALLOC_BASE + 0x0020U)
+#define	RALLOC_DANN			(RALLOC_BASE + 0x0030U)
+#define	RALLOC_DANT			(RALLOC_BASE + 0x0038U)
+#define	RALLOC_EC			(RALLOC_BASE + 0x003CU)
+#define	RALLOC_EMS			(RALLOC_BASE + 0x0040U)
+#define	RALLOC_FSS			(RALLOC_BASE + 0x0048U)
+#define	RALLOC_INSFC			(RALLOC_BASE + 0x0050U)
+#define	RALLOC_BERR			(RALLOC_BASE + 0x0054U)
+#define	RALLOC_RACNT0			(RALLOC_BASE + 0x0080U)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+static const mstat_slot_t mstat_fix[] = {
+	{0x0000U, 0x0000000000000000UL},
+	{0x0008U, 0x0000000000000000UL},
+	{0x0010U, 0x0000000000000000UL},
+	{0x0018U, 0x0000000000000000UL},
+	{0x0020U, 0x0000000000000000UL},
+	{0x0028U, 0x0000000000000000UL},
+	{0x0030U, 0x001004030000FFFFUL},
+	{0x0038U, 0x001004030000FFFFUL},
+	{0x0040U, 0x001414090000FFFFUL},
+	{0x0048U, 0x0000000000000000UL},
+	{0x0050U, 0x001410010000FFFFUL},
+	{0x0058U, 0x00140C090000FFFFUL},
+	{0x0060U, 0x00140C090000FFFFUL},
+	{0x0068U, 0x0000000000000000UL},
+	{0x0070U, 0x001410010000FFFFUL},
+	{0x0078U, 0x001004020000FFFFUL},
+	{0x0080U, 0x0000000000000000UL},
+	{0x0088U, 0x001414090000FFFFUL},
+	{0x0090U, 0x001408060000FFFFUL},
+	{0x0098U, 0x0000000000000000UL},
+	{0x00A0U, 0x000C08020000FFFFUL},
+	{0x00A8U, 0x000C04010000FFFFUL},
+	{0x00B0U, 0x000C04010000FFFFUL},
+	{0x00B8U, 0x0000000000000000UL},
+	{0x00C0U, 0x000C08020000FFFFUL},
+	{0x00C8U, 0x000C04010000FFFFUL},
+	{0x00D0U, 0x000C04010000FFFFUL},
+	{0x00D8U, 0x000C04030000FFFFUL},
+	{0x00E0U, 0x000C100F0000FFFFUL},
+	{0x00E8U, 0x0000000000000000UL},
+	{0x00F0U, 0x001010080000FFFFUL},
+	{0x00F8U, 0x0000000000000000UL},
+	{0x0100U, 0x0000000000000000UL},
+	{0x0108U, 0x0000000000000000UL},
+	{0x0110U, 0x001010080000FFFFUL},
+	{0x0118U, 0x0000000000000000UL},
+	{0x0120U, 0x0000000000000000UL},
+	{0x0128U, 0x0000000000000000UL},
+	{0x0130U, 0x0000000000000000UL},
+	{0x0138U, 0x00100C0A0000FFFFUL},
+	{0x0140U, 0x0000000000000000UL},
+	{0x0148U, 0x0000000000000000UL},
+	{0x0150U, 0x00100C0A0000FFFFUL},
+	{0x0158U, 0x0000000000000000UL},
+	{0x0160U, 0x00100C0A0000FFFFUL},
+	{0x0168U, 0x0000000000000000UL},
+	{0x0170U, 0x0000000000000000UL},
+	{0x0178U, 0x001008050000FFFFUL},
+	{0x0180U, 0x0000000000000000UL},
+	{0x0188U, 0x0000000000000000UL},
+	{0x0190U, 0x001028280000FFFFUL},
+	{0x0198U, 0x0000000000000000UL},
+	{0x01A0U, 0x00100C0A0000FFFFUL},
+	{0x01A8U, 0x0000000000000000UL},
+	{0x01B0U, 0x0000000000000000UL},
+	{0x01B8U, 0x0000000000000000UL},
+	{0x01C0U, 0x0000000000000000UL},
+	{0x01C8U, 0x0000000000000000UL},
+	{0x01D0U, 0x0000000000000000UL},
+	{0x01D8U, 0x0000000000000000UL},
+	{0x01E0U, 0x0000000000000000UL},
+	{0x01E8U, 0x0000000000000000UL},
+	{0x01F0U, 0x0000000000000000UL},
+	{0x01F8U, 0x0000000000000000UL},
+	{0x0200U, 0x0000000000000000UL},
+	{0x0208U, 0x0000000000000000UL},
+	{0x0210U, 0x0000000000000000UL},
+	{0x0218U, 0x0000000000000000UL},
+	{0x0220U, 0x0000000000000000UL},
+	{0x0228U, 0x0000000000000000UL},
+	{0x0230U, 0x0000000000000000UL},
+	{0x0238U, 0x0000000000000000UL},
+	{0x0240U, 0x0000000000000000UL},
+	{0x0248U, 0x0000000000000000UL},
+	{0x0250U, 0x0000000000000000UL},
+	{0x0258U, 0x0000000000000000UL},
+	{0x0260U, 0x0000000000000000UL},
+	{0x0268U, 0x001408010000FFFFUL},
+	{0x0270U, 0x001404010000FFFFUL},
+	{0x0278U, 0x0000000000000000UL},
+	{0x0280U, 0x0000000000000000UL},
+	{0x0288U, 0x0000000000000000UL},
+	{0x0290U, 0x001408010000FFFFUL},
+	{0x0298U, 0x001404010000FFFFUL},
+	{0x02A0U, 0x000C04010000FFFFUL},
+	{0x02A8U, 0x000C04010000FFFFUL},
+	{0x02B0U, 0x001404010000FFFFUL},
+	{0x02B8U, 0x0000000000000000UL},
+	{0x02C0U, 0x0000000000000000UL},
+	{0x02C8U, 0x0000000000000000UL},
+	{0x02D0U, 0x000C04010000FFFFUL},
+	{0x02D8U, 0x000C04010000FFFFUL},
+	{0x02E0U, 0x001404010000FFFFUL},
+	{0x02E8U, 0x0000000000000000UL},
+	{0x02F0U, 0x0000000000000000UL},
+	{0x02F8U, 0x0000000000000000UL},
+	{0x0300U, 0x0000000000000000UL},
+	{0x0308U, 0x0000000000000000UL},
+	{0x0310U, 0x0000000000000000UL},
+	{0x0318U, 0x0000000000000000UL},
+	{0x0320U, 0x0000000000000000UL},
+	{0x0328U, 0x0000000000000000UL},
+	{0x0330U, 0x0000000000000000UL},
+	{0x0338U, 0x0000000000000000UL},
+	{0x0340U, 0x0000000000000000UL},
+	{0x0348U, 0x0000000000000000UL},
+	{0x0350U, 0x0000000000000000UL},
+};
+
+static const mstat_slot_t mstat_be[] = {
+	{0x0000U, 0x001200100C89C401UL},
+	{0x0008U, 0x001200100C89C401UL},
+	{0x0010U, 0x001200100C89C401UL},
+	{0x0018U, 0x001200100C89C401UL},
+	{0x0020U, 0x0000000000000000UL},
+	{0x0028U, 0x001100100C803401UL},
+	{0x0030U, 0x0000000000000000UL},
+	{0x0038U, 0x0000000000000000UL},
+	{0x0040U, 0x0000000000000000UL},
+	{0x0048U, 0x0000000000000000UL},
+	{0x0050U, 0x0000000000000000UL},
+	{0x0058U, 0x0000000000000000UL},
+	{0x0060U, 0x0000000000000000UL},
+	{0x0068U, 0x0000000000000000UL},
+	{0x0070U, 0x0000000000000000UL},
+	{0x0078U, 0x0000000000000000UL},
+	{0x0080U, 0x0000000000000000UL},
+	{0x0088U, 0x0000000000000000UL},
+	{0x0090U, 0x0000000000000000UL},
+	{0x0098U, 0x0000000000000000UL},
+	{0x00A0U, 0x0000000000000000UL},
+	{0x00A8U, 0x0000000000000000UL},
+	{0x00B0U, 0x0000000000000000UL},
+	{0x00B8U, 0x0000000000000000UL},
+	{0x00C0U, 0x0000000000000000UL},
+	{0x00C8U, 0x0000000000000000UL},
+	{0x00D0U, 0x0000000000000000UL},
+	{0x00D8U, 0x0000000000000000UL},
+	{0x00E0U, 0x0000000000000000UL},
+	{0x00E8U, 0x0000000000000000UL},
+	{0x00F0U, 0x0000000000000000UL},
+	{0x00F8U, 0x0000000000000000UL},
+	{0x0100U, 0x0000000000000000UL},
+	{0x0108U, 0x0000000000000000UL},
+	{0x0110U, 0x0000000000000000UL},
+	{0x0118U, 0x0000000000000000UL},
+	{0x0120U, 0x0000000000000000UL},
+	{0x0128U, 0x0000000000000000UL},
+	{0x0130U, 0x0000000000000000UL},
+	{0x0138U, 0x0000000000000000UL},
+	{0x0140U, 0x0000000000000000UL},
+	{0x0148U, 0x0000000000000000UL},
+	{0x0150U, 0x0000000000000000UL},
+	{0x0158U, 0x0000000000000000UL},
+	{0x0160U, 0x0000000000000000UL},
+	{0x0168U, 0x0000000000000000UL},
+	{0x0170U, 0x0000000000000000UL},
+	{0x0178U, 0x0000000000000000UL},
+	{0x0180U, 0x0000000000000000UL},
+	{0x0188U, 0x0000000000000000UL},
+	{0x0190U, 0x0000000000000000UL},
+	{0x0198U, 0x0000000000000000UL},
+	{0x01A0U, 0x0000000000000000UL},
+	{0x01A8U, 0x0000000000000000UL},
+	{0x01B0U, 0x0000000000000000UL},
+	{0x01B8U, 0x0000000000000000UL},
+	{0x01C0U, 0x001100500C8FFC01UL},
+	{0x01C8U, 0x001100500C8FFC01UL},
+	{0x01D0U, 0x001100500C8FFC01UL},
+	{0x01D8U, 0x001100500C8FFC01UL},
+	{0x01E0U, 0x0000000000000000UL},
+	{0x01E8U, 0x001200100C803401UL},
+	{0x01F0U, 0x001100100C80FC01UL},
+	{0x01F8U, 0x0000000000000000UL},
+	{0x0200U, 0x0000000000000000UL},
+	{0x0208U, 0x001200100C80FC01UL},
+	{0x0210U, 0x001100100C80FC01UL},
+	{0x0218U, 0x001100100C825801UL},
+	{0x0220U, 0x001100100C825801UL},
+	{0x0228U, 0x0000000000000000UL},
+	{0x0230U, 0x001100100C825801UL},
+	{0x0238U, 0x001100100C825801UL},
+	{0x0240U, 0x001200100C8BB801UL},
+	{0x0248U, 0x001100100C8EA401UL},
+	{0x0250U, 0x001200100C8BB801UL},
+	{0x0258U, 0x001100100C8EA401UL},
+	{0x0260U, 0x001100100C84E401UL},
+	{0x0268U, 0x0000000000000000UL},
+	{0x0270U, 0x0000000000000000UL},
+	{0x0278U, 0x001100100C81F401UL},
+	{0x0280U, 0x0000000000000000UL},
+	{0x0288U, 0x0000000000000000UL},
+	{0x0290U, 0x0000000000000000UL},
+	{0x0298U, 0x0000000000000000UL},
+	{0x02A0U, 0x0000000000000000UL},
+	{0x02A8U, 0x0000000000000000UL},
+	{0x02B0U, 0x0000000000000000UL},
+	{0x02B8U, 0x001100100C803401UL},
+	{0x02C0U, 0x0000000000000000UL},
+	{0x02C8U, 0x0000000000000000UL},
+	{0x02D0U, 0x0000000000000000UL},
+	{0x02D8U, 0x0000000000000000UL},
+	{0x02E0U, 0x0000000000000000UL},
+	{0x02E8U, 0x001100100C803401UL},
+	{0x02F0U, 0x001100300C8FFC01UL},
+	{0x02F8U, 0x001100500C8FFC01UL},
+	{0x0300U, 0x0000000000000000UL},
+	{0x0308U, 0x001100300C8FFC01UL},
+	{0x0310U, 0x001100500C8FFC01UL},
+	{0x0318U, 0x001200100C803401UL},
+	{0x0320U, 0x0000000000000000UL},
+	{0x0328U, 0x0000000000000000UL},
+	{0x0330U, 0x0000000000000000UL},
+	{0x0338U, 0x0000000000000000UL},
+	{0x0340U, 0x0000000000000000UL},
+	{0x0348U, 0x0000000000000000UL},
+	{0x0350U, 0x0000000000000000UL},
+};
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md = 0;
+
+	/* BUFCAM settings */
+	/* DBSC_DBCAM0CNF0 not set */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218);	/* dbcam0cnf1 */
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);	/* dbcam0cnf2 */
+	io_write_32(DBSC_DBCAM0CNF3, 0x00000000);	/* dbcam0cnf3 */
+	io_write_32(DBSC_DBSCHCNT0, 0x080F0037);	/* dbschcnt0 */
+	/* DBSC_DBSCHCNT1 not set */
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001);	/* dbschsz0 */
+	io_write_32(DBSC_DBSCHRW0, 0x22421111);	/* dbschrw0 */
+
+	md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
+
+	switch (md) {
+	case 0x0:
+		/* DDR3200 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x1:		/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
+		/* DDR2800 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x4:		/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
+		/* DDR2400 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	default:		/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00);
+	io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00);
+	io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000);
+	io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000);
+	/* DBSC_DBSCHQOS_1_0 not set */
+	/* DBSC_DBSCHQOS_1_1 not set */
+	/* DBSC_DBSCHQOS_1_2 not set */
+	/* DBSC_DBSCHQOS_1_3 not set */
+	/* DBSC_DBSCHQOS_2_0 not set */
+	/* DBSC_DBSCHQOS_2_1 not set */
+	/* DBSC_DBSCHQOS_2_2 not set */
+	/* DBSC_DBSCHQOS_2_3 not set */
+	/* DBSC_DBSCHQOS_3_0 not set */
+	/* DBSC_DBSCHQOS_3_1 not set */
+	/* DBSC_DBSCHQOS_3_2 not set */
+	/* DBSC_DBSCHQOS_3_3 not set */
+	io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300);
+	io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0);
+	io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200);
+	io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100);
+	/* DBSC_DBSCHQOS_5_0 not set */
+	/* DBSC_DBSCHQOS_5_1 not set */
+	/* DBSC_DBSCHQOS_5_2 not set */
+	/* DBSC_DBSCHQOS_5_3 not set */
+	/* DBSC_DBSCHQOS_6_0 not set */
+	/* DBSC_DBSCHQOS_6_1 not set */
+	/* DBSC_DBSCHQOS_6_2 not set */
+	/* DBSC_DBSCHQOS_6_3 not set */
+	/* DBSC_DBSCHQOS_7_0 not set */
+	/* DBSC_DBSCHQOS_7_1 not set */
+	/* DBSC_DBSCHQOS_7_2 not set */
+	/* DBSC_DBSCHQOS_7_3 not set */
+	/* DBSC_DBSCHQOS_8_0 not set */
+	/* DBSC_DBSCHQOS_8_1 not set */
+	/* DBSC_DBSCHQOS_8_2 not set */
+	/* DBSC_DBSCHQOS_8_3 not set */
+	io_write_32(DBSC_DBSCHQOS_9_0, 0x00000300);
+	io_write_32(DBSC_DBSCHQOS_9_1, 0x000002F0);
+	io_write_32(DBSC_DBSCHQOS_9_2, 0x00000200);
+	io_write_32(DBSC_DBSCHQOS_9_3, 0x00000100);
+	/* DBSC_DBSCHQOS_10_0 not set */
+	/* DBSC_DBSCHQOS_10_1 not set */
+	/* DBSC_DBSCHQOS_10_2 not set */
+	/* DBSC_DBSCHQOS_10_3 not set */
+	/* DBSC_DBSCHQOS_11_0 not set */
+	/* DBSC_DBSCHQOS_11_1 not set */
+	/* DBSC_DBSCHQOS_11_2 not set */
+	/* DBSC_DBSCHQOS_11_3 not set */
+	/* DBSC_DBSCHQOS_12_0 not set */
+	/* DBSC_DBSCHQOS_12_1 not set */
+	/* DBSC_DBSCHQOS_12_2 not set */
+	/* DBSC_DBSCHQOS_12_3 not set */
+	io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0);
+	io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0);
+	io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080);
+	io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030);
+	io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020);
+	io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010);
+}
+
+void qos_init_m3_v10(void)
+{
+	dbsc_setting();
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_M3
+#error "Don't set DRAM Split 4ch(M3)"
+#else
+	ERROR("DRAM Split 4ch not supported.(M3)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+      (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 2ch\n");
+	io_write_32(AXI_ADSPLCR0, 0x00000000U);
+	io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1CU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR2, 0x089A0000U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_RAS, 0x00000028U);
+	io_write_32(RALLOC_FIXTH, 0x000F0005U);
+	io_write_32(RALLOC_REGGD, 0x00000000U);
+	io_write_64(RALLOC_DANN, 0x0101010102020201UL);
+	io_write_32(RALLOC_DANT, 0x00100804U);
+	io_write_32(RALLOC_EC, 0x00000000U);
+	io_write_64(RALLOC_EMS, 0x0000000000000000UL);
+	io_write_32(RALLOC_FSS, 0x000003e8U);
+	io_write_32(RALLOC_INSFC, 0xC7840001U);
+	io_write_32(RALLOC_BERR, 0x00000000U);
+	io_write_32(RALLOC_RACNT0, 0x00000000U);
+
+	/* MSTAT setting */
+	io_write_32(MSTAT_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
+	io_write_32(MSTAT_REF_ARS, 0x00330000U);
+
+	/* MSTAT SRAM setting */
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr,
+				    mstat_fix[i].value);
+			io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr,
+				    mstat_fix[i].value);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr,
+				    mstat_be[i].value);
+			io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr,
+				    mstat_be[i].value);
+		}
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(0xFD820808U, 0x00001234U);
+	io_write_32(0xFD820800U, 0x00000006U);
+	io_write_32(0xFD821800U, 0x00000006U);
+	io_write_32(0xFD822800U, 0x00000006U);
+	io_write_32(0xFD823800U, 0x00000006U);
+	io_write_32(0xFD824800U, 0x00000006U);
+	io_write_32(0xFD825800U, 0x00000006U);
+	io_write_32(0xFD826800U, 0x00000006U);
+	io_write_32(0xFD827800U, 0x00000006U);
+
+	/* RT bus Leaf setting */
+	io_write_32(0xFFC50800U, 0x00000000U);
+	io_write_32(0xFFC51800U, 0x00000000U);
+
+	/* Resource Alloc start */
+	io_write_32(RALLOC_RAEN, 0x00000001U);
+
+	/* MSTAT start */
+	io_write_32(MSTAT_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	/* Resource Alloc setting */
+	io_write_32(RALLOC_EC, 0x00000000U);
+	/* Resource Alloc start */
+	io_write_32(RALLOC_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h
new file mode 100644
index 0000000..8371075
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_M3_V10__
+#define QOS_INIT_H_M3_V10__
+
+void qos_init_m3_v10(void);
+
+#endif /* QOS_INIT_H_M3_V10__ */
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
new file mode 100644
index 0000000..fc0d2cc
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_m3_v11.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.17"
+
+#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+
+#define	QOSWT_WTEN_ENABLE				(0x1U)
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11	(SL_INIT_SSLOTCLK_M3_11 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
+#define WT_BASE_SUB_SLOT_NUM0			(12U)
+#define QOSWT_WTSET0_PERIOD0_M3_11		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
+#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3_11		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_11)-1U)
+#define QOSWT_WTSET1_SSLOT1				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET1_SLOTSLOT1			(WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v11_mstat195.h"
+#else
+#include "qos_init_m3_v11_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v11_qoswt195.h"
+#else
+#include "qos_init_m3_v11_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md = 0;
+
+	/* BUFCAM settings */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218);	/* dbcam0cnf1 */
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);	/* dbcam0cnf2 */
+	io_write_32(DBSC_DBCAM0CNF3, 0x00000000);	/* dbcam0cnf3 */
+	io_write_32(DBSC_DBSCHCNT0, 0x000F0037);	/* dbschcnt0 */
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001);	/* dbschsz0 */
+	io_write_32(DBSC_DBSCHRW0, 0x22421111);	/* dbschrw0 */
+
+	md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
+
+	switch (md) {
+	case 0x0:
+		/* DDR3200 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x1:		/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
+		/* DDR2800 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x4:		/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
+		/* DDR2400 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	default:		/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+	io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+	io_write_32(DBSC_DBSCHQOS02, 0x00000000);
+	io_write_32(DBSC_DBSCHQOS03, 0x00000000);
+	io_write_32(DBSC_DBSCHQOS40, 0x00000300);
+	io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+	io_write_32(DBSC_DBSCHQOS42, 0x00000200);
+	io_write_32(DBSC_DBSCHQOS43, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS90, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS93, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS120, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS121, 0x00000030);
+	io_write_32(DBSC_DBSCHQOS122, 0x00000020);
+	io_write_32(DBSC_DBSCHQOS123, 0x00000010);
+	io_write_32(DBSC_DBSCHQOS130, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS133, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+	io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+	io_write_32(DBSC_DBSCHQOS142, 0x00000080);
+	io_write_32(DBSC_DBSCHQOS143, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS150, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS151, 0x00000030);
+	io_write_32(DBSC_DBSCHQOS152, 0x00000020);
+	io_write_32(DBSC_DBSCHQOS153, 0x00000010);
+}
+
+void qos_init_m3_v11(void)
+{
+	dbsc_setting();
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_M3
+#error "Don't set DRAM Split 4ch(M3)"
+#else
+	ERROR("DRAM Split 4ch not supported.(M3)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+      (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+	NOTICE("BL2: DRAM Split is 2ch\n");
+	io_write_32(AXI_ADSPLCR0, 0x00000000U);
+	io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+		    | ADSPLCR0_SPLITSEL(0xFFU)
+		    | ADSPLCR0_AREA(0x1CU)
+		    | ADSPLCR0_SWP);
+	io_write_32(AXI_ADSPLCR2, 0x00001004U);
+	io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_RAS, 0x00000044U);
+	io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+	io_write_32(QOSCTRL_DANT, 0x0020100AU);
+	io_write_32(QOSCTRL_INSFC, 0x06330001U);
+	io_write_32(QOSCTRL_RACNT0, 0x02010003U);	/* GPU Boost Mode ON */
+
+	io_write_32(QOSCTRL_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+		    SL_INIT_SSLOTCLK_M3_11);
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	io_write_32(QOSCTRL_REF_ARS,
+		    ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_11 << 16)));
+#else
+	io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+		}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+		for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+			io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+				    qoswt_fix[i]);
+			io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+				    qoswt_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+			io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+			io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+		}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(GPU_ACT_GRD, 0x00001234U);
+	io_write_32(GPU_ACT0, 0x00000000U);
+	io_write_32(GPU_ACT1, 0x00000000U);
+	io_write_32(GPU_ACT2, 0x00000000U);
+	io_write_32(GPU_ACT3, 0x00000000U);
+
+	/* RT bus Leaf setting */
+	io_write_32(RT_ACT0, 0x00000000U);
+	io_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	io_write_32(CPU_ACT0, 0x00000003U);
+	io_write_32(CPU_ACT1, 0x00000003U);
+	io_write_32(CPU_ACT2, 0x00000003U);
+	io_write_32(CPU_ACT3, 0x00000003U);
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	io_write_32(QOSWT_WTREF,
+		    ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	io_write_32(QOSWT_WTSET0,
+		    ((QOSWT_WTSET0_PERIOD0_M3_11 << 16) |
+		     (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	io_write_32(QOSWT_WTSET1,
+		    ((QOSWT_WTSET1_PERIOD1_M3_11 << 16) |
+		     (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h
new file mode 100644
index 0000000..6e3bc57
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_M3_V11__
+#define QOS_INIT_H_M3_V11__
+
+void qos_init_m3_v11(void);
+
+#endif /* QOS_INIT_H_M3_V11__ */
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
new file mode 100644
index 0000000..d7e7777
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat195.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000FFFFUL,
+	/* 0x0038, */ 0x001004040000FFFFUL,
+	/* 0x0040, */ 0x001414090000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x00140C0A0000FFFFUL,
+	/* 0x0060, */ 0x00140C0A0000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x001004030000FFFFUL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001414090000FFFFUL,
+	/* 0x0090, */ 0x001408070000FFFFUL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C04020000FFFFUL,
+	/* 0x00a8, */ 0x000C04010000FFFFUL,
+	/* 0x00b0, */ 0x000C04010000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C04020000FFFFUL,
+	/* 0x00c8, */ 0x000C04010000FFFFUL,
+	/* 0x00d0, */ 0x000C04010000FFFFUL,
+	/* 0x00d8, */ 0x000C08050000FFFFUL,
+	/* 0x00e0, */ 0x000C14120000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001024090000FFFFUL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100C090000FFFFUL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100C0B0000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0010100D0000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x00100C0B0000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008060000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00102C2C0000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x00100C0B0000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFFFUL,
+	/* 0x0268, */ 0x001408010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C04010000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x001408010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x001408010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x001200200BDFFC01UL,
+	/* 0x0008, */ 0x001200200BDFFC01UL,
+	/* 0x0010, */ 0x001200200BDFFC01UL,
+	/* 0x0018, */ 0x001200200BDFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100600BDFFC01UL,
+	/* 0x01c8, */ 0x002100600BDFFC01UL,
+	/* 0x01d0, */ 0x002100600BDFFC01UL,
+	/* 0x01d8, */ 0x002100600BDFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x002100200BDFFC01UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x002100200BDFFC01UL,
+	/* 0x0218, */ 0x001100200BDFFC01UL,
+	/* 0x0220, */ 0x001100200BDFFC01UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001100200BDFFC01UL,
+	/* 0x0238, */ 0x001100200BDFFC01UL,
+	/* 0x0240, */ 0x001200200BDFFC01UL,
+	/* 0x0248, */ 0x001100200BDFFC01UL,
+	/* 0x0250, */ 0x001200200BDFFC01UL,
+	/* 0x0258, */ 0x001100200BDFFC01UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001100400BDFFC01UL,
+	/* 0x02f8, */ 0x001100600BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x001100400BDFFC01UL,
+	/* 0x0310, */ 0x001100600BDFFC01UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
new file mode 100644
index 0000000..a9520c3
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_mstat390.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000FFFFUL,
+	/* 0x0038, */ 0x001008070000FFFFUL,
+	/* 0x0040, */ 0x001424120000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404010000FFFFUL,
+	/* 0x0058, */ 0x001414130000FFFFUL,
+	/* 0x0060, */ 0x001414130000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404010000FFFFUL,
+	/* 0x0078, */ 0x001008050000FFFFUL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001424120000FFFFUL,
+	/* 0x0090, */ 0x0014100D0000FFFFUL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08040000FFFFUL,
+	/* 0x00a8, */ 0x000C04020000FFFFUL,
+	/* 0x00b0, */ 0x000C04020000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08040000FFFFUL,
+	/* 0x00c8, */ 0x000C04020000FFFFUL,
+	/* 0x00d0, */ 0x000C04020000FFFFUL,
+	/* 0x00d8, */ 0x000C0C0A0000FFFFUL,
+	/* 0x00e0, */ 0x000C24230000FFFFUL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001044110000FFFFUL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001014110000FFFFUL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x001018150000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101C190000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x001018150000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100C0B0000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001058570000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x001018150000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x000C04010000FFFFUL,
+	/* 0x01d8, */ 0x000C04010000FFFFUL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04010000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04010000FFFFUL,
+	/* 0x0210, */ 0x000C04010000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFFFUL,
+	/* 0x0268, */ 0x001410010000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C08020000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04010000FFFFUL,
+	/* 0x02a8, */ 0x000C04010000FFFFUL,
+	/* 0x02b0, */ 0x00140C010000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04010000FFFFUL,
+	/* 0x02d8, */ 0x000C04010000FFFFUL,
+	/* 0x02e0, */ 0x00140C010000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0012003005EFFC01UL,
+	/* 0x0008, */ 0x0012003005EFFC01UL,
+	/* 0x0010, */ 0x0012003005EFFC01UL,
+	/* 0x0018, */ 0x0012003005EFFC01UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002100B005EFFC01UL,
+	/* 0x01c8, */ 0x002100B005EFFC01UL,
+	/* 0x01d0, */ 0x002100B005EFFC01UL,
+	/* 0x01d8, */ 0x002100B005EFFC01UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021003005EFFC01UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021003005EFFC01UL,
+	/* 0x0218, */ 0x0011003005EFFC01UL,
+	/* 0x0220, */ 0x0011003005EFFC01UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011003005EFFC01UL,
+	/* 0x0238, */ 0x0011003005EFFC01UL,
+	/* 0x0240, */ 0x0012003005EFFC01UL,
+	/* 0x0248, */ 0x0011003005EFFC01UL,
+	/* 0x0250, */ 0x0012003005EFFC01UL,
+	/* 0x0258, */ 0x0011003005EFFC01UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011007005EFFC01UL,
+	/* 0x02f8, */ 0x001100B005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0011007005EFFC01UL,
+	/* 0x0310, */ 0x001100B005EFFC01UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
new file mode 100644
index 0000000..04c7efd
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt195.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004040000C010UL,
+	/* 0x0038, */ 0x001004040000C010UL,
+	/* 0x0040, */ 0x001414090000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00140C0A0000C010UL,
+	/* 0x0060, */ 0x00140C0A0000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x001004030000C010UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001414090000FFF0UL,
+	/* 0x0090, */ 0x001408070000C010UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08020000FFF0UL,
+	/* 0x0268, */ 0x001408010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04010000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
new file mode 100644
index 0000000..73f81f5
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11_qoswt390.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008070000C010UL,
+	/* 0x0038, */ 0x001008070000C010UL,
+	/* 0x0040, */ 0x001424120000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001414130000C010UL,
+	/* 0x0060, */ 0x001414130000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x001008050000C010UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x001424120000FFF0UL,
+	/* 0x0090, */ 0x0014100D0000C010UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C030000FFF0UL,
+	/* 0x0268, */ 0x001410010000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C08020000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410010000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
new file mode 100644
index 0000000..e9d6676
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_m3n_v10.h"
+
+#define	RCAR_QOS_VERSION		"rev.0.06"
+
+#define QOSCTRL_EARLYR			(QOS_BASE1 + 0x0060U)
+#define QOSCTRL_FSS			(QOS_BASE1 + 0x0048U)
+
+#define REF_ARS_ARBSTOPCYCLE_M3N	(((SL_INIT_SSLOTCLK_M3N) - 5U) << 16U)
+
+#define QOSWT_TIME_BANK0				(20000000U)	/* unit:ns */
+
+#define	QOSWT_WTEN_ENABLE				(0x1U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT	(3U)
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT	(9U)
+#define QOSWT_WTREF_SLOT0_EN			((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN			QOSWT_WTREF_SLOT0_EN
+
+#define QOSWT_WTSET0_REQ_SSLOT0			(5U)
+#define WT_BASE_SUB_SLOT_NUM0			(12U)
+#define QOSWT_WTSET0_PERIOD0_M3N		((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3N)-1U)
+#define QOSWT_WTSET0_SSLOT0				(QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET0_SLOTSLOT0			(WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3N		QOSWT_WTSET0_PERIOD0_M3N
+#define QOSWT_WTSET1_SSLOT1				QOSWT_WTSET0_SSLOT0
+#define QOSWT_WTSET1_SLOTSLOT1			QOSWT_WTSET0_SLOTSLOT0
+
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3n_v10_mstat195.h"
+#else
+#include "qos_init_m3n_v10_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3n_v10_qoswt195.h"
+#else
+#include "qos_init_m3n_v10_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+static void dbsc_setting(void)
+{
+	uint32_t md = 0;
+
+	/* Register write enable */
+	io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+
+	/* BUFCAM settings */
+	io_write_32(DBSC_DBCAM0CNF1, 0x00043218);	/* dbcam0cnf1 */
+	io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);	/* dbcam0cnf2 */
+	io_write_32(DBSC_DBSCHCNT0, 0x000F0037);	/* dbschcnt0 */
+	io_write_32(DBSC_DBSCHSZ0, 0x00000001);	/* dbschsz0 */
+	io_write_32(DBSC_DBSCHRW0, 0x22421111);	/* dbschrw0 */
+
+	md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
+
+	switch (md) {
+	case 0x0:
+		/* DDR3200 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x1:		/* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
+		/* DDR2800 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	case 0x4:		/* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
+		/* DDR2400 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	default:		/* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
+		/* DDR1600 */
+		io_write_32(DBSC_SCFCTST2, 0x012F1123);
+		break;
+	}
+
+	/* QoS Settings */
+	io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+	io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+	io_write_32(DBSC_DBSCHQOS02, 0x00000000);
+	io_write_32(DBSC_DBSCHQOS03, 0x00000000);
+	io_write_32(DBSC_DBSCHQOS40, 0x00000300);
+	io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+	io_write_32(DBSC_DBSCHQOS42, 0x00000200);
+	io_write_32(DBSC_DBSCHQOS43, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS90, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS93, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS130, 0x00000100);
+	io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+	io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+	io_write_32(DBSC_DBSCHQOS133, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+	io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+	io_write_32(DBSC_DBSCHQOS142, 0x00000080);
+	io_write_32(DBSC_DBSCHQOS143, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS150, 0x00000040);
+	io_write_32(DBSC_DBSCHQOS151, 0x00000030);
+	io_write_32(DBSC_DBSCHQOS152, 0x00000020);
+	io_write_32(DBSC_DBSCHQOS153, 0x00000010);
+
+	/* Register write protect */
+	io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
+}
+
+void qos_init_m3n_v10(void)
+{
+	dbsc_setting();
+
+	/* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_M3N
+#error "Don't set DRAM Split 4ch(M3N)"
+#else
+	ERROR("DRAM Split 4ch not supported.(M3N)");
+	panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RCAR_M3N
+#error "Don't set DRAM Split 2ch(M3N)"
+#else
+	ERROR("DRAM Split 2ch not supported.(M3N)");
+	panic();
+#endif
+#else
+	NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
+	NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+	NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+	NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_RAS, 0x00000028U);
+	io_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
+	io_write_32(QOSCTRL_DANT, 0x00100804U);
+	io_write_32(QOSCTRL_FSS, 0x0000000AU);
+	io_write_32(QOSCTRL_INSFC, 0x06330001U);
+	io_write_32(QOSCTRL_EARLYR, 0x00000001U);
+	io_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+	io_write_32(QOSCTRL_SL_INIT,
+		    SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
+		    SL_INIT_SSLOTCLK_M3N);
+	io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_M3N);
+
+	{
+		uint32_t i;
+
+		for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+			io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
+			io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+			io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
+			io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
+		}
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+		for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+			io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
+				    qoswt_fix[i]);
+			io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
+				    qoswt_fix[i]);
+		}
+		for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+			io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
+			io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
+		}
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+	}
+
+	/* 3DG bus Leaf setting */
+	io_write_32(GPU_ACT_GRD, 0x00001234U);
+	io_write_32(GPU_ACT0, 0x00000000U);
+	io_write_32(GPU_ACT1, 0x00000000U);
+	io_write_32(GPU_ACT2, 0x00000000U);
+	io_write_32(GPU_ACT3, 0x00000000U);
+	io_write_32(GPU_ACT_GRD, 0x00000000U);
+
+	/* RT bus Leaf setting */
+	io_write_32(RT_ACT0, 0x00000000U);
+	io_write_32(RT_ACT1, 0x00000000U);
+
+	/* CCI bus Leaf setting */
+	io_write_32(CPU_ACT0, 0x00000003U);
+	io_write_32(CPU_ACT1, 0x00000003U);
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+	/*  re-write training setting */
+	io_write_32(QOSWT_WTREF,
+		    ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+	io_write_32(QOSWT_WTSET0,
+		    ((QOSWT_WTSET0_PERIOD0_M3N << 16) |
+		     (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+	io_write_32(QOSWT_WTSET1,
+		    ((QOSWT_WTSET1_PERIOD1_M3N << 16) |
+		     (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+	io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+	io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+	NOTICE("BL2: QoS is None\n");
+
+	io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
new file mode 100644
index 0000000..ae7d2e2
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_M3N_V10__
+#define QOS_INIT_H_M3N_V10__
+
+void qos_init_m3n_v10(void);
+
+#endif /* QOS_INIT_H_M3N_V10__ */
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
new file mode 100644
index 0000000..d30e95f
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004320000FFFFUL,
+	/* 0x0038, */ 0x001004320000FFFFUL,
+	/* 0x0040, */ 0x00140C5D0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404040000FFFFUL,
+	/* 0x0058, */ 0x00140C940000FFFFUL,
+	/* 0x0060, */ 0x00140C940000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404040000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014041F0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C041D0000FFFFUL,
+	/* 0x00a8, */ 0x000C04090000FFFFUL,
+	/* 0x00b0, */ 0x000C04090000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C041D0000FFFFUL,
+	/* 0x00c8, */ 0x000C04090000FFFFUL,
+	/* 0x00d0, */ 0x000C04090000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001024840000FFFFUL,
+	/* 0x00f8, */ 0x000C084F0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x00100C840000FFFFUL,
+	/* 0x0118, */ 0x000C21E60000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x00100CA50000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x001010C90000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x00100CA50000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x001008530000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x00101D9D0000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x00100CA50000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04010000FFFFUL,
+	/* 0x01f0, */ 0x000C04050000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04050000FFFFUL,
+	/* 0x0210, */ 0x000C04050000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08150000FFFFUL,
+	/* 0x0268, */ 0x001408020000FFFFUL,
+	/* 0x0270, */ 0x001404010000FFFFUL,
+	/* 0x0278, */ 0x000C04090000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408020000FFFFUL,
+	/* 0x0298, */ 0x001404010000FFFFUL,
+	/* 0x02a0, */ 0x000C04050000FFFFUL,
+	/* 0x02a8, */ 0x000C04050000FFFFUL,
+	/* 0x02b0, */ 0x001408050000FFFFUL,
+	/* 0x02b8, */ 0x000C04010000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04050000FFFFUL,
+	/* 0x02d8, */ 0x000C04050000FFFFUL,
+	/* 0x02e0, */ 0x001408050000FFFFUL,
+	/* 0x02e8, */ 0x000C04010000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04010000FFFFUL,
+	/* 0x0378, */ 0x000C04010000FFFFUL,
+	/* 0x0380, */ 0x000C04050000FFFFUL,
+	/* 0x0388, */ 0x000C04050000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x001200100BD03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x002106000BDFFC01UL,
+	/* 0x01c8, */ 0x002106000BDFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x002101000BDF2401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x002101000BDF2401UL,
+	/* 0x0218, */ 0x001101000BDF2401UL,
+	/* 0x0220, */ 0x001101000BDF2401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x001101000BDF2401UL,
+	/* 0x0238, */ 0x001101000BDF2401UL,
+	/* 0x0240, */ 0x001201000BDF2401UL,
+	/* 0x0248, */ 0x001101000BDF2401UL,
+	/* 0x0250, */ 0x001201000BDF2401UL,
+	/* 0x0258, */ 0x001101000BDF2401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x001106000BDFFC01UL,
+	/* 0x02f8, */ 0x001106000BDFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x001200100BD03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x001206000BDFFC01UL,
+	/* 0x0360, */ 0x001206000BDFFC01UL,
+	/* 0x0368, */ 0x001200100BD03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x001200100BD03401UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
new file mode 100644
index 0000000..0dc37ca
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t mstat_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008630000FFFFUL,
+	/* 0x0038, */ 0x001008630000FFFFUL,
+	/* 0x0040, */ 0x001418BA0000FFFFUL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x001404070000FFFFUL,
+	/* 0x0058, */ 0x001415270000FFFFUL,
+	/* 0x0060, */ 0x001415270000FFFFUL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x001404070000FFFFUL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014083E0000FFFFUL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x000C08390000FFFFUL,
+	/* 0x00a8, */ 0x000C04110000FFFFUL,
+	/* 0x00b0, */ 0x000C04110000FFFFUL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x000C08390000FFFFUL,
+	/* 0x00c8, */ 0x000C04110000FFFFUL,
+	/* 0x00d0, */ 0x000C04110000FFFFUL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x001045080000FFFFUL,
+	/* 0x00f8, */ 0x000C0C9E0000FFFFUL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x001015080000FFFFUL,
+	/* 0x0118, */ 0x000C43CB0000FFFFUL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0010194A0000FFFFUL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x00101D910000FFFFUL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0010194A0000FFFFUL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x00100CA50000FFFFUL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x001037390000FFFFUL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0010194A0000FFFFUL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x000C04010000FFFFUL,
+	/* 0x01c8, */ 0x000C04010000FFFFUL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x000C04020000FFFFUL,
+	/* 0x01f0, */ 0x000C04090000FFFFUL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x000C04090000FFFFUL,
+	/* 0x0210, */ 0x000C04090000FFFFUL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C2A0000FFFFUL,
+	/* 0x0268, */ 0x001410040000FFFFUL,
+	/* 0x0270, */ 0x001404020000FFFFUL,
+	/* 0x0278, */ 0x000C08110000FFFFUL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFFFUL,
+	/* 0x0298, */ 0x001404020000FFFFUL,
+	/* 0x02a0, */ 0x000C04090000FFFFUL,
+	/* 0x02a8, */ 0x000C04090000FFFFUL,
+	/* 0x02b0, */ 0x00140C090000FFFFUL,
+	/* 0x02b8, */ 0x000C04020000FFFFUL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x000C04090000FFFFUL,
+	/* 0x02d8, */ 0x000C04090000FFFFUL,
+	/* 0x02e0, */ 0x00140C090000FFFFUL,
+	/* 0x02e8, */ 0x000C04020000FFFFUL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x000C04020000FFFFUL,
+	/* 0x0378, */ 0x000C04020000FFFFUL,
+	/* 0x0380, */ 0x000C04090000FFFFUL,
+	/* 0x0388, */ 0x000C04090000FFFFUL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0012001005E03401UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0021060005EFFC01UL,
+	/* 0x01c8, */ 0x0021060005EFFC01UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0021010005E79401UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0021010005E79401UL,
+	/* 0x0218, */ 0x0011010005E79401UL,
+	/* 0x0220, */ 0x0011010005E79401UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0011010005E79401UL,
+	/* 0x0238, */ 0x0011010005E79401UL,
+	/* 0x0240, */ 0x0012010005E79401UL,
+	/* 0x0248, */ 0x0011010005E79401UL,
+	/* 0x0250, */ 0x0012010005E79401UL,
+	/* 0x0258, */ 0x0011010005E79401UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0011060005EFFC01UL,
+	/* 0x02f8, */ 0x0011060005EFFC01UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0012001005E03401UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0012060005EFFC01UL,
+	/* 0x0360, */ 0x0012060005EFFC01UL,
+	/* 0x0368, */ 0x0012001005E03401UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0012001005E03401UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
new file mode 100644
index 0000000..d2e8040
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt195.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001004320000C010UL,
+	/* 0x0038, */ 0x001004320000C010UL,
+	/* 0x0040, */ 0x00140C5D0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x00140C940000C010UL,
+	/* 0x0060, */ 0x00140C940000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014041F0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C08150000FFF0UL,
+	/* 0x0268, */ 0x001408020000FFF0UL,
+	/* 0x0270, */ 0x001404010000FFF0UL,
+	/* 0x0278, */ 0x000C04090000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001408020000FFF0UL,
+	/* 0x0298, */ 0x001404010000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
new file mode 100644
index 0000000..84f657a
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_qoswt390.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+static uint64_t qoswt_fix[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x001008630000C010UL,
+	/* 0x0038, */ 0x001008630000C010UL,
+	/* 0x0040, */ 0x001418BA0000FFF0UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x001415270000C010UL,
+	/* 0x0060, */ 0x001415270000C010UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0014083E0000FFF0UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x000C0C2A0000FFF0UL,
+	/* 0x0268, */ 0x001410040000FFF0UL,
+	/* 0x0270, */ 0x001404020000FFF0UL,
+	/* 0x0278, */ 0x000C08110000FFF0UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x001410040000FFF0UL,
+	/* 0x0298, */ 0x001404020000FFF0UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+	/* 0x0000, */ 0x0000000000000000UL,
+	/* 0x0008, */ 0x0000000000000000UL,
+	/* 0x0010, */ 0x0000000000000000UL,
+	/* 0x0018, */ 0x0000000000000000UL,
+	/* 0x0020, */ 0x0000000000000000UL,
+	/* 0x0028, */ 0x0000000000000000UL,
+	/* 0x0030, */ 0x0000000000000000UL,
+	/* 0x0038, */ 0x0000000000000000UL,
+	/* 0x0040, */ 0x0000000000000000UL,
+	/* 0x0048, */ 0x0000000000000000UL,
+	/* 0x0050, */ 0x0000000000000000UL,
+	/* 0x0058, */ 0x0000000000000000UL,
+	/* 0x0060, */ 0x0000000000000000UL,
+	/* 0x0068, */ 0x0000000000000000UL,
+	/* 0x0070, */ 0x0000000000000000UL,
+	/* 0x0078, */ 0x0000000000000000UL,
+	/* 0x0080, */ 0x0000000000000000UL,
+	/* 0x0088, */ 0x0000000000000000UL,
+	/* 0x0090, */ 0x0000000000000000UL,
+	/* 0x0098, */ 0x0000000000000000UL,
+	/* 0x00a0, */ 0x0000000000000000UL,
+	/* 0x00a8, */ 0x0000000000000000UL,
+	/* 0x00b0, */ 0x0000000000000000UL,
+	/* 0x00b8, */ 0x0000000000000000UL,
+	/* 0x00c0, */ 0x0000000000000000UL,
+	/* 0x00c8, */ 0x0000000000000000UL,
+	/* 0x00d0, */ 0x0000000000000000UL,
+	/* 0x00d8, */ 0x0000000000000000UL,
+	/* 0x00e0, */ 0x0000000000000000UL,
+	/* 0x00e8, */ 0x0000000000000000UL,
+	/* 0x00f0, */ 0x0000000000000000UL,
+	/* 0x00f8, */ 0x0000000000000000UL,
+	/* 0x0100, */ 0x0000000000000000UL,
+	/* 0x0108, */ 0x0000000000000000UL,
+	/* 0x0110, */ 0x0000000000000000UL,
+	/* 0x0118, */ 0x0000000000000000UL,
+	/* 0x0120, */ 0x0000000000000000UL,
+	/* 0x0128, */ 0x0000000000000000UL,
+	/* 0x0130, */ 0x0000000000000000UL,
+	/* 0x0138, */ 0x0000000000000000UL,
+	/* 0x0140, */ 0x0000000000000000UL,
+	/* 0x0148, */ 0x0000000000000000UL,
+	/* 0x0150, */ 0x0000000000000000UL,
+	/* 0x0158, */ 0x0000000000000000UL,
+	/* 0x0160, */ 0x0000000000000000UL,
+	/* 0x0168, */ 0x0000000000000000UL,
+	/* 0x0170, */ 0x0000000000000000UL,
+	/* 0x0178, */ 0x0000000000000000UL,
+	/* 0x0180, */ 0x0000000000000000UL,
+	/* 0x0188, */ 0x0000000000000000UL,
+	/* 0x0190, */ 0x0000000000000000UL,
+	/* 0x0198, */ 0x0000000000000000UL,
+	/* 0x01a0, */ 0x0000000000000000UL,
+	/* 0x01a8, */ 0x0000000000000000UL,
+	/* 0x01b0, */ 0x0000000000000000UL,
+	/* 0x01b8, */ 0x0000000000000000UL,
+	/* 0x01c0, */ 0x0000000000000000UL,
+	/* 0x01c8, */ 0x0000000000000000UL,
+	/* 0x01d0, */ 0x0000000000000000UL,
+	/* 0x01d8, */ 0x0000000000000000UL,
+	/* 0x01e0, */ 0x0000000000000000UL,
+	/* 0x01e8, */ 0x0000000000000000UL,
+	/* 0x01f0, */ 0x0000000000000000UL,
+	/* 0x01f8, */ 0x0000000000000000UL,
+	/* 0x0200, */ 0x0000000000000000UL,
+	/* 0x0208, */ 0x0000000000000000UL,
+	/* 0x0210, */ 0x0000000000000000UL,
+	/* 0x0218, */ 0x0000000000000000UL,
+	/* 0x0220, */ 0x0000000000000000UL,
+	/* 0x0228, */ 0x0000000000000000UL,
+	/* 0x0230, */ 0x0000000000000000UL,
+	/* 0x0238, */ 0x0000000000000000UL,
+	/* 0x0240, */ 0x0000000000000000UL,
+	/* 0x0248, */ 0x0000000000000000UL,
+	/* 0x0250, */ 0x0000000000000000UL,
+	/* 0x0258, */ 0x0000000000000000UL,
+	/* 0x0260, */ 0x0000000000000000UL,
+	/* 0x0268, */ 0x0000000000000000UL,
+	/* 0x0270, */ 0x0000000000000000UL,
+	/* 0x0278, */ 0x0000000000000000UL,
+	/* 0x0280, */ 0x0000000000000000UL,
+	/* 0x0288, */ 0x0000000000000000UL,
+	/* 0x0290, */ 0x0000000000000000UL,
+	/* 0x0298, */ 0x0000000000000000UL,
+	/* 0x02a0, */ 0x0000000000000000UL,
+	/* 0x02a8, */ 0x0000000000000000UL,
+	/* 0x02b0, */ 0x0000000000000000UL,
+	/* 0x02b8, */ 0x0000000000000000UL,
+	/* 0x02c0, */ 0x0000000000000000UL,
+	/* 0x02c8, */ 0x0000000000000000UL,
+	/* 0x02d0, */ 0x0000000000000000UL,
+	/* 0x02d8, */ 0x0000000000000000UL,
+	/* 0x02e0, */ 0x0000000000000000UL,
+	/* 0x02e8, */ 0x0000000000000000UL,
+	/* 0x02f0, */ 0x0000000000000000UL,
+	/* 0x02f8, */ 0x0000000000000000UL,
+	/* 0x0300, */ 0x0000000000000000UL,
+	/* 0x0308, */ 0x0000000000000000UL,
+	/* 0x0310, */ 0x0000000000000000UL,
+	/* 0x0318, */ 0x0000000000000000UL,
+	/* 0x0320, */ 0x0000000000000000UL,
+	/* 0x0328, */ 0x0000000000000000UL,
+	/* 0x0330, */ 0x0000000000000000UL,
+	/* 0x0338, */ 0x0000000000000000UL,
+	/* 0x0340, */ 0x0000000000000000UL,
+	/* 0x0348, */ 0x0000000000000000UL,
+	/* 0x0350, */ 0x0000000000000000UL,
+	/* 0x0358, */ 0x0000000000000000UL,
+	/* 0x0360, */ 0x0000000000000000UL,
+	/* 0x0368, */ 0x0000000000000000UL,
+	/* 0x0370, */ 0x0000000000000000UL,
+	/* 0x0378, */ 0x0000000000000000UL,
+	/* 0x0380, */ 0x0000000000000000UL,
+	/* 0x0388, */ 0x0000000000000000UL,
+	/* 0x0390, */ 0x0000000000000000UL,
+};
diff --git a/drivers/staging/renesas/rcar/qos/qos.mk b/drivers/staging/renesas/rcar/qos/qos.mk
new file mode 100644
index 0000000..153d1d8
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/qos.mk
@@ -0,0 +1,87 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${RCAR_LSI},${RCAR_AUTO})
+#   E3, H3N not available for LSI_AUTO
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+else ifdef RCAR_LSI_CUT_COMPAT
+  ifeq (${RCAR_LSI},${RCAR_H3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_H3N})
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3N})
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+  endif
+  ifeq (${RCAR_LSI},${RCAR_E3})
+    BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
+  endif
+else
+  ifeq (${RCAR_LSI},${RCAR_H3})
+    ifeq (${LSI_CUT},10)
+      BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v10.c
+    else ifeq (${LSI_CUT},11)
+      BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v11.c
+    else ifeq (${LSI_CUT},20)
+      BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
+    else ifeq (${LSI_CUT},30)
+      BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+    else
+#     LSI_CUT 30 or later
+      BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RCAR_H3N})
+    ifeq (${LSI_CUT},30)
+      BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+    else
+#     LSI_CUT 30 or later
+      BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3})
+    ifeq (${LSI_CUT},10)
+     BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
+    else ifeq (${LSI_CUT},11)
+     BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+    else
+#    LSI_CUT 11 or later
+     BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RCAR_M3N})
+    ifeq (${LSI_CUT},10)
+     BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+    else
+#    LSI_CUT 10 or later
+     BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
+    endif
+  endif
+  ifeq (${RCAR_LSI},${RCAR_E3})
+    ifeq (${LSI_CUT},10)
+     BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
+    else
+#    LSI_CUT 10 or later
+     BL2_SOURCES += drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
+    endif
+  endif
+endif
+
+BL2_SOURCES += drivers/staging/renesas/rcar/qos/qos_init.c
diff --git a/drivers/staging/renesas/rcar/qos/qos_common.h b/drivers/staging/renesas/rcar/qos/qos_common.h
new file mode 100644
index 0000000..a5963f3
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/qos_common.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_COMMON_H_
+#define QOS_COMMON_H_
+
+#define RCAR_REF_DEFAULT		(0U)
+
+#if (RCAR_LSI == RCAR_E3)
+/* define used for E3 */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 3.9usec */
+#define SUB_SLOT_CYCLE_E3		(0xAFU)	/* 175 */
+#else /* REF 7.8usec */
+#define SUB_SLOT_CYCLE_E3		(0x15EU)	/* 350 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define OPERATING_FREQ_E3		(266U)	/* MHz */
+#define SL_INIT_SSLOTCLK_E3		(SUB_SLOT_CYCLE_E3 -1U)
+#define QOSWT_WTSET0_CYCLE_E3		((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3)	/* unit:ns */
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+/* define used for M3N */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_M3N		(0x84U)	/* 132 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_M3N		(0x108U)	/* 264 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_M3N		(SUB_SLOT_CYCLE_M3N -1U)
+#define QOSWT_WTSET0_CYCLE_M3N		((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
+/* define used for H3 */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_H3_20		(0x84U)	/* 132 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_H3_20		(0x108U)	/* 264 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_H3_20		(SUB_SLOT_CYCLE_H3_20 -1U)
+#define QOSWT_WTSET0_CYCLE_H3_20	((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+
+/* define used for H3 Cut 30 */
+#define SUB_SLOT_CYCLE_H3_30		(SUB_SLOT_CYCLE_H3_20)	/* same as H3 Cut 20 */
+#define SL_INIT_SSLOTCLK_H3_30		(SUB_SLOT_CYCLE_H3_30 -1U)
+#define QOSWT_WTSET0_CYCLE_H3_30	((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+
+#endif
+
+#if (RCAR_LSI == RCAR_H3N)
+/* define used for H3N */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_H3N		(0x84U)	/* 132 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_H3N		(0x108U)	/* 264 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_H3N		(SUB_SLOT_CYCLE_H3N -1U)
+#define QOSWT_WTSET0_CYCLE_H3N	((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+/* define used for M3 */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT)	/* REF 1.95usec */
+#define SUB_SLOT_CYCLE_M3_11		(0x84U)	/* 132 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_M3_11		(0x108U)	/* 264 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_M3_11		(SUB_SLOT_CYCLE_M3_11 -1U)
+#define QOSWT_WTSET0_CYCLE_M3_11	((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+#endif
+
+#define OPERATING_FREQ			(400U)	/* MHz */
+#define BASE_SUB_SLOT_NUM		(0x6U)
+#define SUB_SLOT_CYCLE			(0x7EU)	/* 126 */
+
+#define QOSWT_WTSET0_CYCLE		((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+
+#define SL_INIT_REFFSSLOT		(0x3U << 24U)
+#define SL_INIT_SLOTSSLOT		((BASE_SUB_SLOT_NUM - 1U) << 16U)
+#define SL_INIT_SSLOTCLK		(SUB_SLOT_CYCLE -1U)
+
+static inline void io_write_32(uintptr_t addr, uint32_t value)
+{
+	*(volatile uint32_t *)addr = value;
+}
+
+static inline uint32_t io_read_32(uintptr_t addr)
+{
+	return *(volatile uint32_t *)addr;
+}
+
+static inline void io_write_64(uintptr_t addr, uint64_t value)
+{
+	*(volatile uint64_t *)addr = value;
+}
+
+typedef struct {
+	uintptr_t addr;
+	uint64_t value;
+} mstat_slot_t;
+
+extern uint32_t qos_init_ddr_ch;
+extern uint8_t qos_init_ddr_phyvalid;
+
+#endif /* QOS_COMMON_H_ */
diff --git a/drivers/staging/renesas/rcar/qos/qos_init.c b/drivers/staging/renesas/rcar/qos/qos_init.c
new file mode 100644
index 0000000..54c8803
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/qos_init.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include <mmio.h>
+#include "qos_init.h"
+#include "qos_common.h"
+#if RCAR_LSI == RCAR_AUTO
+#include "H3/qos_init_h3_v10.h"
+#include "H3/qos_init_h3_v11.h"
+#include "H3/qos_init_h3_v20.h"
+#include "H3/qos_init_h3_v30.h"
+#include "M3/qos_init_m3_v10.h"
+#include "M3/qos_init_m3_v11.h"
+#include "M3N/qos_init_m3n_v10.h"
+#endif
+#if RCAR_LSI == RCAR_H3		/* H3 */
+#include "H3/qos_init_h3_v10.h"
+#include "H3/qos_init_h3_v11.h"
+#include "H3/qos_init_h3_v20.h"
+#include "H3/qos_init_h3_v30.h"
+#endif
+#if RCAR_LSI == RCAR_H3N	/* H3 */
+#include "H3/qos_init_h3n_v30.h"
+#endif
+#if RCAR_LSI == RCAR_M3		/* M3 */
+#include "M3/qos_init_m3_v10.h"
+#include "M3/qos_init_m3_v11.h"
+#endif
+#if RCAR_LSI == RCAR_M3N	/* M3N */
+#include "M3N/qos_init_m3n_v10.h"
+#endif
+#if RCAR_LSI == RCAR_E3		/* E3 */
+#include "E3/qos_init_e3_v10.h"
+#endif
+
+ /* Product Register */
+#define PRR			(0xFFF00044U)
+#define PRR_PRODUCT_MASK	(0x00007F00U)
+#define PRR_CUT_MASK		(0x000000FFU)
+#define PRR_PRODUCT_H3		(0x00004F00U)	/* R-Car H3 */
+#define PRR_PRODUCT_M3		(0x00005200U)	/* R-Car M3 */
+#define PRR_PRODUCT_M3N		(0x00005500U)	/* R-Car M3N */
+#define PRR_PRODUCT_E3		(0x00005700U)	/* R-Car E3 */
+#define PRR_PRODUCT_10		(0x00U)
+#define PRR_PRODUCT_11		(0x01U)
+#define PRR_PRODUCT_20		(0x10U)
+#define PRR_PRODUCT_30		(0x20U)
+
+#if !(RCAR_LSI == RCAR_E3)
+
+#define DRAM_CH_CNT			0x04
+uint32_t qos_init_ddr_ch;
+uint8_t qos_init_ddr_phyvalid;
+
+#endif
+
+#define PRR_PRODUCT_ERR(reg)				\
+	do{						\
+		ERROR("LSI Product ID(PRR=0x%x) QoS "	\
+		"initialize not supported.\n",reg);	\
+		panic();				\
+	} while(0)
+
+#define PRR_CUT_ERR(reg)				\
+	do{						\
+		ERROR("LSI Cut ID(PRR=0x%x) QoS "	\
+		"initialize not supported.\n",reg);	\
+		panic();				\
+	} while(0)
+
+void rcar_qos_init(void)
+{
+	uint32_t reg;
+#if !(RCAR_LSI == RCAR_E3)
+	uint32_t i;
+
+	qos_init_ddr_ch = 0;
+	qos_init_ddr_phyvalid = get_boardcnf_phyvalid();
+	for (i = 0; i < DRAM_CH_CNT; i++) {
+		if ((qos_init_ddr_phyvalid & (1 << i))) {
+			qos_init_ddr_ch++;
+		}
+	}
+#endif
+
+	reg = mmio_read_32(PRR);
+#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
+	switch (reg & PRR_PRODUCT_MASK) {
+	case PRR_PRODUCT_H3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+			qos_init_h3_v10();
+			break;
+		case PRR_PRODUCT_11:
+			qos_init_h3_v11();
+			break;
+		case PRR_PRODUCT_20:
+			qos_init_h3_v20();
+			break;
+		case PRR_PRODUCT_30:
+		default:
+			qos_init_h3_v30();
+			break;
+		}
+#elif (RCAR_LSI == RCAR_H3N)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_30:
+		default:
+			qos_init_h3n_v30();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif
+		break;
+	case PRR_PRODUCT_M3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+			qos_init_m3_v10();
+			break;
+		case PRR_PRODUCT_20:	/* M3 Cut 11 */
+		default:
+			qos_init_m3_v11();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif
+		break;
+	case PRR_PRODUCT_M3N:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		default:
+			qos_init_m3n_v10();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif
+		break;
+	case PRR_PRODUCT_E3:
+#if (RCAR_LSI == RCAR_E3)
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		default:
+			qos_init_e3_v10();
+			break;
+		}
+#else
+		PRR_PRODUCT_ERR(reg);
+#endif
+		break;
+	default:
+		PRR_PRODUCT_ERR(reg);
+		break;
+	}
+#else
+#if RCAR_LSI == RCAR_H3		/* H3 */
+#if RCAR_LSI_CUT == RCAR_CUT_10
+	/* H3 Cut 10 */
+	if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10)
+	    != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_h3_v10();
+#elif RCAR_LSI_CUT == RCAR_CUT_11
+	/* H3 Cut 11 */
+	if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11)
+	    != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_h3_v11();
+#elif RCAR_LSI_CUT == RCAR_CUT_20
+	/* H3 Cut 20 */
+	if ((PRR_PRODUCT_H3 | PRR_PRODUCT_20)
+	    != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_h3_v20();
+#else
+	/* H3 Cut 30 or later */
+	if ((PRR_PRODUCT_H3)
+	    != (reg & (PRR_PRODUCT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_h3_v30();
+#endif
+#elif RCAR_LSI == RCAR_H3N	/* H3 */
+	/* H3N Cut 30 or later */
+	if ((PRR_PRODUCT_H3)
+	    != (reg & (PRR_PRODUCT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_h3n_v30();
+#elif RCAR_LSI == RCAR_M3	/* M3 */
+#if RCAR_LSI_CUT == RCAR_CUT_10
+	/* M3 Cut 10 */
+	if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10)
+	    != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_m3_v10();
+#else
+	/* M3 Cut 11 or later */
+	if ((PRR_PRODUCT_M3)
+	    != (reg & (PRR_PRODUCT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_m3_v11();
+#endif
+#elif RCAR_LSI == RCAR_M3N	/* M3N */
+	/* M3N Cut 10 or later */
+	if ((PRR_PRODUCT_M3N)
+	    != (reg & (PRR_PRODUCT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_m3n_v10();
+#elif RCAR_LSI == RCAR_E3	/* E3 */
+	/* E3 Cut 10 or later */
+	if ((PRR_PRODUCT_E3)
+	    != (reg & (PRR_PRODUCT_MASK))) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	qos_init_e3_v10();
+#else
+#error "Don't have QoS initialize routine(Unknown chip)."
+#endif
+#endif
+}
+
+uint32_t get_refperiod(void)
+{
+	uint32_t refperiod = QOSWT_WTSET0_CYCLE;
+
+#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
+	uint32_t reg;
+
+	reg = mmio_read_32(PRR);
+	switch (reg & PRR_PRODUCT_MASK) {
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
+	case PRR_PRODUCT_H3:
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+		case PRR_PRODUCT_11:
+			break;
+		case PRR_PRODUCT_20:
+			refperiod = QOSWT_WTSET0_CYCLE_H3_20;
+			break;
+		case PRR_PRODUCT_30:
+		default:
+			refperiod = QOSWT_WTSET0_CYCLE_H3_30;
+			break;
+		}
+		break;
+#elif (RCAR_LSI == RCAR_H3N)
+	case PRR_PRODUCT_H3:
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_30:
+		default:
+			refperiod = QOSWT_WTSET0_CYCLE_H3N;
+			break;
+		}
+		break;
+#endif
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+	case PRR_PRODUCT_M3:
+		switch (reg & PRR_CUT_MASK) {
+		case PRR_PRODUCT_10:
+			break;
+		case PRR_PRODUCT_20:	/* M3 Cut 11 */
+		default:
+			refperiod = QOSWT_WTSET0_CYCLE_M3_11;
+			break;
+		}
+		break;
+#endif
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+	case PRR_PRODUCT_M3N:
+		refperiod = QOSWT_WTSET0_CYCLE_M3N;
+		break;
+#endif
+#if (RCAR_LSI == RCAR_E3)
+	case PRR_PRODUCT_E3:
+		refperiod = QOSWT_WTSET0_CYCLE_E3;
+		break;
+#endif
+	default:
+		break;
+	}
+#elif RCAR_LSI == RCAR_H3
+#if RCAR_LSI_CUT == RCAR_CUT_10
+	/* H3 Cut 10 */
+#elif RCAR_LSI_CUT == RCAR_CUT_11
+	/* H3 Cut 11 */
+#elif RCAR_LSI_CUT == RCAR_CUT_20
+	/* H3 Cut 20 */
+	refperiod = QOSWT_WTSET0_CYCLE_H3_20;
+#else
+	/* H3 Cut 30 or later */
+	refperiod = QOSWT_WTSET0_CYCLE_H3_30;
+#endif
+#elif RCAR_LSI == RCAR_H3N
+	/* H3N Cut 30 or later */
+	refperiod = QOSWT_WTSET0_CYCLE_H3N;
+#elif RCAR_LSI == RCAR_M3
+#if RCAR_LSI_CUT == RCAR_CUT_10
+	/* M3 Cut 10 */
+#else
+	/* M3 Cut 11 or later */
+	refperiod = QOSWT_WTSET0_CYCLE_M3_11;
+#endif
+#elif RCAR_LSI == RCAR_M3N	/* for M3N */
+	refperiod = QOSWT_WTSET0_CYCLE_M3N;
+#elif RCAR_LSI == RCAR_E3	/* for E3 */
+	refperiod = QOSWT_WTSET0_CYCLE_E3;
+#endif
+
+	return refperiod;
+}
diff --git a/drivers/staging/renesas/rcar/qos/qos_init.h b/drivers/staging/renesas/rcar/qos/qos_init.h
new file mode 100644
index 0000000..d2f3ec8
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/qos_init.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_
+#define QOS_INIT_H_
+
+extern void rcar_qos_init(void);
+extern uint8_t get_boardcnf_phyvalid(void);
+
+#endif /* QOS_INIT_H_ */
diff --git a/drivers/staging/renesas/rcar/qos/qos_reg.h b/drivers/staging/renesas/rcar/qos/qos_reg.h
new file mode 100644
index 0000000..1bf70b2
--- /dev/null
+++ b/drivers/staging/renesas/rcar/qos/qos_reg.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_REG_H_
+#define QOS_REG_H_
+
+#define	RCAR_QOS_NONE				(3U)
+#define	RCAR_QOS_TYPE_DEFAULT		(0U)
+
+#define	RCAR_DRAM_SPLIT_LINEAR		(0U)
+#define	RCAR_DRAM_SPLIT_4CH			(1U)
+#define	RCAR_DRAM_SPLIT_2CH			(2U)
+#define	RCAR_DRAM_SPLIT_AUTO		(3U)
+#define	RST_BASE					(0xE6160000U)
+#define	RST_MODEMR					(RST_BASE + 0x0060U)
+
+#define	DBSC_BASE					(0xE6790000U)
+#define DBSC_DBSYSCNT0				(DBSC_BASE + 0x0100U)
+#define DBSC_DBCAM0CNF1				(DBSC_BASE + 0x0904U)
+#define DBSC_DBCAM0CNF2				(DBSC_BASE + 0x0908U)
+#define DBSC_DBCAM0CNF3				(DBSC_BASE + 0x090CU)
+#define DBSC_DBSCHCNT0				(DBSC_BASE + 0x1000U)
+#define DBSC_DBSCHSZ0				(DBSC_BASE + 0x1010U)
+#define DBSC_DBSCHRW0				(DBSC_BASE + 0x1020U)
+#define DBSC_DBSCHQOS00				(DBSC_BASE + 0x1030U)
+#define DBSC_DBSCHQOS01				(DBSC_BASE + 0x1034U)
+#define DBSC_DBSCHQOS02				(DBSC_BASE + 0x1038U)
+#define DBSC_DBSCHQOS03				(DBSC_BASE + 0x103CU)
+#define DBSC_DBSCHQOS40				(DBSC_BASE + 0x1070U)
+#define DBSC_DBSCHQOS41				(DBSC_BASE + 0x1074U)
+#define DBSC_DBSCHQOS42				(DBSC_BASE + 0x1078U)
+#define DBSC_DBSCHQOS43				(DBSC_BASE + 0x107CU)
+#define DBSC_DBSCHQOS90				(DBSC_BASE + 0x10C0U)
+#define DBSC_DBSCHQOS91				(DBSC_BASE + 0x10C4U)
+#define DBSC_DBSCHQOS92				(DBSC_BASE + 0x10C8U)
+#define DBSC_DBSCHQOS93				(DBSC_BASE + 0x10CCU)
+#define DBSC_DBSCHQOS120			(DBSC_BASE + 0x10F0U)
+#define DBSC_DBSCHQOS121			(DBSC_BASE + 0x10F4U)
+#define DBSC_DBSCHQOS122			(DBSC_BASE + 0x10F8U)
+#define DBSC_DBSCHQOS123			(DBSC_BASE + 0x10FCU)
+#define DBSC_DBSCHQOS130			(DBSC_BASE + 0x1100U)
+#define DBSC_DBSCHQOS131			(DBSC_BASE + 0x1104U)
+#define DBSC_DBSCHQOS132			(DBSC_BASE + 0x1108U)
+#define DBSC_DBSCHQOS133			(DBSC_BASE + 0x110CU)
+#define DBSC_DBSCHQOS140			(DBSC_BASE + 0x1110U)
+#define DBSC_DBSCHQOS141			(DBSC_BASE + 0x1114U)
+#define DBSC_DBSCHQOS142			(DBSC_BASE + 0x1118U)
+#define DBSC_DBSCHQOS143			(DBSC_BASE + 0x111CU)
+#define DBSC_DBSCHQOS150			(DBSC_BASE + 0x1120U)
+#define DBSC_DBSCHQOS151			(DBSC_BASE + 0x1124U)
+#define DBSC_DBSCHQOS152			(DBSC_BASE + 0x1128U)
+#define DBSC_DBSCHQOS153			(DBSC_BASE + 0x112CU)
+#define DBSC_SCFCTST2				(DBSC_BASE + 0x170CU)
+
+#define	AXI_BASE					(0xE6784000U)
+#define	AXI_ADSPLCR0				(AXI_BASE + 0x0008U)
+#define	AXI_ADSPLCR1				(AXI_BASE + 0x000CU)
+#define	AXI_ADSPLCR2				(AXI_BASE + 0x0010U)
+#define	AXI_ADSPLCR3				(AXI_BASE + 0x0014U)
+#define	AXI_MMCR					(AXI_BASE + 0x0300U)
+#define	ADSPLCR0_ADRMODE_DEFAULT	((uint32_t)0U << 31U)
+#define	ADSPLCR0_ADRMODE_GEN2		((uint32_t)1U << 31U)
+#define	ADSPLCR0_SPLITSEL(x)		((uint32_t)(x) << 16U)
+#define	ADSPLCR0_AREA(x)			((uint32_t)(x) <<  8U)
+#define	ADSPLCR0_SWP				(0x0CU)
+
+#define	AXI_TR3CR					(0xE67D100CU)
+#define	AXI_TR4CR					(0xE67D1014U)
+
+#define	QOS_BASE0					(0xE67E0000U)
+#define	QOSBW_FIX_QOS_BANK0			(QOS_BASE0 + 0x0000U)
+#define	QOSBW_FIX_QOS_BANK1			(QOS_BASE0 + 0x1000U)
+#define	QOSBW_BE_QOS_BANK0			(QOS_BASE0 + 0x2000U)
+#define	QOSBW_BE_QOS_BANK1			(QOS_BASE0 + 0x3000U)
+#define	QOSCTRL_SL_INIT				(QOS_BASE0 + 0x8000U)
+#define	QOSCTRL_REF_ARS				(QOS_BASE0 + 0x8004U)
+#define	QOSCTRL_STATQC				(QOS_BASE0 + 0x8008U)
+
+#define	QOS_BASE1					(0xE67F0000U)
+#define	QOSCTRL_RAS					(QOS_BASE1 + 0x0000U)
+#define	QOSCTRL_RAEN				(QOS_BASE1 + 0x0018U)
+#define	QOSCTRL_DANN				(QOS_BASE1 + 0x0030U)
+#define	QOSCTRL_DANT				(QOS_BASE1 + 0x0038U)
+#define	QOSCTRL_INSFC				(QOS_BASE1 + 0x0050U)
+#define	QOSCTRL_RACNT0				(QOS_BASE1 + 0x0080U)
+#define	QOSCTRL_STATGEN0			(QOS_BASE1 + 0x0088U)
+
+#define	GPU_ACT_GRD					(0xFD820808U)
+#define	GPU_ACT0					(0xFD820800U)
+#define	GPU_ACT1					(0xFD821800U)
+#define	GPU_ACT2					(0xFD822800U)
+#define	GPU_ACT3					(0xFD823800U)
+#define	GPU_ACT4					(0xFD824800U)
+#define	GPU_ACT5					(0xFD825800U)
+#define	GPU_ACT6					(0xFD826800U)
+#define	GPU_ACT7					(0xFD827800U)
+
+#define	RT_ACT0						(0xFFC50800U)
+#define	RT_ACT1						(0xFFC51800U)
+
+#define	CPU_ACT0					(0xF1300800U)
+#define	CPU_ACT1					(0xF1340800U)
+#define	CPU_ACT2					(0xF1380800U)
+#define	CPU_ACT3					(0xF13C0800U)
+
+#define	RCAR_REWT_TRAINING_DISABLE	(0U)
+#define	RCAR_REWT_TRAINING_ENABLE	(1U)
+
+#define QOSWT_FIX_WTQOS_BANK0		(QOSBW_FIX_QOS_BANK0 + 0x0800U)
+#define QOSWT_FIX_WTQOS_BANK1		(QOSBW_FIX_QOS_BANK1 + 0x0800U)
+#define QOSWT_BE_WTQOS_BANK0		(QOSBW_BE_QOS_BANK0  + 0x0800U)
+#define QOSWT_BE_WTQOS_BANK1		(QOSBW_BE_QOS_BANK1  + 0x0800U)
+#define	QOSWT_WTEN					(QOS_BASE0 + 0x8030U)
+#define	QOSWT_WTREF					(QOS_BASE0 + 0x8034U)
+#define	QOSWT_WTSET0				(QOS_BASE0 + 0x8038U)
+#define	QOSWT_WTSET1				(QOS_BASE0 + 0x803CU)
+
+#endif /* QOS_REG_H_ */
diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S
index 7703be3..525e18c 100644
--- a/include/lib/cpus/aarch32/cpu_macros.S
+++ b/include/lib/cpus/aarch32/cpu_macros.S
@@ -214,5 +214,18 @@
 	bl	errata_print_msg
 	.endm
 #endif
+	/*
+	 * Helper macro that reads the part number of the current CPU and jumps
+	 * to the given label if it matches the CPU MIDR provided.
+	 *
+	 * Clobbers: r0-r1
+	 */
+	.macro  jump_if_cpu_midr _cpu_midr, _label
+	ldcopr	r0, MIDR
+	ubfx	r0, r0, #MIDR_PN_SHIFT, #12
+	ldr	r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+	cmp	r0, r1
+	beq	\_label
+	.endm
 
 #endif /* __CPU_MACROS_S__ */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 026a48e..4672cbc 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -272,3 +272,17 @@
 	cmp	\_reg, #1
 	beq	\_label
 	.endm
+
+	/*
+	 * Helper macro that reads the part number of the current
+	 * CPU and jumps to the given label if it matches the CPU
+	 * MIDR provided.
+	 *
+	 * Clobbers x0.
+	 */
+	.macro  jump_if_cpu_midr _cpu_midr, _label
+	mrs	x0, midr_el1
+	ubfx	x0, x0, MIDR_PN_SHIFT, #12
+	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+	b.eq	\_label
+	.endm
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
deleted file mode 100644
index a927208..0000000
--- a/include/plat/arm/board/common/board_arm_def.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef __BOARD_ARM_DEF_H__
-#define __BOARD_ARM_DEF_H__
-
-#include <v2m_def.h>
-
-/*
- * Required platform porting definitions common to all ARM
- * development platforms
- */
-
-/* Size of cacheable stacks */
-#if defined(IMAGE_BL1)
-#if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
-#else
-# define PLATFORM_STACK_SIZE 0x440
-#endif
-#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
-# else
-#  define PLATFORM_STACK_SIZE 0x400
-# endif
-#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
-#elif defined(IMAGE_BL31)
-#if ENABLE_SPM
-# define PLATFORM_STACK_SIZE 0x500
-#elif PLAT_XLAT_TABLES_DYNAMIC
-# define PLATFORM_STACK_SIZE 0x800
-#else
-# define PLATFORM_STACK_SIZE 0x400
-#endif
-#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
-#endif
-
-#define MAX_IO_DEVICES			3
-#define MAX_IO_HANDLES			4
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
-
-/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-/*
- * Map mem_protect flash region with read and write permissions
- */
-#define ARM_V2M_MAP_MEM_PROTECT		MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR,	\
-						V2M_FLASH_BLOCK_SIZE,		\
-						MT_DEVICE | MT_RW | MT_SECURE)
-
-#endif /* __BOARD_ARM_DEF_H__ */
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index b0a6baf..1a80e16 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -40,6 +40,16 @@
 #endif /* __ASSEMBLY__ */
 
 
+#define MAX_IO_DEVICES			3
+#define MAX_IO_HANDLES			4
+
+/* Reserve the last block of flash for PSCI MEM PROTECT flag */
+#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
 /*
  * Required platform porting definitions common to all ARM CSS-based
  * development platforms
@@ -63,6 +73,5 @@
 #define PLAT_ARM_TSP_UART_BASE			V2M_IOFPGA_UART0_BASE
 #define PLAT_ARM_TSP_UART_CLK_IN_HZ		V2M_IOFPGA_UART0_CLK_IN_HZ
 
-
 #endif /* __BOARD_CSS_DEF_H__ */
 
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 8d81af9..d5f5c15 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -277,6 +277,13 @@
 #endif
 
 /*
+ * Map mem_protect flash region with read and write permissions
+ */
+#define ARM_V2M_MAP_MEM_PROTECT		MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR,	\
+						V2M_FLASH_BLOCK_SIZE,		\
+						MT_DEVICE | MT_RW | MT_SECURE)
+
+/*
  * The max number of regions like RO(code), coherent and data required by
  * different BL stages which need to be mapped in the MMU.
  */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index d543894..848f4ee 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -11,6 +11,7 @@
 #include <cassert.h>
 #include <cpu_data.h>
 #include <stdint.h>
+#include <spinlock.h>
 #include <tzc_common.h>
 #include <utils_def.h>
 
@@ -80,6 +81,14 @@
  */
 #define ARM_INSTANTIATE_LOCK	static DEFINE_BAKERY_LOCK(arm_lock)
 #define ARM_LOCK_GET_INSTANCE	(&arm_lock)
+
+#if !HW_ASSISTED_COHERENCY
+#define ARM_SCMI_INSTANTIATE_LOCK	DEFINE_BAKERY_LOCK(arm_scmi_lock)
+#else
+#define ARM_SCMI_INSTANTIATE_LOCK	spinlock_t arm_scmi_lock
+#endif
+#define ARM_SCMI_LOCK_GET_INSTANCE	(&arm_scmi_lock)
+
 /*
  * These are wrapper macros to the Coherent Memory Bakery Lock API.
  */
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 3a23e02..108509f 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -228,11 +228,13 @@
 func cortex_a53_core_pwr_dwn
 	mov	x18, x30
 
+#if !TI_AM65X_WORKAROUND
 	/* ---------------------------------------------
 	 * Turn off caches.
 	 * ---------------------------------------------
 	 */
 	bl	cortex_a53_disable_dcache
+#endif
 
 	/* ---------------------------------------------
 	 * Flush L1 caches.
@@ -252,11 +254,13 @@
 func cortex_a53_cluster_pwr_dwn
 	mov	x18, x30
 
+#if !TI_AM65X_WORKAROUND
 	/* ---------------------------------------------
 	 * Turn off caches.
 	 * ---------------------------------------------
 	 */
 	bl	cortex_a53_disable_dcache
+#endif
 
 	/* ---------------------------------------------
 	 * Flush L1 caches.
diff --git a/maintainers.rst b/maintainers.rst
index cb4f420..5fb4494 100644
--- a/maintainers.rst
+++ b/maintainers.rst
@@ -140,6 +140,15 @@
 :F: docs/plat/rpi3.rst
 :F: plat/rpi3/
 
+Renesas rcar-gen3 platform port
+-------------------------------
+:M: Jorge Ramirez-Ortiz  <jramirez@baylibre.com>
+:G: `ldts`_
+:F: docs/plat/rcar-gen3.rst
+:F: plat/renesas/rcar
+:F: drivers/renesas/rcar
+:F: tools/renesas/rcar_layout_create
+
 RockChip platform port
 ----------------------
 :M: Tony Xie <tony.xie@rock-chips.com>
@@ -208,6 +217,7 @@
 .. _glneo: https://github.com/glneo
 .. _hzhuang1: https://github.com/hzhuang1
 .. _jenswi-linaro: https://github.com/jenswi-linaro
+.. _ldts: https://github.com/ldts
 .. _niej: https://github.com/niej
 .. _kostapr: https://github.com/kostapr
 .. _masahir0y: https://github.com/masahir0y
diff --git a/plat/arm/board/common/board_css.mk b/plat/arm/board/common/board_css.mk
deleted file mode 100644
index 5ac213a..0000000
--- a/plat/arm/board/common/board_css.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-PLAT_BL_COMMON_SOURCES	+=	plat/arm/board/common/board_css_common.c
-
-include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 8f1a0cd..ed1a302 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -20,7 +20,6 @@
 
 #include <arm_def.h>
 #include <arm_spm_def.h>
-#include <board_arm_def.h>
 #include <common_def.h>
 #include <tzc400.h>
 #include <utils_def.h>
@@ -45,6 +44,8 @@
  */
 #define PLAT_ARM_CLUSTER_COUNT		FVP_CLUSTER_COUNT
 
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+
 #define PLAT_ARM_TRUSTED_ROM_BASE	0x00000000
 #define PLAT_ARM_TRUSTED_ROM_SIZE	0x04000000	/* 64 MB */
 
@@ -133,6 +134,45 @@
 # define PLAT_ARM_MAX_BL32_SIZE		0x3B000
 #endif
 
+/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# if ENABLE_SPM
+#  define PLATFORM_STACK_SIZE 0x500
+# elif PLAT_XLAT_TABLES_DYNAMIC
+#  define PLATFORM_STACK_SIZE 0x800
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+#define MAX_IO_DEVICES			3
+#define MAX_IO_HANDLES			4
+
+/* Reserve the last block of flash for PSCI MEM PROTECT flag */
+#define PLAT_ARM_FIP_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_FIP_MAX_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE		V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE		(V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
 /*
  * PL011 related constants
  */
diff --git a/plat/arm/board/juno/aarch32/juno_helpers.S b/plat/arm/board/juno/aarch32/juno_helpers.S
index 824002a..1bc4e30 100644
--- a/plat/arm/board/juno/aarch32/juno_helpers.S
+++ b/plat/arm/board/juno/aarch32/juno_helpers.S
@@ -10,6 +10,7 @@
 #include <cortex_a53.h>
 #include <cortex_a57.h>
 #include <cortex_a72.h>
+#include <cpu_macros.S>
 #include <v2m_def.h>
 #include "../juno_def.h"
 
@@ -34,21 +35,6 @@
 	.endm
 
 	/* --------------------------------------------------------------------
-	 * Helper macro that reads the part number of the current CPU and jumps
-	 * to the given label if it matches the CPU MIDR provided.
-	 *
-	 * Clobbers r0.
-	 * --------------------------------------------------------------------
-	 */
-	.macro  jump_if_cpu_midr _cpu_midr, _label
-	ldcopr	r0, MIDR
-	ubfx	r0, r0, #MIDR_PN_SHIFT, #12
-	ldr	r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
-	cmp	r0, r1
-	beq	\_label
-	.endm
-
-	/* --------------------------------------------------------------------
 	 * Platform reset handler for Juno R0.
 	 *
 	 * Juno R0 has the following topology:
diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S
index 29c2c0a..edcfc74 100644
--- a/plat/arm/board/juno/aarch64/juno_helpers.S
+++ b/plat/arm/board/juno/aarch64/juno_helpers.S
@@ -40,20 +40,6 @@
 	.endm
 
 	/* --------------------------------------------------------------------
-	 * Helper macro that reads the part number of the current CPU and jumps
-	 * to the given label if it matches the CPU MIDR provided.
-	 *
-	 * Clobbers x0.
-	 * --------------------------------------------------------------------
-	 */
-	.macro  jump_if_cpu_midr _cpu_midr, _label
-	mrs	x0, midr_el1
-	ubfx	x0, x0, MIDR_PN_SHIFT, #12
-	cmp     w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
-	b.eq	\_label
-	.endm
-
-	/* --------------------------------------------------------------------
 	 * Platform reset handler for Juno R0.
 	 *
 	 * Juno R0 has the following topology:
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index ed78b46..0e5c6d9 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -20,7 +20,6 @@
 
 
 #include <arm_def.h>
-#include <board_arm_def.h>
 #include <board_css_def.h>
 #include <common_def.h>
 #include <css_def.h>
@@ -53,6 +52,8 @@
  */
 #define PLAT_ARM_CLUSTER_COUNT		JUNO_CLUSTER_COUNT
 
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+
 /* Use the bypass address */
 #define PLAT_ARM_TRUSTED_ROM_BASE	V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
 
@@ -163,6 +164,33 @@
 #endif
 
 /*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# if PLAT_XLAT_TABLES_DYNAMIC
+#  define PLATFORM_STACK_SIZE 0x800
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+/*
  * Since free SRAM space is scant, enable the ASSERTION message size
  * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40).
  */
diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/juno/juno_common.c
similarity index 100%
rename from plat/arm/board/common/board_css_common.c
rename to plat/arm/board/juno/juno_common.c
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index e2ec3c1..f28139d 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -29,7 +29,8 @@
 PLAT_INCLUDES		:=	-Iplat/arm/board/juno/include		\
 				-Iplat/arm/css/drivers/sds
 
-PLAT_BL_COMMON_SOURCES	:=	plat/arm/board/juno/${ARCH}/juno_helpers.S
+PLAT_BL_COMMON_SOURCES	:=	plat/arm/board/juno/${ARCH}/juno_helpers.S \
+				plat/arm/board/juno/juno_common.c
 
 # Flag to enable support for AArch32 state on JUNO
 JUNO_AARCH32_EL3_RUNTIME	:=	0
@@ -123,7 +124,7 @@
 # Do not enable SVE
 ENABLE_SVE_FOR_NS		:=	0
 
-include plat/arm/board/common/board_css.mk
+include plat/arm/board/common/board_common.mk
 include plat/arm/common/arm_common.mk
 include plat/arm/soc/common/soc_css.mk
 include plat/arm/css/common/css_common.mk
diff --git a/plat/arm/css/drivers/scmi/scmi.h b/plat/arm/css/drivers/scmi/scmi.h
index 723fd06..71a8c2d 100644
--- a/plat/arm/css/drivers/scmi/scmi.h
+++ b/plat/arm/css/drivers/scmi/scmi.h
@@ -10,6 +10,7 @@
 #include <bakery_lock.h>
 #include <stddef.h>
 #include <stdint.h>
+#include <spinlock.h>
 
 /* Supported SCMI Protocol Versions */
 #define SCMI_AP_CORE_PROTO_VER			MAKE_SCMI_VERSION(1, 0)
@@ -116,13 +117,20 @@
 	void *cookie;
 } scmi_channel_plat_info_t;
 
+
+#if HW_ASSISTED_COHERENCY
+typedef spinlock_t scmi_lock_t;
+#else
+typedef bakery_lock_t scmi_lock_t;
+#endif
+
 /*
  * Structure to represent an SCMI channel.
  */
 typedef struct scmi_channel {
 	scmi_channel_plat_info_t *info;
 	 /* The lock for channel access */
-	bakery_lock_t *lock;
+	scmi_lock_t *lock;
 	/* Indicate whether the channel is initialized */
 	int is_initialized;
 } scmi_channel_t;
diff --git a/plat/arm/css/drivers/scmi/scmi_common.c b/plat/arm/css/drivers/scmi/scmi_common.c
index 8482d21..b34178e 100644
--- a/plat/arm/css/drivers/scmi/scmi_common.c
+++ b/plat/arm/css/drivers/scmi/scmi_common.c
@@ -10,13 +10,25 @@
 #include "scmi.h"
 #include "scmi_private.h"
 
+
+#if HW_ASSISTED_COHERENCY
+#define scmi_lock_init(lock)
+#define scmi_lock_get(lock)		spin_lock(lock)
+#define scmi_lock_release(lock)		spin_unlock(lock)
+#else
+#define scmi_lock_init(lock)		bakery_lock_init(lock)
+#define scmi_lock_get(lock)		bakery_lock_get(lock)
+#define scmi_lock_release(lock)		bakery_lock_release(lock)
+#endif
+
+
 /*
  * Private helper function to get exclusive access to SCMI channel.
  */
 void scmi_get_channel(scmi_channel_t *ch)
 {
 	assert(ch->lock);
-	bakery_lock_get(ch->lock);
+	scmi_lock_get(ch->lock);
 
 	/* Make sure any previous command has finished */
 	assert(SCMI_IS_CHANNEL_FREE(
@@ -68,7 +80,7 @@
 			((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status));
 
 	assert(ch->lock);
-	bakery_lock_release(ch->lock);
+	scmi_lock_release(ch->lock);
 }
 
 /*
@@ -152,7 +164,7 @@
 
 	assert(ch->lock);
 
-	bakery_lock_init(ch->lock);
+	scmi_lock_init(ch->lock);
 
 	ch->is_initialized = 1;
 
diff --git a/plat/arm/css/drivers/scp/css_pm_scmi.c b/plat/arm/css/drivers/scp/css_pm_scmi.c
index d280101..9297e9f 100644
--- a/plat/arm/css/drivers/scp/css_pm_scmi.c
+++ b/plat/arm/css/drivers/scp/css_pm_scmi.c
@@ -71,7 +71,7 @@
 /* The SCMI channel global object */
 static scmi_channel_t channel;
 
-ARM_INSTANTIATE_LOCK;
+ARM_SCMI_INSTANTIATE_LOCK;
 
 /*
  * Helper function to suspend a CPU power domain and its parent power domains
@@ -331,7 +331,7 @@
 void __init plat_arm_pwrc_setup(void)
 {
 	channel.info = &plat_css_scmi_plat_info;
-	channel.lock = ARM_LOCK_GET_INSTANCE;
+	channel.lock = ARM_SCMI_LOCK_GET_INSTANCE;
 	scmi_handle = scmi_init(&channel);
 	if (scmi_handle == NULL) {
 		ERROR("SCMI Initialization failed\n");
diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S
index dd0fc5b..27bae43 100644
--- a/plat/arm/css/sgi/aarch64/sgi_helper.S
+++ b/plat/arm/css/sgi/aarch64/sgi_helper.S
@@ -8,6 +8,7 @@
 #include <asm_macros.S>
 #include <platform_def.h>
 #include <cortex_a75.h>
+#include <cpu_macros.S>
 
 	.globl	plat_arm_calc_core_pos
 	.globl	plat_reset_handler
@@ -48,21 +49,6 @@
 	ret
 endfunc plat_arm_calc_core_pos
 
-	/* ------------------------------------------------------
-	 * Helper macro that reads the part number of the current
-	 * CPU and jumps to the given label if it matches the CPU
-	 * MIDR provided.
-	 *
-	 * Clobbers x0.
-	 * -----------------------------------------------------
-	 */
-	.macro  jump_if_cpu_midr _cpu_midr, _label
-	mrs	x0, midr_el1
-	ubfx	x0, x0, MIDR_PN_SHIFT, #12
-	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
-	b.eq	\_label
-	.endm
-
 	/* -----------------------------------------------------
 	 * void plat_reset_handler(void);
 	 *
diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h
index b87bded..6297490 100644
--- a/plat/arm/css/sgi/include/platform_def.h
+++ b/plat/arm/css/sgi/include/platform_def.h
@@ -9,12 +9,12 @@
 
 #include <arm_def.h>
 #include <arm_spm_def.h>
-#include <board_arm_def.h>
 #include <board_css_def.h>
 #include <common_def.h>
 #include <css_def.h>
 #include <soc_css_def.h>
 #include <utils_def.h>
+#include <v2m_def.h>
 #include <xlat_tables_defs.h>
 
 #define CSS_SGI_MAX_CPUS_PER_CLUSTER	4
@@ -26,6 +26,8 @@
 					CSS_SGI_MAX_CPUS_PER_CLUSTER * \
 					CSS_SGI_MAX_PE_PER_CPU)
 
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+
 /*
  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
  * plat_arm_mmap array defined for each BL stage.
@@ -86,6 +88,34 @@
  */
 #define PLAT_ARM_MAX_BL31_SIZE		0x3B000
 
+/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# if ENABLE_SPM
+#  define PLATFORM_STACK_SIZE 0x500
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+
 #define PLAT_ARM_NSTIMER_FRAME_ID	0
 
 #define PLAT_CSS_MHU_BASE		0x45000000
diff --git a/plat/arm/css/sgm/aarch64/css_sgm_helpers.S b/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
index d9b3df6..32ca1bb 100644
--- a/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
+++ b/plat/arm/css/sgm/aarch64/css_sgm_helpers.S
@@ -9,6 +9,7 @@
 #include <platform_def.h>
 #include <cortex_a75.h>
 #include <cortex_a55.h>
+#include <cpu_macros.S>
 
 	.globl	plat_arm_calc_core_pos
 	.globl	plat_reset_handler
@@ -50,21 +51,6 @@
 	ret
 endfunc plat_arm_calc_core_pos
 
-	/* ------------------------------------------------------
-	 * Helper macro that reads the part number of the current
-	 * CPU and jumps to the given label if it matches the CPU
-	 * MIDR provided.
-	 *
-	 * Clobbers x0.
-	 * -----------------------------------------------------
-	 */
-	.macro  jump_if_cpu_midr _cpu_midr, _label
-	mrs	x0, midr_el1
-	ubfx	x0, x0, MIDR_PN_SHIFT, #12
-	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
-	b.eq	\_label
-	.endm
-
 	/* -----------------------------------------------------
 	 * void plat_reset_handler(void);
 	 *
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index 7d35bd5..eaba619 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -8,13 +8,13 @@
 #define __SGM_BASE_PLATFORM_DEF_H__
 
 #include <arm_def.h>
-#include <board_arm_def.h>
 #include <board_css_def.h>
 #include <common_def.h>
 #include <css_def.h>
 #include <soc_css_def.h>
 #include <tzc400.h>
 #include <tzc_common.h>
+#include <v2m_def.h>
 
 /* CPU topology */
 #define PLAT_ARM_CLUSTER_COUNT		1
@@ -82,6 +82,8 @@
  * platforms
  *************************************************************************/
 
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+
 /* MHU related constants */
 #define PLAT_CSS_MHU_BASE		0x2b1f0000
 
@@ -204,6 +206,29 @@
  */
 #define PLAT_ARM_MAX_BL31_SIZE		0x3B000
 
+/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+#  define PLATFORM_STACK_SIZE 0x1000
+# else
+#  define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
 /*******************************************************************************
  * Memprotect definitions
  ******************************************************************************/
diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S
new file mode 100644
index 0000000..5079937
--- /dev/null
+++ b/plat/renesas/rcar/aarch64/plat_helpers.S
@@ -0,0 +1,376 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <bl_common.h>
+#include <cortex_a57.h>
+#include <platform_def.h>
+#include <runtime_svc.h>
+#include "rcar_def.h"
+
+	.globl	plat_get_my_entrypoint
+	.extern	plat_set_my_stack
+	.globl	platform_mem_init
+
+	.globl	plat_crash_console_init
+	.globl	plat_crash_console_putc
+	.globl	plat_invalidate_icache
+	.globl	plat_report_exception
+	.globl	plat_secondary_reset
+	.globl	plat_reset_handler
+	.globl	plat_my_core_pos
+	.extern	rcar_log_init
+
+#if IMAGE_BL2
+	#define	INT_ID_MASK	(0x3ff)
+	.extern bl2_interrupt_error_type
+	.extern bl2_interrupt_error_id
+	.globl  bl2_enter_bl31
+	.extern gicv2_acknowledge_interrupt
+	.extern rcar_swdt_exec
+#endif
+
+	/* -----------------------------------------------------
+	 * void platform_get_core_pos (mpidr)
+	 * -----------------------------------------------------
+	 */
+func platform_get_core_pos
+	and     x1, x0, #MPIDR_CPU_MASK
+	and     x0, x0, #MPIDR_CLUSTER_MASK
+	add     x0, x1, x0, LSR #6
+	ret
+endfunc platform_get_core_pos
+
+	/* -----------------------------------------------------
+	 * void platform_my_core_pos
+	 * -----------------------------------------------------
+	 */
+func plat_my_core_pos
+	mrs     x0, mpidr_el1
+	b	platform_get_core_pos
+endfunc plat_my_core_pos
+
+	/* -----------------------------------------------------
+	 * void platform_get_my_entrypoint (unsigned int mpid);
+	 *
+	 * Main job of this routine is to distinguish between
+	 * a cold and warm boot.
+	 * On a cold boot the secondaries first wait for the
+	 * platform to be initialized after which they are
+	 * hotplugged in. The primary proceeds to perform the
+	 * platform initialization.
+	 * On a warm boot, each cpu jumps to the address in its
+	 * mailbox.
+	 *
+	 * TODO: Not a good idea to save lr in a temp reg
+	 * -----------------------------------------------------
+	 */
+func plat_get_my_entrypoint
+	mrs	x0, mpidr_el1
+	mov	x9, x30 /* lr */
+
+#if defined(IMAGE_BL2)
+	/* always cold boot on bl2 */
+	mov	x0, #0
+	ret	x9
+#else
+       ldr 	x1, =BOOT_KIND_BASE
+       ldr	x21, [x1]
+
+	/* Check the reset info */
+	and	x1, x21, #0x000c
+	cmp	x1, #0x0008
+	beq	el3_panic
+	cmp	x1, #0x000c
+	beq	el3_panic
+
+	/* Check the boot kind */
+	and	x1, x21, #0x0003
+	cmp	x1, #0x0002
+	beq	el3_panic
+	cmp	x1, #0x0003
+	beq	el3_panic
+
+	/* warm boot or cold boot */
+	and	x1, x21, #1
+	cmp	x1, #0
+	bne	warm_reset
+
+	/* Cold boot */
+	mov	x0, #0
+	b	exit
+
+warm_reset:
+	/* --------------------------------------------------------------------
+	 * A per-cpu mailbox is maintained in the trusted SDRAM. Its flushed out
+	 * of the caches after every update using normal memory so its safe to
+	 * read it here with SO attributes
+	 * ---------------------------------------------------------------------
+	 */
+	ldr	x10, =MBOX_BASE
+	bl	platform_get_core_pos
+	lsl	x0, x0, #CACHE_WRITEBACK_SHIFT
+	ldr	x0, [x10, x0]
+	cbz	x0, _panic
+exit:
+	ret	x9
+_panic:
+	b	do_panic
+#endif
+
+endfunc plat_get_my_entrypoint
+
+	/* ---------------------------------------------
+	 * plat_secondary_reset
+	 *
+	 * ---------------------------------------------
+	 */
+func plat_secondary_reset
+	mrs	x0, sctlr_el3
+	bic	x0, x0, #SCTLR_EE_BIT
+	msr	sctlr_el3, x0
+	isb
+
+	mrs	x0, cptr_el3
+	bic	w0, w0, #TCPAC_BIT
+	bic	w0, w0, #TTA_BIT
+	bic	w0, w0, #TFP_BIT
+	msr	cptr_el3, x0
+
+	mov_imm	x0, PARAMS_BASE
+	mov_imm	x2, BL31_BASE
+       ldr x3, =BOOT_KIND_BASE
+	mov x1, #0x1
+	str x1, [x3]
+	br	x2	/* jump to BL31 */
+	nop
+	nop
+	nop
+endfunc plat_secondary_reset
+
+	/* ---------------------------------------------
+	 * plat_enter_bl31
+	 *
+	 * ---------------------------------------------
+	 */
+func bl2_enter_bl31
+	mov	x20, x0
+        /*
+         * MMU needs to be disabled because both BL2 and BL31 execute
+         * in EL3, and therefore share the same address space.
+         * BL31 will initialize the address space according to its
+         * own requirement.
+         */
+#if RCAR_BL2_DCACHE == 1
+	/* Disable mmu and data cache */
+	bl	disable_mmu_el3
+	/* Data cache clean and invalidate */
+	mov	x0, #DCCISW
+	bl	dcsw_op_all
+	/* TLB invalidate all, EL3 */
+	tlbi	alle3
+#endif /* RCAR_BL2_DCACHE == 1 */
+	bl	disable_mmu_icache_el3
+	/* Invalidate instruction cache */
+	ic	iallu
+	dsb	sy
+	isb
+	ldp	x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
+	msr	elr_el3, x0
+	msr	spsr_el3, x1
+	eret
+endfunc bl2_enter_bl31
+
+	/* -----------------------------------------------------
+	 * void platform_mem_init (void);
+	 *
+	 * Zero out the mailbox registers in the shared memory
+	 * and set the rcar_boot_kind_flag.
+	 * The mmu is turned off right now and only the primary can
+	 * ever execute this code. Secondaries will read the
+	 * mailboxes using SO accesses.
+	 * -----------------------------------------------------
+	 */
+func platform_mem_init
+#if !IMAGE_BL2
+	ldr	x0, =MBOX_BASE
+	mov	w1, #PLATFORM_CORE_COUNT
+loop:
+	str	xzr, [x0], #CACHE_WRITEBACK_GRANULE
+	subs	w1, w1, #1
+	b.gt	loop
+#endif
+	ret
+endfunc platform_mem_init
+
+	/* ---------------------------------------------
+	 * void plat_report_exception(unsigned int type)
+	 * Function to report an unhandled exception
+	 * with platform-specific means.
+	 * ---------------------------------------------
+	 */
+func plat_report_exception
+#if IMAGE_BL2
+	mov	w1, #FIQ_SP_EL0
+	cmp	w0, w1
+	beq	rep_exec_fiq_elx
+	b	rep_exec_panic_type
+rep_exec_fiq_elx:
+	bl	gicv2_acknowledge_interrupt
+	mov	x2, #INT_ID_MASK
+	and	x0, x0, x2
+	mov	x1, #ARM_IRQ_SEC_WDT
+	cmp	x0, x1
+	bne	rep_exec_panic_id
+	mrs	x0, ELR_EL3
+	b	rcar_swdt_exec
+rep_exec_panic_type:
+	/* x0 is interrupt TYPE */
+	b	bl2_interrupt_error_type
+rep_exec_panic_id:
+	/* x0 is interrupt ID */
+	b	bl2_interrupt_error_id
+rep_exec_end:
+#endif
+	ret
+endfunc plat_report_exception
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_init(void)
+	 * Function to initialize log area
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_init
+#if IMAGE_BL2
+	mov	x0, #0
+#else
+	mov	x1, sp
+	mov_imm	x2, RCAR_CRASH_STACK
+	mov	sp, x2
+	str	x1, [sp, #-16]!
+	str	x30, [sp, #-16]!
+	bl	console_core_init
+	ldr	x30, [sp], #16
+	ldr	x1, [sp], #16
+	mov	sp, x1
+#endif
+	ret
+endfunc plat_crash_console_init
+
+	/* ---------------------------------------------
+	 * int plat_crash_console_putc(int c)
+	 * Function to store a character to log area
+	 * ---------------------------------------------
+	 */
+func plat_crash_console_putc
+	mov	x1, sp
+	mov_imm	x2, RCAR_CRASH_STACK
+	mov	sp, x2
+	str	x1, [sp, #-16]!
+	str	x30, [sp, #-16]!
+	str	x3, [sp, #-16]!
+	str	x4, [sp, #-16]!
+	str	x5, [sp, #-16]!
+	bl	console_core_putc
+	ldr	x5, [sp], #16
+	ldr	x4, [sp], #16
+	ldr	x3, [sp], #16
+	ldr	x30, [sp], #16
+	ldr	x1, [sp], #16
+	mov	sp, x1
+	ret
+endfunc plat_crash_console_putc
+
+	/* --------------------------------------------------------------------
+	 * void plat_reset_handler(void);
+	 *
+	 * Before adding code in this function, refer to the guidelines in
+	 * docs/firmware-design.md to determine whether the code should reside
+	 * within the FIRST_RESET_HANDLER_CALL block or not.
+	 *
+	 * For R-Car H3:
+	 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
+	 * - Set the L2 Data setup latency to 1 (i.e. 1 cycles) for Cortex-A57
+	 * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
+	 * For R-Car M3/M3N:
+	 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
+	 * - Set the L2 Data setup latency to 0 (i.e. 0 cycles) for Cortex-A57
+	 * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
+	 *
+	 * --------------------------------------------------------------------
+	 */
+func plat_reset_handler
+	/*
+	 * On R-Car H3    :  x2 := 0
+	 * On R-Car M3/M3N:  x2 := 1
+	 */
+	/* read PRR */
+	ldr	x0, =0xFFF00044
+	ldr	w0, [x0]
+	ubfx	w0, w0, 8, 8
+	/* H3? */
+	cmp	w0, #0x4F
+	b.eq	H3
+	/* set R-Car M3/M3N */
+	mov	x2, #1
+	b	CHK_A5x
+H3:
+	/* set R-Car H3 */
+	mov	x2, #0
+	/* --------------------------------------------------------------------
+	 * Determine whether this code is executed on a Cortex-A53 or on a
+	 * Cortex-A57 core.
+	 * --------------------------------------------------------------------
+	 */
+CHK_A5x:
+	mrs	x0, midr_el1
+	ubfx	x1, x0, MIDR_PN_SHIFT, #12
+	cmp     w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+	b.eq	A57
+	ret
+A57:
+	/* Get data from CORTEX_A57_L2CTLR_EL1	*/
+	mrs	x0, CORTEX_A57_L2CTLR_EL1
+	/*
+	 * On R-Car H3/M3/M3N
+	 *
+	 * L2 Tag RAM latency is bit8-6 of CORTEX_A57_L2CTLR_EL1
+	 * L2 Data RAM setup is bit5 of CORTEX_A57_L2CTLR_EL1
+	 * L2 Data RAM latency is bit2-0 of CORTEX_A57_L2CTLR_EL1
+	 */
+	/* clear bit of L2 RAM	*/
+	/* ~(0x1e7) -> x1	*/
+	mov	x1, #0x1e7
+	neg	x1, x1
+	/* clear bit of L2 RAM -> x0 */
+	and	x0, x0, x1
+	/* L2 Tag RAM latency (3 cycles) */
+	orr	x0, x0, #0x2 << 6
+	/* If M3/M3N then L2 RAM setup is 0 */
+	cbnz	x2, M3_L2
+	/* L2 Data RAM setup (1 cycle) */
+	orr	x0, x0, #0x1 << 5
+M3_L2:
+	/* L2 Data RAM latency (4 cycles) */
+	orr	x0, x0, #0x3
+	/* Store data to L2CTLR_EL1 */
+	msr	CORTEX_A57_L2CTLR_EL1, x0
+apply_l2_ram_latencies:
+	ret
+endfunc plat_reset_handler
+
+	/* ---------------------------------------------
+	 * void plat_invalidate_icache(void)
+	 * Instruction Cache Invalidate All to PoU
+	 * ---------------------------------------------
+	 */
+func plat_invalidate_icache
+	ic	iallu
+
+	ret
+endfunc plat_invalidate_icache
diff --git a/plat/renesas/rcar/aarch64/platform_common.c b/plat/renesas/rcar/aarch64/platform_common.c
new file mode 100644
index 0000000..f344b37
--- /dev/null
+++ b/plat/renesas/rcar/aarch64/platform_common.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <bl_common.h>
+#include <debug.h>
+#include <gicv2.h>
+#include <gic_common.h>
+#include <interrupt_props.h>
+#include <mmio.h>
+#include <platform.h>
+#include <platform_def.h>
+#include <xlat_tables_v2.h>
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "rcar_version.h"
+
+#if (IMAGE_BL2)
+extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
+extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
+#endif
+
+const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
+		__attribute__ ((__section__("ro"))) = VERSION_OF_RENESAS;
+
+#define MAP_SHARED_RAM		MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE,	\
+					RCAR_SHARED_MEM_SIZE,		\
+					MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_FLASH0		MAP_REGION_FLAT(FLASH0_BASE,		\
+					FLASH0_SIZE,			\
+					MT_MEMORY | MT_RO | MT_SECURE)
+
+#define MAP_DRAM1_NS		MAP_REGION_FLAT(DRAM1_NS_BASE,		\
+					DRAM1_NS_SIZE,			\
+					MT_MEMORY | MT_RW | MT_NS)
+
+#define MAP_DEVICE_RCAR		MAP_REGION_FLAT(DEVICE_RCAR_BASE,	\
+					DEVICE_RCAR_SIZE,		\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_DEVICE_RCAR2	MAP_REGION_FLAT(DEVICE_RCAR_BASE2,	\
+					DEVICE_RCAR_SIZE2,		\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_SRAM		MAP_REGION_FLAT(DEVICE_SRAM_BASE,	\
+					DEVICE_SRAM_SIZE,		\
+					MT_MEMORY | MT_RO | MT_SECURE)
+
+#define MAP_SRAM_STACK		MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE,	\
+					DEVICE_SRAM_STACK_SIZE,		\
+					MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_ATFW_CRASH  	MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE,	\
+					RCAR_BL31_CRASH_SIZE,		\
+					MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_ATFW_LOG		MAP_REGION_FLAT(RCAR_BL31_LOG_BASE,	\
+					RCAR_BL31_LOG_SIZE,		\
+					MT_DEVICE | MT_RW | MT_SECURE)
+#if IMAGE_BL2
+#define MAP_DRAM0		MAP_REGION_FLAT(DRAM1_BASE,		\
+					DRAM1_SIZE,			\
+					MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_REG0		MAP_REGION_FLAT(DEVICE_RCAR_BASE,	\
+					DEVICE_RCAR_SIZE,		\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_RAM0		MAP_REGION_FLAT(RCAR_SYSRAM_BASE,	\
+					RCAR_SYSRAM_SIZE,		\
+					MT_MEMORY | MT_RW | MT_SECURE)
+
+#define MAP_REG1		MAP_REGION_FLAT(REG1_BASE,		\
+					REG1_SIZE,			\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_ROM			MAP_REGION_FLAT(ROM0_BASE,		\
+					ROM0_SIZE,			\
+					MT_MEMORY | MT_RO | MT_SECURE)
+
+#define MAP_REG2		MAP_REGION_FLAT(REG2_BASE,		\
+					REG2_SIZE,			\
+					MT_DEVICE | MT_RW | MT_SECURE)
+
+#define MAP_DRAM1		MAP_REGION_FLAT(DRAM_40BIT_BASE,	\
+					DRAM_40BIT_SIZE,		\
+					MT_MEMORY | MT_RW | MT_SECURE)
+#endif
+
+#ifdef BL32_BASE
+#define MAP_BL32_MEM		MAP_REGION_FLAT(BL32_BASE,		\
+					BL32_LIMIT - BL32_BASE,		\
+					MT_MEMORY | MT_RW | MT_SECURE)
+#endif
+
+#if IMAGE_BL2
+const mmap_region_t rcar_mmap[] = {
+	MAP_FLASH0,	/*   0x08000000 -   0x0BFFFFFF  RPC area            */
+	MAP_DRAM0,	/*   0x40000000 -   0xBFFFFFFF  DRAM area(Legacy)   */
+	MAP_REG0,	/*   0xE6000000 -   0xE62FFFFF  SoC register area   */
+	MAP_RAM0,	/*   0xE6300000 -   0xE6303FFF  System RAM area     */
+	MAP_REG1,	/*   0xE6400000 -   0xEAFFFFFF  SoC register area   */
+	MAP_ROM,	/*   0xEB100000 -   0xEB127FFF  boot ROM area       */
+	MAP_REG2,	/*   0xEC000000 -   0xFFFFFFFF  SoC register area   */
+	MAP_DRAM1,	/* 0x0400000000 - 0x07FFFFFFFF  DRAM area(4GB over) */
+	{0}
+};
+#endif
+
+#if IMAGE_BL31
+const mmap_region_t rcar_mmap[] = {
+	MAP_SHARED_RAM,
+	MAP_ATFW_CRASH,
+	MAP_ATFW_LOG,
+	MAP_DEVICE_RCAR,
+	MAP_DEVICE_RCAR2,
+	MAP_SRAM,
+	MAP_SRAM_STACK,
+	{0}
+};
+#endif
+
+#if IMAGE_BL32
+const mmap_region_t rcar_mmap[] = {
+	MAP_DEVICE0,
+	MAP_DEVICE1,
+	{0}
+};
+#endif
+
+CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS
+	<= MAX_MMAP_REGIONS, assert_max_mmap_regions);
+
+/*
+ * Macro generating the code for the function setting up the pagetables as per
+ * the platform memory map & initialize the mmu, for the given exception level
+ */
+#if USE_COHERENT_MEM
+void rcar_configure_mmu_el3(unsigned long total_base,
+			    unsigned long total_size,
+			    unsigned long ro_start,
+			    unsigned long ro_limit,
+			    unsigned long coh_start,
+			    unsigned long coh_limit)
+{
+	mmap_add_region(total_base, total_base, total_size,
+			MT_MEMORY | MT_RW | MT_SECURE);
+	mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+			MT_MEMORY | MT_RO | MT_SECURE);
+	mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
+			MT_DEVICE | MT_RW | MT_SECURE);
+	mmap_add(rcar_mmap);
+
+	init_xlat_tables();
+	enable_mmu_el3(0);
+}
+#else
+void rcar_configure_mmu_el3(unsigned long total_base,
+			    unsigned long total_size,
+			    unsigned long ro_start,
+			    unsigned long ro_limit)
+{
+	mmap_add_region(total_base, total_base, total_size,
+			MT_MEMORY | MT_RW | MT_SECURE);
+	mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+			MT_MEMORY | MT_RO | MT_SECURE);
+	mmap_add(rcar_mmap);
+
+	init_xlat_tables();
+	enable_mmu_el3(0);
+}
+#endif
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+#if (IMAGE_BL2)
+	uint32_t cert, len;
+	uintptr_t dst;
+	int32_t ret;
+
+	ret = rcar_get_certificate(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert);
+	if (ret) {
+		ERROR("%s : cert file load error", __func__);
+		return NS_IMAGE_OFFSET;
+	}
+
+	rcar_read_certificate((uint64_t) cert, &len, &dst);
+
+	return dst;
+#else
+	return NS_IMAGE_OFFSET;
+#endif
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	unsigned int freq;
+
+	freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
+	if (freq == 0)
+		panic();
+
+	return freq;
+}
+
+void plat_rcar_gic_init(void)
+{
+	gicv2_distif_init();
+	gicv2_pcpu_distif_init();
+	gicv2_cpuif_enable();
+}
+
+static const interrupt_prop_t interrupt_props[] = {
+#if IMAGE_BL2
+	INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+#else
+	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(ARM_IRQ_SEC_RPC, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+	INTR_PROP_DESC(ARM_IRQ_SEC_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+	INTR_PROP_DESC(ARM_IRQ_SEC_TIMER_UP, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+	INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+	INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+	INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_SecPKA, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+	INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_PubPKA, GIC_HIGHEST_SEC_PRIORITY,
+		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+#endif
+};
+
+static const gicv2_driver_data_t plat_gicv2_driver_data = {
+	.interrupt_props = interrupt_props,
+	.interrupt_props_num = (uint32_t) ARRAY_SIZE(interrupt_props),
+	.gicd_base = RCAR_GICD_BASE,
+	.gicc_base = RCAR_GICC_BASE,
+};
+
+void plat_rcar_gic_driver_init(void)
+{
+	gicv2_driver_init(&plat_gicv2_driver_data);
+}
diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
new file mode 100644
index 0000000..eb533ce
--- /dev/null
+++ b/plat/renesas/rcar/bl2_cpg_init.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <mmio.h>
+#include "rcar_def.h"
+#include "cpg_registers.h"
+#include "rcar_private.h"
+
+static void bl2_secure_cpg_init(void);
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+static void bl2_realtime_cpg_init_h3(void);
+static void bl2_system_cpg_init_h3(void);
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+static void bl2_realtime_cpg_init_m3(void);
+static void bl2_system_cpg_init_m3(void);
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+static void bl2_realtime_cpg_init_m3n(void);
+static void bl2_system_cpg_init_m3n(void);
+#endif
+
+#if (RCAR_LSI == RCAR_E3)
+static void bl2_realtime_cpg_init_e3(void);
+static void bl2_system_cpg_init_e3(void);
+#endif
+
+typedef struct {
+	uintptr_t adr;
+	uint32_t val;
+} reg_setting_t;
+
+static void bl2_secure_cpg_init(void)
+{
+	uint32_t stop_cr2, reset_cr2;
+
+#if (RCAR_LSI == RCAR_E3)
+	reset_cr2 = 0x10000000U stop_cr2 = 0xEFFFFFFFU;
+#else
+	reset_cr2 = 0x14000000U;
+	stop_cr2 = 0xEBFFFFFFU;
+#endif
+	/** Secure Module Stop Control Registers */
+	cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
+	cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(SCMSTPCR2, stop_cr2);
+	cpg_write(SCMSTPCR3, 0xFFFFFFFFU);
+	cpg_write(SCMSTPCR4, 0x7FFFFFFFU);
+	cpg_write(SCMSTPCR5, 0xBFFFFFFFU);
+	cpg_write(SCMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(SCMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(SCMSTPCR8, 0xFFFFFFFFU);
+	cpg_write(SCMSTPCR9, 0xFFFDFFFFU);
+	cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
+	cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
+
+	/** Secure Software Reset Access Enable Control Registers */
+	cpg_write(SCSRSTECR0, 0x00000000U);
+	cpg_write(SCSRSTECR1, 0x00000000U);
+	cpg_write(SCSRSTECR2, reset_cr2);
+	cpg_write(SCSRSTECR3, 0x00000000U);
+	cpg_write(SCSRSTECR4, 0x80000003U);
+	cpg_write(SCSRSTECR5, 0x40000000U);
+	cpg_write(SCSRSTECR6, 0x00000000U);
+	cpg_write(SCSRSTECR7, 0x00000000U);
+	cpg_write(SCSRSTECR8, 0x00000000U);
+	cpg_write(SCSRSTECR9, 0x00020000U);
+	cpg_write(SCSRSTECR10, 0x00000000U);
+	cpg_write(SCSRSTECR11, 0x00000000U);
+}
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+static void bl2_realtime_cpg_init_h3(void)
+{
+	uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+	uint32_t cr0, cr8;
+
+	cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+	    0x00200000U : 0x00210000U;
+	cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+	    0x01F1FFF4U : 0x01F1FFF7U;
+
+	cpg_write(RMSTPCR0, cr0);
+	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR2, 0x040E0FDCU);
+	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+	cpg_write(RMSTPCR4, 0x80000004U);
+	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR8, cr8);
+	cpg_write(RMSTPCR9, 0xFFFFFFFEU);
+	cpg_write(RMSTPCR10, 0xFFFEFFE0U);
+	cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_h3(void)
+{
+	/** System Module Stop Control Registers */
+	cpg_write(SMSTPCR0, 0x00210000U);
+	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR2, 0x040E2FDCU);
+	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+	cpg_write(SMSTPCR4, 0x80000004U);
+	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR8, 0x01F1FFF5U);
+	cpg_write(SMSTPCR9, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR10, 0xFFFEFFE0U);
+	cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
+static void bl2_realtime_cpg_init_m3(void)
+{
+	/** Realtime Module Stop Control Registers */
+	cpg_write(RMSTPCR0, 0x00200000U);
+	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR2, 0x040E0FDCU);
+	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+	cpg_write(RMSTPCR4, 0x80000004U);
+	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR8, 0x01F1FFF7U);
+	cpg_write(RMSTPCR9, 0xFFFFFFFEU);
+	cpg_write(RMSTPCR10, 0xFFFEFFE0U);
+	cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_m3(void)
+{
+	/** System Module Stop Control Registers */
+	cpg_write(SMSTPCR0, 0x00200000U);
+	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR2, 0x040E2FDCU);
+	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+	cpg_write(SMSTPCR4, 0x80000004U);
+	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR8, 0x01F1FFF7U);
+	cpg_write(SMSTPCR9, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR10, 0xFFFEFFE0U);
+	cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+static void bl2_realtime_cpg_init_m3n(void)
+{
+	/** Realtime Module Stop Control Registers */
+	cpg_write(RMSTPCR0, 0x00210000U);
+	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR2, 0x040E0FDCU);
+	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+	cpg_write(RMSTPCR4, 0x80000004U);
+	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR8, 0x00F1FFF7U);
+	cpg_write(RMSTPCR9, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR10, 0xFFFFFFE0U);
+	cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_m3n(void)
+{
+	/* System Module Stop Control Registers */
+	cpg_write(SMSTPCR0, 0x00210000U);
+	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR2, 0x040E2FDCU);
+	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+	cpg_write(SMSTPCR4, 0x80000004U);
+	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR8, 0x00F1FFF7U);
+	cpg_write(SMSTPCR9, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR10, 0xFFFFFFE0U);
+	cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+#if (RCAR_LSI == RCAR_E3)
+static void bl2_realtime_cpg_init_e3(void)
+{
+	/* Realtime Module Stop Control Registers */
+	cpg_write(RMSTPCR0, 0x00210000U);
+	cpg_write(RMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR2, 0x000E0FDCU);
+	cpg_write(RMSTPCR3, 0xFFFFFFDFU);
+	cpg_write(RMSTPCR4, 0x80000004U);
+	cpg_write(RMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(RMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(RMSTPCR8, 0x00F1FFF7U);
+	cpg_write(RMSTPCR9, 0xFFFFFFDFU);
+	cpg_write(RMSTPCR10, 0xFFFFFFE8U);
+	cpg_write(RMSTPCR11, 0x000000B7U);
+}
+
+static void bl2_system_cpg_init_e3(void)
+{
+	/* System Module Stop Control Registers */
+	cpg_write(SMSTPCR0, 0x00210000U);
+	cpg_write(SMSTPCR1, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR2, 0x000E2FDCU);
+	cpg_write(SMSTPCR3, 0xFFFFFBDFU);
+	cpg_write(SMSTPCR4, 0x80000004U);
+	cpg_write(SMSTPCR5, 0xC3FFFFFFU);
+	cpg_write(SMSTPCR6, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR7, 0xFFFFFFFFU);
+	cpg_write(SMSTPCR8, 0x00F1FFF7U);
+	cpg_write(SMSTPCR9, 0xFFFFFFDFU);
+	cpg_write(SMSTPCR10, 0xFFFFFFE8U);
+	cpg_write(SMSTPCR11, 0x000000B7U);
+}
+#endif
+
+void bl2_cpg_init(void)
+{
+	uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
+#if RCAR_LSI == RCAR_AUTO
+	uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+#endif
+	bl2_secure_cpg_init();
+
+	if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
+	    boot_cpu == MODEMR_BOOT_CPU_CA53) {
+#if RCAR_LSI == RCAR_AUTO
+
+		switch (product) {
+		case RCAR_PRODUCT_H3:
+			bl2_realtime_cpg_init_h3();
+			break;
+		case RCAR_PRODUCT_M3:
+			bl2_realtime_cpg_init_m3();
+			break;
+		case RCAR_PRODUCT_M3N:
+			bl2_realtime_cpg_init_m3n();
+			break;
+		default:
+			panic();
+			break;
+		}
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+		bl2_realtime_cpg_init_h3();
+#elif RCAR_LSI == RCAR_M3
+		bl2_realtime_cpg_init_m3();
+#elif RCAR_LSI == RCAR_M3N
+		bl2_realtime_cpg_init_m3n();
+#elif RCAR_LSI == RCAR_E3
+		bl2_realtime_cpg_init_e3();
+#else
+#error "Don't have CPG initialize routine(unknown)."
+#endif
+	}
+}
+
+void bl2_system_cpg_init(void)
+{
+#if RCAR_LSI == RCAR_AUTO
+	uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+
+	switch (product) {
+	case RCAR_PRODUCT_H3:
+		bl2_system_cpg_init_h3();
+		break;
+	case RCAR_PRODUCT_M3:
+		bl2_system_cpg_init_m3();
+		break;
+	case RCAR_PRODUCT_M3N:
+		bl2_system_cpg_init_m3n();
+		break;
+	default:
+		panic();
+		break;
+	}
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+	bl2_system_cpg_init_h3();
+#elif RCAR_LSI == RCAR_M3
+	bl2_system_cpg_init_m3();
+#elif RCAR_LSI == RCAR_M3N
+	bl2_system_cpg_init_m3n();
+#elif RCAR_LSI == RCAR_E3
+	bl2_system_cpg_init_e3();
+#else
+#error "Don't have CPG initialize routine(unknown)."
+#endif
+}
diff --git a/plat/renesas/rcar/bl2_interrupt_error.c b/plat/renesas/rcar/bl2_interrupt_error.c
new file mode 100644
index 0000000..c50c603
--- /dev/null
+++ b/plat/renesas/rcar/bl2_interrupt_error.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <bl_common.h>
+#include <debug.h>
+#include <gicv2.h>
+#include <mmio.h>
+#include <runtime_svc.h>
+#include "rcar_def.h"
+
+#define SWDT_ERROR_ID	(1024U)
+#define SWDT_ERROR_TYPE	(16U)
+#define SWDT_CHAR_MAX	(13U)
+
+extern void rcar_swdt_release(void);
+
+void bl2_interrupt_error_id(uint32_t int_id)
+{
+	ERROR("\n");
+	if (int_id >= SWDT_ERROR_ID) {
+		ERROR("Unhandled exception occurred.\n");
+		ERROR("     Exception type = FIQ_SP_ELX\n");
+		panic();
+	}
+
+	/* Clear the interrupt request */
+	gicv2_end_of_interrupt((uint32_t) int_id);
+	rcar_swdt_release();
+	ERROR("Unhandled exception occurred.\n");
+	ERROR("     Exception type = FIQ_SP_ELX\n");
+	ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
+	ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
+	ERROR("     ESR_EL1  = 0x%x\n", (uint32_t) read_esr_el1());
+	ERROR("     FAR_EL1  = 0x%x\n", (uint32_t) read_far_el1());
+	ERROR("\n");
+	panic();
+}
+
+void bl2_interrupt_error_type(uint32_t ex_type)
+{
+	const uint8_t interrupt_ex[SWDT_ERROR_TYPE][SWDT_CHAR_MAX] = {
+		"SYNC SP EL0",
+		"IRQ SP EL0",
+		"FIQ SP EL0",
+		"SERR SP EL0",
+		"SYNC SP ELx",
+		"IRQ SP ELx",
+		"FIQ SP ELx",
+		"SERR SP ELx",
+		"SYNC AARCH64",
+		"IRQ AARCH64",
+		"FIQ AARCH64",
+		"SERR AARCH64",
+		"SYNC AARCH32",
+		"IRQ AARCH32",
+		"FIQ AARCH32",
+		"SERR AARCH32"
+	};
+	char msg[128];
+
+	/* Clear the interrupt request  */
+	if (ex_type >= SWDT_ERROR_TYPE) {
+		ERROR("\n");
+		ERROR("Unhandled exception occurred.\n");
+		ERROR("     Exception type = Unknown (%d)\n", ex_type);
+		goto loop;
+	}
+
+	rcar_swdt_release();
+	ERROR("\n");
+	ERROR("Unhandled exception occurred.\n");
+	snprintf(msg, sizeof(msg), "     Exception type = %s\n",
+		 &interrupt_ex[ex_type][0]);
+	ERROR("%s", msg);
+	switch (ex_type) {
+	case SYNC_EXCEPTION_SP_ELX:
+		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
+		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
+		ERROR("     ESR_EL1  = 0x%x\n", (uint32_t) read_esr_el1());
+		ERROR("     FAR_EL1  = 0x%x\n", (uint32_t) read_far_el1());
+		break;
+	case IRQ_SP_ELX:
+		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
+		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
+		ERROR("     IAR_EL1  = 0x%x\n", gicv2_acknowledge_interrupt());
+		break;
+	case FIQ_SP_ELX:
+		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
+		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
+		ERROR("     IAR_EL1  = 0x%x\n", gicv2_acknowledge_interrupt());
+		break;
+	case SERROR_SP_ELX:
+		ERROR("     SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
+		ERROR("     ELR_EL1  = 0x%x\n", (uint32_t) read_elr_el1());
+		ERROR("     ESR_EL1  = 0x%x\n", (uint32_t) read_esr_el1());
+		ERROR("     FAR_EL1  = 0x%x\n", (uint32_t) read_far_el1());
+		break;
+	default:
+		break;
+	}
+loop:
+	ERROR("\n");
+	panic();
+}
diff --git a/plat/renesas/rcar/bl2_plat_mem_params_desc.c b/plat/renesas/rcar/bl2_plat_mem_params_desc.c
new file mode 100644
index 0000000..112a1ed
--- /dev/null
+++ b/plat/renesas/rcar/bl2_plat_mem_params_desc.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <desc_image_load.h>
+#include <platform.h>
+#include <platform_def.h>
+
+#if (RCAR_BL33_EXECUTION_EL != 0) && (RCAR_BL33_EXECUTION_EL != 1)
+#error
+#endif
+
+#if (RCAR_BL33_EXECUTION_EL == 0)
+#define BL33_MODE MODE_EL1
+#else
+#define BL33_MODE MODE_EL2
+#endif
+
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+	{
+		.image_id = BL31_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+			entry_point_info_t, SECURE | EXECUTABLE | EP_FIRST_EXE),
+		.ep_info.spsr = SPSR_64(MODE_EL3,
+			MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS),
+		.ep_info.pc = BL31_BASE,
+
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+			image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+		.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+		.image_info.image_base = BL31_BASE,
+
+# ifdef BL32_BASE
+		.next_handoff_image_id = BL32_IMAGE_ID,
+# else
+		.next_handoff_image_id = BL33_IMAGE_ID,
+# endif
+	},
+# ifdef BL32_BASE
+	{
+		.image_id = BL32_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+			entry_point_info_t, SECURE | EXECUTABLE),
+		.ep_info.pc = BL32_BASE,
+		.ep_info.spsr = 0,
+
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+			image_info_t, 0),
+		.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+		.image_info.image_base = BL32_BASE,
+
+		.next_handoff_image_id = BL33_IMAGE_ID,
+	},
+#endif
+	{
+		.image_id = BL33_IMAGE_ID,
+
+		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+			entry_point_info_t, NON_SECURE | EXECUTABLE),
+		.ep_info.spsr = SPSR_64(BL33_MODE, MODE_SP_ELX,
+			DISABLE_ALL_EXCEPTIONS),
+		.ep_info.pc = BL33_BASE,
+#ifdef RCAR_BL33_ARG0
+		.ep_info.args.arg0 = RCAR_BL33_ARG0,
+#endif
+		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+			image_info_t, 0),
+		.image_info.image_max_size =
+				(uint32_t) (DRAM_LIMIT - BL33_BASE),
+		.image_info.image_base = BL33_BASE,
+
+		.next_handoff_image_id = INVALID_IMAGE_ID,
+	}
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
new file mode 100644
index 0000000..4f3329f
--- /dev/null
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -0,0 +1,626 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <desc_image_load.h>
+#include <arch_helpers.h>
+#include <bl_common.h>
+#include <bl1.h>
+#include <console.h>
+#include <debug.h>
+#include <mmio.h>
+#include <platform.h>
+#include <platform_def.h>
+#include <string.h>
+
+#include "avs_driver.h"
+#include "boot_init_dram.h"
+#include "cpg_registers.h"
+#include "board.h"
+#include "emmc_def.h"
+#include "emmc_hal.h"
+#include "emmc_std.h"
+
+#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
+#include "iic_dvfs.h"
+#endif
+
+#include "io_common.h"
+#include "qos_init.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "rcar_version.h"
+#include "rom_api.h"
+
+IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE)
+IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT)
+
+#if USE_COHERENT_MEM
+IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE)
+IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT)
+#endif
+
+extern void plat_rcar_gic_driver_init(void);
+extern void plat_rcar_gic_init(void);
+extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
+extern void bl2_system_cpg_init(void);
+extern void bl2_secure_setting(void);
+extern void bl2_cpg_init(void);
+extern void rcar_io_emmc_setup(void);
+extern void rcar_io_setup(void);
+extern void rcar_swdt_release(void);
+extern void rcar_swdt_init(void);
+extern void rcar_rpc_init(void);
+extern void rcar_pfc_init(void);
+extern void rcar_dma_init(void);
+
+/* R-Car Gen3 product check */
+#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#define TARGET_PRODUCT			RCAR_PRODUCT_H3
+#define TARGET_NAME			"R-Car H3"
+#elif RCAR_LSI == RCAR_M3
+#define TARGET_PRODUCT			RCAR_PRODUCT_M3
+#define TARGET_NAME			"R-Car M3"
+#elif RCAR_LSI == RCAR_M3N
+#define TARGET_PRODUCT			RCAR_PRODUCT_M3N
+#define TARGET_NAME			"R-Car M3N"
+#elif RCAR_LSI == RCAR_E3
+#define TARGET_PRODUCT			RCAR_PRODUCT_E3
+#define TARGET_NAME			"R-Car E3"
+#endif
+
+#if (RCAR_LSI == RCAR_E3)
+#define GPIO_INDT			(GPIO_INDT6)
+#define GPIO_BKUP_TRG_SHIFT		((uint32_t)1U<<13U)
+#else
+#define GPIO_INDT			(GPIO_INDT1)
+#define GPIO_BKUP_TRG_SHIFT		((uint32_t)1U<<8U)
+#endif
+
+CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
+	 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
+	assert_bl31_params_do_not_fit_in_shared_memory);
+
+static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
+
+#if (RCAR_LOSSY_ENABLE == 1)
+typedef struct bl2_lossy_info {
+	uint32_t magic;
+	uint32_t a0;
+	uint32_t b0;
+} bl2_lossy_info_t;
+
+static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
+			      uint64_t end_addr, uint32_t format,
+			      uint32_t enable)
+{
+	bl2_lossy_info_t info;
+	uint32_t reg;
+
+	reg = format | (start_addr >> 20);
+	mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
+	mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
+	mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
+
+	info.magic = 0x12345678U;
+	info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
+	info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
+
+	mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
+	mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
+	mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
+
+	NOTICE("     Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
+	       mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
+	       mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
+}
+#endif
+
+void bl2_plat_flush_bl31_params(void)
+{
+	uint32_t product_cut, product, cut;
+	uint32_t boot_dev, boot_cpu;
+	uint32_t lcs, reg, val;
+
+	reg = mmio_read_32(RCAR_MODEMR);
+	boot_dev = reg & MODEMR_BOOT_DEV_MASK;
+
+	if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
+	    boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
+		emmc_terminate();
+
+	if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
+		bl2_secure_setting();
+
+	reg = mmio_read_32(RCAR_PRR);
+	product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	product = reg & RCAR_PRODUCT_MASK;
+	cut = reg & RCAR_CUT_MASK;
+
+	if (product == RCAR_PRODUCT_M3)
+		goto tlb;
+
+	if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut)
+		goto tlb;
+
+	/* Disable MFIS write protection */
+	mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
+
+tlb:
+	reg = mmio_read_32(RCAR_MODEMR);
+	boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
+	if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
+	    boot_cpu != MODEMR_BOOT_CPU_CA53)
+		goto mmu;
+
+	if (product_cut == RCAR_PRODUCT_H3_CUT20) {
+		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
+	} else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
+		   product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
+		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
+	} else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
+		mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
+	}
+
+	if (product_cut == (RCAR_PRODUCT_H3_CUT20) ||
+	    product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
+	    product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) ||
+	    product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
+		mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
+
+		mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
+		mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
+	}
+
+mmu:
+	mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
+	mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
+
+	val = rcar_rom_get_lcs(&lcs);
+	if (val) {
+		ERROR("BL2: Failed to get the LCS. (%d)\n", val);
+		panic();
+	}
+
+	if (lcs == LCS_SE)
+		mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
+
+	rcar_swdt_release();
+	bl2_system_cpg_init();
+
+#if RCAR_BL2_DCACHE == 1
+	/* Disable data cache (clean and invalidate) */
+	disable_mmu_el3();
+#endif
+}
+
+static uint32_t is_ddr_backup_mode(void)
+{
+#if RCAR_SYSTEM_SUSPEND
+	static uint32_t reason = RCAR_COLD_BOOT;
+	static uint32_t once;
+
+#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
+	uint8_t data;
+#endif
+	if (once)
+		return reason;
+
+	once = 1;
+	if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
+		return reason;
+
+#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
+	if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
+		ERROR("BL2: REG Keep10 READ ERROR.\n");
+		panic();
+	}
+
+	if (KEEP10_MAGIC != data)
+		reason = RCAR_WARM_BOOT;
+#else
+	reason = RCAR_WARM_BOOT;
+#endif
+	return reason;
+#else
+	return RCAR_COLD_BOOT;
+#endif
+}
+
+int bl2_plat_handle_pre_image_load(unsigned int image_id)
+{
+	u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
+	bl_mem_params_node_t *bl_mem_params;
+
+	if (image_id != BL31_IMAGE_ID)
+		return 0;
+
+	bl_mem_params = get_bl_mem_params_node(image_id);
+
+	if (is_ddr_backup_mode() == RCAR_COLD_BOOT)
+		goto cold_boot;
+
+	*boot_kind  = RCAR_WARM_BOOT;
+	flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
+
+	console_flush();
+	bl2_plat_flush_bl31_params();
+
+	/* will not return */
+	bl2_enter_bl31(&bl_mem_params->ep_info);
+
+cold_boot:
+	*boot_kind  = RCAR_COLD_BOOT;
+	flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
+
+	return 0;
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+	static bl2_to_bl31_params_mem_t *params;
+	bl_mem_params_node_t *bl_mem_params;
+
+	if (!params) {
+		params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
+		memset((void *)PARAMS_BASE, 0, sizeof(*params));
+	}
+
+	bl_mem_params = get_bl_mem_params_node(image_id);
+
+	switch (image_id) {
+	case BL31_IMAGE_ID:
+		break;
+	case BL32_IMAGE_ID:
+		memcpy(&params->bl32_ep_info, &bl_mem_params->ep_info,
+			sizeof(entry_point_info_t));
+		break;
+	case BL33_IMAGE_ID:
+		memcpy(&params->bl33_ep_info, &bl_mem_params->ep_info,
+			sizeof(entry_point_info_t));
+		break;
+	}
+
+	return 0;
+}
+
+meminfo_t *bl2_plat_sec_mem_layout(void)
+{
+	return &bl2_tzram_layout;
+}
+
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+				  u_register_t arg3, u_register_t arg4)
+{
+	uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
+	uint32_t cut, product, product_cut, major, minor;
+	int32_t ret;
+	const char *str;
+	const char *unknown = "unknown";
+	const char *cpu_ca57 = "CA57";
+	const char *cpu_ca53 = "CA53";
+	const char *product_m3n = "M3N";
+	const char *product_h3 = "H3";
+	const char *product_m3 = "M3";
+	const char *product_e3 = "E3";
+	const char *lcs_secure = "SE";
+	const char *lcs_cm = "CM";
+	const char *lcs_dm = "DM";
+	const char *lcs_sd = "SD";
+	const char *lcs_fa = "FA";
+	const char *sscg_off = "PLL1 nonSSCG Clock select";
+	const char *sscg_on = "PLL1 SSCG Clock select";
+	const char *boot_hyper80 = "HyperFlash(80MHz)";
+	const char *boot_qspi40 = "QSPI Flash(40MHz)";
+	const char *boot_qspi80 = "QSPI Flash(80MHz)";
+	const char *boot_emmc25x1 = "eMMC(25MHz x1)";
+	const char *boot_emmc50x8 = "eMMC(50MHz x8)";
+#if RCAR_LSI == RCAR_E3
+	const char *boot_hyper160 = "HyperFlash(150MHz)";
+#else
+	const char *boot_hyper160 = "HyperFlash(160MHz)";
+#endif
+
+	reg = mmio_read_32(RCAR_MODEMR);
+	boot_dev = reg & MODEMR_BOOT_DEV_MASK;
+	boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
+
+	bl2_cpg_init();
+
+	if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
+	    boot_cpu == MODEMR_BOOT_CPU_CA53) {
+		rcar_pfc_init();
+		/* console configuration (platform specific) done in driver */
+		console_init(0, 0, 0);
+	}
+
+	plat_rcar_gic_driver_init();
+	plat_rcar_gic_init();
+	rcar_swdt_init();
+
+	/* FIQ interrupts are taken to EL3 */
+	write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
+
+	write_daifclr(DAIF_FIQ_BIT);
+
+	reg = read_midr();
+	midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
+	switch (midr) {
+	case MIDR_CA57:
+		str = cpu_ca57;
+		break;
+	case MIDR_CA53:
+		str = cpu_ca53;
+		break;
+	default:
+		str = unknown;
+		break;
+	}
+
+	NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
+	       version_of_renesas);
+
+	reg = mmio_read_32(RCAR_PRR);
+	product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+	product = reg & RCAR_PRODUCT_MASK;
+	cut = reg & RCAR_CUT_MASK;
+
+	switch (product) {
+	case RCAR_PRODUCT_H3:
+		str = product_h3;
+		break;
+	case RCAR_PRODUCT_M3:
+		str = product_m3;
+		break;
+	case RCAR_PRODUCT_M3N:
+		str = product_m3n;
+		break;
+	case RCAR_PRODUCT_E3:
+		str = product_e3;
+		break;
+	default:
+		str = unknown;
+		break;
+	}
+
+	if (RCAR_PRODUCT_M3_CUT11 == product_cut) {
+		NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str);
+	} else {
+		major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
+		major = major + RCAR_MAJOR_OFFSET;
+		minor = reg & RCAR_MINOR_MASK;
+		NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
+	}
+
+	if (product == RCAR_PRODUCT_E3) {
+		reg = mmio_read_32(RCAR_MODEMR);
+		sscg = reg & RCAR_SSCG_MASK;
+		str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
+		NOTICE("BL2: %s\n", str);
+	}
+
+	rcar_get_board_type(&type, &rev);
+
+	switch (type) {
+	case BOARD_SALVATOR_X:
+	case BOARD_KRIEK:
+	case BOARD_STARTER_KIT:
+	case BOARD_SALVATOR_XS:
+	case BOARD_EBISU:
+	case BOARD_STARTER_KIT_PRE:
+	case BOARD_EBISU_4D:
+		break;
+	default:
+		type = BOARD_UNKNOWN;
+		break;
+	}
+
+	if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
+		NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
+	else {
+		NOTICE("BL2: Board is %s Rev.%d.%d\n",
+		       GET_BOARD_NAME(type),
+		       GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
+	}
+
+#if RCAR_LSI != RCAR_AUTO
+	if (product != TARGET_PRODUCT) {
+		ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
+		ERROR("BL2: Please write the correct IPL to flash memory.\n");
+		panic();
+	}
+#endif
+	rcar_avs_init();
+	rcar_avs_setting();
+
+	switch (boot_dev) {
+	case MODEMR_BOOT_DEV_HYPERFLASH160:
+		str = boot_hyper160;
+		break;
+	case MODEMR_BOOT_DEV_HYPERFLASH80:
+		str = boot_hyper80;
+		break;
+	case MODEMR_BOOT_DEV_QSPI_FLASH40:
+		str = boot_qspi40;
+		break;
+	case MODEMR_BOOT_DEV_QSPI_FLASH80:
+		str = boot_qspi80;
+		break;
+	case MODEMR_BOOT_DEV_EMMC_25X1:
+		str = boot_emmc25x1;
+		break;
+	case MODEMR_BOOT_DEV_EMMC_50X8:
+		str = boot_emmc50x8;
+		break;
+	default:
+		str = unknown;
+		break;
+	}
+	NOTICE("BL2: Boot device is %s\n", str);
+
+	rcar_avs_setting();
+	reg = rcar_rom_get_lcs(&lcs);
+	if (reg) {
+		str = unknown;
+		goto lcm_state;
+	}
+
+	switch (lcs) {
+	case LCS_CM:
+		str = lcs_cm;
+		break;
+	case LCS_DM:
+		str = lcs_dm;
+		break;
+	case LCS_SD:
+		str = lcs_sd;
+		break;
+	case LCS_SE:
+		str = lcs_secure;
+		break;
+	case LCS_FA:
+		str = lcs_fa;
+		break;
+	default:
+		str = unknown;
+		break;
+	}
+
+lcm_state:
+	NOTICE("BL2: LCM state is %s\n", str);
+
+	rcar_avs_end();
+	is_ddr_backup_mode();
+
+	bl2_tzram_layout.total_base = BL31_BASE;
+	bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
+
+	if (product == RCAR_PRODUCT_H3 && cut >= RCAR_CUT_VER30) {
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+		NOTICE("BL2: CH0: 0x400000000 - 0x440000000, 1 GiB\n");
+		NOTICE("BL2: CH1: 0x500000000 - 0x540000000, 1 GiB\n");
+		NOTICE("BL2: CH2: 0x600000000 - 0x640000000, 1 GiB\n");
+		NOTICE("BL2: CH3: 0x700000000 - 0x740000000, 1 GiB\n");
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
+      (RCAR_DRAM_CHANNEL        == 5) && \
+      (RCAR_DRAM_SPLIT          == 2)
+		NOTICE("BL2: CH0: 0x400000000 - 0x480000000, 2 GiB\n");
+		NOTICE("BL2: CH1: 0x500000000 - 0x580000000, 2 GiB\n");
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
+		NOTICE("BL2: CH0: 0x400000000 - 0x480000000, 2 GiB\n");
+		NOTICE("BL2: CH1: 0x500000000 - 0x580000000, 2 GiB\n");
+		NOTICE("BL2: CH2: 0x600000000 - 0x680000000, 2 GiB\n");
+		NOTICE("BL2: CH3: 0x700000000 - 0x780000000, 2 GiB\n");
+#endif
+	}
+
+	if (product == RCAR_PRODUCT_E3) {
+#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
+		NOTICE("BL2: 0x400000000 - 0x440000000, 1 GiB\n");
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
+		NOTICE("BL2: 0x400000000 - 0x480000000, 2 GiB\n");
+#endif
+	}
+
+	if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
+	    boot_cpu == MODEMR_BOOT_CPU_CA53) {
+		ret = rcar_dram_init();
+		if (ret) {
+			NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
+			panic();
+		}
+		rcar_qos_init();
+	}
+
+	if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
+	    boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
+		if (rcar_emmc_init() != EMMC_SUCCESS) {
+			NOTICE("BL2: Failed to eMMC driver initialize.\n");
+			panic();
+		}
+		rcar_emmc_memcard_power(EMMC_POWER_ON);
+		if (rcar_emmc_mount() != EMMC_SUCCESS) {
+			NOTICE("BL2: Failed to eMMC mount operation.\n");
+			panic();
+		}
+	} else {
+		rcar_rpc_init();
+		rcar_dma_init();
+	}
+
+	reg = mmio_read_32(RST_WDTRSTCR);
+	reg &= ~WDTRSTCR_RWDT_RSTMSK;
+	reg |= WDTRSTCR_PASSWORD;
+	mmio_write_32(RST_WDTRSTCR, reg);
+
+	mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
+	mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
+
+	reg = mmio_read_32(RCAR_PRR);
+	if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
+		mmio_write_32(CPG_CA57DBGRCR,
+			      DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
+
+	if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
+		mmio_write_32(CPG_CA53DBGRCR,
+			      DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
+
+	if (product_cut == RCAR_PRODUCT_H3_CUT10) {
+		reg = mmio_read_32(CPG_PLL2CR);
+		reg &= ~((uint32_t) 1 << 5);
+		mmio_write_32(CPG_PLL2CR, reg);
+
+		reg = mmio_read_32(CPG_PLL4CR);
+		reg &= ~((uint32_t) 1 << 5);
+		mmio_write_32(CPG_PLL4CR, reg);
+
+		reg = mmio_read_32(CPG_PLL0CR);
+		reg &= ~((uint32_t) 1 << 12);
+		mmio_write_32(CPG_PLL0CR, reg);
+	}
+#if (RCAR_LOSSY_ENABLE == 1)
+	NOTICE("BL2: Lossy Decomp areas\n");
+	bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
+			  LOSSY_FMT0, LOSSY_ENA_DIS0);
+	bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
+			  LOSSY_FMT1, LOSSY_ENA_DIS1);
+	bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
+			  LOSSY_FMT2, LOSSY_ENA_DIS2);
+#endif
+
+	if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
+	    boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
+		rcar_io_emmc_setup();
+	else
+		rcar_io_setup();
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+#if RCAR_BL2_DCACHE == 1
+	NOTICE("BL2: D-Cache enable\n");
+	rcar_configure_mmu_el3(BL2_BASE,
+			       RCAR_SYSRAM_LIMIT - BL2_BASE,
+			       BL2_RO_BASE, BL2_RO_LIMIT
+#if USE_COHERENT_MEM
+			       , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
+#endif
+	    );
+#endif
+}
+
+void bl2_platform_setup(void)
+{
+
+}
diff --git a/plat/renesas/rcar/bl2_secure_setting.c b/plat/renesas/rcar/bl2_secure_setting.c
new file mode 100644
index 0000000..35c658c
--- /dev/null
+++ b/plat/renesas/rcar/bl2_secure_setting.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "axi_registers.h"
+#include "lifec_registers.h"
+#include "micro_delay.h"
+#include "mmio.h"
+#include "utils_def.h"
+
+static void lifec_security_setting(void);
+static void axi_security_setting(void);
+
+static const struct {
+	uint32_t reg;
+	uint32_t val;
+} lifec[] = {
+	/** LIFEC0 (SECURITY) settings					*/
+	/* Security attribute setting for master ports                  */
+	/* Bit 0: ARM realtime core (Cortex-R7) master port             */
+	/*       0: Non-Secure                                          */
+	{
+	SEC_SRC, 0x0000001EU},
+	/** Security attribute setting for slave ports 0 to 15		*/
+	    /*      {SEC_SEL0,              0xFFFFFFFFU},                   */
+	    /*      {SEC_SEL1,              0xFFFFFFFFU},                   */
+	    /*      {SEC_SEL2,              0xFFFFFFFFU},                   */
+	    /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports          */
+	    /*        0: registers accessed from secure resource only       */
+	    /* Bit 9: DBSC4 register access slave ports.                    */
+	    /*        0: registers accessed from secure resource only.      */
+#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
+	{
+	SEC_SEL3, 0xFFF7FDFFU},
+#else
+	{
+	SEC_SEL3, 0xFFFFFFFFU},
+#endif
+	    /*      {SEC_SEL4,              0xFFFFFFFFU},                   */
+	    /* Bit 6: Boot ROM slave ports.                                 */
+	    /*        0: registers accessed from secure resource only       */
+	{
+	SEC_SEL5, 0xFFFFFFBFU},
+	    /* Bit13: SCEG PKA (secure APB) slave ports                     */
+	    /*        0: registers accessed from secure resource only       */
+	    /*        1: Reserved[R-Car E3]                                 */
+	    /* Bit12: SCEG PKA (public APB) slave ports                     */
+	    /*        0: registers accessed from secure resource only       */
+	    /*        1: Reserved[R-Car E3]                                 */
+	    /* Bit10: SCEG Secure Core slave ports                          */
+	    /*        0: registers accessed from secure resource only       */
+#if RCAR_LSI == RCAR_E3
+	{
+	SEC_SEL6, 0xFFFFFBFFU},
+#else
+	{
+	SEC_SEL6, 0xFFFFCBFFU},
+#endif
+	    /*      {SEC_SEL7,              0xFFFFFFFFU},                   */
+	    /*      {SEC_SEL8,              0xFFFFFFFFU},                   */
+	    /*      {SEC_SEL9,              0xFFFFFFFFU},                   */
+	    /*      {SEC_SEL10,             0xFFFFFFFFU},                   */
+	    /*      {SEC_SEL11,             0xFFFFFFFFU},                   */
+	    /*      {SEC_SEL12,             0xFFFFFFFFU},                   */
+	    /* Bit22: RPC slave ports.                                      */
+	    /*        0: registers accessed from secure resource only.      */
+	    /* {SEC_SEL13,          0xFFBFFFFFU},*/
+	    /* Bit27: System Timer (SCMT) slave ports                       */
+	    /*        0: registers accessed from secure resource only       */
+	    /* Bit26: System Watchdog Timer (SWDT) slave ports              */
+	    /*        0: registers accessed from secure resource only       */
+	{
+	SEC_SEL14, 0xF3FFFFFFU},
+	    /* Bit13: RST slave ports. */
+	    /*        0: registers accessed from secure resource only       */
+	    /* Bit 7: Life Cycle 0 slave ports                              */
+	    /*        0: registers accessed from secure resource only       */
+	{
+	SEC_SEL15, 0xFFFFFF3FU},
+	/** Security group 0 attribute setting for master ports 0	*/
+	/** Security group 1 attribute setting for master ports 0	*/
+	    /*      {SEC_GRP0CR0,           0x00000000U},                   */
+	    /*      {SEC_GRP1CR0,           0x00000000U},                   */
+	/** Security group 0 attribute setting for master ports 1	*/
+	/** Security group 1 attribute setting for master ports 1	*/
+	    /*      {SEC_GRP0CR1,           0x00000000U},                   */
+	    /*      {SEC_GRP1CR1,           0x00000000U},                   */
+	/** Security group 0 attribute setting for master ports 2 	*/
+	/** Security group 1 attribute setting for master ports 2 	*/
+	    /* Bit17: SCEG Secure Core master ports.                        */
+	    /*        SecurityGroup3                                        */
+	{
+	SEC_GRP0CR2, 0x00020000U}, {
+	SEC_GRP1CR2, 0x00020000U},
+	/** Security group 0 attribute setting for master ports 3 	*/
+	/** Security group 1 attribute setting for master ports 3 	*/
+	    /*      {SEC_GRP0CR3,           0x00000000U},                   */
+	    /*      {SEC_GRP1CR3,           0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 0 	*/
+	/** Security group 1 attribute setting for slave ports 0 	*/
+	    /*      {SEC_GRP0COND0,         0x00000000U},                   */
+	    /*      {SEC_GRP1COND0,         0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 1 	*/
+	/** Security group 1 attribute setting for slave ports 1 	*/
+	    /*      {SEC_GRP0COND1,         0x00000000U},                   */
+	    /*      {SEC_GRP1COND1,         0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 2 	*/
+	/** Security group 1 attribute setting for slave ports 2 	*/
+	    /*      {SEC_GRP0COND2,         0x00000000U},                   */
+	    /*      {SEC_GRP1COND2,         0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 3	*/
+	/** Security group 1 attribute setting for slave ports 3	*/
+	    /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports.         */
+	    /*        SecurityGroup3                                        */
+	    /* Bit 9: DBSC4 register access slave ports.                    */
+	    /*        SecurityGroup3                                        */
+#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
+	{
+	SEC_GRP0COND3, 0x00080200U}, {
+	SEC_GRP1COND3, 0x00080200U},
+#else
+	{
+	SEC_GRP0COND3, 0x00000000U}, {
+	SEC_GRP1COND3, 0x00000000U},
+#endif
+	/** Security group 0 attribute setting for slave ports 4	*/
+	/** Security group 1 attribute setting for slave ports 4	*/
+	    /*      {SEC_GRP0COND4,         0x00000000U},                   */
+	    /*      {SEC_GRP1COND4,         0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 5	*/
+	/** Security group 1 attribute setting for slave ports 5	*/
+	    /* Bit 6: Boot ROM slave ports                                  */
+	    /*        SecurityGroup3                                        */
+	{
+	SEC_GRP0COND5, 0x00000040U}, {
+	SEC_GRP1COND5, 0x00000040U},
+	/** Security group 0 attribute setting for slave ports 6	*/
+	/** Security group 1 attribute setting for slave ports 6	*/
+	    /* Bit13: SCEG PKA (secure APB) slave ports                     */
+	    /*        SecurityGroup3                                        */
+	    /*        Reserved[R-Car E3]                                    */
+	    /* Bit12: SCEG PKA (public APB) slave ports                     */
+	    /*        SecurityGroup3                                        */
+	    /*        Reserved[R-Car E3]                                    */
+	    /* Bit10: SCEG Secure Core slave ports                          */
+	    /*        SecurityGroup3                                        */
+#if RCAR_LSI == RCAR_E3
+	{
+	SEC_GRP0COND6, 0x00000400U}, {
+	SEC_GRP1COND6, 0x00000400U},
+#else
+	{
+	SEC_GRP0COND6, 0x00003400U}, {
+	SEC_GRP1COND6, 0x00003400U},
+#endif
+	/** Security group 0 attribute setting for slave ports 7	*/
+	/** Security group 1 attribute setting for slave ports 7	*/
+	    /*      {SEC_GRP0COND7,         0x00000000U},                   */
+	    /*      {SEC_GRP1COND7,         0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 8	*/
+	/** Security group 1 attribute setting for slave ports 8	*/
+	    /*      {SEC_GRP0COND8,         0x00000000U},                   */
+	    /*      {SEC_GRP1COND8,         0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 9	*/
+	/** Security group 1 attribute setting for slave ports 9	*/
+	    /*      {SEC_GRP0COND9,         0x00000000U},                   */
+	    /*      {SEC_GRP1COND9,         0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 10	*/
+	/** Security group 1 attribute setting for slave ports 10	*/
+	    /*      {SEC_GRP0COND10,        0x00000000U},                   */
+	    /*      {SEC_GRP1COND10,        0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 11	*/
+	/** Security group 1 attribute setting for slave ports 11	*/
+	    /*      {SEC_GRP0COND11,        0x00000000U},                   */
+	    /*      {SEC_GRP1COND11,        0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 12	*/
+	/** Security group 1 attribute setting for slave ports 12	*/
+	    /*      {SEC_GRP0COND12,        0x00000000U},                   */
+	    /*      {SEC_GRP1COND12,        0x00000000U},                   */
+	/** Security group 0 attribute setting for slave ports 13	*/
+	/** Security group 1 attribute setting for slave ports 13	*/
+	    /* Bit22: RPC slave ports.                                      */
+	    /*        SecurityGroup3                                        */
+	    /* {SEC_GRP0COND13,     0x00400000U}, */
+	    /* {SEC_GRP1COND13,     0x00400000U}, */
+	/** Security group 0 attribute setting for slave ports 14	*/
+	/** Security group 1 attribute setting for slave ports 14	*/
+	    /* Bit26: System Timer (SCMT) slave ports                       */
+	    /*        SecurityGroup3                                        */
+	    /* Bit27: System Watchdog Timer (SWDT) slave ports              */
+	    /*        SecurityGroup3                                        */
+	{
+	SEC_GRP0COND14, 0x0C000000U}, {
+	SEC_GRP1COND14, 0x0C000000U},
+	/** Security group 0 attribute setting for slave ports 15	*/
+	/** Security group 1 attribute setting for slave ports 15 	*/
+	    /* Bit13: RST slave ports                                       */
+	    /*        SecurityGroup3                                        */
+	    /* Bit 7: Life Cycle 0 slave ports                              */
+	    /*        SecurityGroup3                                        */
+	    /* Bit 6: TDBG slave ports                                      */
+	    /*        SecurityGroup3                                        */
+	{
+	SEC_GRP0COND15, 0x000000C0U}, {
+	SEC_GRP1COND15, 0x000000C0U},
+	/** Security write protection attribute setting slave ports 0	*/
+	    /*      {SEC_READONLY0,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 1	*/
+	    /*      {SEC_READONLY1,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 2	*/
+	    /*      {SEC_READONLY2,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 3	*/
+	    /*      {SEC_READONLY3,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 4	*/
+	    /*      {SEC_READONLY4,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 5	*/
+	    /*      {SEC_READONLY5,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 6	*/
+	    /*      {SEC_READONLY6,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 7	*/
+	    /*      {SEC_READONLY7,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 8	*/
+	    /*      {SEC_READONLY8,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 9	*/
+	    /*      {SEC_READONLY9,         0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 10	*/
+	    /*      {SEC_READONLY10,        0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 11	*/
+	    /*      {SEC_READONLY11,        0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 12	*/
+	    /*      {SEC_READONLY12,        0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 13	*/
+	    /*      {SEC_READONLY13,        0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 14	*/
+	    /*      {SEC_READONLY14,        0x00000000U},                   */
+	/** Security write protection attribute setting slave ports 15	*/
+	    /*      {SEC_READONLY15,        0x00000000U}                    */
+};
+
+/* AXI settings */
+static const struct {
+	uint32_t reg;
+	uint32_t val;
+} axi[] = {
+	/* DRAM protection                      */
+	/* AXI dram protected area division     */
+	{
+	AXI_DPTDIVCR0,  0x0E0403F0U}, {
+	AXI_DPTDIVCR1,  0x0E0407E0U}, {
+	AXI_DPTDIVCR2,  0x0E080000U}, {
+	AXI_DPTDIVCR3,  0x0E080000U}, {
+	AXI_DPTDIVCR4,  0x0E080000U}, {
+	AXI_DPTDIVCR5,  0x0E080000U}, {
+	AXI_DPTDIVCR6,  0x0E080000U}, {
+	AXI_DPTDIVCR7,  0x0E080000U}, {
+	AXI_DPTDIVCR8,  0x0E080000U}, {
+	AXI_DPTDIVCR9,  0x0E080000U}, {
+	AXI_DPTDIVCR10, 0x0E080000U}, {
+	AXI_DPTDIVCR11, 0x0E080000U}, {
+	AXI_DPTDIVCR12, 0x0E080000U}, {
+	AXI_DPTDIVCR13, 0x0E080000U}, {
+	AXI_DPTDIVCR14, 0x0E080000U},
+	    /* AXI dram protected area setting      */
+	{
+	AXI_DPTCR0,  0x0E000000U}, {
+	AXI_DPTCR1,  0x0E000E0EU}, {
+	AXI_DPTCR2,  0x0E000000U}, {
+	AXI_DPTCR3,  0x0E000000U}, {
+	AXI_DPTCR4,  0x0E000000U}, {
+	AXI_DPTCR5,  0x0E000000U}, {
+	AXI_DPTCR6,  0x0E000000U}, {
+	AXI_DPTCR7,  0x0E000000U}, {
+	AXI_DPTCR8,  0x0E000000U}, {
+	AXI_DPTCR9,  0x0E000000U}, {
+	AXI_DPTCR10, 0x0E000000U}, {
+	AXI_DPTCR11, 0x0E000000U}, {
+	AXI_DPTCR12, 0x0E000000U}, {
+	AXI_DPTCR13, 0x0E000000U}, {
+	AXI_DPTCR14, 0x0E000000U}, {
+	AXI_DPTCR15, 0x0E000000U},
+	    /* SRAM ptotection                      */
+	    /* AXI sram protected area division     */
+	{
+	AXI_SPTDIVCR0,  0x0E0E6304U}, {
+	AXI_SPTDIVCR1,  0x0E0E6360U}, {
+	AXI_SPTDIVCR2,  0x0E0E6360U}, {
+	AXI_SPTDIVCR3,  0x0E0E6360U}, {
+	AXI_SPTDIVCR4,  0x0E0E6360U}, {
+	AXI_SPTDIVCR5,  0x0E0E6360U}, {
+	AXI_SPTDIVCR6,  0x0E0E6360U}, {
+	AXI_SPTDIVCR7,  0x0E0E6360U}, {
+	AXI_SPTDIVCR8,  0x0E0E6360U}, {
+	AXI_SPTDIVCR9,  0x0E0E6360U}, {
+	AXI_SPTDIVCR10, 0x0E0E6360U}, {
+	AXI_SPTDIVCR11, 0x0E0E6360U}, {
+	AXI_SPTDIVCR12, 0x0E0E6360U}, {
+	AXI_SPTDIVCR13, 0x0E0E6360U}, {
+	AXI_SPTDIVCR14, 0x0E0E6360U},
+	    /* AXI sram protected area setting      */
+	{
+	AXI_SPTCR0,  0x0E000E0EU}, {
+	AXI_SPTCR1,  0x0E000000U}, {
+	AXI_SPTCR2,  0x0E000000U}, {
+	AXI_SPTCR3,  0x0E000000U}, {
+	AXI_SPTCR4,  0x0E000000U}, {
+	AXI_SPTCR5,  0x0E000000U}, {
+	AXI_SPTCR6,  0x0E000000U}, {
+	AXI_SPTCR7,  0x0E000000U}, {
+	AXI_SPTCR8,  0x0E000000U}, {
+	AXI_SPTCR9,  0x0E000000U}, {
+	AXI_SPTCR10, 0x0E000000U}, {
+	AXI_SPTCR11, 0x0E000000U}, {
+	AXI_SPTCR12, 0x0E000000U}, {
+	AXI_SPTCR13, 0x0E000000U}, {
+	AXI_SPTCR14, 0x0E000000U}, {
+	AXI_SPTCR15, 0x0E000000U}
+};
+
+static void lifec_security_setting(void)
+{
+	uint32_t i;
+
+	for (i = 0; i < ARRAY_SIZE(lifec); i++)
+		mmio_write_32(lifec[i].reg, lifec[i].val);
+}
+
+/* SRAM/DRAM protection setting */
+static void axi_security_setting(void)
+{
+	uint32_t i;
+
+	for (i = 0; i < ARRAY_SIZE(axi); i++)
+		mmio_write_32(axi[i].reg, axi[i].val);
+}
+
+void bl2_secure_setting(void)
+{
+	const uint32_t delay = 10;
+
+	lifec_security_setting();
+	axi_security_setting();
+	rcar_micro_delay(delay);
+
+	return;
+}
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
new file mode 100644
index 0000000..00f6d10
--- /dev/null
+++ b/plat/renesas/rcar/bl31_plat_setup.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <bl_common.h>
+#include <bl31.h>
+#include <cci.h>
+#include <console.h>
+#include <mmio.h>
+#include <platform.h>
+#include <stddef.h>
+#include <debug.h>
+#include "pwrc.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+#include "rcar_version.h"
+
+IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE)
+IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT)
+
+#if USE_COHERENT_MEM
+IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE)
+IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT)
+#endif
+
+extern void plat_rcar_gic_driver_init(void);
+extern void plat_rcar_gic_init(void);
+
+u_register_t rcar_boot_mpidr;
+
+static int cci_map[] = {
+	CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3,
+	CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3
+};
+
+void plat_cci_init(void)
+{
+	uint32_t prd;
+
+	prd = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+
+	if (RCAR_PRODUCT_H3_CUT10 == prd || RCAR_PRODUCT_H3_CUT11 == prd) {
+		cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
+		cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
+	}
+
+	cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
+}
+
+void plat_cci_enable(void)
+{
+	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+}
+
+void plat_cci_disable(void)
+{
+	cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
+}
+
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+	bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
+					     PARAMS_BASE;
+	entry_point_info_t *next_image_info;
+
+	next_image_info = (type == NON_SECURE) ?
+		&from_bl2->bl33_ep_info : &from_bl2->bl32_ep_info;
+
+	return next_image_info->pc ? next_image_info : NULL;
+}
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
+{
+	/* dummy config: the actual console configuration (platform specific)
+	   is done in the driver (scif.c) */
+	console_init(1, 0, 0);
+
+	NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
+
+	if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) {
+		plat_cci_init();
+		plat_cci_enable();
+	}
+}
+
+void bl31_plat_arch_setup(void)
+{
+	rcar_configure_mmu_el3(BL31_BASE,
+			       BL31_LIMIT - BL31_BASE,
+			       BL31_RO_BASE, BL31_RO_LIMIT
+#if USE_COHERENT_MEM
+			       , BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
+#endif
+	    );
+}
+
+void bl31_platform_setup(void)
+{
+	plat_rcar_gic_driver_init();
+	plat_rcar_gic_init();
+
+	/* enable the system level generic timer */
+	mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
+
+	rcar_pwrc_setup();
+#if 0
+	/* TODO: there is a broad number of rcar-gen3 SoC configurations; to
+	   support all of them, Renesas use the pwrc driver to discover what
+	   cores are on/off before announcing the topology.
+	   This code hasnt been ported yet
+	   */
+
+	rcar_setup_topology();
+#endif
+
+	/* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
+	   identified during cpuhotplug (check the kernel's psci migrate set of
+	   functions */
+	rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
+}
diff --git a/plat/renesas/rcar/include/plat.ld.S b/plat/renesas/rcar/include/plat.ld.S
new file mode 100644
index 0000000..90c132d
--- /dev/null
+++ b/plat/renesas/rcar/include/plat.ld.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __RCAR_PLAT_LD_S__
+#define __RCAR_PLAT_LD_S__
+
+#include <platform_def.h>
+#include <xlat_tables_defs.h>
+
+MEMORY {
+    SRAM (rwx): ORIGIN = BL31_SRAM_BASE, LENGTH = DEVICE_SRAM_SIZE
+    PRAM (r): ORIGIN = BL31_LIMIT - DEVICE_SRAM_SIZE, LENGTH = DEVICE_SRAM_SIZE
+}
+
+SECTIONS
+{
+	/* SRAM_COPY is in PRAM */
+	. = BL31_LIMIT - DEVICE_SRAM_SIZE;
+	__SRAM_COPY_START__ = .;
+
+	.system_ram : {
+		/* system ram start is in SRAM */
+		__system_ram_start__ = .;
+		*(.system_ram*)
+		*iic_dvfs.o(.rodata)
+	        __system_ram_end__ = .;
+	} >SRAM AT>PRAM
+
+    ASSERT(__BL31_END__ <= BL31_LIMIT - DEVICE_SRAM_SIZE,
+    "BL31 image too large - writing on top of SRAM!")
+
+}
+
+#endif /* __RCAR_PLAT_LD_S__ */
diff --git a/plat/renesas/rcar/include/plat_macros.S b/plat/renesas/rcar/include/plat_macros.S
new file mode 100644
index 0000000..eb10928
--- /dev/null
+++ b/plat/renesas/rcar/include/plat_macros.S
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cci.h>
+#include <gic_common.h>
+#include <gicv2.h>
+#include "rcar_def.h"
+
+.section .rodata.gic_reg_name, "aS"
+gicc_regs:
+	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+gicd_pend_reg:
+	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+newline:
+	.asciz "\n"
+spacer:
+	.asciz ":\t\t0x"
+
+	/* ---------------------------------------------
+	 * The below macro prints out relevant GIC
+	 * registers whenever an unhandled exception is
+	 * taken in BL3-1.
+	 * Clobbers: x0 - x10, x16, x17, sp
+	 * ---------------------------------------------
+	 */
+	.macro plat_print_gic_regs
+	mov_imm	x17, RCAR_GICC_BASE
+	mov_imm	x16, RCAR_GICD_BASE
+print_gicc_regs:
+	/* gicc base address is now in x17 */
+	adr	x6, gicc_regs	/* Load the gicc reg list to x6 */
+	/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
+	ldr	w8, [x17, #GICC_HPPIR]
+	ldr	w9, [x17, #GICC_AHPPIR]
+	ldr	w10, [x17, #GICC_CTLR]
+	/* Store to the crash buf and print to console */
+	bl	str_in_crash_buf_print
+
+	/* Print the GICD_ISPENDR regs */
+	add	x7, x16, #GICD_ISPENDR
+	adr	x4, gicd_pend_reg
+	bl	asm_print_str
+gicd_ispendr_loop:
+	sub	x4, x7, x16
+	cmp	x4, #0x280
+	b.eq	exit_print_gic_regs
+	bl	asm_print_hex
+	adr	x4, spacer
+	bl	asm_print_str
+	ldr	x4, [x7], #8
+	bl	asm_print_hex
+	adr	x4, newline
+	bl	asm_print_str
+	b	gicd_ispendr_loop
+exit_print_gic_regs:
+	.endm
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+	.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+	/* ------------------------------------------------
+	 * The below macro prints out relevant interconnect
+	 * registers whenever an unhandled exception is
+	 * taken in BL3-1.
+	 * Clobbers: x0 - x9, sp
+	 * ------------------------------------------------
+	 */
+	.macro plat_print_interconnect_regs
+	adr	x6, cci_iface_regs
+	/* Store in x7 the base address of the first interface */
+	mov_imm	x7, (CCI500_BASE + SLAVE_IFACE3_OFFSET)
+	ldr	w8, [x7, #SNOOP_CTRL_REG]
+	/* Store in x7 the base address of the second interface */
+	mov_imm	x7, (CCI500_BASE + SLAVE_IFACE4_OFFSET)
+	ldr	w9, [x7, #SNOOP_CTRL_REG]
+	/* Store to the crash buf and print to console */
+	bl	str_in_crash_buf_print
+	.endm
+
+	.macro plat_crash_print_regs
+	plat_print_gic_regs
+	plat_print_interconnect_regs
+	.endm
diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h
new file mode 100644
index 0000000..d38eebc
--- /dev/null
+++ b/plat/renesas/rcar/include/platform_def.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H__
+#define PLATFORM_DEF_H__
+
+#include <arch.h>
+#ifndef __ASSEMBLY__
+#include <stdlib.h>
+#endif
+#include "rcar_def.h"
+
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH            aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+ #define FIRMWARE_WELCOME_STR	"Booting Rcar-gen3 Trusted Firmware\n"
+
+/* Size of cacheable stacks */
+#if IMAGE_BL1
+#if TRUSTED_BOARD_BOOT
+#define PLATFORM_STACK_SIZE 	U(0x1000)
+#else
+#define PLATFORM_STACK_SIZE 	U(0x440)
+#endif
+#elif IMAGE_BL2
+#if TRUSTED_BOARD_BOOT
+#define PLATFORM_STACK_SIZE 	U(0x1000)
+#else
+#define PLATFORM_STACK_SIZE 	U(0x400)
+#endif
+#elif IMAGE_BL31
+#define PLATFORM_STACK_SIZE 	U(0x400)
+#elif IMAGE_BL32
+#define PLATFORM_STACK_SIZE 	U(0x440)
+#endif
+
+#define BL332_IMAGE_ID		(NS_BL2U_IMAGE_ID + 1)
+#define BL333_IMAGE_ID		(NS_BL2U_IMAGE_ID + 2)
+#define BL334_IMAGE_ID		(NS_BL2U_IMAGE_ID + 3)
+#define BL335_IMAGE_ID		(NS_BL2U_IMAGE_ID + 4)
+#define BL336_IMAGE_ID		(NS_BL2U_IMAGE_ID + 5)
+#define BL337_IMAGE_ID		(NS_BL2U_IMAGE_ID + 6)
+#define BL338_IMAGE_ID		(NS_BL2U_IMAGE_ID + 7)
+
+#define BL332_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 8)
+#define BL333_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 9)
+#define BL334_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 10)
+#define BL335_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 11)
+#define BL336_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 12)
+#define BL337_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 13)
+#define BL338_KEY_CERT_ID	(NS_BL2U_IMAGE_ID + 14)
+
+#define BL332_CERT_ID		(NS_BL2U_IMAGE_ID + 15)
+#define BL333_CERT_ID		(NS_BL2U_IMAGE_ID + 16)
+#define BL334_CERT_ID		(NS_BL2U_IMAGE_ID + 17)
+#define BL335_CERT_ID		(NS_BL2U_IMAGE_ID + 18)
+#define BL336_CERT_ID		(NS_BL2U_IMAGE_ID + 19)
+#define BL337_CERT_ID		(NS_BL2U_IMAGE_ID + 20)
+#define BL338_CERT_ID		(NS_BL2U_IMAGE_ID + 21)
+
+/* io drivers id */
+#define FLASH_DEV_ID		U(0)
+#define EMMC_DEV_ID		U(1)
+
+/*
+ * R-Car H3 Cortex-A57
+ * L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way)
+ *          Cortex-A53
+ * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
+ */
+#define PLATFORM_CACHE_LINE_SIZE	128
+#define PLATFORM_CLUSTER_COUNT		U(2)
+#define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
+#define PLATFORM_CLUSTER1_CORE_COUNT	U(4)
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
+					 PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER	U(4)
+
+#define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL2
+#define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CORE_COUNT + \
+					 PLATFORM_CLUSTER_COUNT + 1)
+
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(2)
+
+#define MAX_IO_DEVICES			U(3)
+#define MAX_IO_HANDLES			U(4)
+
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+/* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
+ * size plus a little space for growth. */
+#define RCAR_SYSRAM_BASE		U(0xE6300000)
+#if RCAR_LSI == RCAR_E3
+#define RCAR_SYSRAM_LIMIT		U(0xE6320000)
+#else
+#define RCAR_SYSRAM_LIMIT		U(0xE6360000)
+#endif
+
+#define BL2_BASE			U(0xE6304000)
+#if RCAR_LSI == RCAR_E3
+#define BL2_LIMIT			U(0xE6318000)
+#else
+#define BL2_LIMIT			U(0xE632E800)
+#endif
+#define RCAR_SYSRAM_SIZE		(BL2_BASE - RCAR_SYSRAM_BASE)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
+ * current BL3-1 debug size plus a little space for growth. */
+#define BL31_BASE		(RCAR_TRUSTED_SRAM_BASE)
+#define BL31_LIMIT		(RCAR_TRUSTED_SRAM_BASE + \
+				 RCAR_TRUSTED_SRAM_SIZE)
+#define	RCAR_BL31_LOG_BASE	(0x44040000)
+#define	RCAR_BL31_SDRAM_BTM	(RCAR_BL31_LOG_BASE + 0x14000)
+#define	RCAR_BL31_LOG_SIZE	(RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
+#define BL31_SRAM_BASE		(DEVICE_SRAM_BASE)
+#define BL31_SRAM_LIMIT		(DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
+
+/*******************************************************************************
+ * BL32 specific defines.
+ ******************************************************************************/
+#ifndef SPD_NONE
+#define BL32_BASE		U(0x44100000)
+#define BL32_LIMIT		(BL32_BASE + U(0x100000))
+#endif
+
+/*******************************************************************************
+ * BL33
+ ******************************************************************************/
+#define BL33_BASE		DRAM1_NS_BASE
+
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#if IMAGE_BL1
+#define MAX_XLAT_TABLES		U(2)
+#elif IMAGE_BL2
+#define MAX_XLAT_TABLES		U(5)
+#elif IMAGE_BL31
+#define MAX_XLAT_TABLES		U(4)
+#elif IMAGE_BL32
+#define MAX_XLAT_TABLES		U(3)
+#endif
+
+#if IMAGE_BL2
+#define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 40)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 32)
+#endif
+
+#define MAX_MMAP_REGIONS	(RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS)
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT   (6)
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/*******************************************************************************
+ * Size of the per-cpu data in bytes that should be reserved in the generic
+ * per-cpu data structure for the RCAR port.
+ ******************************************************************************/
+#if !USE_COHERENT_MEM
+#define PLAT_PCPU_DATA_SIZE	(2)
+#endif
+
+#endif
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h
new file mode 100644
index 0000000..eb195b4
--- /dev/null
+++ b/plat/renesas/rcar/include/rcar_def.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_DEF_H__
+#define RCAR_DEF_H__
+
+#include <tbbr_img_def.h>
+#include <utils_def.h>
+
+#define RCAR_PRIMARY_CPU		0x0
+#define RCAR_TRUSTED_SRAM_BASE		0x44000000
+#define RCAR_TRUSTED_SRAM_SIZE		0x0003E000
+#define RCAR_SHARED_MEM_BASE		(RCAR_TRUSTED_SRAM_BASE + \
+					RCAR_TRUSTED_SRAM_SIZE)
+#define RCAR_SHARED_MEM_SIZE		U(0x00001000)
+#define FLASH0_BASE			U(0x08000000)
+#define FLASH0_SIZE			U(0x04000000)
+#define FLASH_MEMORY_SIZE		U(0x04000000)	/* hyper flash */
+#define FLASH_TRANS_SIZE_UNIT		U(0x00000100)
+#define DEVICE_RCAR_BASE		U(0xE6000000)
+#define DEVICE_RCAR_SIZE		U(0x00300000)
+#define DEVICE_RCAR_BASE2		U(0xE6360000)
+#define DEVICE_RCAR_SIZE2		U(0x19CA0000)
+#define DEVICE_SRAM_BASE		U(0xE6310000)
+#define DEVICE_SRAM_SIZE		U(0x00002000)
+#define DEVICE_SRAM_STACK_BASE		(DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
+#define DEVICE_SRAM_STACK_SIZE		U(0x00001000)
+#define DRAM_LIMIT			ULL(0x0000010000000000)
+#define DRAM1_BASE			U(0x40000000)
+#define DRAM1_SIZE			U(0x80000000)
+#define DRAM1_NS_BASE			(DRAM1_BASE + U(0x10000000))
+#define DRAM1_NS_SIZE			(DRAM1_SIZE - DRAM1_NS_BASE)
+#define	DRAM_40BIT_BASE			ULL(0x0400000000)
+#define	DRAM_40BIT_SIZE			ULL(0x0400000000)
+#define	DRAM_PROTECTED_BASE		ULL(0x43F00000)
+#define	DRAM_40BIT_PROTECTED_BASE	ULL(0x0403F00000)
+#define	DRAM_PROTECTED_SIZE		ULL(0x03F00000)
+#define	RCAR_BL31_CRASH_BASE		U(0x4403F000)
+#define	RCAR_BL31_CRASH_SIZE		U(0x00001000)
+/* Entrypoint mailboxes */
+#define MBOX_BASE			RCAR_SHARED_MEM_BASE
+#define MBOX_SIZE			0x200
+/* Base address where parameters to BL31 are stored */
+#define PARAMS_BASE			(MBOX_BASE + MBOX_SIZE)
+#define BOOT_KIND_BASE			(RCAR_SHARED_MEM_BASE + \
+					RCAR_SHARED_MEM_SIZE - 0x100)
+/* The number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU */
+#if USE_COHERENT_MEM
+#define RCAR_BL_REGIONS			(3)
+#else
+#define RCAR_BL_REGIONS			(2)
+#endif
+/* The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[]
+ * defined for each BL stage in rcar_common.c. */
+#if IMAGE_BL2
+#define RCAR_MMAP_ENTRIES		(9)
+#endif
+#if IMAGE_BL31
+#define RCAR_MMAP_ENTRIES		(9)
+#endif
+#if IMAGE_BL2
+#define REG1_BASE			U(0xE6400000)
+#define REG1_SIZE			U(0x04C00000)
+#define ROM0_BASE			U(0xEB100000)
+#define ROM0_SIZE			U(0x00028000)
+#define REG2_BASE			U(0xEC000000)
+#define REG2_SIZE			U(0x14000000)
+#endif
+/* BL33  */
+#define NS_IMAGE_OFFSET			(DRAM1_BASE + U(0x09000000))
+/* BL31 */
+#define	RCAR_DEVICE_BASE		DEVICE_RCAR_BASE
+#define	RCAR_DEVICE_SIZE		(0x1A000000)
+#define	RCAR_LOG_RES_SIZE		(512/8)
+#define	RCAR_LOG_HEADER_SIZE		(16)
+#define	RCAR_LOG_OTHER_SIZE		(RCAR_LOG_HEADER_SIZE + \
+					RCAR_LOG_RES_SIZE)
+#define	RCAR_BL31_LOG_MAX		(RCAR_BL31_LOG_SIZE - \
+					RCAR_LOG_OTHER_SIZE)
+#define	RCAR_CRASH_STACK		RCAR_BL31_CRASH_BASE
+#define	AARCH64_SPACE_BASE		ULL(0x00000000000)
+#define	AARCH64_SPACE_SIZE		ULL(0x10000000000)
+/* CCI related constants */
+#define CCI500_BASE				U(0xF1200000)
+#define CCI500_CLUSTER0_SL_IFACE_IX		(2)
+#define CCI500_CLUSTER1_SL_IFACE_IX		(3)
+#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3	(1)
+#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3	(2)
+#define	RCAR_CCI_BASE				CCI500_BASE
+/* GIC */
+#define RCAR_GICD_BASE			U(0xF1010000)
+#define RCAR_GICR_BASE			U(0xF1010000)
+#define RCAR_GICC_BASE			U(0xF1020000)
+#define RCAR_GICH_BASE			U(0xF1040000)
+#define RCAR_GICV_BASE			U(0xF1060000)
+#define ARM_IRQ_SEC_PHY_TIMER		U(29)
+#define ARM_IRQ_SEC_SGI_0		U(8)
+#define ARM_IRQ_SEC_SGI_1		U(9)
+#define ARM_IRQ_SEC_SGI_2		U(10)
+#define ARM_IRQ_SEC_SGI_3		U(11)
+#define ARM_IRQ_SEC_SGI_4		U(12)
+#define ARM_IRQ_SEC_SGI_5		U(13)
+#define ARM_IRQ_SEC_SGI_6		U(14)
+#define ARM_IRQ_SEC_SGI_7		U(15)
+#define	ARM_IRQ_SEC_RPC			U(70)
+#define	ARM_IRQ_SEC_TIMER		U(166)
+#define	ARM_IRQ_SEC_TIMER_UP		U(171)
+#define	ARM_IRQ_SEC_WDT			U(173)
+#define	ARM_IRQ_SEC_CRYPT		U(102)
+#define	ARM_IRQ_SEC_CRYPT_SecPKA	U(97)
+#define	ARM_IRQ_SEC_CRYPT_PubPKA	U(98)
+/* Timer control */
+#define	RCAR_CNTC_BASE		U(0xE6080000)
+/* Reset */
+#define	RCAR_CPGWPR		U(0xE6150900)	/* CPG write protect    */
+#define	RCAR_MODEMR		U(0xE6160060)	/* Mode pin             */
+#define	RCAR_CA57RESCNT		U(0xE6160040)	/* Reset control A57    */
+#define	RCAR_CA53RESCNT		U(0xE6160044)	/* Reset control A53    */
+#define	RCAR_SRESCR		U(0xE6160110)	/* Soft Power On Reset  */
+#define	RCAR_CA53WUPCR		U(0xE6151010)	/* Wake-up control A53  */
+#define	RCAR_CA57WUPCR		U(0xE6152010)	/* Wake-up control A57  */
+#define	RCAR_CA53PSTR		U(0xE6151040)	/* Power status A53     */
+#define	RCAR_CA57PSTR		U(0xE6152040)	/* Power status A57     */
+#define	RCAR_CA53CPU0CR		U(0xE6151100)	/* CPU control  A53     */
+#define	RCAR_CA57CPU0CR		U(0xE6152100)	/* CPU control  A57     */
+#define	RCAR_CA53CPUCMCR	U(0xE6151184)	/* Common power A53     */
+#define	RCAR_CA57CPUCMCR	U(0xE6152184)	/* Common power A57     */
+#define	RCAR_WUPMSKCA57		U(0xE6180014)	/* Wake-up mask A57     */
+#define	RCAR_WUPMSKCA53		U(0xE6180018)	/* Wake-up mask A53     */
+/* SYSC	*/
+#define	RCAR_PWRSR3		U(0xE6180140)	/* Power stat A53-SCU   */
+#define	RCAR_PWRSR5		U(0xE61801C0)	/* Power stat A57-SCU   */
+#define	RCAR_SYSCIER		U(0xE618000C)	/* Interrupt enable     */
+#define	RCAR_SYSCIMR		U(0xE6180010)	/* Interrupt mask       */
+#define	RCAR_SYSCSR		U(0xE6180000)	/* SYSC status          */
+#define	RCAR_PWRONCR3		U(0xE618014C)	/* Power resume A53-SCU */
+#define	RCAR_PWRONCR5		U(0xE61801CC)	/* Power resume A57-SCU */
+#define	RCAR_PWROFFCR3		U(0xE6180144)	/* Power shutof A53-SCU */
+#define	RCAR_PWROFFCR5		U(0xE61801C4)	/* Power shutof A57-SCU */
+#define	RCAR_PWRER3		U(0xE6180154)	/* shutoff/resume error */
+#define	RCAR_PWRER5		U(0xE61801D4)	/* shutoff/resume error */
+#define	RCAR_SYSCISR		U(0xE6180004)	/* Interrupt status     */
+#define	RCAR_SYSCISCR		U(0xE6180008)	/* Interrupt stat clear */
+/* Product register */
+#define	RCAR_PRR			U(0xFFF00044)
+#define RCAR_PRODUCT_MASK		U(0x00007F00)
+#define RCAR_CUT_MASK			U(0x000000FF)
+#define RCAR_PRODUCT_H3			U(0x00004F00)
+#define RCAR_PRODUCT_M3			U(0x00005200)
+#define RCAR_PRODUCT_M3N		U(0x00005500)
+#define RCAR_PRODUCT_E3			U(0x00005700)
+#define RCAR_CUT_VER10			U(0x00000000)
+#define RCAR_CUT_VER11			U(0x00000001)	/* H3/M3N Ver.1.1 */
+#define RCAR_M3_CUT_VER11		U(0x00000010)	/* M3 Ver.1.1/Ver.1.2 */
+#define RCAR_CUT_VER20			U(0x00000010)
+#define RCAR_CUT_VER30			U(0x00000020)
+#define RCAR_MAJOR_MASK			U(0x000000F0)
+#define RCAR_MINOR_MASK			U(0x0000000F)
+#define RCAR_PRODUCT_SHIFT		U(8)
+#define RCAR_MAJOR_SHIFT		U(4)
+#define RCAR_MINOR_SHIFT		U(0)
+#define RCAR_MAJOR_OFFSET		U(1)
+#define RCAR_PRODUCT_H3_CUT10		(RCAR_PRODUCT_H3 | U(0x00))	/* 1.0 */
+#define RCAR_PRODUCT_H3_CUT11		(RCAR_PRODUCT_H3 | U(0x01))	/* 1.1 */
+#define RCAR_PRODUCT_H3_CUT20		(RCAR_PRODUCT_H3 | U(0x10))	/* 2.0 */
+#define RCAR_PRODUCT_M3_CUT10		(RCAR_PRODUCT_M3 | U(0x00))	/* 1.0 */
+#define RCAR_PRODUCT_M3_CUT11		(RCAR_PRODUCT_M3 | U(0x10))
+#define RCAR_CPU_MASK_CA57		U(0x80000000)
+#define RCAR_CPU_MASK_CA53		U(0x04000000)
+#define RCAR_CPU_HAVE_CA57		U(0x00000000)
+#define RCAR_CPU_HAVE_CA53		U(0x00000000)
+#define RCAR_SSCG_MASK			U(0x1000)	/* MD12 */
+#define RCAR_SSCG_ENABLE		U(0x1000)
+/* MD pin information */
+#define MODEMR_BOOT_CPU_MASK		U(0x000000C0)
+#define MODEMR_BOOT_CPU_CR7		U(0x000000C0)
+#define MODEMR_BOOT_CPU_CA57		U(0x00000000)
+#define MODEMR_BOOT_CPU_CA53		U(0x00000040)
+#define MODEMR_BOOT_DEV_MASK		U(0x0000001E)
+#define MODEMR_BOOT_DEV_HYPERFLASH160	U(0x00000004)
+#define MODEMR_BOOT_DEV_HYPERFLASH80	U(0x00000006)
+#define MODEMR_BOOT_DEV_QSPI_FLASH40	U(0x00000008)
+#define MODEMR_BOOT_DEV_QSPI_FLASH80	U(0x0000000C)
+#define MODEMR_BOOT_DEV_EMMC_25X1	U(0x0000000A)
+#define MODEMR_BOOT_DEV_EMMC_50X8	U(0x0000001A)
+#define MODEMR_BOOT_PLL_MASK		U(0x00006000)
+#define MODEMR_BOOT_PLL_SHIFT		U(13)
+/* Memory mapped Generic timer interfaces */
+#define ARM_SYS_CNTCTL_BASE		RCAR_CNTC_BASE
+/* MODEMR PLL masks and bitfield values */
+#define	CHECK_MD13_MD14			U(0x6000)
+#define	MD14_MD13_TYPE_0		U(0x0000)	/* MD14=0 MD13=0 */
+#define	MD14_MD13_TYPE_1		U(0x2000)	/* MD14=0 MD13=1 */
+#define	MD14_MD13_TYPE_2		U(0x4000)	/* MD14=1 MD13=0 */
+#define	MD14_MD13_TYPE_3		U(0x6000)	/* MD14=1 MD13=1 */
+/* Frequency of EXTAL(Hz) */
+#define	EXTAL_MD14_MD13_TYPE_0		U(8333300)	/* MD14=0 MD13=0 */
+#define	EXTAL_MD14_MD13_TYPE_1		U(10000000)	/* MD14=0 MD13=1 */
+#define	EXTAL_MD14_MD13_TYPE_2		U(12500000)	/* MD14=1 MD13=0 */
+#define	EXTAL_MD14_MD13_TYPE_3		U(16666600)	/* MD14=1 MD13=1 */
+#define	EXTAL_SALVATOR_XS		U(8320000)	/* Salvator-XS */
+#define EXTAL_EBISU			U(24000000)	/* Ebisu */
+/* CPU Auxiliary Control Register */
+#define RCAR_CA57_DIS_LOAD_PASS_STORE	(ULL(1) << 55)
+/* CPG write protect registers 	*/
+#define	CPGWPR_PASSWORD			(0x5A5AFFFFU)
+#define	CPGWPCR_PASSWORD		(0xA5A50000U)
+/* CA5x Debug Resource control registers */
+#define	CPG_CA57DBGRCR			(CPG_BASE + 0x2180U)
+#define	CPG_CA53DBGRCR			(CPG_BASE + 0x1180U)
+#define	DBGCPUPREN			((uint32_t)1U << 19U)
+#define	CPG_PLL0CR			(CPG_BASE + 0x00D8U)
+#define	CPG_PLL2CR			(CPG_BASE + 0x002CU)
+#define	CPG_PLL4CR			(CPG_BASE + 0x01F4U)
+/* RST Registers */
+#define	RST_BASE			(0xE6160000U)
+#define	RST_WDTRSTCR			(RST_BASE + 0x0054U)
+#define	WDTRSTCR_PASSWORD		(0xA55A0000U)
+#define	WDTRSTCR_RWDT_RSTMSK		((uint32_t)1U << 0U)
+/* MFIS Registers */
+#define	MFISWPCNTR_PASSWORD		(0xACCE0000U)
+#define	MFISWPCNTR			(0xE6260900U)
+/* IPMMU registers */
+#define IPMMU_MM_BASE			(0xE67B0000U)
+#define IPMMUMM_IMSCTLR			(IPMMU_MM_BASE + 0x0500U)
+#define IPMMUMM_IMAUXCTLR		(IPMMU_MM_BASE + 0x0504U)
+#define IPMMUMM_IMSCTLR_ENABLE		(0xC0000000U)
+#define IPMMUMM_IMAUXCTLR_NMERGE40_BIT	(0x01000000U)
+#define IMSCTLR_DISCACHE		(0xE0000000U)
+#define IPMMU_VI0_BASE			(0xFEBD0000U)
+#define IPMMUVI0_IMSCTLR		(IPMMU_VI0_BASE + 0x0500U)
+#define IPMMU_VI1_BASE			(0xFEBE0000U)
+#define IPMMUVI1_IMSCTLR		(IPMMU_VI1_BASE + 0x0500U)
+#define IPMMU_PV0_BASE			(0xFD800000U)
+#define IPMMUPV0_IMSCTLR		(IPMMU_PV0_BASE + 0x0500U)
+#define IPMMU_PV1_BASE			(0xFD950000U)
+#define IPMMUPV1_IMSCTLR		(IPMMU_PV1_BASE + 0x0500U)
+#define IPMMU_PV2_BASE			(0xFD960000U)
+#define IPMMUPV2_IMSCTLR		(IPMMU_PV2_BASE + 0x0500U)
+#define IPMMU_PV3_BASE			(0xFD970000U)
+#define IPMMUPV3_IMSCTLR		(IPMMU_PV3_BASE + 0x0500U)
+#define IPMMU_HC_BASE			(0xE6570000U)
+#define IPMMUHC_IMSCTLR			(IPMMU_HC_BASE + 0x0500U)
+#define IPMMU_RT_BASE			(0xFFC80000U)
+#define IPMMURT_IMSCTLR			(IPMMU_RT_BASE + 0x0500U)
+#define IPMMU_MP_BASE			(0xEC670000U)
+#define IPMMUMP_IMSCTLR			(IPMMU_MP_BASE + 0x0500U)
+#define IPMMU_DS0_BASE			(0xE6740000U)
+#define IPMMUDS0_IMSCTLR		(IPMMU_DS0_BASE + 0x0500U)
+#define IPMMU_DS1_BASE			(0xE7740000U)
+#define IPMMUDS1_IMSCTLR		(IPMMU_DS1_BASE + 0x0500U)
+/* ARMREG registers */
+#define	P_ARMREG_SEC_CTRL		(0xE62711F0U)
+#define	P_ARMREG_SEC_CTRL_PROT		(0x00000001U)
+/* MIDR */
+#define MIDR_CA57			(0x0D07U << MIDR_PN_SHIFT)
+#define MIDR_CA53			(0x0D03U << MIDR_PN_SHIFT)
+/* for SuspendToRAM */
+#define	GPIO_BASE			(0xE6050000U)
+#define	GPIO_INDT1			(GPIO_BASE + 0x100CU)
+#define GPIO_INDT6			(GPIO_BASE + 0x540CU)
+#define	RCAR_COLD_BOOT			(0x00U)
+#define	RCAR_WARM_BOOT			(0x01U)
+#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
+#define	KEEP10_MAGIC		(0x55U)
+#endif
+/* lossy registers */
+#define LOSSY_PARAMS_BASE 		(0x47FD7000U)
+#define	AXI_DCMPAREACRA0		(0xE6784100U)
+#define	AXI_DCMPAREACRB0		(0xE6784104U)
+#define LOSSY_ENABLE			(0x80000000U)
+#define LOSSY_DISABLE			(0x00000000U)
+#define LOSSY_FMT_YUVPLANAR		(0x00000000U)
+#define LOSSY_FMT_YUV422INTLV		(0x20000000U)
+#define LOSSY_FMT_ARGB8888		(0x40000000U)
+#define	LOSSY_ST_ADDR0			(0x54000000U)
+#define	LOSSY_END_ADDR0			(0x57000000U)
+#define	LOSSY_FMT0			LOSSY_FMT_YUVPLANAR
+#define	LOSSY_ENA_DIS0			LOSSY_ENABLE
+#define	LOSSY_ST_ADDR1			0x0U
+#define	LOSSY_END_ADDR1			0x0U
+#define	LOSSY_FMT1			LOSSY_FMT_ARGB8888
+#define	LOSSY_ENA_DIS1			LOSSY_DISABLE
+#define	LOSSY_ST_ADDR2			0x0U
+#define	LOSSY_END_ADDR2			0x0U
+#define	LOSSY_FMT2			LOSSY_FMT_YUV422INTLV
+#define	LOSSY_ENA_DIS2			LOSSY_DISABLE
+
+#endif
diff --git a/plat/renesas/rcar/include/rcar_private.h b/plat/renesas/rcar/include/rcar_private.h
new file mode 100644
index 0000000..dd35826
--- /dev/null
+++ b/plat/renesas/rcar/include/rcar_private.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RCAR_PRIVATE_H__
+#define RCAR_PRIVATE_H__
+
+#include <bakery_lock.h>
+#include <bl_common.h>
+#include <cpu_data.h>
+#include <platform_def.h>
+
+typedef volatile struct mailbox {
+	unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
+} mailbox_t;
+
+/*
+ * This structure represents the superset of information that is passed to
+ * BL31 e.g. while passing control to it from BL2 which is bl31_params
+ * and bl31_plat_params and its elements
+ */
+typedef struct bl2_to_bl31_params_mem {
+	image_info_t bl32_image_info;
+	image_info_t bl33_image_info;
+	entry_point_info_t bl33_ep_info;
+	entry_point_info_t bl32_ep_info;
+} bl2_to_bl31_params_mem_t;
+
+#if USE_COHERENT_MEM
+#define RCAR_INSTANTIATE_LOCK	DEFINE_BAKERY_LOCK(rcar_lock);
+#define rcar_lock_init()	bakery_lock_init(&rcar_lock)
+#define rcar_lock_get()		bakery_lock_get(&rcar_lock)
+#define rcar_lock_release()	bakery_lock_release(&rcar_lock)
+#else
+/*
+ * Constants to specify how many bakery locks this platform implements. These
+ * are used if the platform chooses not to use coherent memory for bakery lock
+ * data structures.
+ */
+#define RCAR_MAX_BAKERIES	2
+#define RCAR_PWRC_BAKERY_ID	0
+
+/*
+ * Definition of structure which holds platform specific per-cpu data. Currently
+ * it holds only the bakery lock information for each cpu. Constants to
+ * specify how many bakeries this platform implements and bakery ids are
+ * specified in rcar_def.h
+ */
+typedef struct rcar_cpu_data {
+	bakery_info_t pcpu_bakery_info[RCAR_MAX_BAKERIES];
+} rcar_cpu_data_t;
+
+#define RCAR_CPU_DATA_LOCK_OFFSET	\
+	__builtin_offsetof(rcar_cpu_data_t, pcpu_bakery_info)
+/*
+ * Helper macros for bakery lock api when using the above rcar_cpu_data_t for
+ * bakery lock data structures. It assumes that the bakery_info is at the
+ * beginning of the platform specific per-cpu data.
+ */
+#define rcar_lock_init(_lock_arg)
+
+#define rcar_lock_get(_lock_arg) 					\
+	bakery_lock_get(_lock_arg, 					\
+		CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
+
+#define rcar_lock_release(_lock_arg)					\
+	bakery_lock_release(_lock_arg,	    				\
+		CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
+/* Ensure that the size of the RCAR specific per-cpu data structure and the size
+ * of the memory allocated in generic per-cpu data for the platform are the same
+ */
+CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t),
+	rcar_pcpu_data_size_mismatch);
+#endif
+/*
+ * Function and variable prototypes
+ */
+void rcar_configure_mmu_el3(unsigned long total_base,
+			    unsigned long total_size,
+			    unsigned long ro_start, unsigned long ro_limit
+#if USE_COHERENT_MEM
+			    , unsigned long coh_start, unsigned long coh_limit
+#endif
+    );
+
+void rcar_setup_topology(void);
+void rcar_cci_disable(void);
+void rcar_cci_enable(void);
+void rcar_cci_init(void);
+
+void plat_invalidate_icache(void);
+void plat_cci_disable(void);
+void plat_cci_enable(void);
+void plat_cci_init(void);
+
+void mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit);
+void cpg_write(uintptr_t regadr, uint32_t regval);
+
+#endif
diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/rcar/include/rcar_version.h
new file mode 100644
index 0000000..9a9ad9c
--- /dev/null
+++ b/plat/renesas/rcar/include/rcar_version.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	RCAR_VERSION_H__
+#define	RCAR_VERSION_H__
+
+#include <arch_helpers.h>
+
+#define VERSION_OF_RENESAS		"1.0.22"
+#define	VERSION_OF_RENESAS_MAXLEN	(128)
+
+extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
+
+#endif
diff --git a/plat/renesas/rcar/include/registers/axi_registers.h b/plat/renesas/rcar/include/registers/axi_registers.h
new file mode 100644
index 0000000..1d8f41d
--- /dev/null
+++ b/plat/renesas/rcar/include/registers/axi_registers.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	AXI_REGISTER_H__
+#define	AXI_REGISTER_H__
+
+/* AXI registers */
+
+/* AXI base address */
+#define	AXI_BASE	(0xE6780000U)
+
+/* address split */
+
+/* AXI address split control 0 */
+#define	AXI_ADSPLCR0	(AXI_BASE + 0x4008U)
+/* AXI address split control 1 */
+#define	AXI_ADSPLCR1	(AXI_BASE + 0x400CU)
+/* AXI address split control 2 */
+#define	AXI_ADSPLCR2	(AXI_BASE + 0x4010U)
+/* AXI address split control 3 */
+#define	AXI_ADSPLCR3	(AXI_BASE + 0x4014U)
+
+/* functional safety */
+
+/* AXI functional safety control */
+#define	AXI_FUSACR	(AXI_BASE + 0x4020U)
+
+/* decompression */
+
+/* AXI decompression area configuration A0 */
+#define	AXI_DCMPAREACRA0	(AXI_BASE + 0x4100U)
+/* AXI decompression area configuration B0 */
+#define	AXI_DCMPAREACRB0	(AXI_BASE + 0x4104U)
+/* AXI decompression area configuration A1 */
+#define	AXI_DCMPAREACRA1	(AXI_BASE + 0x4108U)
+/* AXI decompression area configuration B1 */
+#define	AXI_DCMPAREACRB1	(AXI_BASE + 0x410CU)
+/* AXI decompression area configuration A2 */
+#define	AXI_DCMPAREACRA2	(AXI_BASE + 0x4110U)
+/* AXI decompression area configuration B2 */
+#define	AXI_DCMPAREACRB2	(AXI_BASE + 0x4114U)
+/* AXI decompression area configuration A3 */
+#define	AXI_DCMPAREACRA3	(AXI_BASE + 0x4118U)
+/* AXI decompression area configuration B3 */
+#define	AXI_DCMPAREACRB3	(AXI_BASE + 0x411CU)
+/* AXI decompression area configuration A4 */
+#define	AXI_DCMPAREACRA4	(AXI_BASE + 0x4120U)
+/* AXI decompression area configuration B4 */
+#define	AXI_DCMPAREACRB4	(AXI_BASE + 0x4124U)
+/* AXI decompression area configuration A5 */
+#define	AXI_DCMPAREACRA5	(AXI_BASE + 0x4128U)
+/* AXI decompression area configuration B5 */
+#define	AXI_DCMPAREACRB5	(AXI_BASE + 0x412CU)
+/* AXI decompression area configuration A6 */
+#define	AXI_DCMPAREACRA6	(AXI_BASE + 0x4130U)
+/* AXI decompression area configuration B6 */
+#define	AXI_DCMPAREACRB6	(AXI_BASE + 0x4134U)
+/* AXI decompression area configuration A7 */
+#define	AXI_DCMPAREACRA7	(AXI_BASE + 0x4138U)
+/* AXI decompression area configuration B7 */
+#define	AXI_DCMPAREACRB7	(AXI_BASE + 0x413CU)
+/* AXI decompression area configuration A8 */
+#define	AXI_DCMPAREACRA8	(AXI_BASE + 0x4140U)
+/* AXI decompression area configuration B8 */
+#define	AXI_DCMPAREACRB8	(AXI_BASE + 0x4144U)
+/* AXI decompression area configuration A9 */
+#define	AXI_DCMPAREACRA9	(AXI_BASE + 0x4148U)
+/* AXI decompression area configuration B9 */
+#define	AXI_DCMPAREACRB9	(AXI_BASE + 0x414CU)
+/* AXI decompression area configuration A10 */
+#define	AXI_DCMPAREACRA10	(AXI_BASE + 0x4150U)
+/* AXI decompression area configuration B10 */
+#define	AXI_DCMPAREACRB10	(AXI_BASE + 0x4154U)
+/* AXI decompression area configuration A11 */
+#define	AXI_DCMPAREACRA11	(AXI_BASE + 0x4158U)
+/* AXI decompression area configuration B11 */
+#define	AXI_DCMPAREACRB11	(AXI_BASE + 0x415CU)
+/* AXI decompression area configuration A12 */
+#define	AXI_DCMPAREACRA12	(AXI_BASE + 0x4160U)
+/* AXI decompression area configuration B12 */
+#define	AXI_DCMPAREACRB12	(AXI_BASE + 0x4164U)
+/* AXI decompression area configuration A13 */
+#define	AXI_DCMPAREACRA13	(AXI_BASE + 0x4168U)
+/* AXI decompression area configuration B13 */
+#define	AXI_DCMPAREACRB13	(AXI_BASE + 0x416CU)
+/* AXI decompression area configuration A14 */
+#define	AXI_DCMPAREACRA14	(AXI_BASE + 0x4170U)
+/* AXI decompression area configuration B14 */
+#define	AXI_DCMPAREACRB14	(AXI_BASE + 0x4174U)
+/* AXI decompression area configuration A15 */
+#define	AXI_DCMPAREACRA15	(AXI_BASE + 0x4178U)
+/* AXI decompression area configuration B15 */
+#define	AXI_DCMPAREACRB15	(AXI_BASE + 0x417CU)
+/* AXI decompression shadow area configuration */
+#define	AXI_DCMPSHDWCR	(AXI_BASE + 0x4280U)
+
+/* SDRAM protection */
+
+/* AXI dram protected area division 0 */
+#define	AXI_DPTDIVCR0	(AXI_BASE + 0x4400U)
+/* AXI dram protected area division 1 */
+#define	AXI_DPTDIVCR1	(AXI_BASE + 0x4404U)
+/* AXI dram protected area division 2 */
+#define	AXI_DPTDIVCR2	(AXI_BASE + 0x4408U)
+/* AXI dram protected area division 3 */
+#define	AXI_DPTDIVCR3	(AXI_BASE + 0x440CU)
+/* AXI dram protected area division 4 */
+#define	AXI_DPTDIVCR4	(AXI_BASE + 0x4410U)
+/* AXI dram protected area division 5 */
+#define	AXI_DPTDIVCR5	(AXI_BASE + 0x4414U)
+/* AXI dram protected area division 6 */
+#define	AXI_DPTDIVCR6	(AXI_BASE + 0x4418U)
+/* AXI dram protected area division 7 */
+#define	AXI_DPTDIVCR7	(AXI_BASE + 0x441CU)
+/* AXI dram protected area division 8 */
+#define	AXI_DPTDIVCR8	(AXI_BASE + 0x4420U)
+/* AXI dram protected area division 9 */
+#define	AXI_DPTDIVCR9	(AXI_BASE + 0x4424U)
+/* AXI dram protected area division 10 */
+#define	AXI_DPTDIVCR10	(AXI_BASE + 0x4428U)
+/* AXI dram protected area division 11 */
+#define	AXI_DPTDIVCR11	(AXI_BASE + 0x442CU)
+/* AXI dram protected area division 12 */
+#define	AXI_DPTDIVCR12	(AXI_BASE + 0x4430U)
+/* AXI dram protected area division 13 */
+#define	AXI_DPTDIVCR13	(AXI_BASE + 0x4434U)
+/* AXI dram protected area division 14 */
+#define	AXI_DPTDIVCR14	(AXI_BASE + 0x4438U)
+
+/* AXI dram protected area setting 0 */
+#define	AXI_DPTCR0	(AXI_BASE + 0x4440U)
+/* AXI dram protected area setting 1 */
+#define	AXI_DPTCR1	(AXI_BASE + 0x4444U)
+/* AXI dram protected area setting 2 */
+#define	AXI_DPTCR2	(AXI_BASE + 0x4448U)
+/* AXI dram protected area setting 3 */
+#define	AXI_DPTCR3	(AXI_BASE + 0x444CU)
+/* AXI dram protected area setting 4 */
+#define	AXI_DPTCR4	(AXI_BASE + 0x4450U)
+/* AXI dram protected area setting 5 */
+#define	AXI_DPTCR5	(AXI_BASE + 0x4454U)
+/* AXI dram protected area setting 6 */
+#define	AXI_DPTCR6	(AXI_BASE + 0x4458U)
+/* AXI dram protected area setting 7 */
+#define	AXI_DPTCR7	(AXI_BASE + 0x445CU)
+/* AXI dram protected area setting 8 */
+#define	AXI_DPTCR8	(AXI_BASE + 0x4460U)
+/* AXI dram protected area setting 9 */
+#define	AXI_DPTCR9	(AXI_BASE + 0x4464U)
+/* AXI dram protected area setting 10 */
+#define	AXI_DPTCR10	(AXI_BASE + 0x4468U)
+/* AXI dram protected area setting 11 */
+#define	AXI_DPTCR11	(AXI_BASE + 0x446CU)
+/* AXI dram protected area setting 12 */
+#define	AXI_DPTCR12	(AXI_BASE + 0x4470U)
+/* AXI dram protected area setting 13 */
+#define	AXI_DPTCR13	(AXI_BASE + 0x4474U)
+/* AXI dram protected area setting 14 */
+#define	AXI_DPTCR14	(AXI_BASE + 0x4478U)
+/* AXI dram protected area setting 15 */
+#define	AXI_DPTCR15	(AXI_BASE + 0x447CU)
+
+/* SRAM protection */
+
+/* AXI sram protected area division 0 */
+#define	AXI_SPTDIVCR0	(AXI_BASE + 0x4500U)
+/* AXI sram protected area division 1 */
+#define	AXI_SPTDIVCR1	(AXI_BASE + 0x4504U)
+/* AXI sram protected area division 2 */
+#define	AXI_SPTDIVCR2	(AXI_BASE + 0x4508U)
+/* AXI sram protected area division 3 */
+#define	AXI_SPTDIVCR3	(AXI_BASE + 0x450CU)
+/* AXI sram protected area division 4 */
+#define	AXI_SPTDIVCR4	(AXI_BASE + 0x4510U)
+/* AXI sram protected area division 5 */
+#define	AXI_SPTDIVCR5	(AXI_BASE + 0x4514U)
+/* AXI sram protected area division 6 */
+#define	AXI_SPTDIVCR6	(AXI_BASE + 0x4518U)
+/* AXI sram protected area division 7 */
+#define	AXI_SPTDIVCR7	(AXI_BASE + 0x451CU)
+/* AXI sram protected area division 8 */
+#define	AXI_SPTDIVCR8	(AXI_BASE + 0x4520U)
+/* AXI sram protected area division 9 */
+#define	AXI_SPTDIVCR9	(AXI_BASE + 0x4524U)
+/* AXI sram protected area division 10 */
+#define	AXI_SPTDIVCR10	(AXI_BASE + 0x4528U)
+/* AXI sram protected area division 11 */
+#define	AXI_SPTDIVCR11	(AXI_BASE + 0x452CU)
+/* AXI sram protected area division 12 */
+#define	AXI_SPTDIVCR12	(AXI_BASE + 0x4530U)
+/* AXI sram protected area division 13 */
+#define	AXI_SPTDIVCR13	(AXI_BASE + 0x4534U)
+/* AXI sram protected area division 14 */
+#define	AXI_SPTDIVCR14	(AXI_BASE + 0x4538U)
+
+/* AXI sram protected area setting 0 */
+#define	AXI_SPTCR0	(AXI_BASE + 0x4540U)
+/* AXI sram protected area setting 1 */
+#define	AXI_SPTCR1	(AXI_BASE + 0x4544U)
+/* AXI sram protected area setting 2 */
+#define	AXI_SPTCR2	(AXI_BASE + 0x4548U)
+/* AXI sram protected area setting 3 */
+#define	AXI_SPTCR3	(AXI_BASE + 0x454CU)
+/* AXI sram protected area setting 4 */
+#define	AXI_SPTCR4	(AXI_BASE + 0x4550U)
+/* AXI sram protected area setting 5 */
+#define	AXI_SPTCR5	(AXI_BASE + 0x4554U)
+/* AXI sram protected area setting 6 */
+#define	AXI_SPTCR6	(AXI_BASE + 0x4558U)
+/* AXI sram protected area setting 7 */
+#define	AXI_SPTCR7	(AXI_BASE + 0x455CU)
+/* AXI sram protected area setting 8 */
+#define	AXI_SPTCR8	(AXI_BASE + 0x4560U)
+/* AXI sram protected area setting 9 */
+#define	AXI_SPTCR9	(AXI_BASE + 0x4564U)
+/* AXI sram protected area setting 10 */
+#define	AXI_SPTCR10	(AXI_BASE + 0x4568U)
+/* AXI sram protected area setting 11 */
+#define	AXI_SPTCR11	(AXI_BASE + 0x456CU)
+/* AXI sram protected area setting 12 */
+#define	AXI_SPTCR12	(AXI_BASE + 0x4570U)
+/* AXI sram protected area setting 13 */
+#define	AXI_SPTCR13	(AXI_BASE + 0x4574U)
+/* AXI sram protected area setting 14 */
+#define	AXI_SPTCR14	(AXI_BASE + 0x4578U)
+/* AXI sram protected area setting 15 */
+#define	AXI_SPTCR15	(AXI_BASE + 0x457CU)
+
+/* EDC base address */
+#define	EDC_BASE	(0xFF840000U)
+
+/* EDC edc enable */
+#define	EDC_EDCEN	(EDC_BASE + 0x0010U)
+/* EDC edc status 0 */
+#define	EDC_EDCST0	(EDC_BASE + 0x0020U)
+/* EDC edc status 1 */
+#define	EDC_EDCST1	(EDC_BASE + 0x0024U)
+/* EDC edc interrupt enable 0 */
+#define	EDC_EDCINTEN0	(EDC_BASE + 0x0040U)
+/* EDC edc interrupt enable 1 */
+#define	EDC_EDCINTEN1	(EDC_BASE + 0x0044U)
+
+#endif
diff --git a/plat/renesas/rcar/include/registers/cpg_registers.h b/plat/renesas/rcar/include/registers/cpg_registers.h
new file mode 100644
index 0000000..bd6e557
--- /dev/null
+++ b/plat/renesas/rcar/include/registers/cpg_registers.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	CPG_REGISTER_H__
+#define	CPG_REGISTER_H__
+
+/* CPG base address */
+#define	CPG_BASE	(0xE6150000U)
+
+/* CPG system module stop control 2 */
+#define CPG_SMSTPCR2	(CPG_BASE + 0x0138U)
+/* CPG software reset 2 */
+#define CPG_SRCR2	(CPG_BASE + 0x00B0U)
+/* CPG module stop status 2 */
+#define CPG_MSTPSR2	(CPG_BASE + 0x0040U)
+/* CPG write protect */
+#define CPG_CPGWPR	(CPG_BASE + 0x0900U)
+/* CPG write protect control */
+#define CPG_CPGWPCR	(CPG_BASE + 0x0904U)
+/* CPG system module stop control 9 */
+#define CPG_SMSTPCR9    (CPG_BASE + 0x0994U)
+/* CPG module stop status 9 */
+#define CPG_MSTPSR9     (CPG_BASE + 0x09A4U)
+
+/* CPG (SECURITY) registers */
+
+/* Secure Module Stop Control Register 0 */
+#define	SCMSTPCR0	(CPG_BASE + 0x0B20U)
+/* Secure Module Stop Control Register 1 */
+#define	SCMSTPCR1	(CPG_BASE + 0x0B24U)
+/* Secure Module Stop Control Register 2 */
+#define	SCMSTPCR2	(CPG_BASE + 0x0B28U)
+/* Secure Module Stop Control Register 3 */
+#define	SCMSTPCR3	(CPG_BASE + 0x0B2CU)
+/* Secure Module Stop Control Register 4 */
+#define	SCMSTPCR4	(CPG_BASE + 0x0B30U)
+/* Secure Module Stop Control Register 5 */
+#define	SCMSTPCR5	(CPG_BASE + 0x0B34U)
+/* Secure Module Stop Control Register 6 */
+#define	SCMSTPCR6	(CPG_BASE + 0x0B38U)
+/* Secure Module Stop Control Register 7 */
+#define	SCMSTPCR7	(CPG_BASE + 0x0B3CU)
+/* Secure Module Stop Control Register 8 */
+#define	SCMSTPCR8	(CPG_BASE + 0x0B40U)
+/* Secure Module Stop Control Register 9 */
+#define	SCMSTPCR9	(CPG_BASE + 0x0B44U)
+/* Secure Module Stop Control Register 10 */
+#define	SCMSTPCR10	(CPG_BASE + 0x0B48U)
+/* Secure Module Stop Control Register 11 */
+#define	SCMSTPCR11	(CPG_BASE + 0x0B4CU)
+
+/* CPG (SECURITY) registers */
+
+/* Secure Software Reset Access Enable Control Register 0 */
+#define	SCSRSTECR0	(CPG_BASE + 0x0B80U)
+/* Secure Software Reset Access Enable Control Register 1 */
+#define	SCSRSTECR1	(CPG_BASE + 0x0B84U)
+/* Secure Software Reset Access Enable Control Register 2 */
+#define	SCSRSTECR2	(CPG_BASE + 0x0B88U)
+/* Secure Software Reset Access Enable Control Register 3 */
+#define	SCSRSTECR3	(CPG_BASE + 0x0B8CU)
+/* Secure Software Reset Access Enable Control Register 4 */
+#define	SCSRSTECR4	(CPG_BASE + 0x0B90U)
+/* Secure Software Reset Access Enable Control Register 5 */
+#define	SCSRSTECR5	(CPG_BASE + 0x0B94U)
+/* Secure Software Reset Access Enable Control Register 6 */
+#define	SCSRSTECR6	(CPG_BASE + 0x0B98U)
+/* Secure Software Reset Access Enable Control Register 7 */
+#define	SCSRSTECR7	(CPG_BASE + 0x0B9CU)
+/* Secure Software Reset Access Enable Control Register 8 */
+#define	SCSRSTECR8	(CPG_BASE + 0x0BA0U)
+/* Secure Software Reset Access Enable Control Register 9 */
+#define	SCSRSTECR9	(CPG_BASE + 0x0BA4U)
+/* Secure Software Reset Access Enable Control Register 10 */
+#define	SCSRSTECR10	(CPG_BASE + 0x0BA8U)
+/* Secure Software Reset Access Enable Control Register 11 */
+#define	SCSRSTECR11	(CPG_BASE + 0x0BACU)
+
+/* CPG (REALTIME) registers */
+
+/* Realtime Module Stop Control Register 0 */
+#define	RMSTPCR0	(CPG_BASE + 0x0110U)
+/* Realtime Module Stop Control Register 1 */
+#define	RMSTPCR1	(CPG_BASE + 0x0114U)
+/* Realtime Module Stop Control Register 2 */
+#define	RMSTPCR2	(CPG_BASE + 0x0118U)
+/* Realtime Module Stop Control Register 3 */
+#define	RMSTPCR3	(CPG_BASE + 0x011CU)
+/* Realtime Module Stop Control Register 4 */
+#define	RMSTPCR4	(CPG_BASE + 0x0120U)
+/* Realtime Module Stop Control Register 5 */
+#define	RMSTPCR5	(CPG_BASE + 0x0124U)
+/* Realtime Module Stop Control Register 6 */
+#define	RMSTPCR6	(CPG_BASE + 0x0128U)
+/* Realtime Module Stop Control Register 7 */
+#define	RMSTPCR7	(CPG_BASE + 0x012CU)
+/* Realtime Module Stop Control Register 8 */
+#define	RMSTPCR8	(CPG_BASE + 0x0980U)
+/* Realtime Module Stop Control Register 9 */
+#define	RMSTPCR9	(CPG_BASE + 0x0984U)
+/* Realtime Module Stop Control Register 10 */
+#define	RMSTPCR10	(CPG_BASE + 0x0988U)
+/* Realtime Module Stop Control Register 11 */
+#define	RMSTPCR11	(CPG_BASE + 0x098CU)
+
+/* CPG (SYSTEM) registers */
+
+/* System Module Stop Control Register 0 */
+#define	SMSTPCR0	(CPG_BASE + 0x0130U)
+/* System Module Stop Control Register 1 */
+#define	SMSTPCR1	(CPG_BASE + 0x0134U)
+/* System Module Stop Control Register 2 */
+#define	SMSTPCR2	(CPG_BASE + 0x0138U)
+/* System Module Stop Control Register 3 */
+#define	SMSTPCR3	(CPG_BASE + 0x013CU)
+/* System Module Stop Control Register 4 */
+#define	SMSTPCR4	(CPG_BASE + 0x0140U)
+/* System Module Stop Control Register 5 */
+#define	SMSTPCR5	(CPG_BASE + 0x0144U)
+/* System Module Stop Control Register 6 */
+#define	SMSTPCR6	(CPG_BASE + 0x0148U)
+/* System Module Stop Control Register 7 */
+#define	SMSTPCR7	(CPG_BASE + 0x014CU)
+/* System Module Stop Control Register 8 */
+#define	SMSTPCR8	(CPG_BASE + 0x0990U)
+/* System Module Stop Control Register 9 */
+#define	SMSTPCR9	(CPG_BASE + 0x0994U)
+/* System Module Stop Control Register 10 */
+#define	SMSTPCR10	(CPG_BASE + 0x0998U)
+/* System Module Stop Control Register 11 */
+#define	SMSTPCR11	(CPG_BASE + 0x099CU)
+
+#endif
diff --git a/plat/renesas/rcar/include/registers/lifec_registers.h b/plat/renesas/rcar/include/registers/lifec_registers.h
new file mode 100644
index 0000000..b331be3
--- /dev/null
+++ b/plat/renesas/rcar/include/registers/lifec_registers.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef	LIFEC_REGISTER_H__
+#define	LIFEC_REGISTER_H__
+
+#define	LIFEC_SEC_BASE	(0xE6110000U)
+
+#define	SEC_SRC		(LIFEC_SEC_BASE + 0x0008U)
+#define	SEC_SEL0	(LIFEC_SEC_BASE + 0x0030U)
+#define	SEC_SEL1	(LIFEC_SEC_BASE + 0x0034U)
+#define	SEC_SEL2	(LIFEC_SEC_BASE + 0x0038U)
+#define	SEC_SEL3	(LIFEC_SEC_BASE + 0x003CU)
+#define	SEC_SEL4	(LIFEC_SEC_BASE + 0x0058U)
+#define	SEC_SEL5	(LIFEC_SEC_BASE + 0x005CU)
+#define SEC_SEL6	(LIFEC_SEC_BASE + 0x0060U)
+#define	SEC_SEL7	(LIFEC_SEC_BASE + 0x0064U)
+#define	SEC_SEL8	(LIFEC_SEC_BASE + 0x0068U)
+#define	SEC_SEL9	(LIFEC_SEC_BASE + 0x006CU)
+#define	SEC_SEL10	(LIFEC_SEC_BASE + 0x0070U)
+#define	SEC_SEL11	(LIFEC_SEC_BASE + 0x0074U)
+#define	SEC_SEL12	(LIFEC_SEC_BASE + 0x0078U)
+#define	SEC_SEL13	(LIFEC_SEC_BASE + 0x007CU)
+#define	SEC_SEL14	(LIFEC_SEC_BASE + 0x0080U)
+#define	SEC_SEL15	(LIFEC_SEC_BASE + 0x0084U)
+#define	SEC_GRP0CR0	(LIFEC_SEC_BASE + 0x0138U)
+#define	SEC_GRP1CR0	(LIFEC_SEC_BASE + 0x013CU)
+#define	SEC_GRP0CR1	(LIFEC_SEC_BASE + 0x0140U)
+#define	SEC_GRP1CR1	(LIFEC_SEC_BASE + 0x0144U)
+#define	SEC_GRP0CR2	(LIFEC_SEC_BASE + 0x0148U)
+#define	SEC_GRP1CR2	(LIFEC_SEC_BASE + 0x014CU)
+#define	SEC_GRP0CR3	(LIFEC_SEC_BASE + 0x0150U)
+#define	SEC_GRP1CR3	(LIFEC_SEC_BASE + 0x0154U)
+#define	SEC_GRP0COND0	(LIFEC_SEC_BASE + 0x0158U)
+#define	SEC_GRP1COND0	(LIFEC_SEC_BASE + 0x015CU)
+#define	SEC_GRP0COND1	(LIFEC_SEC_BASE + 0x0160U)
+#define	SEC_GRP1COND1	(LIFEC_SEC_BASE + 0x0164U)
+#define	SEC_GRP0COND2	(LIFEC_SEC_BASE + 0x0168U)
+#define	SEC_GRP1COND2	(LIFEC_SEC_BASE + 0x016CU)
+#define	SEC_GRP0COND3	(LIFEC_SEC_BASE + 0x0170U)
+#define	SEC_GRP1COND3	(LIFEC_SEC_BASE + 0x0174U)
+#define	SEC_GRP0COND4	(LIFEC_SEC_BASE + 0x0178U)
+#define	SEC_GRP1COND4	(LIFEC_SEC_BASE + 0x017CU)
+#define	SEC_GRP0COND5	(LIFEC_SEC_BASE + 0x0180U)
+#define	SEC_GRP1COND5	(LIFEC_SEC_BASE + 0x0184U)
+#define	SEC_GRP0COND6	(LIFEC_SEC_BASE + 0x0188U)
+#define	SEC_GRP1COND6	(LIFEC_SEC_BASE + 0x018CU)
+#define	SEC_GRP0COND7	(LIFEC_SEC_BASE + 0x0190U)
+#define	SEC_GRP1COND7	(LIFEC_SEC_BASE + 0x0194U)
+#define	SEC_GRP0COND8	(LIFEC_SEC_BASE + 0x0198U)
+#define	SEC_GRP1COND8	(LIFEC_SEC_BASE + 0x019CU)
+#define	SEC_GRP0COND9	(LIFEC_SEC_BASE + 0x01A0U)
+#define	SEC_GRP1COND9	(LIFEC_SEC_BASE + 0x01A4U)
+#define	SEC_GRP0COND10	(LIFEC_SEC_BASE + 0x01A8U)
+#define	SEC_GRP1COND10	(LIFEC_SEC_BASE + 0x01ACU)
+#define	SEC_GRP0COND11	(LIFEC_SEC_BASE + 0x01B0U)
+#define	SEC_GRP1COND11	(LIFEC_SEC_BASE + 0x01B4U)
+#define	SEC_GRP0COND12	(LIFEC_SEC_BASE + 0x01B8U)
+#define	SEC_GRP1COND12	(LIFEC_SEC_BASE + 0x01BCU)
+#define	SEC_GRP0COND13	(LIFEC_SEC_BASE + 0x01C0U)
+#define	SEC_GRP1COND13	(LIFEC_SEC_BASE + 0x01C4U)
+#define	SEC_GRP0COND14	(LIFEC_SEC_BASE + 0x01C8U)
+#define	SEC_GRP1COND14	(LIFEC_SEC_BASE + 0x01CCU)
+#define	SEC_GRP0COND15	(LIFEC_SEC_BASE + 0x01D0U)
+#define	SEC_GRP1COND15	(LIFEC_SEC_BASE + 0x01D4U)
+#define	SEC_READONLY0	(LIFEC_SEC_BASE + 0x01D8U)
+#define	SEC_READONLY1	(LIFEC_SEC_BASE + 0x01DCU)
+#define	SEC_READONLY2	(LIFEC_SEC_BASE + 0x01E0U)
+#define	SEC_READONLY3	(LIFEC_SEC_BASE + 0x01E4U)
+#define	SEC_READONLY4	(LIFEC_SEC_BASE + 0x01E8U)
+#define	SEC_READONLY5	(LIFEC_SEC_BASE + 0x01ECU)
+#define	SEC_READONLY6	(LIFEC_SEC_BASE + 0x01F0U)
+#define	SEC_READONLY7	(LIFEC_SEC_BASE + 0x01F4U)
+#define	SEC_READONLY8	(LIFEC_SEC_BASE + 0x01F8U)
+#define	SEC_READONLY9	(LIFEC_SEC_BASE + 0x01FCU)
+#define	SEC_READONLY10	(LIFEC_SEC_BASE + 0x0200U)
+#define	SEC_READONLY11	(LIFEC_SEC_BASE + 0x0204U)
+#define	SEC_READONLY12	(LIFEC_SEC_BASE + 0x0208U)
+#define	SEC_READONLY13	(LIFEC_SEC_BASE + 0x020CU)
+#define	SEC_READONLY14	(LIFEC_SEC_BASE + 0x0210U)
+#define	SEC_READONLY15	(LIFEC_SEC_BASE + 0x0214U)
+
+#define	LIFEC_SAFE_BASE	(0xE6120000U)
+#define	SAFE_GRP0CR0	(LIFEC_SAFE_BASE + 0x0138U)
+#define	SAFE_GRP1CR0	(LIFEC_SAFE_BASE + 0x013CU)
+#define	SAFE_GRP0CR1	(LIFEC_SAFE_BASE + 0x0140U)
+#define	SAFE_GRP1CR1	(LIFEC_SAFE_BASE + 0x0144U)
+#define	SAFE_GRP0CR2	(LIFEC_SAFE_BASE + 0x0148U)
+#define	SAFE_GRP1CR2	(LIFEC_SAFE_BASE + 0x014CU)
+#define	SAFE_GRP0CR3	(LIFEC_SAFE_BASE + 0x0150U)
+#define	SAFE_GRP1CR3	(LIFEC_SAFE_BASE + 0x0154U)
+#define	SAFE_GRP0COND0	(LIFEC_SAFE_BASE + 0x0158U)
+#define	SAFE_GRP1COND0	(LIFEC_SAFE_BASE + 0x015CU)
+#define	SAFE_GRP0COND1	(LIFEC_SAFE_BASE + 0x0160U)
+#define	SAFE_GRP1COND1	(LIFEC_SAFE_BASE + 0x0164U)
+#define	SAFE_GRP0COND2	(LIFEC_SAFE_BASE + 0x0168U)
+#define	SAFE_GRP1COND2	(LIFEC_SAFE_BASE + 0x016CU)
+#define	SAFE_GRP0COND3	(LIFEC_SAFE_BASE + 0x0170U)
+#define	SAFE_GRP1COND3	(LIFEC_SAFE_BASE + 0x0174U)
+#define	SAFE_GRP0COND4	(LIFEC_SAFE_BASE + 0x0178U)
+#define	SAFE_GRP1COND4	(LIFEC_SAFE_BASE + 0x017CU)
+#define	SAFE_GRP0COND5	(LIFEC_SAFE_BASE + 0x0180U)
+#define	SAFE_GRP1COND5	(LIFEC_SAFE_BASE + 0x0184U)
+#define	SAFE_GRP0COND6	(LIFEC_SAFE_BASE + 0x0188U)
+#define	SAFE_GRP1COND6	(LIFEC_SAFE_BASE + 0x018CU)
+#define	SAFE_GRP0COND7	(LIFEC_SAFE_BASE + 0x0190U)
+#define	SAFE_GRP1COND7	(LIFEC_SAFE_BASE + 0x0194U)
+#define	SAFE_GRP0COND8	(LIFEC_SAFE_BASE + 0x0198U)
+#define	SAFE_GRP1COND8	(LIFEC_SAFE_BASE + 0x019CU)
+#define	SAFE_GRP0COND9	(LIFEC_SAFE_BASE + 0x01A0U)
+#define	SAFE_GRP1COND9	(LIFEC_SAFE_BASE + 0x01A4U)
+#define	SAFE_GRP0COND10	(LIFEC_SAFE_BASE + 0x01A8U)
+#define	SAFE_GRP1COND10	(LIFEC_SAFE_BASE + 0x01ACU)
+#define	SAFE_GRP0COND11	(LIFEC_SAFE_BASE + 0x01B0U)
+#define	SAFE_GRP1COND11	(LIFEC_SAFE_BASE + 0x01B4U)
+#define	SAFE_GRP0COND12	(LIFEC_SAFE_BASE + 0x01B8U)
+#define	SAFE_GRP1COND12	(LIFEC_SAFE_BASE + 0x01BCU)
+#define	SAFE_GRP0COND13	(LIFEC_SAFE_BASE + 0x01C0U)
+#define	SAFE_GRP1COND13	(LIFEC_SAFE_BASE + 0x01C4U)
+#define	SAFE_GRP0COND14	(LIFEC_SAFE_BASE + 0x01C8U)
+#define	SAFE_GRP1COND14	(LIFEC_SAFE_BASE + 0x01CCU)
+#define	SAFE_GRP0COND15	(LIFEC_SAFE_BASE + 0x01D0U)
+#define	SAFE_GRP1COND15	(LIFEC_SAFE_BASE + 0x01D4U)
+#define	SAFE_READONLY0	(LIFEC_SAFE_BASE + 0x01D8U)
+#define	SAFE_READONLY1	(LIFEC_SAFE_BASE + 0x01DCU)
+#define	SAFE_READONLY2	(LIFEC_SAFE_BASE + 0x01E0U)
+#define	SAFE_READONLY3	(LIFEC_SAFE_BASE + 0x01E4U)
+#define	SAFE_READONLY4	(LIFEC_SAFE_BASE + 0x01E8U)
+#define	SAFE_READONLY5	(LIFEC_SAFE_BASE + 0x01ECU)
+#define	SAFE_READONLY6	(LIFEC_SAFE_BASE + 0x01F0U)
+#define	SAFE_READONLY7	(LIFEC_SAFE_BASE + 0x01F4U)
+#define	SAFE_READONLY8	(LIFEC_SAFE_BASE + 0x01F8U)
+#define	SAFE_READONLY9	(LIFEC_SAFE_BASE + 0x01FCU)
+#define	SAFE_READONLY10	(LIFEC_SAFE_BASE + 0x0200U)
+#define	SAFE_READONLY11	(LIFEC_SAFE_BASE + 0x0204U)
+#define	SAFE_READONLY12	(LIFEC_SAFE_BASE + 0x0208U)
+#define	SAFE_READONLY13	(LIFEC_SAFE_BASE + 0x020CU)
+#define	SAFE_READONLY14	(LIFEC_SAFE_BASE + 0x0210U)
+#define	SAFE_READONLY15	(LIFEC_SAFE_BASE + 0x0214U)
+
+#endif
diff --git a/plat/renesas/rcar/plat_image_load.c b/plat/renesas/rcar/plat_image_load.c
new file mode 100644
index 0000000..469ac29
--- /dev/null
+++ b/plat/renesas/rcar/plat_image_load.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <desc_image_load.h>
+#include <platform.h>
+
+extern void bl2_plat_flush_bl31_params(void);
+
+/*******************************************************************************
+ * This function flushes the data structures so that they are visible
+ * in memory for the next BL image.
+ ******************************************************************************/
+void plat_flush_next_bl_params(void)
+{
+#if IMAGE_BL2
+	bl2_plat_flush_bl31_params();
+#endif
+}
+
+/*******************************************************************************
+ * This function returns the list of loadable images.
+ ******************************************************************************/
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+	return get_bl_load_info_from_mem_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of executable images.
+ ******************************************************************************/
+bl_params_t *plat_get_next_bl_params(void)
+{
+	return get_next_bl_params_from_mem_params_desc();
+}
diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c
new file mode 100644
index 0000000..84cc47e
--- /dev/null
+++ b/plat/renesas/rcar/plat_pm.c
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <bakery_lock.h>
+#include <bl_common.h>
+#include <cci.h>
+#include <debug.h>
+#include <errno.h>
+#include <gicv2.h>
+#include <mmio.h>
+#include <platform.h>
+#include <platform_def.h>
+#include <psci.h>
+
+#include "iic_dvfs.h"
+#include "pwrc.h"
+#include "rcar_def.h"
+#include "rcar_private.h"
+
+#define	DVFS_SET_VID_0V		(0x00)
+#define	P_ALL_OFF		(0x80)
+#define	KEEPON_DDR1C		(0x08)
+#define	KEEPON_DDR0C		(0x04)
+#define	KEEPON_DDR1		(0x02)
+#define	KEEPON_DDR0		(0x01)
+
+#define SYSTEM_PWR_STATE(s)	((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
+#define CLUSTER_PWR_STATE(s)	((s)->pwr_domain_state[MPIDR_AFFLVL1])
+#define CORE_PWR_STATE(s)	((s)->pwr_domain_state[MPIDR_AFFLVL0])
+
+uint64_t rcar_stack_generic_timer[5] __attribute__ ((section("data")));
+
+extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
+extern void plat_rcar_gic_driver_init(void);
+extern void plat_rcar_gic_init(void);
+extern u_register_t rcar_boot_mpidr;
+
+#if (RCAR_GEN3_ULCB == 1)
+extern void rcar_cpld_reset_cpu(void);
+#endif
+
+static uintptr_t rcar_sec_entrypoint;
+
+static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
+{
+	mailbox_t *rcar_mboxes = (mailbox_t *) MBOX_BASE;
+	uint64_t linear_id = plat_core_pos_by_mpidr(mpidr);
+	unsigned long range;
+
+	rcar_mboxes[linear_id].value = address;
+	range = (unsigned long)&rcar_mboxes[linear_id];
+
+	flush_dcache_range(range, sizeof(range));
+}
+
+static void rcar_cpu_standby(plat_local_state_t cpu_state)
+{
+	uint32_t scr_el3 = read_scr_el3();
+
+	write_scr_el3(scr_el3 | SCR_IRQ_BIT);
+	dsb();
+	wfi();
+	write_scr_el3(scr_el3);
+}
+
+static int rcar_pwr_domain_on(u_register_t mpidr)
+{
+	rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
+	rcar_pwrc_cpuon(mpidr);
+
+	return PSCI_E_SUCCESS;
+}
+
+static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+	uint32_t cluster_type = rcar_pwrc_get_cluster();
+	unsigned long mpidr = read_mpidr_el1();
+
+	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
+		if (cluster_type == RCAR_CLUSTER_A53A57)
+			plat_cci_enable();
+
+	rcar_pwrc_disable_interrupt_wakeup(mpidr);
+	rcar_program_mailbox(mpidr, 0);
+
+	gicv2_cpuif_enable();
+	gicv2_pcpu_distif_init();
+}
+
+static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
+{
+	uint32_t cluster_type = rcar_pwrc_get_cluster();
+	unsigned long mpidr = read_mpidr_el1();
+
+	gicv2_cpuif_disable();
+	rcar_pwrc_cpuoff(mpidr);
+
+	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
+		if (cluster_type == RCAR_CLUSTER_A53A57)
+			plat_cci_disable();
+
+		rcar_pwrc_clusteroff(mpidr);
+	}
+}
+
+static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
+{
+	uint32_t cluster_type = rcar_pwrc_get_cluster();
+	unsigned long mpidr = read_mpidr_el1();
+
+	if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
+		return;
+
+	rcar_program_mailbox(mpidr, rcar_sec_entrypoint);
+	rcar_pwrc_enable_interrupt_wakeup(mpidr);
+	gicv2_cpuif_disable();
+	rcar_pwrc_cpuoff(mpidr);
+
+	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
+		if (cluster_type == RCAR_CLUSTER_A53A57)
+			plat_cci_disable();
+
+		rcar_pwrc_clusteroff(mpidr);
+	}
+
+#if RCAR_SYSTEM_SUSPEND
+	if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
+		rcar_pwrc_suspend_to_ram();
+#endif
+}
+
+static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
+					   *target_state)
+{
+	uint32_t cluster_type = rcar_pwrc_get_cluster();
+
+	if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
+		goto finish;
+
+	plat_rcar_gic_driver_init();
+	plat_rcar_gic_init();
+
+	if (cluster_type == RCAR_CLUSTER_A53A57)
+		plat_cci_init();
+
+	rcar_pwrc_restore_generic_timer(rcar_stack_generic_timer);
+
+	/* start generic timer */
+	write_cntfrq_el0(plat_get_syscnt_freq2());
+	mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
+	rcar_pwrc_setup();
+
+#if RCAR_SYSTEM_SUSPEND
+	rcar_pwrc_init_suspend_to_ram();
+#endif
+finish:
+	rcar_pwr_domain_on_finish(target_state);
+}
+
+static void __dead2 rcar_system_off(void)
+{
+#if PMIC_ROHM_BD9571
+#if PMIC_LEVEL_MODE
+	rcar_pwrc_code_copy_to_system_ram();
+	if (rcar_iic_dvfs_send(PMIC, DVFS_SET_VID, DVFS_SET_VID_0V))
+		ERROR("BL3-1:Failed the SYSTEM-OFF.\n");
+#else
+	rcar_pwrc_code_copy_to_system_ram();
+	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
+		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
+#endif
+#else
+	uint64_t cpu = read_mpidr_el1() & 0x0000ffff;
+	int32_t rtn_on;
+
+	rtn_on = cpu_on_check(cpu);
+
+	if (cpu == rcar_boot_mpidr)
+		panic();
+
+	if (rtn_on)
+		panic();
+
+	rcar_pwrc_cpuoff(cpu);
+	rcar_pwrc_clusteroff(cpu);
+
+#endif /* PMIC_ROHM_BD9571 */
+	wfi();
+	ERROR("RCAR System Off: operation not handled.\n");
+	panic();
+}
+
+static void __dead2 rcar_system_reset(void)
+{
+#if PMIC_ROHM_BD9571
+#if PMIC_LEVEL_MODE
+#if RCAR_SYSTEM_RESET_KEEPON_DDR
+	uint8_t mode;
+	int32_t error;
+
+	rcar_pwrc_code_copy_to_system_ram();
+	error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
+	if (error) {
+		ERROR("Failed send KEEP10 magic ret=%d \n", error);
+		goto done;
+	}
+
+	error = rcar_iic_dvfs_receive(PMIC, BKUP_MODE_CNT, &mode);
+	if (error) {
+		ERROR("Failed recieve BKUP_Mode_Cnt ret=%d \n", error);
+		goto done;
+	}
+
+	mode |= KEEPON_DDR1C | KEEPON_DDR0C | KEEPON_DDR1 | KEEPON_DDR0;
+	error = rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, mode);
+	if (error) {
+		ERROR("Failed send KEEPON_DDRx ret=%d \n", error);
+		goto done;
+	}
+
+	rcar_pwrc_set_suspend_to_ram();
+done:
+#else
+	rcar_pwrc_code_copy_to_system_ram();
+	if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
+		ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
+#endif
+#else
+#if (RCAR_GEN3_ULCB == 1)
+	rcar_cpld_reset_cpu();
+#endif
+#endif
+#else
+	rcar_pwrc_system_reset();
+#endif
+	wfi();
+
+	ERROR("RCAR System Reset: operation not handled.\n");
+	panic();
+}
+
+static int rcar_validate_power_state(unsigned int power_state,
+				    psci_power_state_t *req_state)
+{
+	unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
+	unsigned int pstate = psci_get_pstate_type(power_state);
+	uint32_t i;
+
+	if (pstate == PSTATE_TYPE_STANDBY) {
+		if (pwr_lvl != MPIDR_AFFLVL0)
+			return PSCI_E_INVALID_PARAMS;
+
+		req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
+	} else {
+		for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
+			req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
+	}
+
+	if (psci_get_pstate_id(power_state))
+		return PSCI_E_INVALID_PARAMS;
+
+	return PSCI_E_SUCCESS;
+}
+
+#if RCAR_SYSTEM_SUSPEND
+static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+	unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU;
+	int i;
+
+	if (mpidr != rcar_boot_mpidr)
+		goto deny;
+
+	for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
+		req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
+
+	return;
+deny:
+	/* deny system suspend entry */
+	req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN;
+	for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
+		req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
+}
+#endif
+
+static const plat_psci_ops_t rcar_plat_psci_ops = {
+	.cpu_standby			= rcar_cpu_standby,
+	.pwr_domain_on			= rcar_pwr_domain_on,
+	.pwr_domain_off			= rcar_pwr_domain_off,
+	.pwr_domain_suspend		= rcar_pwr_domain_suspend,
+	.pwr_domain_on_finish		= rcar_pwr_domain_on_finish,
+	.pwr_domain_suspend_finish	= rcar_pwr_domain_suspend_finish,
+	.system_off			= rcar_system_off,
+	.system_reset			= rcar_system_reset,
+	.validate_power_state		= rcar_validate_power_state,
+#if RCAR_SYSTEM_SUSPEND
+	.get_sys_suspend_power_state 	= rcar_get_sys_suspend_power_state,
+#endif
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops)
+{
+	*psci_ops = &rcar_plat_psci_ops;
+	rcar_sec_entrypoint = sec_entrypoint;
+
+#if RCAR_SYSTEM_SUSPEND
+	rcar_pwrc_init_suspend_to_ram();
+#endif
+	return 0;
+}
+
diff --git a/plat/renesas/rcar/plat_storage.c b/plat/renesas/rcar/plat_storage.c
new file mode 100644
index 0000000..3b5d620
--- /dev/null
+++ b/plat/renesas/rcar/plat_storage.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <io_driver.h>
+#include <io_storage.h>
+#include <io_semihosting.h>
+#include <platform_def.h>
+#include <string.h>
+#include "io_common.h"
+#include "io_rcar.h"
+#include "io_memdrv.h"
+#include "io_emmcdrv.h"
+#include "io_private.h"
+
+static uintptr_t emmcdrv_dev_handle;
+static uintptr_t memdrv_dev_handle;
+static uintptr_t rcar_dev_handle;
+
+static uintptr_t boot_io_drv_id;
+
+static const io_block_spec_t rcar_block_spec = {
+	.offset = FLASH0_BASE,
+	.length = FLASH0_SIZE
+};
+
+static const io_block_spec_t bl2_file_spec = {
+	.offset = BL2_IMAGE_ID,
+};
+
+static const io_block_spec_t bl31_file_spec = {
+	.offset = BL31_IMAGE_ID,
+};
+
+static const io_block_spec_t bl32_file_spec = {
+	.offset = BL32_IMAGE_ID,
+};
+
+static const io_block_spec_t bl33_file_spec = {
+	.offset = BL33_IMAGE_ID,
+};
+
+static const io_block_spec_t bl332_file_spec = {
+	.offset = BL332_IMAGE_ID,
+};
+
+static const io_block_spec_t bl333_file_spec = {
+	.offset = BL333_IMAGE_ID,
+};
+
+static const io_block_spec_t bl334_file_spec = {
+	.offset = BL334_IMAGE_ID,
+};
+
+static const io_block_spec_t bl335_file_spec = {
+	.offset = BL335_IMAGE_ID,
+};
+
+static const io_block_spec_t bl336_file_spec = {
+	.offset = BL336_IMAGE_ID,
+};
+
+static const io_block_spec_t bl337_file_spec = {
+	.offset = BL337_IMAGE_ID,
+};
+
+static const io_block_spec_t bl338_file_spec = {
+	.offset = BL338_IMAGE_ID,
+};
+
+#if TRUSTED_BOARD_BOOT
+static const io_block_spec_t trusted_key_cert_file_spec = {
+	.offset = TRUSTED_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl31_key_cert_file_spec = {
+	.offset = SOC_FW_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl32_key_cert_file_spec = {
+	.offset = TRUSTED_OS_FW_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl33_key_cert_file_spec = {
+	.offset = NON_TRUSTED_FW_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl332_key_cert_file_spec = {
+	.offset = BL332_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl333_key_cert_file_spec = {
+	.offset = BL333_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl334_key_cert_file_spec = {
+	.offset = BL334_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl335_key_cert_file_spec = {
+	.offset = BL335_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl336_key_cert_file_spec = {
+	.offset = BL336_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl337_key_cert_file_spec = {
+	.offset = BL337_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl338_key_cert_file_spec = {
+	.offset = BL338_KEY_CERT_ID,
+};
+
+static const io_block_spec_t bl31_cert_file_spec = {
+	.offset = SOC_FW_CONTENT_CERT_ID,
+};
+
+static const io_block_spec_t bl32_cert_file_spec = {
+	.offset = TRUSTED_OS_FW_CONTENT_CERT_ID,
+};
+
+static const io_block_spec_t bl33_cert_file_spec = {
+	.offset = NON_TRUSTED_FW_CONTENT_CERT_ID,
+};
+
+static const io_block_spec_t bl332_cert_file_spec = {
+	.offset = BL332_CERT_ID,
+};
+
+static const io_block_spec_t bl333_cert_file_spec = {
+	.offset = BL333_CERT_ID,
+};
+
+static const io_block_spec_t bl334_cert_file_spec = {
+	.offset = BL334_CERT_ID,
+};
+
+static const io_block_spec_t bl335_cert_file_spec = {
+	.offset = BL335_CERT_ID,
+};
+
+static const io_block_spec_t bl336_cert_file_spec = {
+	.offset = BL336_CERT_ID,
+};
+
+static const io_block_spec_t bl337_cert_file_spec = {
+	.offset = BL337_CERT_ID,
+};
+
+static const io_block_spec_t bl338_cert_file_spec = {
+	.offset = BL338_CERT_ID,
+};
+#endif
+
+static int32_t open_emmcdrv(const uintptr_t spec);
+static int32_t open_memmap(const uintptr_t spec);
+static int32_t open_rcar(const uintptr_t spec);
+
+struct plat_io_policy {
+	uintptr_t *dev_handle;
+	uintptr_t image_spec;
+	 int32_t(*check) (const uintptr_t spec);
+};
+
+static const struct plat_io_policy policies[] = {
+	[FIP_IMAGE_ID] = {
+			  &memdrv_dev_handle,
+			  (uintptr_t) &rcar_block_spec,
+			  &open_memmap},
+	[BL2_IMAGE_ID] = {
+			  &rcar_dev_handle,
+			  (uintptr_t) &bl2_file_spec,
+			  &open_rcar},
+	[BL31_IMAGE_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl31_file_spec,
+			   &open_rcar},
+	[BL32_IMAGE_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl32_file_spec,
+			   &open_rcar},
+	[BL33_IMAGE_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl33_file_spec,
+			   &open_rcar},
+	[BL332_IMAGE_ID] = {
+			    &rcar_dev_handle,
+			    (uintptr_t) &bl332_file_spec,
+			    &open_rcar},
+	[BL333_IMAGE_ID] = {
+			    &rcar_dev_handle,
+			    (uintptr_t) &bl333_file_spec,
+			    &open_rcar},
+	[BL334_IMAGE_ID] = {
+			    &rcar_dev_handle,
+			    (uintptr_t) &bl334_file_spec,
+			    &open_rcar},
+	[BL335_IMAGE_ID] = {
+			    &rcar_dev_handle,
+			    (uintptr_t) &bl335_file_spec,
+			    &open_rcar},
+	[BL336_IMAGE_ID] = {
+			    &rcar_dev_handle,
+			    (uintptr_t) &bl336_file_spec,
+			    &open_rcar},
+	[BL337_IMAGE_ID] = {
+			    &rcar_dev_handle,
+			    (uintptr_t) &bl337_file_spec,
+			    &open_rcar},
+	[BL338_IMAGE_ID] = {
+			    &rcar_dev_handle,
+			    (uintptr_t) &bl338_file_spec,
+			    &open_rcar},
+#if TRUSTED_BOARD_BOOT
+	[TRUSTED_KEY_CERT_ID] = {
+				 &rcar_dev_handle,
+				 (uintptr_t) &trusted_key_cert_file_spec,
+				 &open_rcar},
+	[SOC_FW_KEY_CERT_ID] = {
+				&rcar_dev_handle,
+				(uintptr_t) &bl31_key_cert_file_spec,
+				&open_rcar},
+	[TRUSTED_OS_FW_KEY_CERT_ID] = {
+				       &rcar_dev_handle,
+				       (uintptr_t) &bl32_key_cert_file_spec,
+				       &open_rcar},
+	[NON_TRUSTED_FW_KEY_CERT_ID] = {
+					&rcar_dev_handle,
+					(uintptr_t) &bl33_key_cert_file_spec,
+					&open_rcar},
+	[BL332_KEY_CERT_ID] = {
+			       &rcar_dev_handle,
+			       (uintptr_t) &bl332_key_cert_file_spec,
+			       &open_rcar},
+	[BL333_KEY_CERT_ID] = {
+			       &rcar_dev_handle,
+			       (uintptr_t) &bl333_key_cert_file_spec,
+			       &open_rcar},
+	[BL334_KEY_CERT_ID] = {
+			       &rcar_dev_handle,
+			       (uintptr_t) &bl334_key_cert_file_spec,
+			       &open_rcar},
+	[BL335_KEY_CERT_ID] = {
+			       &rcar_dev_handle,
+			       (uintptr_t) &bl335_key_cert_file_spec,
+			       &open_rcar},
+	[BL336_KEY_CERT_ID] = {
+			       &rcar_dev_handle,
+			       (uintptr_t) &bl336_key_cert_file_spec,
+			       &open_rcar},
+	[BL337_KEY_CERT_ID] = {
+			       &rcar_dev_handle,
+			       (uintptr_t) &bl337_key_cert_file_spec,
+			       &open_rcar},
+	[BL338_KEY_CERT_ID] = {
+			       &rcar_dev_handle,
+			       (uintptr_t) &bl338_key_cert_file_spec,
+			       &open_rcar},
+	[SOC_FW_CONTENT_CERT_ID] = {
+				    &rcar_dev_handle,
+				    (uintptr_t) &bl31_cert_file_spec,
+				    &open_rcar},
+	[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
+					   &rcar_dev_handle,
+					   (uintptr_t) &bl32_cert_file_spec,
+					   &open_rcar},
+	[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
+					    &rcar_dev_handle,
+					    (uintptr_t) &bl33_cert_file_spec,
+					    &open_rcar},
+	[BL332_CERT_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl332_cert_file_spec,
+			   &open_rcar},
+	[BL333_CERT_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl333_cert_file_spec,
+			   &open_rcar},
+	[BL334_CERT_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl334_cert_file_spec,
+			   &open_rcar},
+	[BL335_CERT_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl335_cert_file_spec,
+			   &open_rcar},
+	[BL336_CERT_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl336_cert_file_spec,
+			   &open_rcar},
+	[BL337_CERT_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl337_cert_file_spec,
+			   &open_rcar},
+	[BL338_CERT_ID] = {
+			   &rcar_dev_handle,
+			   (uintptr_t) &bl338_cert_file_spec,
+			   &open_rcar}, {
+#else
+				   {
+#endif
+					 0, 0, 0}
+};
+
+static io_drv_spec_t io_drv_spec_memdrv = {
+	FLASH0_BASE,
+	FLASH0_SIZE,
+	0,
+};
+
+static io_drv_spec_t io_drv_spec_emmcdrv = {
+	0,
+	0,
+	0,
+};
+
+static struct plat_io_policy drv_policies[]
+    __attribute__ ((section(".data"))) = {
+	/* FLASH_DEV_ID */
+	{
+	&memdrv_dev_handle,
+		    (uintptr_t) &io_drv_spec_memdrv, &open_memmap,},
+	    /* EMMC_DEV_ID */
+	{
+	&emmcdrv_dev_handle,
+		    (uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv,}
+};
+
+static int32_t open_rcar(const uintptr_t spec)
+{
+	return io_dev_init(rcar_dev_handle, boot_io_drv_id);
+}
+
+static int32_t open_memmap(const uintptr_t spec)
+{
+	uintptr_t handle;
+	int32_t result;
+
+	result = io_dev_init(memdrv_dev_handle, 0);
+	if (result != IO_SUCCESS)
+		return result;
+
+	result = io_open(memdrv_dev_handle, spec, &handle);
+	if (result == IO_SUCCESS)
+		io_close(handle);
+
+	return result;
+}
+
+static int32_t open_emmcdrv(const uintptr_t spec)
+{
+	return io_dev_init(emmcdrv_dev_handle, 0);
+}
+
+void rcar_io_setup(void)
+{
+	const io_dev_connector_t *memmap;
+	const io_dev_connector_t *rcar;
+
+	boot_io_drv_id = FLASH_DEV_ID;
+
+	rcar_register_io_dev(&rcar);
+	rcar_register_io_dev_memdrv(&memmap);
+	io_dev_open(rcar, 0, &rcar_dev_handle);
+	io_dev_open(memmap, 0, &memdrv_dev_handle);
+}
+
+void rcar_io_emmc_setup(void)
+{
+	const io_dev_connector_t *rcar;
+	const io_dev_connector_t *emmc;
+
+	boot_io_drv_id = EMMC_DEV_ID;
+
+	rcar_register_io_dev(&rcar);
+	rcar_register_io_dev_emmcdrv(&emmc);
+	io_dev_open(rcar, 0, &rcar_dev_handle);
+	io_dev_open(emmc, 0, &emmcdrv_dev_handle);
+}
+
+int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
+			  uintptr_t *image_spec)
+{
+	const struct plat_io_policy *policy;
+	int result;
+
+	policy = &policies[image_id];
+
+	result = policy->check(policy->image_spec);
+	if (result != IO_SUCCESS)
+		return result;
+
+	*image_spec = policy->image_spec;
+	*dev_handle = *(policy->dev_handle);
+
+	return IO_SUCCESS;
+}
+
+int32_t plat_get_drv_source(uint32_t io_drv_id, uintptr_t *dev_handle,
+			    uintptr_t *image_spec)
+{
+	const struct plat_io_policy *policy;
+	int32_t result;
+
+	policy = &drv_policies[io_drv_id];
+
+	result = policy->check(policy->image_spec);
+	if (result != IO_SUCCESS)
+		return result;
+
+	*image_spec = policy->image_spec;
+	*dev_handle = *(policy->dev_handle);
+
+	return IO_SUCCESS;
+}
diff --git a/plat/renesas/rcar/plat_topology.c b/plat/renesas/rcar/plat_topology.c
new file mode 100644
index 0000000..3582c2b
--- /dev/null
+++ b/plat/renesas/rcar/plat_topology.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <platform_def.h>
+#include <psci.h>
+
+static const unsigned char rcar_power_domain_tree_desc[] = {
+	1,
+	PLATFORM_CLUSTER_COUNT,
+	PLATFORM_CLUSTER0_CORE_COUNT,
+	PLATFORM_CLUSTER1_CORE_COUNT
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return rcar_power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+	unsigned int cluster_id, cpu_id;
+
+	mpidr &= MPIDR_AFFINITY_MASK;
+
+	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
+		return -1;
+
+	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+	if (cluster_id >= PLATFORM_CLUSTER_COUNT)
+		return -1;
+
+	if (cluster_id == 0 && cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT)
+		return -1;
+
+	if (cluster_id == 1 && cpu_id >= PLATFORM_CLUSTER1_CORE_COUNT)
+		return -1;
+
+	return (cpu_id + cluster_id * PLATFORM_CLUSTER0_CORE_COUNT);
+}
+
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
new file mode 100644
index 0000000..95b7902
--- /dev/null
+++ b/plat/renesas/rcar/platform.mk
@@ -0,0 +1,414 @@
+#
+# Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PROGRAMMABLE_RESET_ADDRESS	:= 0
+COLD_BOOT_SINGLE_CPU		:= 1
+ARM_CCI_PRODUCT_ID		:= 500
+TRUSTED_BOARD_BOOT		:= 1
+RESET_TO_BL31			:= 1
+GENERATE_COT			:= 1
+BL2_AT_EL3			:= 1
+
+$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
+
+ifeq (${SPD},none)
+  SPD_NONE:=1
+  $(eval $(call add_define,SPD_NONE))
+endif
+
+# LSI setting common define
+RCAR_H3:=0
+RCAR_M3:=1
+RCAR_M3N:=2
+RCAR_E3:=3
+RCAR_H3N:=4
+RCAR_AUTO:=99
+$(eval $(call add_define,RCAR_H3))
+$(eval $(call add_define,RCAR_M3))
+$(eval $(call add_define,RCAR_M3N))
+$(eval $(call add_define,RCAR_E3))
+$(eval $(call add_define,RCAR_H3N))
+$(eval $(call add_define,RCAR_AUTO))
+RCAR_CUT_10:=0
+RCAR_CUT_11:=1
+RCAR_CUT_20:=10
+RCAR_CUT_30:=20
+$(eval $(call add_define,RCAR_CUT_10))
+$(eval $(call add_define,RCAR_CUT_11))
+$(eval $(call add_define,RCAR_CUT_20))
+$(eval $(call add_define,RCAR_CUT_30))
+
+ifndef LSI
+  $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI")
+else
+  ifeq (${LSI},AUTO)
+    RCAR_LSI:=${RCAR_AUTO}
+  else ifeq (${LSI},H3)
+    RCAR_LSI:=${RCAR_H3}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else ifeq (${LSI_CUT},20)
+        RCAR_LSI_CUT:=10
+      else ifeq (${LSI_CUT},30)
+        RCAR_LSI_CUT:=20
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},H3N)
+    RCAR_LSI:=${RCAR_H3N}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},30)
+        RCAR_LSI_CUT:=20
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},M3)
+    RCAR_LSI:=${RCAR_M3}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},M3N)
+    RCAR_LSI:=${RCAR_M3N}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},E3)
+    RCAR_LSI:=${RCAR_E3}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else
+    $(error "Error: ${LSI} is not supported.")
+  endif
+  $(eval $(call add_define,RCAR_LSI))
+endif
+
+# Process RCAR_SECURE_BOOT flag
+ifndef RCAR_SECURE_BOOT
+RCAR_SECURE_BOOT := 1
+endif
+$(eval $(call add_define,RCAR_SECURE_BOOT))
+
+# Process RCAR_QOS_TYPE flag
+ifndef RCAR_QOS_TYPE
+RCAR_QOS_TYPE := 0
+endif
+$(eval $(call add_define,RCAR_QOS_TYPE))
+
+# Process RCAR_DRAM_SPLIT flag
+ifndef RCAR_DRAM_SPLIT
+RCAR_DRAM_SPLIT := 0
+endif
+$(eval $(call add_define,RCAR_DRAM_SPLIT))
+
+# Process RCAR_BL33_EXECUTION_EL flag
+ifndef RCAR_BL33_EXECUTION_EL
+RCAR_BL33_EXECUTION_EL := 0
+endif
+$(eval $(call add_define,RCAR_BL33_EXECUTION_EL))
+
+# Process RCAR_AVS_SETTING_ENABLE flag
+ifeq (${RCAR_AVS_SETTING_ENABLE},0)
+AVS_SETTING_ENABLE := 0
+else
+AVS_SETTING_ENABLE := 1
+endif
+$(eval $(call add_define,AVS_SETTING_ENABLE))
+
+# Process RCAR_LOSSY_ENABLE flag
+ifndef RCAR_LOSSY_ENABLE
+RCAR_LOSSY_ENABLE := 0
+endif
+$(eval $(call add_define,RCAR_LOSSY_ENABLE))
+
+# Process LIFEC_DBSC_PROTECT_ENABLE flag
+ifndef LIFEC_DBSC_PROTECT_ENABLE
+LIFEC_DBSC_PROTECT_ENABLE := 1
+endif
+$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE))
+
+# Process PMIC_ROHM_BD9571 flag
+ifndef PMIC_ROHM_BD9571
+PMIC_ROHM_BD9571 := 1
+endif
+$(eval $(call add_define,PMIC_ROHM_BD9571))
+
+# Process PMIC_LEVEL_MODE flag
+ifndef PMIC_LEVEL_MODE
+PMIC_LEVEL_MODE := 1
+endif
+$(eval $(call add_define,PMIC_LEVEL_MODE))
+
+# Process RCAR_GEN3_ULCB flag
+ifndef RCAR_GEN3_ULCB
+RCAR_GEN3_ULCB := 0
+endif
+ifeq (${RCAR_GEN3_ULCB},1)
+ BOARD_DEFAULT := 0x10
+ $(eval $(call add_define,BOARD_DEFAULT))
+endif
+$(eval $(call add_define,RCAR_GEN3_ULCB))
+
+# Process RCAR_REF_INT flag
+ifndef RCAR_REF_INT
+RCAR_REF_INT :=0
+endif
+$(eval $(call add_define,RCAR_REF_INT))
+
+# Process RCAR_REWT_TRAINING flag
+ifndef RCAR_REWT_TRAINING
+RCAR_REWT_TRAINING := 0
+endif
+$(eval $(call add_define,RCAR_REWT_TRAINING))
+
+# Process RCAR_SYSTEM_SUSPEND flag
+ifndef RCAR_SYSTEM_SUSPEND
+RCAR_SYSTEM_SUSPEND := 1
+endif
+$(eval $(call add_define,RCAR_SYSTEM_SUSPEND))
+
+# SYSTEM_SUSPEND requires power control of PMIC etc.
+# When executing SYSTEM_SUSPEND other than Salvator-X, Salvator-XS and Ebisu,
+# processing equivalent to that implemented in PMIC_ROHM_BD9571 is necessary.
+ifeq (${RCAR_SYSTEM_SUSPEND},1)
+  ifeq (${PMIC_ROHM_BD9571},0)
+    $(error "Error: When you want RCAR_SYSTEM_SUSPEND to be enable, please also set PMIC_ROHM_BD9571 to enable.")
+  endif
+endif
+
+# Process RCAR_DRAM_LPDDR4_MEMCONF flag
+ifndef RCAR_DRAM_LPDDR4_MEMCONF
+RCAR_DRAM_LPDDR4_MEMCONF :=1
+endif
+$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF))
+
+# Process RCAR_DRAM_DDR3L_MEMCONF flag
+ifndef RCAR_DRAM_DDR3L_MEMCONF
+RCAR_DRAM_DDR3L_MEMCONF :=1
+endif
+$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMCONF))
+
+# Process RCAR_DRAM_DDR3L_MEMDUAL flag
+ifndef RCAR_DRAM_DDR3L_MEMDUAL
+RCAR_DRAM_DDR3L_MEMDUAL :=1
+endif
+$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMDUAL))
+
+# Process RCAR_BL33_ARG0 flag
+ifdef RCAR_BL33_ARG0
+$(eval $(call add_define,RCAR_BL33_ARG0))
+endif
+
+#Process RCAR_BL2_DCACHE flag
+ifndef RCAR_BL2_DCACHE
+RCAR_BL2_DCACHE := 0
+endif
+$(eval $(call add_define,RCAR_BL2_DCACHE))
+
+# Process RCAR_DRAM_CHANNEL flag
+ifndef RCAR_DRAM_CHANNEL
+RCAR_DRAM_CHANNEL :=15
+endif
+$(eval $(call add_define,RCAR_DRAM_CHANNEL))
+
+#Process RCAR_SYSTEM_RESET_KEEPON_DDR flag
+ifndef RCAR_SYSTEM_RESET_KEEPON_DDR
+RCAR_SYSTEM_RESET_KEEPON_DDR := 0
+endif
+$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
+
+# RCAR_SYSTEM_RESET_KEEPON_DDR requires power control of PMIC etc.
+# When executing SYSTEM_SUSPEND other than Salvator-X, Salvator-XS and Ebisu,
+# processing equivalent to that implemented in PMIC_ROHM_BD9571 is necessary.
+# Also, it is necessary to enable RCAR_SYSTEM_SUSPEND.
+ifeq (${RCAR_SYSTEM_RESET_KEEPON_DDR},1)
+  ifeq (${PMIC_ROHM_BD9571},0)
+    $(error "Error: When you want RCAR_SYSTEM_RESET_KEEPON_DDR to be enable, please also set PMIC_ROHM_BD9571 to enable.")
+  endif
+  ifeq (${RCAR_SYSTEM_SUSPEND},0)
+    $(error "Error: When you want RCAR_SYSTEM_RESET_KEEPON_DDR to be enable, please also set RCAR_SYSTEM_SUSPEND to enable.")
+  endif
+endif
+
+# Enable workarounds for selected Cortex-A53 erratas.
+ERRATA_A53_835769  := 1
+ERRATA_A53_843419  := 1
+ERRATA_A53_855873  := 1
+
+# Enable workarounds for selected Cortex-A57 erratas.
+ERRATA_A57_859972  := 1
+ERRATA_A57_813419  := 1
+
+include drivers/staging/renesas/rcar/ddr/ddr.mk
+include drivers/staging/renesas/rcar/qos/qos.mk
+include drivers/staging/renesas/rcar/pfc/pfc.mk
+
+PLAT_INCLUDES	:=	-Iinclude/common/tbbr			\
+			-Idrivers/staging/renesas/rcar/ddr	\
+			-Idrivers/staging/renesas/rcar/qos	\
+			-Idrivers/renesas/rcar/iic_dvfs		\
+			-Idrivers/renesas/rcar/board		\
+			-Idrivers/renesas/rcar/avs		\
+			-Idrivers/renesas/rcar/delay		\
+			-Idrivers/renesas/rcar/rom		\
+			-Idrivers/renesas/rcar/scif		\
+			-Idrivers/renesas/rcar/emmc		\
+			-Idrivers/renesas/rcar/pwrc		\
+			-Idrivers/renesas/rcar/io		\
+			-Iplat/renesas/rcar/include/registers	\
+			-Iplat/renesas/rcar/include		\
+			-Iplat/renesas/rcar
+
+PLAT_BL_COMMON_SOURCES	:=	drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
+
+
+RCAR_GIC_SOURCES	:=	drivers/arm/gic/common/gic_common.c	\
+				drivers/arm/gic/v2/gicv2_main.c		\
+				drivers/arm/gic/v2/gicv2_helpers.c	\
+				plat/common/plat_gicv2.c
+
+BL2_SOURCES	+=	${RCAR_GIC_SOURCES}				\
+			lib/cpus/aarch64/cortex_a53.S			\
+			lib/cpus/aarch64/cortex_a57.S			\
+			common/desc_image_load.c			\
+			plat/renesas/rcar/aarch64/platform_common.c	\
+			plat/renesas/rcar/aarch64/plat_helpers.S	\
+			plat/renesas/rcar/bl2_interrupt_error.c		\
+			plat/renesas/rcar/bl2_secure_setting.c		\
+			plat/renesas/rcar/bl2_plat_setup.c		\
+			plat/renesas/rcar/plat_storage.c		\
+			plat/renesas/rcar/bl2_plat_mem_params_desc.c	\
+			plat/renesas/rcar/plat_image_load.c		\
+			plat/renesas/rcar/bl2_cpg_init.c		\
+			drivers/renesas/rcar/console/rcar_printf.c	\
+			drivers/renesas/rcar/scif/scif.S		\
+			drivers/renesas/rcar/common.c			\
+			drivers/renesas/rcar/io/io_emmcdrv.c		\
+			drivers/renesas/rcar/io/io_memdrv.c		\
+			drivers/renesas/rcar/io/io_rcar.c		\
+			drivers/renesas/rcar/auth/auth_mod.c		\
+			drivers/renesas/rcar/rpc/rpc_driver.c		\
+			drivers/renesas/rcar/dma/dma_driver.c		\
+			drivers/renesas/rcar/avs/avs_driver.c		\
+			drivers/renesas/rcar/delay/micro_delay.S	\
+			drivers/renesas/rcar/emmc/emmc_interrupt.c	\
+			drivers/renesas/rcar/emmc/emmc_utility.c	\
+			drivers/renesas/rcar/emmc/emmc_mount.c		\
+			drivers/renesas/rcar/emmc/emmc_init.c		\
+			drivers/renesas/rcar/emmc/emmc_read.c		\
+			drivers/renesas/rcar/emmc/emmc_cmd.c		\
+			drivers/renesas/rcar/watchdog/swdt.c		\
+			drivers/renesas/rcar/rom/rom_api.c		\
+			drivers/renesas/rcar/board/board.c		\
+			drivers/io/io_storage.c
+
+BL31_SOURCES	+=	${RCAR_GIC_SOURCES}				\
+			lib/cpus/aarch64/cortex_a53.S			\
+			lib/cpus/aarch64/cortex_a57.S			\
+			plat/common/plat_psci_common.c			\
+			plat/renesas/rcar/plat_topology.c		\
+			plat/renesas/rcar/aarch64/plat_helpers.S	\
+			plat/renesas/rcar/aarch64/platform_common.c	\
+			plat/renesas/rcar/bl31_plat_setup.c		\
+			plat/renesas/rcar/plat_pm.c			\
+			drivers/renesas/rcar/console/rcar_console.S	\
+			drivers/renesas/rcar/console/rcar_printf.c	\
+			drivers/renesas/rcar/pwrc/call_sram.S		\
+			drivers/renesas/rcar/pwrc/pwrc.c		\
+			drivers/renesas/rcar/common.c			\
+			drivers/arm/cci/cci.c
+
+ifeq (${RCAR_GEN3_ULCB},1)
+BL31_SOURCES		+=	drivers/renesas/rcar/cpld/ulcb_cpld.c
+endif
+
+include lib/xlat_tables_v2/xlat_tables.mk
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+PLAT_BL_COMMON_SOURCES	+=	${XLAT_TABLES_LIB_SRCS}
+
+# build the layout images for the bootrom and the necessary srecords
+rcar: rcar_layout_tool rcar_srecord
+distclean realclean clean: clean_layout_tool clean_srecord
+
+# layout images
+LAYOUT_TOOLPATH ?= tools/renesas/rcar_layout_create
+
+clean_layout_tool:
+	@echo "clean layout tool"
+	${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean
+
+.PHONY: rcar_layout_tool
+rcar_layout_tool:
+	@echo "generating layout srecs"
+	${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH}
+
+# srecords
+SREC_PATH	= ${BUILD_PLAT}
+BL2_ELF_SRC	= ${SREC_PATH}/bl2/bl2.elf
+BL31_ELF_SRC	= ${SREC_PATH}/bl31/bl31.elf
+
+clean_srecord:
+	@echo "clean bl2 and bl31 srecs"
+	rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
+
+.PHONY: rcar_srecord
+rcar_srecord:
+	@echo "generating srec: ${SREC_PATH}/bl2.srec"
+	$(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC}  ${SREC_PATH}/bl2.srec
+	@echo "generating srec: ${SREC_PATH}/bl31.srec"
+	$(Q)$(OC) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec
+
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index e75ebac..787cc82 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -6,9 +6,12 @@
 
 #include <arch_helpers.h>
 #include <assert.h>
+#include <cpu_data.h>
 #include <debug.h>
 #include <k3_gicv3.h>
 #include <psci.h>
+/* Need to flush psci internal locks before shutdown or their values are lost */
+#include <../../lib/psci/psci_private.h>
 #include <platform.h>
 #include <stdbool.h>
 
@@ -99,6 +102,14 @@
 	k3_gic_cpuif_enable();
 }
 
+static void  __dead2 k3_pwr_domain_pwr_down_wfi(const psci_power_state_t
+						  *target_state)
+{
+	flush_cpu_data(psci_svc_cpu_data);
+	flush_dcache_range((uintptr_t) psci_locks, sizeof(psci_locks));
+	psci_power_down_wfi();
+}
+
 static void __dead2 k3_system_reset(void)
 {
 	/* Send the system reset request to system firmware */
@@ -128,6 +139,7 @@
 	.pwr_domain_on = k3_pwr_domain_on,
 	.pwr_domain_off = k3_pwr_domain_off,
 	.pwr_domain_on_finish = k3_pwr_domain_on_finish,
+	.pwr_domain_pwr_down_wfi = k3_pwr_domain_pwr_down_wfi,
 	.system_reset = k3_system_reset,
 	.validate_power_state = k3_validate_power_state,
 	.validate_ns_entrypoint = k3_validate_ns_entrypoint
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 3148178..d835436 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -12,7 +12,7 @@
 PROGRAMMABLE_RESET_ADDRESS:=	1
 
 # System coherency is managed in hardware
-WARMBOOT_ENABLE_DCACHE_EARLY:=	1
+HW_ASSISTED_COHERENCY	:=	1
 USE_COHERENT_MEM	:=	0
 
 # A53 erratum for SoC. (enable them all)
@@ -22,6 +22,10 @@
 ERRATA_A53_843419	:=	1
 ERRATA_A53_855873	:=	1
 
+# Leave the caches enabled on core powerdown path
+TI_AM65X_WORKAROUND	:=	1
+$(eval $(call add_define,TI_AM65X_WORKAROUND))
+
 MULTI_CONSOLE_API	:=	1
 TI_16550_MDR_QUIRK	:=	1
 $(eval $(call add_define,TI_16550_MDR_QUIRK))
diff --git a/tools/renesas/rcar_layout_create/makefile b/tools/renesas/rcar_layout_create/makefile
new file mode 100644
index 0000000..b3af401
--- /dev/null
+++ b/tools/renesas/rcar_layout_create/makefile
@@ -0,0 +1,112 @@
+#
+# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+###################################################
+# makefile
+###################################################
+
+#output file name
+FILE_NAME_SA0   = bootparam_sa0
+FILE_NAME_SA6   = cert_header_sa6
+
+OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf
+OUTPUT_FILE_SA6 = $(FILE_NAME_SA6).elf
+
+#object file name
+OBJ_FILE_SA0 =	sa0.o
+OBJ_FILE_SA6 =	sa6.o
+
+#linker script name
+MEMORY_DEF_SA0 = sa0.ld.S
+MEMORY_DEF_SA6 = sa6.ld.S
+
+###################################################
+# Convenience function for adding build definitions
+# $(eval $(call add_define,FOO)) will have:
+# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
+define add_define
+DEFINES			+=	-D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+# Process RCAR_SA0_SIZE flag
+ifndef RCAR_SA0_SIZE
+RCAR_SA0_SIZE := 1
+else
+ifeq (${RCAR_SA0_SIZE},0)
+RCAR_SA0_SIZE := 0
+else
+RCAR_SA0_SIZE := 1
+endif
+endif
+$(eval $(call add_define,RCAR_SA0_SIZE))
+
+# Process RCAR_SA6_TYPE flag
+ifndef RCAR_SA6_TYPE
+RCAR_SA6_TYPE := 0
+else
+ifeq (${RCAR_SA6_TYPE},0)
+RCAR_SA6_TYPE := 0
+else
+RCAR_SA6_TYPE := 1
+endif
+endif
+$(eval $(call add_define,RCAR_SA6_TYPE))
+
+###################################################
+
+#c compiler
+CC = $(CROSS_COMPILE)gcc
+CFLAGS += ${DEFINES}
+CFLAGS += -I../../include/lib/stdlib
+
+#Linker
+LD = $(CROSS_COMPILE)ld
+
+#objcopy
+objcopy = $(CROSS_COMPILE)objcopy
+
+#clean
+CL = rm -f
+
+###################################################
+.SUFFIXES : .s .c .o
+
+###################################################
+# command
+
+.PHONY: all
+all: $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6)
+###################################################
+# Linker
+###################################################
+$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0)
+	$(LD) $(OBJ_FILE_SA0)		 	\
+	-T $(MEMORY_DEF_SA0)			\
+	-o $(OUTPUT_FILE_SA0)			\
+	-Map $(FILE_NAME_SA0).map 		\
+
+	$(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec
+	$(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin
+
+$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6)
+	$(LD) $(OBJ_FILE_SA6)		 	\
+	-T $(MEMORY_DEF_SA6)			\
+	-o $(OUTPUT_FILE_SA6)			\
+	-Map $(FILE_NAME_SA6).map 		\
+
+	$(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec
+	$(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3  $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin
+
+###################################################
+# Compile
+###################################################
+
+%.o:../%.c
+	$(CC) -c -I $< -o $@
+
+.PHONY: clean
+clean:
+	$(CL)  *.bin *.map *.srec *.elf *.o
diff --git a/tools/renesas/rcar_layout_create/sa0.c b/tools/renesas/rcar_layout_create/sa0.c
new file mode 100644
index 0000000..b902d33
--- /dev/null
+++ b/tools/renesas/rcar_layout_create/sa0.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define RCAR_SA0_SIZE_SMALL	(0)	/* for E3 */
+#define RCAR_SA0_SIZE_NORMAL	(1)	/* for H3/M3/M3N */
+
+#define BL2_ADDRESS	(0xE6304000)	/* BL2 start address */
+
+#if (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL)
+#define BL2_SIZE	(80*1024/4)	/* BL2 size is 80KB(0x00005000) */
+#else  /* (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL) */
+#define BL2_SIZE	(170*1024/4)	/* BL2 size is 170KB(0x0000AA00) */
+#endif /* (RCAR_SA0_SIZE == RCAR_SA0_SIZE_SMALL) */
+
+/* SA0 */
+/* 0x00000000 */
+const unsigned int __attribute__ ((section (".sa0_bootrom"))) bootrom_paramA = 0x00000100;
+/* 0x00000080 (Map Type 3 for eMMC Boot)*/
+/* 0x000001D4 */
+const unsigned int __attribute__ ((section (".sa0_bl2dst_addr3"))) bl2dst_addr3 = BL2_ADDRESS;
+/* 0x000002E4 */
+const unsigned int __attribute__ ((section (".sa0_bl2dst_size3"))) bl2dst_size3 = BL2_SIZE;
+/* 0x00000C00 (Map Type 1 for HyperFlash/QSPI Flash Boot)*/
+/* 0x00000D54 */
+const unsigned int __attribute__ ((section (".sa0_bl2dst_addr1"))) bl2dst_addr1 = BL2_ADDRESS;
+/* 0x00000E64 */
+const unsigned int __attribute__ ((section (".sa0_bl2dst_size1"))) bl2dst_size1 = BL2_SIZE;
diff --git a/tools/renesas/rcar_layout_create/sa0.ld.S b/tools/renesas/rcar_layout_create/sa0.ld.S
new file mode 100644
index 0000000..98fee23
--- /dev/null
+++ b/tools/renesas/rcar_layout_create/sa0.ld.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+SECTIONS
+{
+	. = 0x00000000;
+	.rodata : {
+		KEEP(*(.sa0_bootrom))
+		/* Map Type 3 for eMMC Boot */
+                /* A-side IPL content cert "Start Address" */
+		. = 0x000001D4;		/* H'00000080 + H'00000154 */
+		KEEP(*(.sa0_bl2dst_addr3))
+                /* A-side IPL content cert "Size" */
+		. = 0x000002E4;		/* H'00000080 + H'00000264 */
+		KEEP(*(.sa0_bl2dst_size3))
+		/* Map Type 1 for HyperFlash/QSPI Flash Boot */
+		/* A-side IPL content cert "Start Address" */
+		. = 0x00000D54;		/* H'00000C00 + H'00000154 */
+		KEEP(*(.sa0_bl2dst_addr1))
+		/* A-side IPL content cert "Size" */
+		. = 0x00000E64;		/* H'00000C00 + H'00000264 */
+		KEEP(*(.sa0_bl2dst_size1))
+	}
+
+}
diff --git a/tools/renesas/rcar_layout_create/sa6.c b/tools/renesas/rcar_layout_create/sa6.c
new file mode 100644
index 0000000..fa828b9
--- /dev/null
+++ b/tools/renesas/rcar_layout_create/sa6.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#define RCAR_SA6_TYPE_HYPERFLASH	(0)
+#define RCAR_SA6_TYPE_EMMC		(1)
+
+#if (RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH)
+
+/* Number of content cert for Non-secure Target Program(BL33x) */
+#define RCAR_IMAGE_NUM			(0x00000001U)
+/* Source address on flash for BL31 */
+#define RCAR_BL31SRC_ADDRESS		(0x001C0000U)
+/* Reserved */
+#define RCAR_BL31_PARTITION		(0x00000000U)
+/* Source address on flash for BL32 */
+#define RCAR_BL32SRC_ADDRESS		(0x00200000U)
+/* Reserved */
+#define RCAR_BL32_PARTITION		(0x00000000U)
+/* Source address on flash for BL33 */
+#define RCAR_BL33SRC_ADDRESS		(0x00640000U)
+/* Reserved */
+#define RCAR_BL33_PARTITION		(0x00000000U)
+#define RCAR_BL332SRC_ADDRESS		(0x00000000U)
+/* Reserved */
+#define RCAR_BL332_PARTITION		(0x00000000U)
+#define RCAR_BL333SRC_ADDRESS		(0x00000000U)
+/* Reserved */
+#define RCAR_BL333_PARTITION		(0x00000000U)
+#define RCAR_BL334SRC_ADDRESS		(0x00000000U)
+/* Reserved */
+#define RCAR_BL334_PARTITION		(0x00000000U)
+#define RCAR_BL335SRC_ADDRESS		(0x00000000U)
+/* Reserved */
+#define RCAR_BL335_PARTITION		(0x00000000U)
+#define RCAR_BL336SRC_ADDRESS		(0x00000000U)
+/* Reserved */
+#define RCAR_BL336_PARTITION		(0x00000000U)
+#define RCAR_BL337SRC_ADDRESS		(0x00000000U)
+/* Reserved */
+#define RCAR_BL337_PARTITION		(0x00000000U)
+#define RCAR_BL338SRC_ADDRESS		(0x00000000U)
+/* Reserved */
+#define RCAR_BL338_PARTITION		(0x00000000U)
+
+#else /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH */
+
+/* Number of content cert for Non-secure Target Program(BL33x) */
+#define RCAR_IMAGE_NUM			(0x00000001U)
+/* Source address on eMMC for BL31 */
+#define RCAR_BL31SRC_ADDRESS		(0x00040000U)
+/* Source partition on eMMC for BL31 */
+#define RCAR_BL31_PARTITION		(0x00000001U)
+/* Source address on eMMC for BL32 */
+#define RCAR_BL32SRC_ADDRESS		(0x00200000U)
+/* Source partition on eMMC for BL32 */
+#define RCAR_BL32_PARTITION		(0x00000001U)
+/* Source address on eMMC for BL33 */
+#define RCAR_BL33SRC_ADDRESS		(0x00000000U)
+/* Source partition on eMMC for BL33 */
+#define RCAR_BL33_PARTITION		(0x00000002U)
+/* Reserved */
+#define RCAR_BL332SRC_ADDRESS		(0x00000000U)
+#define RCAR_BL332_PARTITION		(0x00000000U)
+/* Reserved */
+#define RCAR_BL333SRC_ADDRESS		(0x00000000U)
+#define RCAR_BL333_PARTITION		(0x00000000U)
+/* Reserved */
+#define RCAR_BL334SRC_ADDRESS		(0x00000000U)
+#define RCAR_BL334_PARTITION		(0x00000000U)
+/* Reserved */
+#define RCAR_BL335SRC_ADDRESS		(0x00000000U)
+#define RCAR_BL335_PARTITION		(0x00000000U)
+/* Reserved */
+#define RCAR_BL336SRC_ADDRESS		(0x00000000U)
+#define RCAR_BL336_PARTITION		(0x00000000U)
+/* Reserved */
+#define RCAR_BL337SRC_ADDRESS		(0x00000000U)
+#define RCAR_BL337_PARTITION		(0x00000000U)
+/* Reserved */
+#define RCAR_BL338SRC_ADDRESS		(0x00000000U)
+#define RCAR_BL338_PARTITION		(0x00000000U)
+
+#endif /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH */
+
+/* Destination address for BL31 */
+#define RCAR_BL31DST_ADDRESS		(0x44000000U)
+#define RCAR_BL31DST_ADDRESSH		(0x00000000U)
+/* Destination size for BL31 */
+#define RCAR_BL31DST_SIZE		(0x00004000U)
+/* Destination address for BL32 */
+#define RCAR_BL32DST_ADDRESS		(0x44100000U)
+#define RCAR_BL32DST_ADDRESSH		(0x00000000U)
+/* Destination size for BL32 */
+#define RCAR_BL32DST_SIZE		(0x00040000U)
+/* Destination address for BL33 */
+#define RCAR_BL33DST_ADDRESS		(0x50000000U)
+#define RCAR_BL33DST_ADDRESSH		(0x00000000U)
+/* Destination size for BL33 */
+#define RCAR_BL33DST_SIZE		(0x00040000U)
+/* Reserved */
+#define RCAR_BL332DST_ADDRESS		(0x00000000U)
+#define RCAR_BL332DST_ADDRESSH		(0x00000000U)
+#define RCAR_BL332DST_SIZE		(0x00000000U)
+/* Reserved */
+#define RCAR_BL333DST_ADDRESS		(0x00000000U)
+#define RCAR_BL333DST_ADDRESSH		(0x00000000U)
+#define RCAR_BL333DST_SIZE		(0x00000000U)
+/* Reserved */
+#define RCAR_BL334DST_ADDRESS		(0x00000000U)
+#define RCAR_BL334DST_ADDRESSH		(0x00000000U)
+#define RCAR_BL334DST_SIZE		(0x00000000U)
+/* Reserved */
+#define RCAR_BL335DST_ADDRESS		(0x00000000U)
+#define RCAR_BL335DST_ADDRESSH		(0x00000000U)
+#define RCAR_BL335DST_SIZE		(0x00000000U)
+/* Reserved */
+#define RCAR_BL336DST_ADDRESS		(0x00000000U)
+#define RCAR_BL336DST_ADDRESSH		(0x00000000U)
+#define RCAR_BL336DST_SIZE		(0x00000000U)
+/* Reserved */
+#define RCAR_BL337DST_ADDRESS		(0x00000000U)
+#define RCAR_BL337DST_ADDRESSH		(0x00000000U)
+#define RCAR_BL337DST_SIZE		(0x00000000U)
+/* Reserved */
+#define RCAR_BL338DST_ADDRESS		(0x00000000U)
+#define RCAR_BL338DST_ADDRESSH		(0x00000000U)
+#define RCAR_BL338DST_SIZE		(0x00000000U)
+
+/* SA6 */
+const uint64_t __attribute__ ((section (".sa6_image_num")))	image_num	= RCAR_IMAGE_NUM;
+const uint64_t __attribute__ ((section (".sa6_bl31src_addr")))	bl31src_addr	= RCAR_BL31SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl31partition")))	bl31partition	= RCAR_BL31_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl32src_addr")))	bl32src_addr	= RCAR_BL32SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl32partition")))	bl32partition	= RCAR_BL32_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl33src_addr")))	bl33src_addr	= RCAR_BL33SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl33partition")))	bl33partition	= RCAR_BL33_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl332src_addr")))	bl332src_addr	= RCAR_BL332SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl332partition")))bl332partition	= RCAR_BL332_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl333src_addr")))	bl333src_addr	= RCAR_BL333SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl333partition")))bl333partition	= RCAR_BL333_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl334src_addr")))	bl334src_addr	= RCAR_BL334SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl334partition")))bl334partition	= RCAR_BL334_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl335src_addr")))	bl335src_addr	= RCAR_BL335SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl335partition")))bl335partition	= RCAR_BL335_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl336src_addr")))	bl336src_addr	= RCAR_BL336SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl336partition")))bl336partition	= RCAR_BL336_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl337src_addr")))	bl337src_addr	= RCAR_BL337SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl337partition")))bl337partition	= RCAR_BL337_PARTITION;
+const uint64_t __attribute__ ((section (".sa6_bl338src_addr")))	bl338src_addr	= RCAR_BL338SRC_ADDRESS;
+const uint64_t __attribute__ ((section (".sa6_bl338partition")))bl338partition	= RCAR_BL338_PARTITION;
+const uint32_t __attribute__ ((section (".sa6_bl31dst_addr")))	bl31dst_addr	= RCAR_BL31DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl31dst_addrh")))	bl31dst_addrh	= RCAR_BL31DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl31dst_size")))	bl31dst_size	= RCAR_BL31DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl32dst_addr")))	bl32dst_addr	= RCAR_BL32DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl32dst_addrh")))	bl32dst_addrh	= RCAR_BL32DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl32dst_size")))	bl32dst_size	= RCAR_BL32DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl33dst_addr")))	bl33dst_addr	= RCAR_BL33DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl33dst_addrh")))	bl33dst_addrh	= RCAR_BL33DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl33dst_size")))	bl33dst_size	= RCAR_BL33DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl332dst_addr")))	bl332dst_addr	= RCAR_BL332DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl332dst_addrh")))bl332dst_addrh	= RCAR_BL332DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl332dst_size"))) bl332dst_size	= RCAR_BL332DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl333dst_addr")))	bl333dst_addr	= RCAR_BL333DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl333dst_addrh")))bl333dst_addrh	= RCAR_BL333DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl333dst_size")))	bl333dst_size	= RCAR_BL333DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl334dst_addr")))	bl334dst_addr	= RCAR_BL334DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl334dst_addrh")))bl334dst_addrh	= RCAR_BL334DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl334dst_size")))	bl334dst_size	= RCAR_BL334DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl335dst_addr")))	bl335dst_addr	= RCAR_BL335DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl335dst_addrh")))bl335dst_addrh	= RCAR_BL335DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl335dst_size")))	bl335dst_size	= RCAR_BL335DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl336dst_addr")))	bl336dst_addr	= RCAR_BL336DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl336dst_addrh")))bl336dst_addrh	= RCAR_BL336DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl336dst_size")))	bl336dst_size	= RCAR_BL336DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl337dst_addr")))	bl337dst_addr	= RCAR_BL337DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl337dst_addrh")))bl337dst_addrh	= RCAR_BL337DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl337dst_size")))	bl337dst_size	= RCAR_BL337DST_SIZE;
+const uint32_t __attribute__ ((section (".sa6_bl338dst_addr")))	bl338dst_addr	= RCAR_BL338DST_ADDRESS;
+const uint32_t __attribute__ ((section (".sa6_bl338dst_addrh")))bl338dst_addrh	= RCAR_BL338DST_ADDRESSH;
+const uint32_t __attribute__ ((section (".sa6_bl338dst_size")))	bl338dst_size	= RCAR_BL338DST_SIZE;
diff --git a/tools/renesas/rcar_layout_create/sa6.ld.S b/tools/renesas/rcar_layout_create/sa6.ld.S
new file mode 100644
index 0000000..9ca0c1d
--- /dev/null
+++ b/tools/renesas/rcar_layout_create/sa6.ld.S
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+SECTIONS
+{
+	. = 0x00000000;
+	.rodata : {
+		KEEP(*(.sa6_image_num))
+		. = 0x00000008;
+		KEEP(*(.sa6_bl31src_addr))
+		. = 0x00000010;
+		KEEP(*(.sa6_bl31partition))
+		. = 0x00000018;
+		KEEP(*(.sa6_bl32src_addr))
+		. = 0x00000020;
+		KEEP(*(.sa6_bl32partition))
+		. = 0x00000028;
+		KEEP(*(.sa6_bl33src_addr))
+		. = 0x00000030;
+		KEEP(*(.sa6_bl33partition))
+		. = 0x00000038;
+		KEEP(*(.sa6_bl332src_addr))
+		. = 0x00000040;
+		KEEP(*(.sa6_bl332partition))
+		. = 0x00000048;
+		KEEP(*(.sa6_bl333src_addr))
+		. = 0x00000050;
+		KEEP(*(.sa6_bl333partition))
+		. = 0x00000058;
+		KEEP(*(.sa6_bl334src_addr))
+		. = 0x00000060;
+		KEEP(*(.sa6_bl334partition))
+		. = 0x00000068;
+		KEEP(*(.sa6_bl335src_addr))
+		. = 0x00000070;
+		KEEP(*(.sa6_bl335partition))
+		. = 0x00000078;
+		KEEP(*(.sa6_bl336src_addr))
+		. = 0x00000080;
+		KEEP(*(.sa6_bl336partition))
+		. = 0x00000088;
+		KEEP(*(.sa6_bl337src_addr))
+		. = 0x00000090;
+		KEEP(*(.sa6_bl337partition))
+		. = 0x00000098;
+		KEEP(*(.sa6_bl338src_addr))
+		. = 0x000000A0;
+		KEEP(*(.sa6_bl338partition))
+		. = 0x00000554;
+		KEEP(*(.sa6_bl31dst_addr))
+		. = 0x00000558;
+		KEEP(*(.sa6_bl31dst_addrh))
+		. = 0x00000664;
+		KEEP(*(.sa6_bl31dst_size))
+		. = 0x00000D54;
+		KEEP(*(.sa6_bl32dst_addr))
+		. = 0x00000D58;
+		KEEP(*(.sa6_bl32dst_addrh))
+		. = 0x00000E64;
+		KEEP(*(.sa6_bl32dst_size))
+		. = 0x00001554;
+		KEEP(*(.sa6_bl33dst_addr))
+		. = 0x00001558;
+		KEEP(*(.sa6_bl33dst_addrh))
+		. = 0x00001664;
+		KEEP(*(.sa6_bl33dst_size))
+		. = 0x00001D54;
+		KEEP(*(.sa6_bl332dst_addr))
+		. = 0x00001D58;
+		KEEP(*(.sa6_bl332dst_addrh))
+		. = 0x00001E64;
+		KEEP(*(.sa6_bl332dst_size))
+		. = 0x00002554;
+		KEEP(*(.sa6_bl333dst_addr))
+		. = 0x00002558;
+		KEEP(*(.sa6_bl333dst_addrh))
+		. = 0x00002664;
+		KEEP(*(.sa6_bl333dst_size))
+		. = 0x00002D54;
+		KEEP(*(.sa6_bl334dst_addr))
+		. = 0x00002D58;
+		KEEP(*(.sa6_bl334dst_addrh))
+		. = 0x00002E64;
+		KEEP(*(.sa6_bl334dst_size))
+		. = 0x00003554;
+		KEEP(*(.sa6_bl335dst_addr))
+		. = 0x00003558;
+		KEEP(*(.sa6_bl335dst_addrh))
+		. = 0x00003664;
+		KEEP(*(.sa6_bl335dst_size))
+		. = 0x00003D54;
+		KEEP(*(.sa6_bl336dst_addr))
+		. = 0x00003D58;
+		KEEP(*(.sa6_bl336dst_addrh))
+		. = 0x00003E64;
+		KEEP(*(.sa6_bl336dst_size))
+		. = 0x00004554;
+		KEEP(*(.sa6_bl337dst_addr))
+		. = 0x00004558;
+		KEEP(*(.sa6_bl337dst_addrh))
+		. = 0x00004664;
+		KEEP(*(.sa6_bl337dst_size))
+		. = 0x00004D54;
+		KEEP(*(.sa6_bl338dst_addr))
+		. = 0x00004D58;
+		KEEP(*(.sa6_bl338dst_addrh))
+		. = 0x00004E64;
+		KEEP(*(.sa6_bl338dst_size))
+	}
+
+}