chore: rename hunter_elp to cortex-x4
Rename hunter_elp to cortex-x4
Change-Id: I78c8c009d7bee14b4793dc1d950ed81273216831
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h b/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h
deleted file mode 100644
index f9bb0f3..0000000
--- a/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_HUNTER_ELP_ARM_H
-#define CORTEX_HUNTER_ELP_ARM_H
-
-#define CORTEX_HUNTER_ELP_ARM_MIDR U(0x410FD821)
-
-/* Cortex Hunter ELP loop count for CVE-2022-23960 mitigation */
-#define CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT U(132)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_HUNTER_ELP_ARM_H */
diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h
new file mode 100644
index 0000000..17d07c8
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_x4.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_X4_H
+#define CORTEX_X4_H
+
+#define CORTEX_X4_MIDR U(0x410FD821)
+
+/* Cortex X4 loop count for CVE-2022-23960 mitigation */
+#define CORTEX_X4_BHB_LOOP_COUNT U(132)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_X4_H */
diff --git a/lib/cpus/aarch64/cortex_hunter_elp_arm.S b/lib/cpus/aarch64/cortex_hunter_elp_arm.S
deleted file mode 100644
index 5f86d4e..0000000
--- a/lib/cpus/aarch64/cortex_hunter_elp_arm.S
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_hunter_elp_arm.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-#include "wa_cve_2022_23960_bhb_vector.S"
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Hunter ELP must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Hunter ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT, cortex_hunter_elp_arm
-#endif /* WORKAROUND_CVE_2022_23960 */
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_hunter_elp_arm_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex Hunter ELP generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_hunter_elp_arm
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret
-endfunc cortex_hunter_elp_arm_reset_func
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_hunter_elp_arm_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_hunter_elp_arm_core_pwr_dwn
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Hunter ELP. Must follow AAPCS.
- */
-func cortex_hunter_elp_arm_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_hunter_elp_arm, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_hunter_elp_arm_errata_report
-#endif
-
- /* ---------------------------------------------
- * This function provides Cortex Hunter ELP-specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_hunter_elp_arm_regs, "aS"
-cortex_hunter_elp_arm_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_hunter_elp_arm_cpu_reg_dump
- adr x6, cortex_hunter_elp_arm_regs
- mrs x8, CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1
- ret
-endfunc cortex_hunter_elp_arm_cpu_reg_dump
-
-declare_cpu_ops cortex_hunter_elp_arm, CORTEX_HUNTER_ELP_ARM_MIDR, \
- cortex_hunter_elp_arm_reset_func, \
- cortex_hunter_elp_arm_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
new file mode 100644
index 0000000..db87008
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_x4.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+#include "wa_cve_2022_23960_bhb_vector.S"
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+#if WORKAROUND_CVE_2022_23960
+ wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
+#endif /* WORKAROUND_CVE_2022_23960 */
+
+func check_errata_cve_2022_23960
+#if WORKAROUND_CVE_2022_23960
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
+#endif
+ ret
+endfunc check_errata_cve_2022_23960
+
+func cortex_x4_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+
+#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+ /*
+ * The Cortex X4 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ adr x0, wa_cve_vbar_cortex_x4
+ msr vbar_el3, x0
+#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+
+ isb
+ ret
+endfunc cortex_x4_reset_func
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_x4_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_X4_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_X4_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_x4_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex X4. Must follow AAPCS.
+ */
+func cortex_x4_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata WORKAROUND_CVE_2022_23960, cortex_x4, cve_2022_23960
+
+ ldp x8, x30, [sp], #16
+ ret
+endfunc cortex_x4_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Cortex X4-specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_x4_regs, "aS"
+cortex_x4_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_x4_cpu_reg_dump
+ adr x6, cortex_x4_regs
+ mrs x8, CORTEX_X4_CPUECTLR_EL1
+ ret
+endfunc cortex_x4_cpu_reg_dump
+
+declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
+ cortex_x4_reset_func, \
+ cortex_x4_core_pwr_dwn
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index f88eaa8..d6622c0 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -58,18 +58,18 @@
lib/cpus/aarch64/cortex_a73.S
else
# AArch64-only cores
- FPGA_CPU_LIBS +=lib/cpus/aarch64/cortex_a510.S \
- lib/cpus/aarch64/cortex_a710.S \
- lib/cpus/aarch64/cortex_a715.S \
- lib/cpus/aarch64/cortex_x3.S \
+ FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_a715.S \
+ lib/cpus/aarch64/cortex_x3.S \
+ lib/cpus/aarch64/cortex_x4.S \
lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_n2.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/cortex_hayes.S \
- lib/cpus/aarch64/cortex_hunter.S \
- lib/cpus/aarch64/cortex_hunter_elp_arm.S \
- lib/cpus/aarch64/cortex_chaberton.S \
+ lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/cortex_hayes.S \
+ lib/cpus/aarch64/cortex_hunter.S \
+ lib/cpus/aarch64/cortex_chaberton.S \
lib/cpus/aarch64/cortex_blackhawk.S
# AArch64/AArch32 cores
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index d383ead..1bde94e 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -80,7 +80,7 @@
ifeq (${TARGET_PLATFORM}, 2)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \
lib/cpus/aarch64/cortex_hunter.S \
- lib/cpus/aarch64/cortex_hunter_elp_arm.S
+ lib/cpus/aarch64/cortex_x4.S
endif
INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c