commit 0a01321ab34864ae3d6a8a3b3b5f7fee9b69622a
author Anthony Zhou <anzhou@nvidia.com> Mon May 08 20:17:08 2017 +0800
committer Varun Wadekar <vwadekar@nvidia.com> Wed Jan 16 10:11:52 2019 -0800
tree 0daa7b3f1869b93088bc8e3612a35a539bd81855
parent f9f0f5c9a0d1ac67d5d0e67a41987c6a55f71f8a

Tegra186: mce: fix trivial MISRA defects

This patch fixes MISRA defects for the MCE driver.

* Using logical NOT for bool type function
* Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace
  MPIDR_CLUSTER_MASK

Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

plat/nvidia/tegra/soc/t186/drivers/mce/ari.c

diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index 1429a61..3769599 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -326,9 +326,11 @@
 int32_t ari_online_core(uint32_t ari_base, uint32_t core)
 {
 	uint64_t cpu = read_mpidr() & (uint64_t)(MPIDR_CPU_MASK);
-	uint64_t cluster = (read_mpidr() & (uint64_t)(MPIDR_CLUSTER_MASK)) >>
+	uint64_t cluster = (read_mpidr() & ((uint64_t)(MPIDR_AFFLVL_MASK) <<
+			   (uint64_t)(MPIDR_AFFINITY_BITS))) >>
 			   (uint64_t)(MPIDR_AFFINITY_BITS);
-	uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
+	uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) &
+			(uint64_t)MIDR_IMPL_MASK;
 	int32_t ret;
 
 	/* construct the current CPU # */
@@ -497,8 +499,8 @@
 		uint64_t *data)
 {
 	int32_t ret, result;
-	uint32_t val;
-	uint8_t req_cmd, req_status;
+	uint32_t val, req_status;
+	uint8_t req_cmd;
 
 	req_cmd = (uint8_t)(req >> UNCORE_PERFMON_CMD_SHIFT);
 
@@ -523,7 +525,7 @@
 			result = ret;
 		} else {
 			/* read the command status value */
-			req_status = (uint8_t)ari_get_response_high(ari_base) &
+			req_status = ari_get_response_high(ari_base) &
 					 UNCORE_PERFMON_RESP_STATUS_MASK;
 
 			/*