diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index cc32ec4..3ac5333 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -46,6 +46,11 @@
 #define CACHE_CLEAN_INVAL_SET			(1UL << 1)
 #define CACHE_CLEAN_INVAL_TR_SET		(1UL << 2)
 
+/*******************************************************************************
+ * C-state statistics macros
+ ******************************************************************************/
+#define MCE_STAT_ID_SHIFT			16UL
+
 /* declarations for NVG handler functions */
 uint64_t nvg_get_version(void);
 int32_t nvg_enable_power_perf_mode(void);
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index c797a0c..c7f6591 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -187,9 +187,15 @@
 {
 	int32_t ret = 0;
 
-	/* sanity check stat id */
-	if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) {
-		ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data);
+	/* sanity check stat id and core id*/
+	if ((data >> MCE_STAT_ID_SHIFT) >
+		(uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) {
+		ERROR("%s: unknown stat id (%d)\n", __func__,
+			(uint32_t)(data >> MCE_STAT_ID_SHIFT));
+		ret = EINVAL;
+	} else if ((data & MCE_CORE_ID_MASK) > (uint64_t)PLATFORM_CORE_COUNT) {
+		ERROR("%s: unknown core id (%d)\n", __func__,
+			(uint32_t)(data & MCE_CORE_ID_MASK));
 		ret = EINVAL;
 	} else {
 		nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data);