feat(rdfremont): initialize GPT on GPC SMMU block
GPC SMMU does granule protection checks (GPC) for accesses originating
from the system control block and GIC on RD-Fremont platforms. The GPC
check on this is disabled by the boot firmware. Configure the GPC SMMU
to enable GPC.
The transactions on GPC SMMU should be allowed during boot stages so
don't perform smmuv3_security_init() for this SMMU instance.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I3400c57fe264582a45c6a26f9dae8c669e8a8047
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
index f8d1eaf..f6f06a9 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
@@ -240,6 +240,10 @@
#define NRD_CSS_SMMU_NCI_IO_BASE ULL(0x280000000)
#define NRD_CSS_SMMU_NCI_IO_SIZE UL(0x60000000)
+/* GPC SMMU */
+#define NRD_CSS_GPC_SMMUV3_BASE UL(0x300000000)
+#define NRD_CSS_GPC_SMMUV3_SIZE UL(0x8000000)
+
/* DRAM1 */
#define NRD_CSS_DRAM1_BASE UL(0x80000000)
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
index acbf9b3..1b92ec2 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -75,6 +75,12 @@
ARM_SHARED_RAM_SIZE, \
MT_MEMORY | MT_RW | EL3_PAS)
+#define NRD_CSS_GPC_SMMU_SMMUV3_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_CSS_GPC_SMMUV3_BASE, \
+ NRD_CSS_GPC_SMMUV3_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
#define NRD_CSS_BL1_RW_MMAP \
MAP_REGION_FLAT( \
BL1_RW_BASE, \
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
index fc40508..f9a62ae 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
@@ -205,6 +205,9 @@
* 0x280000000 |1.5GB |L1 GPT |ANY |SMMU & NCI IO |
* 0x2DFFFFFFF | | | | |
* ---------------------------------------------------------------------
+ * 0x300000000 |128MB |L1 GPT |ROOT |GPC SMMU |
+ * 0x308000000 | | | | |
+ * ---------------------------------------------------------------------
* 0x8080000000 |6GB |L1 GPT |ANY |DRAM 2 CHIP 0 |
* 0x81FFFFFFFF | | | | |
* ---------------------------------------------------------------------
@@ -548,6 +551,12 @@
NRD_CSS_SMMU_NCI_IO_SIZE, \
GPT_GPI_ANY)
+#define NRD_PAS_GPC_SMMUV3 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_GPC_SMMUV3_BASE, \
+ NRD_CSS_GPC_SMMUV3_SIZE, \
+ GPT_GPI_ROOT)
+
#define NRD_PAS_DRAM2_CHIP0 \
GPT_MAP_REGION_GRANULE( \
NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 0), \
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
index 4cd9420..7b98052 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_plat3.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
@@ -59,6 +59,7 @@
NRD_ROS_SYSTEM_PERIPH_MMAP,
NRD_CSS_GPT_L1_DRAM_MMAP,
NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
+ NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
{0}
};
#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
index c2dcb00..01bb76d 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
@@ -72,6 +72,7 @@
${RDFREMONT_BASE}/rdfremont_topology.c \
${RDFREMONT_BASE}/rdfremont_plat_attest_token.c \
${RDFREMONT_BASE}/rdfremont_realm_attest_key.c \
+ drivers/arm/smmu/smmu_v3.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
index a121061..29c2101 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
@@ -6,6 +6,8 @@
#include <common/debug.h>
#include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/smmu_v3.h>
+
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <nrd_plat.h>
@@ -78,6 +80,19 @@
void bl31_platform_setup(void)
{
+ /*
+ * Perform SMMUv3 GPT configuration for the GPC SMMU present in system
+ * control block on RD-Fremont platforms. This SMMUv3 initialization is
+ * not fatal.
+ *
+ * Don't perform smmuv3_security_init() for this instance of SMMUv3 as
+ * the global aborts need not be configured to allow the components in
+ * system control block send transations downstream to SMMUv3.
+ */
+ if (smmuv3_init(NRD_CSS_GPC_SMMUV3_BASE) != 0) {
+ WARN("Failed initializing System SMMU.\n");
+ }
+
#if (NRD_PLATFORM_VARIANT == 2)
int ret;
unsigned int i;