fix(versal2): explicitly check operators precedence
This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in parentheses to maintain
the precedence.
Change-Id: I33028cf220fa0768f8f266db294c42810f62b61c
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index d00e50d..077a52e 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -165,7 +165,7 @@
uint32_t i;
/* Validate 'handler' and 'id' parameters */
- if (handler == NULL || index >= MAX_INTR_EL3) {
+ if ((handler == NULL) || (index >= MAX_INTR_EL3)) {
return -EINVAL;
}
diff --git a/plat/amd/versal2/scmi.c b/plat/amd/versal2/scmi.c
index 3c93ebf..6375df3 100644
--- a/plat/amd/versal2/scmi.c
+++ b/plat/amd/versal2/scmi.c
@@ -647,7 +647,7 @@
for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) {
/* Keep i2c on 100MHz to calculate rates properly */
- if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0)
+ if ((i >= CLK_I2C0_0) && (i <= CLK_I2C7_0))
continue;
/* Keep UFS clocks to default values to get the expected rates */