Tegra: common: drivers: fix MISRA defects
Main fixes:
Add suffix U for constant [Rule 10.1]
Match the operands type [Rule 10.4]
Use UL replace U for that constant define that need do "~"
operation [Rule 12.4]
Voided non c-library functions whose return types are not used
[Rule 17.7]
Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
diff --git a/plat/nvidia/tegra/common/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
index 610f32f..bff95d7 100644
--- a/plat/nvidia/tegra/common/drivers/smmu/smmu.c
+++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
@@ -26,40 +26,48 @@
static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
{
+ uint32_t ret = 0U;
+
#if defined(TEGRA_SMMU0_BASE)
- if (smmu_id == TEGRA_SMMU0)
- return mmio_read_32(TEGRA_SMMU0_BASE + off);
+ if (smmu_id == TEGRA_SMMU0) {
+ ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off);
+ }
#endif
#if defined(TEGRA_SMMU1_BASE)
- if (smmu_id == TEGRA_SMMU1)
- return mmio_read_32(TEGRA_SMMU1_BASE + off);
+ if (smmu_id == TEGRA_SMMU1) {
+ ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off);
+ }
#endif
#if defined(TEGRA_SMMU2_BASE)
- if (smmu_id == TEGRA_SMMU2)
- return mmio_read_32(TEGRA_SMMU2_BASE + off);
+ if (smmu_id == TEGRA_SMMU2) {
+ ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off);
+ }
#endif
- return 0;
+ return ret;
}
static void tegra_smmu_write_32(uint32_t smmu_id,
uint32_t off, uint32_t val)
{
#if defined(TEGRA_SMMU0_BASE)
- if (smmu_id == TEGRA_SMMU0)
- mmio_write_32(TEGRA_SMMU0_BASE + off, val);
+ if (smmu_id == TEGRA_SMMU0) {
+ mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val);
+ }
#endif
#if defined(TEGRA_SMMU1_BASE)
- if (smmu_id == TEGRA_SMMU1)
- mmio_write_32(TEGRA_SMMU1_BASE + off, val);
+ if (smmu_id == TEGRA_SMMU1) {
+ mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val);
+ }
#endif
#if defined(TEGRA_SMMU2_BASE)
- if (smmu_id == TEGRA_SMMU2)
- mmio_write_32(TEGRA_SMMU2_BASE + off, val);
+ if (smmu_id == TEGRA_SMMU2) {
+ mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val);
+ }
#endif
}
@@ -70,16 +78,16 @@
{
uint32_t i, num_entries = 0;
smmu_regs_t *smmu_ctx_regs;
- plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+ const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t tzdram_base = params_from_bl2->tzdram_base;
uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
uint32_t reg_id1, pgshift, cb_size;
/* sanity check SMMU settings c*/
reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
- pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
- cb_size = (2 << pgshift) * \
- (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
+ pgshift = ((reg_id1 & ID1_PAGESIZE) != 0U) ? 16U : 12U;
+ cb_size = (2UL << pgshift) * \
+ (1UL << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1UL));
assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
@@ -98,8 +106,9 @@
}
/* panic if the sizes do not match */
- if (num_entries != smmu_ctx_regs[0].val)
+ if (num_entries != smmu_ctx_regs[0].val) {
panic();
+ }
/* save SMMU register values */
for (i = 1; i < num_entries; i++)
@@ -109,8 +118,8 @@
num_entries++;
/* Save SMMU config settings */
- memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
- (sizeof(smmu_regs_t) * num_entries));
+ (void)memcpy16((uint8_t *)smmu_ctx_addr, (uint8_t *)smmu_ctx_regs,
+ (sizeof(smmu_regs_t) * num_entries));
/* save the SMMU table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,