tree d99ce13a2891a11bb714e43349ff4319f85c9a21
parent 04b096f3692c050d724dafad6930d5f7ba5efb8b
author Soby Mathew <soby.mathew@arm.com> 1459769664 +0100
committer Soby Mathew <soby.mathew@arm.com> 1460043045 +0100

Enable SCR_EL3.SIF bit

This patch enables the SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and
BL31 common architectural setup code. When in secure state, this disables
instruction fetches from Non-secure memory.

NOTE: THIS COULD BREAK PLATFORMS THAT HAVE SECURE WORLD CODE EXECUTING FROM
NON-SECURE MEMORY, BUT THIS IS CONSIDERED UNLIKELY AND IS A SERIOUS SECURITY
RISK.

Fixes ARM-Software/tf-issues#372

Change-Id: I684e84b8d523c3b246e9a5fabfa085b6405df319