feat(mt8196): add SPM common driver support
This patch mainly initializes the SPM and provides common APIs for SPM
to enable the use of its various features.
Change-Id: I9facb6bf9962bb2d5fcacd945846bfaeb4c87a55
diff --git a/plat/mediatek/drivers/spm/common/dbg_ctrl.h b/plat/mediatek/drivers/spm/common/dbg_ctrl.h
new file mode 100644
index 0000000..aea2fb8
--- /dev/null
+++ b/plat/mediatek/drivers/spm/common/dbg_ctrl.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DBG_CTRL_H
+#define DBG_CTRL_H
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_TWAM BIT(18)
+#define WAKE_MISC_PCM_TIMER BIT(19)
+#define WAKE_MISC_CPU_WAKE BIT(20)
+
+struct dbg_ctrl {
+ uint32_t count;
+ uint32_t duration;
+ void *ext;
+};
+
+enum dbg_ctrl_enum {
+ DBG_CTRL_COUNT,
+ DBG_CTRL_DURATION,
+ DBG_CTRL_MAX,
+};
+
+#endif /* DBG_CTRL_H */
diff --git a/plat/mediatek/drivers/spm/common/mt_spm_common.h b/plat/mediatek/drivers/spm/common/mt_spm_common.h
new file mode 100644
index 0000000..b44361e
--- /dev/null
+++ b/plat/mediatek/drivers/spm/common/mt_spm_common.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights resrved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_COMMON_H
+#define MT_SPM_COMMON_H
+
+#include <lib/bakery_lock.h>
+#include <lib/spinlock.h>
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. So, there is no doubt to use the spin_lock here
+ */
+#if !HW_ASSISTED_COHERENCY
+#define MT_SPM_USING_BAKERY_LOCK
+#endif
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DECLARE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock() \
+ bakery_lock_get(&spm_lock)
+
+#define plat_spm_unlock() \
+ bakery_lock_release(&spm_lock)
+#else
+extern spinlock_t spm_lock;
+#define plat_spm_lock() \
+ spin_lock(&spm_lock)
+
+#define plat_spm_unlock() \
+ spin_unlock(&spm_lock)
+#endif
+
+#define MT_SPM_ERR_NO_FW_LOAD -1
+#define MT_SPM_ERR_KICKED -2
+#define MT_SPM_ERR_RUNNING -3
+#define MT_SPM_ERR_FW_NOT_FOUND -4
+#define MT_SPM_ERR_INVALID -5
+#define MT_SPM_ERR_OVERFLOW -6
+
+static inline void spm_lock_get(void)
+{
+ plat_spm_lock();
+}
+
+static inline void spm_lock_release(void)
+{
+ plat_spm_unlock();
+}
+
+#endif /* MT_SPM_COMMON_H */
diff --git a/plat/mediatek/drivers/spm/common/mt_spm_constraint.h b/plat/mediatek/drivers/spm/common/mt_spm_constraint.h
new file mode 100644
index 0000000..0dbbfb3
--- /dev/null
+++ b/plat/mediatek/drivers/spm/common/mt_spm_constraint.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <lpm_v2/mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF BIT(0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 BIT(1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 BIT(2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP BIT(3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN BIT(4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF BIT(5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND BIT(6) /* System suspend */
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM BIT(7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS BIT(8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE BIT(9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE BIT(10)
+#define MT_RM_CONSTRAINT_ALLOW_AP_PLAT_SUSPEND BIT(11) /* Kernel suspend */
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_OFF BIT(12)
+
+#define MT_SPM_RC_INVALID 0x0
+#define MT_SPM_RC_VALID_SW BIT(0)
+#define MT_SPM_RC_VALID_FW BIT(1)
+#define MT_SPM_RC_VALID_RESIDNECY BIT(2)
+#define MT_SPM_RC_VALID_COND_CHECK BIT(3)
+#define MT_SPM_RC_VALID_COND_LATCH BIT(4)
+#define MT_SPM_RC_VALID_UFS_H8 BIT(5)
+#define MT_SPM_RC_VALID_FLIGHTMODE BIT(6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM BIT(7)
+#define MT_SPM_RC_VALID_TRACE_EVENT BIT(8)
+#define MT_SPM_RC_VALID_TRACE_TIME BIT(9)
+#define MT_SPM_RC_VALID_NOTIFY BIT(10)
+
+#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_FW)
+
+#define IS_MT_RM_RC_READY(status) \
+ ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+struct constraint_status {
+ uint16_t id;
+ uint16_t is_valid;
+ uint64_t is_cond_block;
+ uint32_t enter_cnt;
+ uint64_t all_pll_dump;
+ unsigned long long residency;
+ struct mt_spm_cond_tables *cond_res;
+};
+
+enum constraint_status_update_type {
+ CONSTRAINT_UPDATE_VALID,
+ CONSTRAINT_UPDATE_COND_CHECK,
+ CONSTRAINT_RESIDNECY,
+};
+
+enum constraint_status_get_type {
+ CONSTRAINT_GET_VALID = 0xD0000000,
+ CONSTRAINT_GET_ENTER_CNT,
+ CONSTRAINT_GET_RESIDENCY,
+ CONSTRAINT_GET_COND_EN,
+ CONSTRAINT_COND_BLOCK,
+ CONSTRAINT_GET_COND_BLOCK_LATCH,
+ CONSTRAINT_GET_COND_BLOCK_DETAIL,
+ CONSTRAINT_GET_RESIDNECY,
+};
+
+struct rc_common_state {
+ unsigned int id;
+ unsigned int act;
+ unsigned int type;
+ void *value;
+};
+
+#define MT_SPM_RC_BBLPM_MODE (MT_SPM_RC_VALID_UFS_H8 | \
+ MT_SPM_RC_VALID_FLIGHTMODE | \
+ MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st) \
+ ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+#define IS_MT_SPM_RC_NOTIFY_ENABLE(st) \
+ ((st & (MT_SPM_RC_VALID_NOTIFY)))
+
+#define MT_SPM_RC_EXTERN_STATUS_SET(v, st) ({v |= (st & 0xffff); })
+#define MT_SPM_RC_EXTERN_STATUS_CLR(v, st) ({v &= ~(st & 0xffff); })
+
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/drivers/spm/common/mt_spm_smc.h b/plat/mediatek/drivers/spm/common/mt_spm_smc.h
new file mode 100644
index 0000000..62f090f
--- /dev/null
+++ b/plat/mediatek/drivers/spm/common/mt_spm_smc.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SMC_H
+#define MT_SPM_SMC_H
+
+/*
+ * SPM dispatcher's smc id definition
+ * Please adding custom smc id here for spm dispatcher
+ */
+#define MT_SPM_STATUS_SUSPEND_SLEEP BIT(27)
+
+enum mt_spm_smc_uid {
+ MT_SPM_SMC_UID_STATUS,
+ MT_SPM_SMC_UID_PCM_WDT,
+ MT_SPM_SMC_UID_PCM_TIMER,
+ MT_SPM_SMC_UID_FW_TYPE,
+ MT_SPM_SMC_UID_PHYPLL_MODE,
+ MT_SPM_SMC_UID_SET_PENDING_IRQ_INIT,
+ MT_SPM_SMC_UID_FW_INIT = 0x5731,
+};
+
+/*
+ * SPM dbg dispatcher's smc id definition
+ * Please adding custom smc id here for spm dbg dispatcher
+ */
+enum mt_spm_dbg_smc_uid {
+ MT_SPM_DBG_SMC_UID_IDLE_PWR_CTRL,
+ MT_SPM_DBG_SMC_UID_IDLE_CNT,
+ MT_SPM_DBG_SMC_UID_SUSPEND_PWR_CTRL,
+ MT_SPM_DBG_SMC_UID_SUSPEND_DBG_CTRL,
+ MT_SPM_DBG_SMC_UID_FS,
+ MT_SPM_DBG_SMC_UID_RC_SWITCH,
+ MT_SPM_DBG_SMC_UID_RC_CNT,
+ MT_SPM_DBG_SMC_UID_COND_CHECK,
+ MT_SPM_DBG_SMC_UID_COND_BLOCK,
+ MT_SPM_DBG_SMC_UID_BLOCK_LATCH,
+ MT_SPM_DBG_SMC_UID_BLOCK_DETAIL,
+ MT_SPM_DBG_SMC_UID_RES_NUM,
+ MT_SPM_DBG_SMC_UID_RES_REQ,
+ MT_SPM_DBG_SMC_UID_RES_USAGE,
+ MT_SPM_DBG_SMC_UID_RES_USER_NUM,
+ MT_SPM_DBG_SMC_UID_RES_USER_VALID,
+ MT_SPM_DBG_SMC_UID_RES_USER_NAME,
+ MT_SPM_DBG_SMC_UID_DOE_RESOURCE_CTRL,
+ MT_SPM_DBG_SMC_UID_DOE_RC,
+ MT_SPM_DBG_SMC_UID_RC_COND_CTRL,
+ MT_SPM_DBG_SMC_UID_RC_RES_CTRL,
+ MT_SPM_DBG_SMC_UID_RC_RES_INFO,
+ MT_SPM_DBG_SMC_UID_RC_BBLPM,
+ MT_SPM_DBG_SMC_UID_RC_TRACE,
+ MT_SPM_DBG_SMC_UID_RC_TRACE_TIME,
+ MT_SPM_DBG_SMC_UID_DUMP_PLL,
+ MT_SPM_DBG_SMC_HWCG_NUM,
+ MT_SPM_DBG_SMC_HWCG_STATUS,
+ MT_SPM_DBG_SMC_HWCG_SETTING,
+ MT_SPM_DBG_SMC_HWCG_DEF_SETTING,
+ MT_SPM_DBG_SMC_HWCG_RES_NAME,
+ MT_SPM_DBG_SMC_UID_RC_NOTIFY_CTRL,
+ MT_SPM_DBG_SMC_VCORE_LP_ENABLE,
+ MT_SPM_DBG_SMC_VCORE_LP_VOLT,
+ MT_SPM_DBG_SMC_VSRAM_LP_ENABLE,
+ MT_SPM_DBG_SMC_VSRAM_LP_VOLT,
+ MT_SPM_DBG_SMC_PERI_REQ_NUM,
+ MT_SPM_DBG_SMC_PERI_REQ_STATUS,
+ MT_SPM_DBG_SMC_PERI_REQ_SETTING,
+ MT_SPM_DBG_SMC_PERI_REQ_DEF_SETTING,
+ MT_SPM_DBG_SMC_PERI_REQ_RES_NAME,
+ MT_SPM_DBG_SMC_PERI_REQ_STATUS_RAW,
+ MT_SPM_DBG_SMC_IDLE_PWR_STAT,
+ MT_SPM_DBG_SMC_SUSPEND_PWR_STAT,
+ MT_SPM_DBG_SMC_LP_REQ_STAT,
+ MT_SPM_DBG_SMC_COMMON_SODI_CTRL,
+ MT_SPM_DBG_SMC_SPM_TIMESTAMP,
+ MT_SPM_DBG_SMC_SPM_TIMESTAMP_SIZE,
+ MT_SPM_DBG_SMC_UID_COMMON_SODI_PWR_CTRL,
+};
+
+enum wake_status_enum {
+ WAKE_STA_ASSERT_PC,
+ WAKE_STA_R12,
+ WAKE_STA_R12_EXT,
+ WAKE_STA_RAW_STA,
+ WAKE_STA_RAW_EXT_STA,
+ WAKE_STA_WAKE_MISC,
+ WAKE_STA_TIMER_OUT,
+ WAKE_STA_R13,
+ WAKE_STA_IDLE_STA,
+ WAKE_STA_REQ_STA,
+ WAKE_STA_DEBUG_FLAG,
+ WAKE_STA_DEBUG_FLAG1,
+ WAKE_STA_EVENT_REG,
+ WAKE_STA_ISR,
+ WAKE_STA_MAX_COUNT,
+};
+
+#endif /* MT_SPM_SMC_H */
diff --git a/plat/mediatek/drivers/spm/common/rules.mk b/plat/mediatek/drivers/spm/common/rules.mk
new file mode 100644
index 0000000..50273de
--- /dev/null
+++ b/plat/mediatek/drivers/spm/common/rules.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+#Prologue, init variable
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+#Define your module name
+MODULE := spm_common
+
+#Add your source code here
+LOCAL_SRCS-y :=
+
+#Epilogue, build as module
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
+$(eval $(call add_defined_option,CONFIG_MTK_VCOREDVFS_SUPPORT))