tree ed5c313c132d0769b12c30332bc16e528ebe59f0
parent e0559ac09dd2515f04f10be26dde14304b2d6ba6
author David Cunado <david.cunado@arm.com> 1500462847 +0100
committer David Cunado <david.cunado@arm.com> 1501066740 +0100

Address edge case for stale PSCI CPU data in cache

There is a theoretical edge case during CPU_ON where the cache
may contain stale data for the target CPU data - this can occur
under the following conditions:

- the target CPU is in another cluster from the current
- the target CPU was the last CPU to shutdown on its cluster
- the cluster was removed from coherency as part of the CPU shutdown

In this case the cache maintenace that was performed as part of the
target CPUs shutdown was not seen by the current CPU's cluster. And
so the cache may contain stale data for the target CPU.

This patch adds a cache maintenance operation (flush) for the
cache-line containing the target CPU data - this ensures that the
target CPU data is read from main memory.

Change-Id: If8cfd42639b03174f60669429b7f7a757027d0fb
Signed-off-by: David Cunado <david.cunado@arm.com>