feat(st-ddr): add STM32MP2 driver
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY
and its firmware, as well as the DDR controller.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
diff --git a/drivers/st/ddr/stm32mp_ddr_test.c b/drivers/st/ddr/stm32mp_ddr_test.c
index 0f6aff1..707a6ff 100644
--- a/drivers/st/ddr/stm32mp_ddr_test.c
+++ b/drivers/st/ddr/stm32mp_ddr_test.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,8 +10,31 @@
#include <platform_def.h>
+#ifdef __aarch64__
+#define DDR_PATTERN 0xAAAAAAAAAAAAAAAAUL
+#define DDR_ANTIPATTERN 0x5555555555555555UL
+#else /* !__aarch64__ */
#define DDR_PATTERN 0xAAAAAAAAU
#define DDR_ANTIPATTERN 0x55555555U
+#endif /* __aarch64__ */
+
+static void mmio_write_pattern(uintptr_t addr, u_register_t value)
+{
+#ifdef __aarch64__
+ mmio_write_64(addr, (uint64_t)value);
+#else /* !__aarch64__ */
+ mmio_write_32(addr, (uint32_t)value);
+#endif /* __aarch64__ */
+}
+
+static u_register_t mmio_read_pattern(uintptr_t addr)
+{
+#ifdef __aarch64__
+ return (u_register_t)mmio_read_64(addr);
+#else /* !__aarch64__ */
+ return (u_register_t)mmio_read_32(addr);
+#endif /* __aarch64__ */
+}
/*******************************************************************************
* This function tests a simple read/write access to the DDR.
@@ -20,15 +43,15 @@
******************************************************************************/
uintptr_t stm32mp_ddr_test_rw_access(void)
{
- uint32_t saved_value = mmio_read_32(STM32MP_DDR_BASE);
+ u_register_t saved_value = mmio_read_pattern(STM32MP_DDR_BASE);
- mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE, DDR_PATTERN);
- if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) {
return STM32MP_DDR_BASE;
}
- mmio_write_32(STM32MP_DDR_BASE, saved_value);
+ mmio_write_pattern(STM32MP_DDR_BASE, saved_value);
return 0UL;
}
@@ -43,12 +66,12 @@
******************************************************************************/
uintptr_t stm32mp_ddr_test_data_bus(void)
{
- uint32_t pattern;
+ u_register_t pattern;
for (pattern = 1U; pattern != 0U; pattern <<= 1U) {
- mmio_write_32(STM32MP_DDR_BASE, pattern);
+ mmio_write_pattern(STM32MP_DDR_BASE, pattern);
- if (mmio_read_32(STM32MP_DDR_BASE) != pattern) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != pattern) {
return STM32MP_DDR_BASE;
}
}
@@ -72,41 +95,41 @@
size_t testoffset = 0U;
/* Write the default pattern at each of the power-of-two offsets. */
- for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
+ for (offset = sizeof(u_register_t); (offset & addressmask) != 0U;
offset <<= 1U) {
- mmio_write_32(STM32MP_DDR_BASE + offset, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + offset, DDR_PATTERN);
}
/* Check for address bits stuck high. */
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
- for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
+ for (offset = sizeof(u_register_t); (offset & addressmask) != 0U;
offset <<= 1U) {
- if (mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE + offset) != DDR_PATTERN) {
return STM32MP_DDR_BASE + offset;
}
}
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
/* Check for address bits stuck low or shorted. */
- for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U;
+ for (testoffset = sizeof(u_register_t); (testoffset & addressmask) != 0U;
testoffset <<= 1U) {
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
- if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) {
return STM32MP_DDR_BASE;
}
- for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
- offset <<= 1) {
- if ((mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) &&
+ for (offset = sizeof(u_register_t); (offset & addressmask) != 0U;
+ offset <<= 1U) {
+ if ((mmio_read_pattern(STM32MP_DDR_BASE + offset) != DDR_PATTERN) &&
(offset != testoffset)) {
return STM32MP_DDR_BASE + offset;
}
}
- mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
}
return 0UL;
@@ -121,15 +144,15 @@
******************************************************************************/
size_t stm32mp_ddr_check_size(void)
{
- size_t offset = sizeof(uint32_t);
+ size_t offset = sizeof(u_register_t);
- mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE, DDR_PATTERN);
while (offset < STM32MP_DDR_MAX_SIZE) {
- mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
+ mmio_write_pattern(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
dsb();
- if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+ if (mmio_read_pattern(STM32MP_DDR_BASE) != DDR_PATTERN) {
break;
}