feat(el3-runtime): introduce UNDEF injection to lower EL
For a feature to be used at lower ELs, EL3 generally needs to disable
the trap so that lower ELs can access the system registers associated
with the feature. Lower ELs generally check ID registers to dynamically
detect if a feature is present (in HW) or not while EL3 Firmware relies
statically on feature build macros to enable a feature.
If a lower EL accesses a system register for a feature that EL3 FW is
unaware of, EL3 traps the access and panics. This happens mostly with
EL2 but sometimes VMs can also cause EL3 panic.
To provide platforms with capability to mitigate this problem, UNDEF
injection support has been introduced which injects a synchronous
exception into the lower EL which is supposed to handle the
synchronous exception.
The current support is only provided for aarch64.
The implementation does the following on encountering sys reg trap
- Get the target EL, which can be either EL2 or EL1
- Update ELR_ELx with ELR_EL3, so that after UNDEF handling in lower EL
control returns to original location.
- ESR_ELx with EC_UNKNOWN
- Update ELR_EL3 with vector address of sync exception handler with
following possible causes
- Current EL with SP0
- Current EL with SPx
- Lower EL using AArch64
- Re-create SPSR_EL3 which will be used to generate PSTATE at ERET
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1b7bf6c043ce7aec1ee4fc1121c389b490b7bfb7
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 06bf3ae..8a4c071 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -75,6 +75,19 @@
#define INVALID_MPID U(0xFFFFFFFF)
/*******************************************************************************
+ * Definitions for Exception vector offsets
+ ******************************************************************************/
+#define CURRENT_EL_SP0 0x0
+#define CURRENT_EL_SPX 0x200
+#define LOWER_EL_AARCH64 0x400
+#define LOWER_EL_AARCH32 0x600
+
+#define SYNC_EXCEPTION 0x0
+#define IRQ_EXCEPTION 0x80
+#define FIQ_EXCEPTION 0x100
+#define SERROR_EXCEPTION 0x180
+
+/*******************************************************************************
* Definitions for CPU system register interface to GICv3
******************************************************************************/
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
diff --git a/include/bl31/sync_handle.h b/include/bl31/sync_handle.h
index 1ac4f98..ae61f31 100644
--- a/include/bl31/sync_handle.h
+++ b/include/bl31/sync_handle.h
@@ -55,6 +55,9 @@
*/
int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx);
+/* Handler for injecting UNDEF exception to lower EL */
+void inject_undef64(cpu_context_t *ctx);
+
/* Prototypes for system register emulation handlers provided by platforms. */
int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx);
int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx);