feat(versal2): add support for AMD Versal Gen 2 platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/plat/amd/versal2/include/versal2-scmi.h b/plat/amd/versal2/include/versal2-scmi.h
new file mode 100644
index 0000000..4d581e4
--- /dev/null
+++ b/plat/amd/versal2/include/versal2-scmi.h
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Macros IDs for AMD Versal Gen 2
+ *
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#ifndef _VERSAL2_SCMI_H
+#define _VERSAL2_SCMI_H
+
+#define CLK_GEM0_0 0
+#define CLK_GEM0_1 1
+#define CLK_GEM0_2 2
+#define CLK_GEM0_3 3
+#define CLK_GEM0_4 4
+#define CLK_GEM1_0 5
+#define CLK_GEM1_1 6
+#define CLK_GEM1_2 7
+#define CLK_GEM1_3 8
+#define CLK_GEM1_4 9
+#define CLK_SERIAL0_0 10
+#define CLK_SERIAL0_1 11
+#define CLK_SERIAL1_0 12
+#define CLK_SERIAL1_1 13
+#define CLK_UFS0_0 14
+#define CLK_UFS0_1 15
+#define CLK_UFS0_2 16
+#define CLK_USB0_0 17
+#define CLK_USB0_1 18
+#define CLK_USB0_2 19
+#define CLK_USB1_0 20
+#define CLK_USB1_1 21
+#define CLK_USB1_2 22
+#define CLK_MMC0_0 23
+#define CLK_MMC0_1 24
+#define CLK_MMC0_2 25
+#define CLK_MMC1_0 26
+#define CLK_MMC1_1 27
+#define CLK_MMC1_2 28
+#define CLK_TTC0_0 29
+#define CLK_TTC1_0 30
+#define CLK_TTC2_0 31
+#define CLK_TTC3_0 32
+#define CLK_TTC4_0 33
+#define CLK_TTC5_0 34
+#define CLK_TTC6_0 35
+#define CLK_TTC7_0 36
+#define CLK_I2C0_0 37
+#define CLK_I2C1_0 38
+#define CLK_I2C2_0 39
+#define CLK_I2C3_0 40
+#define CLK_I2C4_0 41
+#define CLK_I2C5_0 42
+#define CLK_I2C6_0 43
+#define CLK_I2C7_0 44
+#define CLK_OSPI0_0 45
+#define CLK_QSPI0_0 46
+#define CLK_QSPI0_1 47
+#define CLK_WWDT0_0 48
+#define CLK_WWDT1_0 49
+#define CLK_WWDT2_0 50
+#define CLK_WWDT3_0 51
+#define CLK_ADMA0_0 52
+#define CLK_ADMA0_1 53
+#define CLK_ADMA1_0 54
+#define CLK_ADMA1_1 55
+#define CLK_ADMA2_0 56
+#define CLK_ADMA2_1 57
+#define CLK_ADMA3_0 58
+#define CLK_ADMA3_1 59
+#define CLK_ADMA4_0 60
+#define CLK_ADMA4_1 61
+#define CLK_ADMA5_0 62
+#define CLK_ADMA5_1 63
+#define CLK_ADMA6_0 64
+#define CLK_ADMA6_1 65
+#define CLK_ADMA7_0 66
+#define CLK_ADMA7_1 67
+#define CLK_CAN0_0 68
+#define CLK_CAN0_1 69
+#define CLK_CAN1_0 70
+#define CLK_CAN1_1 71
+#define CLK_CAN2_0 72
+#define CLK_CAN2_1 73
+#define CLK_CAN3_0 74
+#define CLK_CAN3_1 75
+#define CLK_PS_GPIO_0 76
+#define CLK_PMC_GPIO_0 77
+#define CLK_SPI0_0 78
+#define CLK_SPI0_1 79
+#define CLK_SPI1_0 80
+#define CLK_SPI1_1 81
+#define CLK_I3C0_0 82
+#define CLK_I3C1_0 83
+#define CLK_I3C2_0 84
+#define CLK_I3C3_0 85
+#define CLK_I3C4_0 86
+#define CLK_I3C5_0 87
+#define CLK_I3C6_0 88
+#define CLK_I3C7_0 89
+
+#define RESET_GEM0_0 0
+#define RESET_GEM1_0 1
+#define RESET_SERIAL0_0 2
+#define RESET_SERIAL1_0 3
+#define RESET_UFS0_0 4
+#define RESET_I2C0_0 5
+#define RESET_I2C1_0 6
+#define RESET_I2C2_0 7
+#define RESET_I2C3_0 8
+#define RESET_I2C4_0 9
+#define RESET_I2C5_0 10
+#define RESET_I2C6_0 11
+#define RESET_I2C7_0 12
+#define RESET_I2C8_0 13
+#define RESET_OSPI0_0 14
+#define RESET_USB0_0 15
+#define RESET_USB0_1 16
+#define RESET_USB0_2 17
+#define RESET_USB1_0 18
+#define RESET_USB1_1 19
+#define RESET_USB1_2 20
+#define RESET_MMC0_0 21
+#define RESET_MMC1_0 22
+#define RESET_SPI0_0 23
+#define RESET_SPI1_0 24
+#define RESET_QSPI0_0 25
+#define RESET_I3C0_0 26
+#define RESET_I3C1_0 27
+#define RESET_I3C2_0 28
+#define RESET_I3C3_0 29
+#define RESET_I3C4_0 30
+#define RESET_I3C5_0 31
+#define RESET_I3C6_0 32
+#define RESET_I3C7_0 33
+#define RESET_I3C8_0 34
+
+#endif /* _VERSAL2_SCMI_H */