commit 055796f4e213dc18a2f619ee4ef55c1b7d1481ef
author Amit Nagal <amit.nagal@amd.com> Wed Jun 05 12:32:38 2024 +0530
committer Michal Šimek <michal.simek@amd.com> Mon Jun 10 08:09:49 2024 +0200
tree 7f1ab431533f532f1971c6a1307a6336e4be8709
parent 5b10efba7b8012a9aa09386c388df8af4915783c

feat(versal2): add support for AMD Versal Gen 2 platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>

changelog.yaml

diff --git a/changelog.yaml b/changelog.yaml
index 6f2458e..101aa48 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -674,6 +674,13 @@
               - plat/zynqmp
               - plat/xilinx/zynqmp
 
+      - title: AMD
+        scope: amd
+
+        subsections:
+          - title: Versal Gen 2
+            scope: versal2
+
       - title: Nuvoton
         scope: nuvoton