plat/arm/sgi: disable Ares cpu power down bit in reset handler
On SGI platforms that include Ares CPUs, the 'CORE_PWRDN_EN' bit of
'CPUPWRCTLR_EL1' register requires an explicit write to clear it to
enable hotplug and idle to function correctly.
The reset value of the CORE_PWRDN_EN bit is zero but it still requires
this explicit clear to zero. This indicates that this could be a model
related issue but for now this issue can be fixed be clearing the
CORE_PWRDN_EN bit in the platform specific reset handler function.
Change-Id: I8b9884ae27a2986d789bfec2e9ae792ef930944e
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S
index 27bae43..d79f1aa 100644
--- a/plat/arm/css/sgi/aarch64/sgi_helper.S
+++ b/plat/arm/css/sgi/aarch64/sgi_helper.S
@@ -8,6 +8,7 @@
#include <asm_macros.S>
#include <platform_def.h>
#include <cortex_a75.h>
+#include <cortex_ares.h>
#include <cpu_macros.S>
.globl plat_arm_calc_core_pos
@@ -58,6 +59,7 @@
*/
func plat_reset_handler
jump_if_cpu_midr CORTEX_A75_MIDR, A75
+ jump_if_cpu_midr CORTEX_ARES_MIDR, ARES
ret
/* -----------------------------------------------------
@@ -70,4 +72,11 @@
msr CORTEX_A75_CPUPWRCTLR_EL1, x0
isb
ret
+
+ARES:
+ mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1
+ bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK
+ msr CORTEX_ARES_CPUPWRCTLR_EL1, x0
+ isb
+ ret
endfunc plat_reset_handler