diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index 1aaf7cc..aa2c900 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -50,6 +50,9 @@
 	case MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP:
 		ret = apusys_kernel_apusys_rv_stop_mp();
 		break;
+	case MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX:
+		ret = apusys_devapc_rcx_init();
+		break;
 	default:
 		ERROR(MODULE_TAG "%s unknown request_ops = %x\n", MODULE_TAG, request_ops);
 		break;
diff --git a/plat/mediatek/drivers/apusys/apusys.h b/plat/mediatek/drivers/apusys/apusys.h
index 93ed6a7..2a9bffb 100644
--- a/plat/mediatek/drivers/apusys/apusys.h
+++ b/plat/mediatek/drivers/apusys/apusys.h
@@ -17,6 +17,7 @@
 	MTK_APUSYS_KERNEL_OP_APUSYS_RV_SETUP_BOOT,	/*  4 */
 	MTK_APUSYS_KERNEL_OP_APUSYS_RV_START_MP,	/*  5 */
 	MTK_APUSYS_KERNEL_OP_APUSYS_RV_STOP_MP,		/*  6 */
+	MTK_APUSYS_KERNEL_OP_DEVAPC_INIT_RCX,		/*  7 */
 	MTK_APUSYS_KERNEL_OP_NUM,
 };
 
diff --git a/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
index 621a08c..2f5d47b 100644
--- a/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
+++ b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
@@ -107,6 +107,13 @@
 /******************************************************************************
  * DAPC Permission Policy
  ******************************************************************************/
+#define SLAVE_FORBID_EXCEPT_D0_SEC_RW(domain)				 \
+	APUSYS_APC_AO_ATTR(domain,					 \
+			   SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   FORBIDDEN, FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
 #define SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT(domain)		     \
 	APUSYS_APC_AO_ATTR(domain,					     \
 			   SEC_RW_ONLY, FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
@@ -156,4 +163,11 @@
 			   FORBIDDEN,     FORBIDDEN,     FORBIDDEN, FORBIDDEN,   \
 			   FORBIDDEN,     FORBIDDEN,     FORBIDDEN, FORBIDDEN)
 
+#define SLAVE_FORBID_EXCEPT_D0_D3_SEC_RW_D5_NO_PROTECT(domain)		       \
+	APUSYS_APC_AO_ATTR(domain,					       \
+			   SEC_RW_ONLY, FORBIDDEN,     FORBIDDEN, SEC_RW_ONLY, \
+			   FORBIDDEN,   NO_PROTECTION, FORBIDDEN, FORBIDDEN,   \
+			   FORBIDDEN,   FORBIDDEN,     FORBIDDEN, FORBIDDEN,   \
+			   FORBIDDEN,   FORBIDDEN,     FORBIDDEN, FORBIDDEN)
+
 #endif /* APUSYS_DAPC_V1_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
index 9bdf875..da5242a 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
@@ -16,6 +16,15 @@
 
 #define DUMP_APUSYS_DAPC	(0)
 
+static const struct apc_dom_16 APU_NOC_DAPC_RCX[] = {
+	/* ctrl index = 0 */
+	SLAVE_MD32_SRAM("slv16-0"),
+	SLAVE_MD32_SRAM("slv16-1"),
+	SLAVE_MD32_SRAM("slv16-2"),
+	SLAVE_MD32_SRAM("slv16-3"),
+	SLAVE_MD32_SRAM("slv16-4"),
+};
+
 static const struct apc_dom_16 APU_CTRL_DAPC_AO[] = {
 	/* ctrl index = 0 */
 	SLAVE_VCORE("apu_ao_ctl_o-0"),
@@ -54,6 +63,85 @@
 	SLAVE_SAE_TO_ACX1_1("apu_sae2acx1_o-1"),
 };
 
+static const struct apc_dom_16 APU_CTRL_DAPC_RCX[] = {
+	/* ctrl index = 0 */
+	SLAVE_MD32_SYSCTRL0("md32_apb_s-0"),
+	SLAVE_MD32_SYSCTRL1("md32_apb_s-1"),
+	SLAVE_MD32_WDT("md32_apb_s-2"),
+	SLAVE_MD32_CACHE("md32_apb_s-3"),
+	SLAVE_RPC("apusys_ao-0"),
+	SLAVE_PCU("apusys_ao-1"),
+	SLAVE_AO_CTRL("apusys_ao-2"),
+	SLAVE_PLL("apusys_ao-3"),
+	SLAVE_ACC("apusys_ao-4"),
+	SLAVE_SEC("apusys_ao-5"),
+
+	/* ctrl index = 10 */
+	SLAVE_ARE0("apusys_ao-6"),
+	SLAVE_ARE1("apusys_ao-7"),
+	SLAVE_ARE2("apusys_ao-8"),
+	SLAVE_UNKNOWN("apusys_ao-9"),
+	SLAVE_AO_BCRM("apusys_ao-10"),
+	SLAVE_AO_DAPC_WRAP("apusys_ao-11"),
+	SLAVE_AO_DAPC_CON("apusys_ao-12"),
+	SLAVE_VCORE("apusys_ao-13"),
+	SLAVE_ACX0_BCRM("apusys_ao-15"),
+	SLAVE_ACX1_BCRM("apusys_ao-16"),
+
+	/* ctrl index = 20 */
+	SLAVE_NOC_AXI("noc_axi"),
+	SLAVE_MD32_DBG("md32_dbg"),
+	SLAVE_DBG_CRTL("apb_infra_dbg"),
+	SLAVE_IOMMU0_BANK0("apu_n_mmu_r0"),
+	SLAVE_IOMMU0_BANK1("apu_n_mmu_r1"),
+	SLAVE_IOMMU0_BANK2("apu_n_mmu_r2"),
+	SLAVE_IOMMU0_BANK3("apu_n_mmu_r3"),
+	SLAVE_IOMMU0_BANK4("apu_n_mmu_r4"),
+	SLAVE_IOMMU1_BANK0("apu_s_mmu_r0"),
+	SLAVE_IOMMU1_BANK1("apu_s_mmu_r1"),
+
+	/* ctrl index = 30 */
+	SLAVE_IOMMU1_BANK2("apu_s_mmu_r2"),
+	SLAVE_IOMMU1_BANK3("apu_s_mmu_r3"),
+	SLAVE_IOMMU1_BANK4("apu_s_mmu_r4"),
+	SLAVE_S0_SSC("apu_s0_ssc_cfg"),
+	SLAVE_N0_SSC("apu_n0_ssc_cfg"),
+	SLAVE_ACP_SSC("apu_acp_ssc_cfg"),
+	SLAVE_S1_SSC("apu_s1_ssc_cfg"),
+	SLAVE_N1_SSC("apu_n1_ssc_cfg"),
+	SLAVE_CFG("apu_rcx_cfg"),
+	SLAVE_SEMA_STIMER("apu_sema_stimer"),
+
+	/* ctrl index = 40 */
+	SLAVE_EMI_CFG("apu_emi_cfg"),
+	SLAVE_LOG("apu_logtop"),
+	SLAVE_CPE_SENSOR("apu_cpe_sensor"),
+	SLAVE_CPE_COEF("apu_cpe_coef"),
+	SLAVE_CPE_CTRL("apu_cpe_ctrl"),
+	SLAVE_UNKNOWN("apu_xpu_rsi"),
+	SLAVE_DFD_REG_SOC("apu_dfd"),
+	SLAVE_SENSOR_WRAP_ACX0_DLA0("apu_sen_ac0_dla0"),
+	SLAVE_SENSOR_WRAP_ACX0_DLA1("apu_sen_ac0_dla1"),
+	SLAVE_SENSOR_WRAP_ACX0_VPU0("apu_sen_ac0_vpu"),
+
+	/* ctrl index = 50 */
+	SLAVE_SENSOR_WRAP_ACX1_DLA0("apu_sen_ac1_dla0"),
+	SLAVE_SENSOR_WRAP_ACX1_DLA1("apu_sen_ac1_dla1"),
+	SLAVE_SENSOR_WRAP_ACX1_VPU0("apu_sen_ac1_vpu"),
+	SLAVE_REVISER("noc_cfg-0"),
+	SLAVE_NOC("noc_cfg-1"),
+	SLAVE_BCRM("infra_bcrm"),
+	SLAVE_DAPC_WRAP("infra_dapc_wrap"),
+	SLAVE_DAPC_CON("infra_dapc_con"),
+	SLAVE_NOC_DAPC_WRAP("noc_dapc_wrap"),
+	SLAVE_NOC_DAPC_CON("noc_dapc_con"),
+
+	/* ctrl index = 60 */
+	SLAVE_NOC_BCRM("noc_bcrm"),
+	SLAVE_ACS("apu_rcx_acs"),
+	SLAVE_HSE("apu_hse"),
+};
+
 static enum apusys_apc_err_status set_slave_ao_ctrl_apc(uint32_t slave,
 							enum apusys_apc_domain_id domain_id,
 							enum apusys_apc_perm_type perm)
@@ -89,6 +177,74 @@
 	return APUSYS_APC_OK;
 }
 
+static enum apusys_apc_err_status set_slave_noc_dapc_rcx(uint32_t slave,
+							 enum apusys_apc_domain_id domain_id,
+							 enum apusys_apc_perm_type perm)
+{
+	uint32_t apc_register_index;
+	uint32_t apc_set_index;
+	uint32_t base;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	if ((perm >= PERM_NUM) || (perm < 0)) {
+		ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
+		return APUSYS_APC_ERR_GENERIC;
+	}
+
+	if ((slave >= APU_NOC_DAPC_RCX_SLAVE_NUM) ||
+	    ((domain_id < 0) || (domain_id >= APU_NOC_DAPC_RCX_DOM_NUM))) {
+		ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
+		      __func__, slave, domain_id);
+		return APUSYS_APC_ERR_GENERIC;
+	}
+
+	apc_register_index = slave / APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+	apc_set_index = slave % APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+
+	clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
+	set_bit = ((uint32_t)perm) << (apc_set_index * DEVAPC_DOM_SHIFT);
+	base = (APU_NOC_DAPC_RCX_BASE + domain_id * DEVAPC_DOM_SIZE +
+		apc_register_index * DEVAPC_REG_SIZE);
+
+	mmio_clrsetbits_32(base, clr_bit, set_bit);
+	return APUSYS_APC_OK;
+}
+
+static enum apusys_apc_err_status set_slave_rcx_ctrl_apc(uint32_t slave,
+							 enum apusys_apc_domain_id domain_id,
+							 enum apusys_apc_perm_type perm)
+{
+	uint32_t apc_register_index;
+	uint32_t apc_set_index;
+	uint32_t base;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	if ((perm < 0) || (perm >= PERM_NUM)) {
+		ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
+		return APUSYS_APC_ERR_GENERIC;
+	}
+
+	if ((slave >= APU_CTRL_DAPC_RCX_SLAVE_NUM) ||
+	    ((domain_id < 0) || (domain_id >= APU_CTRL_DAPC_RCX_DOM_NUM))) {
+		ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
+		      __func__, slave, domain_id);
+		return APUSYS_APC_ERR_GENERIC;
+	}
+
+	apc_register_index = slave / APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+	apc_set_index = slave % APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
+
+	clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
+	set_bit = (uint32_t)perm << (apc_set_index * DEVAPC_DOM_SHIFT);
+	base = (APU_CTRL_DAPC_RCX_BASE + domain_id * DEVAPC_DOM_SIZE +
+		apc_register_index * DEVAPC_REG_SIZE);
+
+	mmio_clrsetbits_32(base, clr_bit, set_bit);
+	return APUSYS_APC_OK;
+}
+
 static void apusys_devapc_init(const char *name, uint32_t base)
 {
 	mmio_write_32(APUSYS_DAPC_CON(base), APUSYS_DAPC_CON_VIO_MASK);
@@ -112,3 +268,40 @@
 
 	return 0;
 }
+
+int apusys_devapc_rcx_init(void)
+{
+	static bool apusys_devapc_rcx_init_called;
+	enum apusys_apc_err_status ret;
+
+	if (apusys_devapc_rcx_init_called == true) {
+		INFO(MODULE_TAG "%s: init more than once!\n", __func__);
+		return -1;
+	}
+	apusys_devapc_rcx_init_called = true;
+
+	apusys_devapc_init("APUAPC_CTRL_RCX", APU_CTRL_DAPC_RCX_BASE);
+	apusys_devapc_init("APUAPC_NOC_RCX", APU_NOC_DAPC_RCX_BASE);
+
+	ret = SET_APUSYS_DAPC_V1(APU_CTRL_DAPC_RCX, set_slave_rcx_ctrl_apc);
+	if (ret != APUSYS_APC_OK) {
+		ERROR(MODULE_TAG "%s: set_slave_rcx_ctrl_apc FAILED!\n", __func__);
+		return -1;
+	}
+
+#if DUMP_APUSYS_DAPC
+	DUMP_APUSYS_DAPC_V1(APU_CTRL_DAPC_RCX);
+#endif
+
+	ret = SET_APUSYS_DAPC_V1(APU_NOC_DAPC_RCX, set_slave_noc_dapc_rcx);
+	if (ret != APUSYS_APC_OK) {
+		ERROR(MODULE_TAG "%s: set_slave_noc_dapc_rcx FAILED\n", __func__);
+		return -1;
+	}
+
+#if DUMP_APUSYS_DAPC
+	DUMP_APUSYS_DAPC_V1(APU_NOC_DAPC_RCX);
+#endif
+
+	return 0;
+}
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
index 345705c..de76459 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
@@ -8,5 +8,6 @@
 #define APUSYS_DEVAPC_H
 
 int apusys_devapc_ao_init(void);
+int apusys_devapc_rcx_init(void);
 
 #endif /* APUSYS_DEVAPC_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
index 3fe69d2..e74b022 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
@@ -10,35 +10,85 @@
 #include <lib/mmio.h>
 #include "../devapc/apusys_dapc_v1.h"
 
+/* NoC */
+#define SLAVE_MD32_SRAM			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+
 /* Control */
-#define SLAVE_VCORE		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_RPC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
-#define SLAVE_PCU		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_AO_CTRL		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_PLL		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
-#define SLAVE_ACC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_SEC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_ARE0		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_ARE1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_ARE2		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_UNKNOWN		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
-#define SLAVE_APU_BULK		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_AO_BCRM		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
-#define SLAVE_AO_DAPC_WRAP	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
-#define SLAVE_AO_DAPC_CON	SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
-#define SLAVE_RCX_ACX_BULK	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
-#define SLAVE_ACX0_BCRM		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
-#define SLAVE_RPCTOP_LITE_ACX0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
-#define SLAVE_ACX1_BCRM		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
-#define SLAVE_RPCTOP_LITE_ACX1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
-#define SLAVE_RCX_TO_ACX0_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
-#define SLAVE_RCX_TO_ACX0_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
-#define SLAVE_SAE_TO_ACX0_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
-#define SLAVE_SAE_TO_ACX0_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
-#define SLAVE_RCX_TO_ACX1_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
-#define SLAVE_RCX_TO_ACX1_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
-#define SLAVE_SAE_TO_ACX1_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
-#define SLAVE_SAE_TO_ACX1_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_VCORE			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RPC			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_PCU			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_CTRL			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_PLL			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_ACC			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_SEC			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE0			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE1			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE2			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_UNKNOWN			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_APU_BULK			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_BCRM			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_WRAP		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_CON		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RCX_ACX_BULK		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_ACX0_BCRM			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_ACX1_BCRM			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX0_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RCX_TO_ACX0_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX0_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_SAE_TO_ACX0_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_1		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_MD32_SYSCTRL0		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_MD32_SYSCTRL1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_MD32_WDT			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_MD32_CACHE		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_NOC_AXI			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_MD32_DBG			SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_DBG_CRTL			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK2		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK3		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU0_BANK4		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK0		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK2		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK3		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_IOMMU1_BANK4		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_S0_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_N0_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_ACP_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_S1_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_N1_SSC			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_CFG			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_SEMA_STIMER		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_EMI_CFG			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_LOG			SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_CPE_SENSOR		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_CPE_COEF			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_CPE_CTRL			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_DFD_REG_SOC		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX0_DLA0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX0_DLA1	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX0_VPU0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX1_DLA0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX1_DLA1	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_SENSOR_WRAP_ACX1_VPU0	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_REVISER			SLAVE_FORBID_EXCEPT_D0_SEC_RW
+#define SLAVE_NOC			SLAVE_FORBID_EXCEPT_D0_D3_SEC_RW_D5_NO_PROTECT
+#define SLAVE_BCRM			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_DAPC_WRAP			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_DAPC_CON			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_NOC_DAPC_WRAP		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_NOC_DAPC_CON		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_NOC_BCRM			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_ACS			SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_HSE			SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+
 
 /* Power Domain: AO */
 #define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM	(16)
@@ -47,4 +97,13 @@
 #define DEVAPC_MASK				(0x3U)
 #define DEVAPC_DOM_SHIFT			(2)
 
+/* Power Domain: RCX */
+#define APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM	(16)
+#define APU_CTRL_DAPC_RCX_DOM_NUM		(16)
+#define APU_CTRL_DAPC_RCX_SLAVE_NUM		(63)
+
+#define APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM	(16)
+#define APU_NOC_DAPC_RCX_DOM_NUM		(16)
+#define APU_NOC_DAPC_RCX_SLAVE_NUM		(5)
+
 #endif /* APUSYS_DEVAPC_DEF_H */
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 29e4d21..0a7ae6d 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -31,6 +31,8 @@
 #define APU_MD32_SYSCTRL	(IO_PHYS + 0x09001000)
 #define APU_MD32_WDT		(IO_PHYS + 0x09002000)
 #define APU_RCX_CONFIG		(IO_PHYS + 0x09020000)
+#define APU_CTRL_DAPC_RCX_BASE	(IO_PHYS + 0x09034000)
+#define APU_NOC_DAPC_RCX_BASE	(IO_PHYS + 0x09038000)
 #define APU_REVISER		(IO_PHYS + 0x0903c000)
 #define APU_RCX_VCORE_CONFIG	(IO_PHYS + 0x090e0000)
 #define APU_MBOX0		(IO_PHYS + 0x090e1000)