commit 03ba5d8fb6b46bc79e03f36ab2fe0d5b47487bfb
author Bipin Ravi <bipin.ravi@arm.com> Tue Oct 17 05:56:01 2023 -0500
committer laurenw-arm <lauren.wehrmeister@arm.com> Thu Nov 02 10:12:33 2023 -0500
tree fa828effba0a67a207d4ba70bccde63f0413a6cf
parent 1daa5a43c409bea280c98b32435b239159c6749f

fix(cpus): workaround for Neoverse N2 erratum 2346952

Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

include/lib/cpus/aarch64/neoverse_n2.h

diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index 0d50854..b379fab 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -65,5 +65,8 @@
 #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV		ULL(9)
 #define CPUECTLR2_EL1_PF_MODE_LSB			U(11)
 #define CPUECTLR2_EL1_PF_MODE_WIDTH			U(4)
+#define CPUECTLR2_EL1_TXREQ_STATIC_FULL 		ULL(0)
+#define CPUECTLR2_EL1_TXREQ_LSB				U(0)
+#define CPUECTLR2_EL1_TXREQ_WIDTH			U(3)
 
 #endif /* NEOVERSE_N2_H */