Merge "plat/arm: Introduce corstone700 platform." into integration
diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S
index 4050678..2c41029 100644
--- a/bl31/aarch64/crash_reporting.S
+++ b/bl31/aarch64/crash_reporting.S
@@ -28,7 +28,7 @@
*/
.section .rodata.crash_prints, "aS"
print_spacer:
- .asciz " =\t\t0x"
+ .asciz " = 0x"
gp_regs:
.asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
@@ -55,11 +55,11 @@
#endif /* CTX_INCLUDE_AARCH32_REGS */
panic_msg:
- .asciz "PANIC in EL3 at x30 = 0x"
+ .asciz "PANIC in EL3.\nx30"
excpt_msg:
- .asciz "Unhandled Exception in EL3.\nx30 =\t\t0x"
+ .asciz "Unhandled Exception in EL3.\nx30"
intr_excpt_msg:
- .asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x"
+ .asciz "Unhandled Interrupt Exception in EL3.\nx30"
/*
* Helper function to print newline to console.
@@ -94,10 +94,11 @@
mov x4, x6
/* asm_print_str updates x4 to point to next entry in list */
bl asm_print_str
+ /* x0 = number of symbols printed + 1 */
+ sub x0, x4, x6
/* update x6 with the updated list pointer */
mov x6, x4
- adr x4, print_spacer
- bl asm_print_str
+ bl print_alignment
ldr x4, [x7], #REGSZ
bl asm_print_hex
bl print_newline
@@ -107,6 +108,20 @@
ret
endfunc size_controlled_print
+ /* -----------------------------------------------------
+ * This function calculates and prints required number
+ * of space characters followed by "= 0x", based on the
+ * length of ascii register name.
+ * x0: length of ascii register name + 1
+ * ------------------------------------------------------
+ */
+func print_alignment
+ /* The minimum ascii length is 3, e.g. for "x0" */
+ adr x4, print_spacer - 3
+ add x4, x4, x0
+ b asm_print_str
+endfunc print_alignment
+
/*
* Helper function to store x8 - x15 registers to
* the crash buf. The system registers values are
@@ -189,7 +204,7 @@
* -----------------------------------------------------
*/
func el3_panic
- msr spsel, #1
+ msr spsel, #MODE_SP_ELX
prepare_crash_buf_save_x0_x1
adr x0, panic_msg
mov sp, x0
@@ -230,6 +245,9 @@
/* Print the crash message. sp points to the crash message */
mov x4, sp
bl asm_print_str
+ /* Print spaces to align "x30" string */
+ mov x0, #4
+ bl print_alignment
/* load the crash buf address */
mrs x0, tpidr_el3
/* report x30 first from the crash buf */
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index da740ef..ac47cbe 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
.globl asm_print_str
.globl asm_print_hex
+ .globl asm_print_hex_bits
.globl asm_assert
.globl do_panic
@@ -107,8 +108,11 @@
* Clobber: x30, x0 - x3, x5
*/
func asm_print_hex
- mov x3, x30
mov x5, #64 /* No of bits to convert to ascii */
+
+ /* Convert to ascii number of bits in x5 */
+asm_print_hex_bits:
+ mov x3, x30
1:
sub x5, x5, #4
lsrv x0, x4, x5
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c
index d9eba7f..215f495 100644
--- a/drivers/console/multi_console.c
+++ b/drivers/console/multi_console.c
@@ -70,6 +70,20 @@
console->flags = (console->flags & ~CONSOLE_FLAG_SCOPE_MASK) | scope;
}
+static int do_putc(int c, console_t *console)
+{
+ int ret;
+
+ if ((c == '\n') &&
+ ((console->flags & CONSOLE_FLAG_TRANSLATE_CRLF) != 0)) {
+ ret = console->putc('\r', console);
+ if (ret < 0)
+ return ret;
+ }
+
+ return console->putc(c, console);
+}
+
int console_putc(int c)
{
int err = ERROR_NO_VALID_CONSOLE;
@@ -77,7 +91,7 @@
for (console = console_list; console != NULL; console = console->next)
if ((console->flags & console_state) && console->putc) {
- int ret = console->putc(c, console);
+ int ret = do_putc(c, console);
if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err))
err = ret;
}
diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/rcar/emmc/emmc_interrupt.c
index 37a3cf9..2557280 100644
--- a/drivers/renesas/rcar/emmc/emmc_interrupt.c
+++ b/drivers/renesas/rcar/emmc/emmc_interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -26,17 +26,17 @@
uint32_t end_bit;
prr_data = mmio_read_32((uintptr_t) RCAR_PRR);
- cut_ver = prr_data & RCAR_CUT_MASK;
- if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_H3) {
- if (cut_ver == RCAR_CUT_VER10) {
+ cut_ver = prr_data & PRR_CUT_MASK;
+ if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_H3) {
+ if (cut_ver == PRR_PRODUCT_10) {
end_bit = BIT17;
- } else if (cut_ver == RCAR_CUT_VER11) {
+ } else if (cut_ver == PRR_PRODUCT_11) {
end_bit = BIT17;
} else {
end_bit = BIT20;
}
- } else if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_M3) {
- if (cut_ver == RCAR_CUT_VER10) {
+ } else if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_M3) {
+ if (cut_ver == PRR_PRODUCT_10) {
end_bit = BIT17;
} else {
end_bit = BIT20;
diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/rcar/emmc/emmc_mount.c
index dd57b0c..df8203e 100644
--- a/drivers/renesas/rcar/emmc/emmc_mount.c
+++ b/drivers/renesas/rcar/emmc/emmc_mount.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,14 +29,14 @@
{
uint32_t reg;
- reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
- if (reg == RCAR_PRODUCT_M3_CUT10) {
+ reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+ if (reg == PRR_PRODUCT_M3_CUT10) {
mmc_drv_obj.boot_partition_en =
(EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] &
EMMC_BOOT_PARTITION_EN_MASK) >>
EMMC_BOOT_PARTITION_EN_SHIFT);
- } else if ((reg == RCAR_PRODUCT_H3_CUT20)
- || (reg == RCAR_PRODUCT_M3_CUT11)) {
+ } else if ((reg == PRR_PRODUCT_H3_CUT20)
+ || (reg == PRR_PRODUCT_M3_CUT11)) {
mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access;
} else {
if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) !=
@@ -460,8 +460,8 @@
uint32_t reg;
EMMC_ERROR_CODE result;
- reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
- if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) {
+ reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+ if ((reg == PRR_PRODUCT_H3_CUT20) || (reg == PRR_PRODUCT_M3_CUT11)) {
SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */
/* CMD8 (EXT_CSD) */
emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U,
diff --git a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
index 39b9bb4..28b56c1 100644
--- a/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -189,8 +189,8 @@
mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
mmio_write_8(IIC_DVFS_REG_ICCR, mode);
- lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
- if (lsi_product == RCAR_PRODUCT_E3)
+ lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+ if (lsi_product == PRR_PRODUCT_E3)
goto start;
reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
diff --git a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
index 0aa3bff..7684c62 100644
--- a/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
+++ b/drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
@@ -615,8 +615,8 @@
uint32_t reg;
reg = mmio_read_32(RCAR_PRR);
- reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
- if (reg == (RCAR_PRODUCT_M3_CUT10)) {
+ reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+ if (reg == (PRR_PRODUCT_M3_CUT10)) {
/* Enable clock supply to RTDMAC. */
mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
@@ -654,14 +654,14 @@
uint32_t prr;
prr = mmio_read_32(RCAR_PRR);
- prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+ prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
mmio_write_32(PFC_PMMR, ~data);
- if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+ if (prr == (PRR_PRODUCT_M3_CUT10)) {
mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
}
mmio_write_32((uintptr_t)addr, data);
- if (prr == (RCAR_PRODUCT_M3_CUT10)) {
+ if (prr == (PRR_PRODUCT_M3_CUT10)) {
mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
}
}
diff --git a/drivers/renesas/rcar/pfc/pfc_init.c b/drivers/renesas/rcar/pfc/pfc_init.c
index e9455af..8810667 100644
--- a/drivers/renesas/rcar/pfc/pfc_init.c
+++ b/drivers/renesas/rcar/pfc/pfc_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -37,20 +37,6 @@
#include "D3/pfc_init_d3.h"
#endif
- /* Product Register */
-#define PRR (0xFFF00044U)
-#define PRR_PRODUCT_MASK (0x00007F00U)
-#define PRR_CUT_MASK (0x000000FFU)
-#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
-#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
-#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */
-#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
-#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
-#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */
-#define PRR_PRODUCT_10 (0x00U)
-#define PRR_PRODUCT_11 (0x01U)
-#define PRR_PRODUCT_20 (0x10U)
-
#define PRR_PRODUCT_ERR(reg) \
do { \
ERROR("LSI Product ID(PRR=0x%x) PFC initialize not supported.\n", \
@@ -71,8 +57,8 @@
reg = mmio_read_32(RCAR_PRR);
#if RCAR_LSI == RCAR_AUTO
- switch (reg & RCAR_PRODUCT_MASK) {
- case RCAR_PRODUCT_H3:
+ switch (reg & PRR_PRODUCT_MASK) {
+ case PRR_PRODUCT_H3:
switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_10: /* H3 Ver.1.0 */
pfc_init_h3_v1();
@@ -85,13 +71,13 @@
break;
}
break;
- case RCAR_PRODUCT_M3:
+ case PRR_PRODUCT_M3:
pfc_init_m3();
break;
- case RCAR_PRODUCT_M3N:
+ case PRR_PRODUCT_M3N:
pfc_init_m3n();
break;
- case RCAR_PRODUCT_V3M:
+ case PRR_PRODUCT_V3M:
pfc_init_v3m();
break;
default:
diff --git a/drivers/renesas/rcar/pfc/pfc_regs.h b/drivers/renesas/rcar/pfc/pfc_regs.h
index e7dd543..4187733 100644
--- a/drivers/renesas/rcar/pfc/pfc_regs.h
+++ b/drivers/renesas/rcar/pfc/pfc_regs.h
@@ -115,7 +115,6 @@
#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U)
#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U)
#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U)
-#define GPIO_INDT6 (GPIO_BASE + 0x540CU)
#define GPIO_INTDT6 (GPIO_BASE + 0x5410U)
#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U)
#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U)
diff --git a/drivers/renesas/rcar/pwrc/pwrc.c b/drivers/renesas/rcar/pwrc/pwrc.c
index 32e04a7..2ce6b61 100644
--- a/drivers/renesas/rcar/pwrc/pwrc.c
+++ b/drivers/renesas/rcar/pwrc/pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -314,16 +314,16 @@
rcar_lock_get();
reg = mmio_read_32(RCAR_PRR);
- product = reg & RCAR_PRODUCT_MASK;
- cut = reg & RCAR_CUT_MASK;
+ product = reg & PRR_PRODUCT_MASK;
+ cut = reg & PRR_CUT_MASK;
c = rcar_pwrc_get_mpidr_cluster(mpidr);
dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
- if (RCAR_PRODUCT_M3 == product && cut < RCAR_CUT_VER30)
+ if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
goto done;
- if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20)
+ if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
goto done;
/* all of the CPUs in the cluster is in the CoreStandby mode */
@@ -424,13 +424,13 @@
uint32_t reg = mmio_read_32(RCAR_PRR);
uint32_t cut, product;
- product = reg & RCAR_PRODUCT_MASK;
- cut = reg & RCAR_CUT_MASK;
+ product = reg & PRR_PRODUCT_MASK;
+ cut = reg & PRR_CUT_MASK;
- if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
goto self_refresh;
- if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+ if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
goto self_refresh;
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
@@ -445,16 +445,16 @@
/* Set the Self-Refresh mode */
mmio_write_32(DBSC4_REG_DBACEN, 0);
- if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+ if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
rcar_micro_delay(100);
- else if (product == RCAR_PRODUCT_H3) {
+ else if (product == PRR_PRODUCT_H3) {
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
DBCAM_FLUSH(0);
DBCAM_FLUSH(1);
DBCAM_FLUSH(2);
DBCAM_FLUSH(3);
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
- } else if (product == RCAR_PRODUCT_M3) {
+ } else if (product == PRR_PRODUCT_M3) {
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
DBCAM_FLUSH(0);
DBCAM_FLUSH(1);
@@ -499,10 +499,10 @@
mmio_write_32(DBSC4_REG_DBRFEN, 0U);
rcar_micro_delay(1U);
- if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
+ if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
return;
- if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
+ if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
return;
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
@@ -648,9 +648,9 @@
uint32_t reg, product;
reg = mmio_read_32(RCAR_PRR);
- product = reg & RCAR_PRODUCT_MASK;
+ product = reg & PRR_PRODUCT_MASK;
- if (product != RCAR_PRODUCT_E3)
+ if (product != PRR_PRODUCT_E3)
rcar_pwrc_set_self_refresh();
else
rcar_pwrc_set_self_refresh_e3();
diff --git a/drivers/renesas/rcar/qos/qos_init.c b/drivers/renesas/rcar/qos/qos_init.c
index 884e031..d0f1730 100644
--- a/drivers/renesas/rcar/qos/qos_init.c
+++ b/drivers/renesas/rcar/qos/qos_init.c
@@ -12,6 +12,7 @@
#include "qos_init.h"
#include "qos_common.h"
#include "qos_reg.h"
+#include "rcar_def.h"
#if RCAR_LSI == RCAR_AUTO
#include "H3/qos_init_h3_v10.h"
#include "H3/qos_init_h3_v11.h"
@@ -50,22 +51,6 @@
#include "D3/qos_init_d3.h"
#endif
- /* Product Register */
-#define PRR 0xFFF00044U
-#define PRR_PRODUCT_MASK 0x00007F00U
-#define PRR_CUT_MASK 0x000000FFU
-#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */
-#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3 */
-#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */
-#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3N */
-#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */
-#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */
-#define PRR_PRODUCT_10 0x00U
-#define PRR_PRODUCT_11 0x01U
-#define PRR_PRODUCT_20 0x10U
-#define PRR_PRODUCT_21 0x11U
-#define PRR_PRODUCT_30 0x20U
-
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RCAR_V3M)
#define DRAM_CH_CNT 0x04
diff --git a/drivers/renesas/rcar/rom/rom_api.c b/drivers/renesas/rcar/rom/rom_api.c
index c9f8f5f..fda2815 100644
--- a/drivers/renesas/rcar/rom/rom_api.c
+++ b/drivers/renesas/rcar/rom/rom_api.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,30 +30,30 @@
uint32_t cut_ver;
uint32_t index;
- product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
- cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+ product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+ cut_ver = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
switch (product) {
- case RCAR_PRODUCT_H3:
- if (cut_ver == RCAR_CUT_VER10)
+ case PRR_PRODUCT_H3:
+ if (cut_ver == PRR_PRODUCT_10)
index = OLD_API_TABLE1;
- else if (cut_ver == RCAR_CUT_VER11)
+ else if (cut_ver == PRR_PRODUCT_11)
index = OLD_API_TABLE1;
- else if (cut_ver == RCAR_CUT_VER20)
+ else if (cut_ver == PRR_PRODUCT_20)
index = OLD_API_TABLE2;
else
/* Later than H3 Ver.2.0 */
index = NEW_API_TABLE;
break;
- case RCAR_PRODUCT_M3:
- if (cut_ver == RCAR_CUT_VER10)
+ case PRR_PRODUCT_M3:
+ if (cut_ver == PRR_PRODUCT_10)
index = OLD_API_TABLE3;
else
/* M3 Ver.1.1 or later */
index = NEW_API_TABLE;
break;
- case RCAR_PRODUCT_V3M:
- if (cut_ver == RCAR_CUT_VER10)
+ case PRR_PRODUCT_V3M:
+ if (cut_ver == PRR_PRODUCT_10)
/* V3M WS1.0 */
index = NEW_API_TABLE2;
else
diff --git a/drivers/renesas/rcar/rpc/rpc_driver.c b/drivers/renesas/rcar/rpc/rpc_driver.c
index 5c11b62..63de5b8 100644
--- a/drivers/renesas/rcar/rpc/rpc_driver.c
+++ b/drivers/renesas/rcar/rpc/rpc_driver.c
@@ -34,10 +34,10 @@
if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
- product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
- cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+ product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
+ cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
- if ((product == RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30))
+ if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
else
phy_strtim = RPC_PHYCNT_STRTIM;
diff --git a/drivers/renesas/rcar/watchdog/swdt.c b/drivers/renesas/rcar/watchdog/swdt.c
index 8b2943c..111e651 100644
--- a/drivers/renesas/rcar/watchdog/swdt.c
+++ b/drivers/renesas/rcar/watchdog/swdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,7 +82,7 @@
uint32_t reg, val, product_cut, chk_data;
reg = mmio_read_32(RCAR_PRR);
- product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+ product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
reg = mmio_read_32(RCAR_MODEMR);
chk_data = reg & CHECK_MD13_MD14;
@@ -108,7 +108,7 @@
val |= WTCNT_COUNT_8p22k;
break;
case MD14_MD13_TYPE_3:
- val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ?
+ val |= product_cut == (PRR_PRODUCT_H3 | PRR_PRODUCT_10) ?
WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
break;
default:
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 89d666c..2cce653 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -20,6 +20,7 @@
#include "boot_init_dram.h"
#include "dram_sub_func.h"
#include "micro_delay.h"
+#include "rcar_def.h"
#define DDR_BACKUPMODE
#define FATAL_MSG(x) NOTICE(x)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index 5d1b078..aaa5f00 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -1622,7 +1622,6 @@
#define PFC_PUD5 0xE6060454U
#define PFC_PUD6 0xE6060458U
#define GPIO_INDT5 0xE605500CU
-#define GPIO_INDT6 0xE605540CU
#define GPIO_GPSR6 0xE6060118U
#if (RCAR_GEN3_ULCB == 0)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
index a1cbfbf..abddf0c 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
@@ -55,19 +55,6 @@
#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
-/* Product Register */
-#define PRR (0xFFF00044U)
-#define PRR_PRODUCT_MASK (0x00007F00U)
-#define PRR_CUT_MASK (0x000000FFU)
-#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
-#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3-W */
-#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3-N */
-#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
-#define PRR_PRODUCT_10 (0x00U) /* Ver.1.0 */
-#define PRR_PRODUCT_11 (0x01U) /* Ver.1.1 */
-#define PRR_PRODUCT_20 (0x10U) /* Ver.2.0 */
-#define PRR_PRODUCT_30 (0x20U) /* Ver.3.0 */
-
/* DBSC registers */
#define DBSC_DBSYSCONF1 0xE6790004U
#define DBSC_DBPHYCONF0 0xE6790010U
diff --git a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
index 6739b0d..c6ab44a 100644
--- a/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
+++ b/drivers/staging/renesas/rcar/ddr/dram_sub_func.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,15 +8,7 @@
#include <lib/mmio.h>
#include "dram_sub_func.h"
-
-#define PRR (0xFFF00044U)
-#define PRR_PRODUCT_MASK (0x00007F00U)
-#define PRR_CUT_MASK (0x000000FFU)
-#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
-#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
-#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
-#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
-#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
+#include "rcar_def.h"
#if RCAR_SYSTEM_SUSPEND
/* Local defines */
@@ -32,11 +24,9 @@
#endif
#define GPIO_OUTDT1 (0xE6051008U)
-#define GPIO_INDT1 (0xE605100CU)
#define GPIO_OUTDT3 (0xE6053008U)
#define GPIO_INDT3 (0xE605300CU)
#define GPIO_OUTDT6 (0xE6055408U)
-#define GPIO_INDT6 (0xE605540CU)
#if DRAM_BACKUP_GPIO_USE == 1
#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index fa857fb..2b4ae1a 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -112,6 +112,7 @@
/* CLIDR definitions */
#define LOUIS_SHIFT U(21)
#define LOC_SHIFT U(24)
+#define CTYPE_SHIFT(n) U(3 * (n - 1))
#define CLIDR_FIELD_WIDTH U(3)
/* CSSELR definitions */
diff --git a/include/drivers/console.h b/include/drivers/console.h
index cada771..a4859d8 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,7 +21,8 @@
#define CONSOLE_FLAG_CRASH (U(1) << 2)
/* Bits 3 to 7 reserved for additional scopes in future expansion. */
#define CONSOLE_FLAG_SCOPE_MASK ((U(1) << 8) - 1)
-/* Bits 8 to 31 reserved for non-scope use in future expansion. */
+/* Bits 8 to 31 for non-scope use. */
+#define CONSOLE_FLAG_TRANSLATE_CRLF (U(1) << 8)
/* Returned by getc callbacks when receive FIFO is empty. */
#define ERROR_NO_PENDING_CHAR (-1)
diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S
index 0bd0daf..d47e4e0 100644
--- a/include/plat/arm/common/aarch64/arm_macros.S
+++ b/include/plat/arm/common/aarch64/arm_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,11 +22,13 @@
/* Registers common to both GICv2 and GICv3 */
gicd_pend_reg:
- .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+ .asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n"
newline:
.asciz "\n"
spacer:
- .asciz ":\t\t0x"
+ .asciz ":\t\t 0x"
+prefix:
+ .asciz "0x"
/* ---------------------------------------------
* The below utility macro prints out relevant GIC
@@ -77,7 +79,15 @@
sub x4, x7, x16
cmp x4, #0x280
b.eq exit_print_gic_regs
- bl asm_print_hex
+
+ /* Print "0x" */
+ adr x4, prefix
+ bl asm_print_str
+
+ /* Print offset */
+ sub x4, x7, x16
+ mov x5, #12
+ bl asm_print_hex_bits
adr x4, spacer
bl asm_print_str
diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c
index 0b36cb6..ea8e2bb 100644
--- a/lib/aarch32/arm32_aeabi_divmod.c
+++ b/lib/aarch32/arm32_aeabi_divmod.c
@@ -33,13 +33,11 @@
unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator);
unsigned int __aeabi_uidiv(unsigned int numerator, unsigned int denominator);
-unsigned int __aeabi_uimod(unsigned int numerator, unsigned int denominator);
/* returns in R0 and R1 by tail calling an asm function */
signed int __aeabi_idivmod(signed int numerator, signed int denominator);
signed int __aeabi_idiv(signed int numerator, signed int denominator);
-signed int __aeabi_imod(signed int numerator, signed int denominator);
/*
* __ste_idivmod_ret_t __aeabi_idivmod(signed numerator, signed denominator)
@@ -106,15 +104,6 @@
return qr.q;
}
-unsigned int __aeabi_uimod(unsigned int numerator, unsigned int denominator)
-{
- struct qr qr = { .q_n = 0, .r_n = 0 };
-
- uint_div_qr(numerator, denominator, &qr);
-
- return qr.r;
-}
-
unsigned int __aeabi_uidivmod(unsigned int numerator, unsigned int denominator)
{
struct qr qr = { .q_n = 0, .r_n = 0 };
@@ -145,42 +134,6 @@
return qr.q;
}
-signed int __aeabi_imod(signed int numerator, signed int denominator)
-{
- signed int s;
- signed int i;
- signed int j;
- signed int h;
- struct qr qr = { .q_n = 0, .r_n = 0 };
-
- /* in case modulo of a power of 2 */
- for (i = 0, j = 0, h = 0, s = denominator; (s != 0) || (h > 1); i++) {
- if (s & 1) {
- j = i;
- h++;
- }
- s = s >> 1;
- }
- if (h == 1)
- return numerator >> j;
-
- if (((numerator < 0) && (denominator > 0)) ||
- ((numerator > 0) && (denominator < 0)))
- qr.q_n = 1; /* quotient shall be negate */
-
- if (numerator < 0) {
- numerator = -numerator;
- qr.r_n = 1; /* remainder shall be negate */
- }
-
- if (denominator < 0)
- denominator = -denominator;
-
- uint_div_qr(numerator, denominator, &qr);
-
- return qr.r;
-}
-
signed int __aeabi_idivmod(signed int numerator, signed int denominator)
{
struct qr qr = { .q_n = 0, .r_n = 0 };
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S
index 51b5ce9..6291e43 100644
--- a/lib/cpus/aarch64/aem_generic.S
+++ b/lib/cpus/aarch64/aem_generic.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,15 +18,43 @@
msr sctlr_el3, x1
isb
+ /* ---------------------------------------------
+ * AEM model supports L3 caches in which case L2
+ * will be private per core caches and flush
+ * from L1 to L2 is not sufficient.
+ * ---------------------------------------------
+ */
+ mrs x1, clidr_el1
+
+ /* ---------------------------------------------
+ * Check if L3 cache is implemented.
+ * ---------------------------------------------
+ */
+ tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3)
+
+ /* ---------------------------------------------
+ * There is no L3 cache, flush L1 to L2 only.
+ * ---------------------------------------------
+ */
mov x0, #DCCISW
+ b.eq dcsw_op_level1
+
+ mov x18, x30
/* ---------------------------------------------
- * Flush L1 cache to PoU.
+ * Flush L1 cache to L2.
* ---------------------------------------------
*/
- b dcsw_op_louis
-endfunc aem_generic_core_pwr_dwn
+ bl dcsw_op_level1
+ mov x30, x18
+ /* ---------------------------------------------
+ * Flush L2 cache to L3.
+ * ---------------------------------------------
+ */
+ mov x0, #DCCISW
+ b dcsw_op_level2
+endfunc aem_generic_core_pwr_dwn
func aem_generic_cluster_pwr_dwn
/* ---------------------------------------------
@@ -39,7 +67,7 @@
isb
/* ---------------------------------------------
- * Flush L1 and L2 caches to PoC.
+ * Flush all caches to PoC.
* ---------------------------------------------
*/
mov x0, #DCCISW
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index b143a2e..31e7a3a 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -43,6 +43,7 @@
msr CPUPMR_EL3, x0
ldr x0, =0x800200071
msr CPUPCR_EL3, x0
+ isb
1:
ret x17
endfunc errata_n1_1043202_wa
diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c
index be8bece..64a4852 100644
--- a/lib/extensions/ras/ras_common.c
+++ b/lib/extensions/ras/ras_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -83,7 +83,8 @@
{
struct ras_interrupt *ras_inrs = ras_interrupt_mappings.intrs;
struct ras_interrupt *selected = NULL;
- int start, end, mid, probe_data, ret __unused;
+ int probe_data = 0;
+ int start, end, mid, ret __unused;
const struct err_handler_data err_data = {
.version = ERR_HANDLER_VERSION,
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 5d24356..022c877 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -198,21 +198,17 @@
/******************************************************************************
* Helper function to update the requested local power state array. This array
* does not store the requested state for the CPU power level. Hence an
- * assertion is added to prevent us from accessing the wrong index.
+ * assertion is added to prevent us from accessing the CPU power level.
*****************************************************************************/
static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
unsigned int cpu_idx,
plat_local_state_t req_pwr_state)
{
- /*
- * This should never happen, we have this here to avoid
- * "array subscript is above array bounds" errors in GCC.
- */
assert(pwrlvl > PSCI_CPU_PWR_LVL);
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Warray-bounds"
- psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
-#pragma GCC diagnostic pop
+ if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
+ (cpu_idx < PLATFORM_CORE_COUNT)) {
+ psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
+ }
}
/******************************************************************************
@@ -245,7 +241,11 @@
{
assert(pwrlvl > PSCI_CPU_PWR_LVL);
- return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
+ if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
+ (cpu_idx < PLATFORM_CORE_COUNT)) {
+ return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
+ } else
+ return NULL;
}
/*
diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c
index e31f9d8..bd6b152 100644
--- a/lib/xlat_tables/aarch32/nonlpae_tables.c
+++ b/lib/xlat_tables/aarch32/nonlpae_tables.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016-2017, Linaro Limited. All rights reserved.
- * Copyright (c) 2014-2017, Arm Limited. All rights reserved.
+ * Copyright (c) 2014-2019, Arm Limited. All rights reserved.
* Copyright (c) 2014, STMicroelectronics International N.V.
* All rights reserved.
*
@@ -445,7 +445,8 @@
} else {
xlat_table = (unsigned long)mmu_l2_base +
next_xlat * MMU32B_L2_TABLE_SIZE;
- assert(++next_xlat <= MAX_XLAT_TABLES);
+ next_xlat++;
+ assert(next_xlat <= MAX_XLAT_TABLES);
memset((char *)xlat_table, 0,
MMU32B_L2_TABLE_SIZE);
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c
index b90ddcd..8f6170d 100644
--- a/plat/arm/board/fvp/fvp_bl1_setup.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -48,6 +48,9 @@
{
arm_bl1_platform_setup();
+ /* Initialize System level generic or SP804 timer */
+ fvp_timer_init();
+
/* On FVP RevC, initialize SMMUv3 */
if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
smmuv3_security_init(PLAT_FVP_SMMUV3_BASE);
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index d280949..89636d1 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,15 +25,6 @@
{
arm_bl2_platform_setup();
-#if FVP_USE_SP804_TIMER
- /* Enable the clock override for SP804 timer 0, which means that no
- * clock dividers are applied and the raw (35 MHz) clock will be used */
- mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
-
- /* Initialize delay timer driver using SP804 dual timer 0 */
- sp804_timer_init(V2M_SP804_TIMER0_BASE,
- SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
-#else
- generic_delay_timer_init();
-#endif /* FVP_USE_SP804_TIMER */
+ /* Initialize System level generic or SP804 timer */
+ fvp_timer_init();
}
diff --git a/plat/arm/board/fvp/fvp_bl2u_setup.c b/plat/arm/board/fvp/fvp_bl2u_setup.c
index a8db055..fd73767 100644
--- a/plat/arm/board/fvp/fvp_bl2u_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2u_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,9 @@
{
arm_bl2u_early_platform_setup(mem_layout, plat_info);
+ /* Initialize System level generic or SP804 timer */
+ fvp_timer_init();
+
/* Initialize the platform config for future decision making */
fvp_config_setup();
}
diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index 3f92d37..8627c5e 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,6 +34,9 @@
*/
fvp_interconnect_enable();
+ /* Initialize System level generic or SP804 timer */
+ fvp_timer_init();
+
/* On FVP RevC, initialize SMMUv3 */
if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
smmuv3_init(PLAT_FVP_SMMUV3_BASE);
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 36cd500..a948796 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -10,6 +10,8 @@
#include <drivers/arm/cci.h>
#include <drivers/arm/ccn.h>
#include <drivers/arm/gicv2.h>
+#include <drivers/arm/sp804_delay_timer.h>
+#include <drivers/generic_delay_timer.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/arm/common/arm_config.h>
@@ -407,3 +409,23 @@
return arm_get_mbedtls_heap(heap_addr, heap_size);
}
#endif
+
+void fvp_timer_init(void)
+{
+#if FVP_USE_SP804_TIMER
+ /* Enable the clock override for SP804 timer 0, which means that no
+ * clock dividers are applied and the raw (35MHz) clock will be used.
+ */
+ mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
+
+ /* Initialize delay timer driver using SP804 dual timer 0 */
+ sp804_timer_init(V2M_SP804_TIMER0_BASE,
+ SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
+#else
+ generic_delay_timer_init();
+
+ /* Enable System level generic timer */
+ mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
+ CNTCR_FCREQ(0U) | CNTCR_EN);
+#endif /* FVP_USE_SP804_TIMER */
+}
diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h
index 5067d3a..3590370 100644
--- a/plat/arm/board/fvp/fvp_private.h
+++ b/plat/arm/board/fvp/fvp_private.h
@@ -18,6 +18,7 @@
void fvp_interconnect_init(void);
void fvp_interconnect_enable(void);
void fvp_interconnect_disable(void);
+void fvp_timer_init(void);
void tsp_early_platform_setup(void);
#endif /* FVP_PRIVATE_H */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 0eb62c4..617da2d 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -127,6 +127,7 @@
BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
drivers/arm/sp805/sp805.c \
+ drivers/delay_timer/delay_timer.c \
drivers/io/io_semihosting.c \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
@@ -138,6 +139,12 @@
${FVP_CPU_LIBS} \
${FVP_INTERCONNECT_SOURCES}
+ifeq (${FVP_USE_SP804_TIMER},1)
+BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
+else
+BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c
+endif
+
BL2_SOURCES += drivers/arm/sp805/sp805.c \
drivers/io/io_semihosting.c \
@@ -167,8 +174,13 @@
BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
${FVP_SECURITY_SOURCES}
+ifeq (${FVP_USE_SP804_TIMER},1)
+BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
+endif
+
BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \
drivers/arm/smmu/smmu_v3.c \
+ drivers/delay_timer/delay_timer.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/board/fvp/fvp_bl31_setup.c \
@@ -181,6 +193,12 @@
${FVP_INTERCONNECT_SOURCES} \
${FVP_SECURITY_SOURCES}
+ifeq (${FVP_USE_SP804_TIMER},1)
+BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
+else
+BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c
+endif
+
# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
ifdef UNIX_MK
FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts
diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
new file mode 100644
index 0000000..a8ab6c5
--- /dev/null
+++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ /* Platform Config */
+ compatible = "arm,tb_fw";
+ /* Disable authentication for development */
+ disable_auth = <0x0>;
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
+};
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index 98c5d3c..9570d2d 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,6 +47,9 @@
ARM_MAP_OPTEE_CORE_MEM,
ARM_OPTEE_PAGEABLE_LOAD_MEM,
#endif
+#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
+ ARM_MAP_BL1_RW,
+#endif
{0}
};
#endif
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
index 6566b15..32823e0 100644
--- a/plat/arm/board/juno/juno_security.c
+++ b/plat/arm/board/juno/juno_security.c
@@ -3,6 +3,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
#include <common/debug.h>
#include <drivers/arm/nic_400.h>
@@ -149,6 +150,9 @@
#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
- return get_mbedtls_heap_helper(heap_addr, heap_size);
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
}
#endif
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index ea7f851..bd6bae5 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -150,8 +150,14 @@
endif
endif
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts
+TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
+
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
include plat/arm/soc/common/soc_css.mk
include plat/arm/css/common/css_common.mk
-
diff --git a/plat/common/aarch64/crash_console_helpers.S b/plat/common/aarch64/crash_console_helpers.S
index 2a48baf..e2950f5 100644
--- a/plat/common/aarch64/crash_console_helpers.S
+++ b/plat/common/aarch64/crash_console_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -125,9 +125,18 @@
b.eq putc_continue
ldr x2, [x15, #CONSOLE_T_PUTC]
cbz x2, putc_continue
+ cmp w14, #'\n'
+ b.ne putc
+ tst w1, #CONSOLE_FLAG_TRANSLATE_CRLF
+ b.eq putc
mov x1, x15
+ mov w0, #'\r'
blr x2
+ ldr x2, [x15, #CONSOLE_T_PUTC]
+putc:
+ mov x1, x15
mov w0, w14
+ blr x2
putc_continue:
ldr x15, [x15] /* X15 = next struct */
b putc_loop
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 385065f..e9ab928 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -69,9 +69,9 @@
deassert_peripheral_reset();
config_hps_hs_before_warm_reset();
- watchdog_init(get_wdt_clk(&reverse_handoff_ptr));
+ watchdog_init(get_wdt_clk());
- console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
+ console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE,
&console);
socfpga_delay_timer_init();
@@ -105,7 +105,7 @@
enable_mmu_el3(0);
- dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000);
+ dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
info.mmc_dev_type = MMC_IS_SD;
info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h
index c1a7546..73e6c4e 100644
--- a/plat/intel/soc/agilex/include/agilex_clock_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h
@@ -80,41 +80,38 @@
#define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16)
#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004
#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008
+#define CLKMGR_INTOSC_HZ 460000000
/* Main PLL Macros */
#define CLKMGR_MAINPLL_EN_RESET 0x000000ff
-#define CLKMGR_MAINPLL_PLLM_MDIV(x) ((x) & 0x000003ff)
-#define CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK 0x00000001
-#define CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK 0x00000002
-
-#define CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
-#define CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8)
-#define CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
-
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC(x) (((x) & 0x00030000) >> 16)
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1 0x0
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC 0x1
-#define CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S 0x2
-#define CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
-#define CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
/* Peripheral PLL Macros */
#define CLKMGR_PERPLL_EN_RESET 0x00000fff
-#define CLKMGR_PERPLL_PLLM_MDIV(x) ((x) & 0x000003ff)
#define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff)
-#define CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK 0x00000001
-
-#define CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
-#define CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8)
-#define CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
-
-#define CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK 0x00000002
-#define CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
-#define CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
/* Altera Macros */
#define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff
+/* Shared Macros */
+#define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16)
+#define CLKMGR_PSRC_MAIN 0
+#define CLKMGR_PSRC_PER 1
+
+#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0
+#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1
+#define CLKMGR_PLLGLOB_PSRC_F2S 0x2
+
+#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff)
+#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001
+#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002
+
+#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8)
+#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8)
+#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
+
+#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff)
+#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000)
+
typedef struct {
uint32_t clk_freq_of_eosc1;
@@ -123,6 +120,8 @@
} CLOCK_SOURCE_CONFIG;
void config_clkmgr_handoff(handoff *hoff_ptr);
-int get_wdt_clk(handoff *hoff_ptr);
+uint32_t get_wdt_clk(void);
+uint32_t get_uart_clk(void);
+uint32_t get_mmc_clk(void);
#endif
diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h
index c0c94e6..419bd2e 100644
--- a/plat/intel/soc/agilex/include/agilex_memory_controller.h
+++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h
@@ -10,6 +10,8 @@
#define AGX_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8
#define AGX_MPFE_IOHMC_CTRLCFG0 0xf8010028
#define AGX_MPFE_IOHMC_CTRLCFG1 0xf801002c
+#define AGX_MPFE_IOHMC_CTRLCFG2 0xf8010030
+#define AGX_MPFE_IOHMC_CTRLCFG3 0xf8010034
#define AGX_MPFE_IOHMC_DRAMADDRW 0xf80100a8
#define AGX_MPFE_IOHMC_DRAMTIMING0 0xf8010050
#define AGX_MPFE_IOHMC_CALTIMING0 0xf801007c
@@ -127,6 +129,7 @@
#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020298
#define AGX_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020200
+#define AGX_SOC_NOC_FW_DDR_SCR_ENABLESET 0xf8020204
#define AGX_CCU_NOC_DI_SET_MSK 0x10
#define AGX_SYSMGR_CORE_HMC_CLK 0xffd120b4
@@ -156,6 +159,7 @@
#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x003e0) >> 5)
#define AGX_SDRAM_0_LB_ADDR 0x0
+#define AGX_DDR_SIZE 0x40000000
int init_hard_memory_controller(void);
diff --git a/plat/intel/soc/agilex/include/agilex_private.h b/plat/intel/soc/agilex/include/agilex_private.h
index 5ccbc8c..fc0e9fd 100644
--- a/plat/intel/soc/agilex/include/agilex_private.h
+++ b/plat/intel/soc/agilex/include/agilex_private.h
@@ -11,14 +11,13 @@
#define AGX_MMC_REG_BASE 0xff808000
#define EMMC_DESC_SIZE (1<<20)
-#define EMMC_INIT_PARAMS(base) \
+#define EMMC_INIT_PARAMS(base, clk) \
{ .bus_width = MMC_BUS_WIDTH_4, \
- .clk_rate = 50000000, \
+ .clk_rate = (clk), \
.desc_base = (base), \
.desc_size = EMMC_DESC_SIZE, \
.flags = 0, \
- .reg_base = AGX_MMC_REG_BASE, \
- \
+ .reg_base = AGX_MMC_REG_BASE \
}
typedef enum {
@@ -26,7 +25,7 @@
BOOT_SOURCE_SDMMC,
BOOT_SOURCE_NAND,
BOOT_SOURCE_RSVD,
- BOOT_SOURCE_QSPI,
+ BOOT_SOURCE_QSPI
} boot_source_type;
void enable_nonsecure_access(void);
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
index 6ec2084..381c2d3 100644
--- a/plat/intel/soc/agilex/include/agilex_system_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -65,6 +65,11 @@
#define AGX_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
#define AGX_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
+#define AGX_SYSMGR_CORE(x) (0xffd12000 + (x))
+#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
+#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
+#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
+
#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 6e7b43e..218676a 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -12,15 +12,8 @@
#include "agilex_clock_manager.h"
#include "agilex_handoff.h"
+#include "agilex_system_manager.h"
-static const CLOCK_SOURCE_CONFIG clk_source = {
- /* clk_freq_of_eosc1 */
- (uint32_t) 25000000,
- /* clk_freq_of_f2h_free */
- (uint32_t) 400000000,
- /* clk_freq_of_cb_intosc_ls */
- (uint32_t) 50000000,
-};
uint32_t wait_pll_lock(void)
{
@@ -114,18 +107,18 @@
/* Put both PLL in reset and power down */
mmio_clrbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
- CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
- CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
+ CLKMGR_PLLGLOB_PD_SET_MSK |
+ CLKMGR_PLLGLOB_RST_SET_MSK);
mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
- CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
- CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
+ CLKMGR_PLLGLOB_PD_SET_MSK |
+ CLKMGR_PLLGLOB_RST_SET_MSK);
/* Setup main PLL dividers */
- mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
+ mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->main_pll_pllm);
- arefclk_div = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(
+ arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
hoff_ptr->main_pll_pllglob);
- drefclk_div = CLKMGR_MAINPLL_PLLGLOB_DREFCLKDIV(
+ drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
hoff_ptr->main_pll_pllglob);
mscnt = 100 / (mdiv / BIT(drefclk_div));
@@ -134,8 +127,8 @@
hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB,
- CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(hscnt) |
- CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(mscnt));
+ CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
+ CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV,
hoff_ptr->main_pll_nocdiv);
@@ -159,11 +152,11 @@
hoff_ptr->main_pll_nocclk);
/* Setup peripheral PLL dividers */
- mdiv = CLKMGR_PERPLL_PLLM_MDIV(hoff_ptr->per_pll_pllm);
+ mdiv = CLKMGR_PLLM_MDIV(hoff_ptr->per_pll_pllm);
- arefclk_div = CLKMGR_PERPLL_PLLGLOB_AREFCLKDIV(
+ arefclk_div = CLKMGR_PLLGLOB_AREFCLKDIV(
hoff_ptr->per_pll_pllglob);
- drefclk_div = CLKMGR_PERPLL_PLLGLOB_DREFCLKDIV(
+ drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV(
hoff_ptr->per_pll_pllglob);
mscnt = 100 / (mdiv / BIT(drefclk_div));
@@ -172,8 +165,8 @@
hscnt = (mdiv * mscnt * BIT(drefclk_div) / arefclk_div) - 4;
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_VCOCALIB,
- CLKMGR_PERPLL_VCOCALIB_HSCNT_SET(hscnt) |
- CLKMGR_PERPLL_VCOCALIB_MSCNT_SET(mscnt));
+ CLKMGR_VCOCALIB_HSCNT_SET(hscnt) |
+ CLKMGR_VCOCALIB_MSCNT_SET(mscnt));
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EMACCTL,
hoff_ptr->per_pll_emacctl);
@@ -197,11 +190,11 @@
/* Take both PLL out of reset and power up */
mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB,
- CLKMGR_MAINPLL_PLLGLOB_PD_SET_MSK |
- CLKMGR_MAINPLL_PLLGLOB_RST_SET_MSK);
+ CLKMGR_PLLGLOB_PD_SET_MSK |
+ CLKMGR_PLLGLOB_RST_SET_MSK);
mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB,
- CLKMGR_PERPLL_PLLGLOB_PD_SET_MSK |
- CLKMGR_PERPLL_PLLGLOB_RST_SET_MSK);
+ CLKMGR_PLLGLOB_PD_SET_MSK |
+ CLKMGR_PLLGLOB_RST_SET_MSK);
wait_pll_lock();
@@ -256,38 +249,123 @@
CLKMGR_MAINPLL_EN_RESET);
mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN,
CLKMGR_PERPLL_EN_RESET);
+
+ /* Pass clock source frequency into scratch register */
+ mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+ hoff_ptr->hps_osc_clk_h);
+ mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+ hoff_ptr->fpga_clk_hz);
}
-int get_wdt_clk(handoff *hoff_ptr)
+/* Extract reference clock from platform clock source */
+uint32_t get_ref_clk(uint32_t pllglob)
{
- int main_noc_base_clk, l3_main_free_clk, l4_sys_free_clk;
- int data32, mdiv, arefclkdiv, ref_clk;
+ uint32_t arefclkdiv, ref_clk;
+ uint32_t scr_reg;
- data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB);
-
- switch (CLKMGR_MAINPLL_PLLGLOB_PSRC(data32)) {
- case CLKMGR_MAINPLL_PLLGLOB_PSRC_EOSC1:
- ref_clk = clk_source.clk_freq_of_eosc1;
+ switch (CLKMGR_PSRC(pllglob)) {
+ case CLKMGR_PLLGLOB_PSRC_EOSC1:
+ scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+ ref_clk = mmio_read_32(scr_reg);
break;
- case CLKMGR_MAINPLL_PLLGLOB_PSRC_INTOSC:
- ref_clk = clk_source.clk_freq_of_cb_intosc_ls;
+ case CLKMGR_PLLGLOB_PSRC_INTOSC:
+ ref_clk = CLKMGR_INTOSC_HZ;
break;
- case CLKMGR_MAINPLL_PLLGLOB_PSRC_F2S:
- ref_clk = clk_source.clk_freq_of_f2h_free;
+ case CLKMGR_PLLGLOB_PSRC_F2S:
+ scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+ ref_clk = mmio_read_32(scr_reg);
break;
default:
ref_clk = 0;
assert(0);
break;
+ }
+
+ arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob);
+ ref_clk /= arefclkdiv;
+
+ return ref_clk;
+}
+
+/* Calculate clock frequency based on parameter */
+uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc)
+{
+ uint32_t clk_psrc, mdiv, ref_clk;
+ uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg;
+
+ clk_psrc = mmio_read_32(CLKMGR_MAINPLL + psrc_reg);
+
+ switch (CLKMGR_PSRC(clk_psrc)) {
+ case CLKMGR_PSRC_MAIN:
+ pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM;
+ pllc_reg = CLKMGR_MAINPLL + main_pllc;
+ pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB;
+ break;
+ case CLKMGR_PSRC_PER:
+ pllm_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM;
+ pllc_reg = CLKMGR_PERPLL + per_pllc;
+ pllglob_reg = CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB;
+ break;
+ default:
+ return 0;
}
+ ref_clk = get_ref_clk(mmio_read_32(pllglob_reg));
+ mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg));
+ ref_clk *= mdiv;
+
+ pllc_div = mmio_read_32(pllc_reg) & 0x7ff;
+
+ return ref_clk / pllc_div;
+}
+
+/* Return L3 interconnect clock */
+uint32_t get_l3_clk(void)
+{
+ uint32_t l3_clk;
+
+ l3_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1,
+ CLKMGR_PERPLL_PLLC1);
+ return l3_clk;
+}
+
+/* Calculate clock frequency to be used for watchdog timer */
+uint32_t get_wdt_clk(void)
+{
+ uint32_t l3_clk, l4_sys_clk;
+
+ l3_clk = get_l3_clk();
+ l4_sys_clk = l3_clk / 4;
+
+ return l4_sys_clk;
+}
+
+/* Calculate clock frequency to be used for UART driver */
+uint32_t get_uart_clk(void)
+{
+ uint32_t data32, l3_clk, l4_sp_clk;
+
+ l3_clk = get_l3_clk();
+
+ data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV);
+ data32 = (data32 >> 16) & 0x3;
+
+ l4_sp_clk = l3_clk >> data32;
+
+ return l4_sp_clk;
+}
+
+/* Calculate clock frequency to be used for SDMMC driver */
+uint32_t get_mmc_clk(void)
+{
+ uint32_t data32, mmc_clk;
+
- arefclkdiv = CLKMGR_MAINPLL_PLLGLOB_AREFCLKDIV(data32);
- mdiv = CLKMGR_MAINPLL_PLLM_MDIV(hoff_ptr->main_pll_pllm);
+ mmc_clk = get_clk_freq(CLKMGR_ALTERA_SDMMCCTR,
+ CLKMGR_MAINPLL_PLLC3, CLKMGR_PERPLL_PLLC3);
- ref_clk = (ref_clk / arefclkdiv) * mdiv;
- main_noc_base_clk = ref_clk / (hoff_ptr->main_pll_pllc1 & 0x7ff);
- l3_main_free_clk = main_noc_base_clk / (hoff_ptr->main_pll_nocclk + 1);
- l4_sys_free_clk = l3_main_free_clk / 4;
+ data32 = mmio_read_32(CLKMGR_ALTERA + CLKMGR_ALTERA_SDMMCCTR);
+ data32 = (data32 & 0x7ff) + 1;
+ mmc_clk = (mmc_clk / data32) / 4;
- return l4_sys_free_clk;
+ return mmc_clk;
}
diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
index 9fc3e0a..5f3cae7 100644
--- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c
+++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c
@@ -19,7 +19,7 @@
#define MAX_MEM_CAL_RETRY 3
#define PRE_CALIBRATION_DELAY 1
#define POST_CALIBRATION_DELAY 1
-#define TIMEOUT_EMIF_CALIBRATION 100
+#define TIMEOUT_EMIF_CALIBRATION 1000
#define CLEAR_EMIF_DELAY 50000
#define CLEAR_EMIF_TIMEOUT 0x100000
#define TIMEOUT_INT_RESP 10000
@@ -109,7 +109,7 @@
static int mem_calibration(void)
{
- int status = 0;
+ int status;
uint32_t data;
unsigned long timeout;
unsigned long retry = 0;
@@ -125,13 +125,13 @@
data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT);
if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1)
break;
- udelay(1);
+ mdelay(1);
} while (++timeout < TIMEOUT_EMIF_CALIBRATION);
if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) {
status = clear_emif();
- if (status)
- ERROR("Failed to clear Emif\n");
+ if (status)
+ ERROR("Failed to clear Emif\n");
} else {
break;
}
@@ -160,8 +160,6 @@
return status;
}
-/* mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, AGX_RSTMGR_BRGMODRST_DDRSCH);*/
-
status = mem_calibration();
if (status) {
ERROR("DDR: Memory Calibration Failed\n");
@@ -169,7 +167,6 @@
}
configure_hmc_adaptor_regs();
-/* configure_ddr_sched_ctrl_regs();*/
return 0;
}
@@ -348,20 +345,28 @@
mmio_read_32(AGX_MPFE_IOHMC_REG_NIOSRESERVE0_OFST));
dram_io_width = (dram_io_width & 0xFF) >> 5;
+ data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG3);
+
+ dram_io_width |= (data & 0x4);
+
- mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_DDRIOCTRL,
- AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK,
- dram_io_width << AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST);
+ mmio_write_32(AGX_MPFE_HMC_ADP_DDRIOCTRL, dram_io_width);
/* Copy dram addr width from IOHMC to HMC ADP */
data = mmio_read_32(AGX_MPFE_IOHMC_DRAMADDRW);
mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data);
/* Enable nonsecure access to DDR */
- mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT,
- 0x4000000 - 1);
- mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT,
- 0x4000000 - 1);
- mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLE, BIT(0) | BIT(8));
+ data = get_physical_dram_size();
+
+ if (data < AGX_DDR_SIZE)
+ data = AGX_DDR_SIZE;
+
+ mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, data - 1);
+ mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1f);
+
+ mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, data - 1);
+
+ mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8));
/* ECC enablement */
data = mmio_read_32(AGX_MPFE_IOHMC_REG_CTRLCFG1);
diff --git a/plat/renesas/rcar/bl2_cpg_init.c b/plat/renesas/rcar/bl2_cpg_init.c
index ed9b772..c3ca9ea 100644
--- a/plat/renesas/rcar/bl2_cpg_init.c
+++ b/plat/renesas/rcar/bl2_cpg_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -109,12 +109,12 @@
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
static void bl2_realtime_cpg_init_h3(void)
{
- uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
+ uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
uint32_t cr0, cr8;
- cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+ cr0 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
0x00200000U : 0x00210000U;
- cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ?
+ cr8 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
0x01F1FFF4U : 0x01F1FFF7U;
cpg_write(RMSTPCR0, cr0);
@@ -329,7 +329,7 @@
{
uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
#if RCAR_LSI == RCAR_AUTO
- uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+ uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
#endif
bl2_secure_cpg_init();
@@ -338,22 +338,22 @@
#if RCAR_LSI == RCAR_AUTO
switch (product) {
- case RCAR_PRODUCT_H3:
+ case PRR_PRODUCT_H3:
bl2_realtime_cpg_init_h3();
break;
- case RCAR_PRODUCT_M3:
+ case PRR_PRODUCT_M3:
bl2_realtime_cpg_init_m3();
break;
- case RCAR_PRODUCT_M3N:
+ case PRR_PRODUCT_M3N:
bl2_realtime_cpg_init_m3n();
break;
- case RCAR_PRODUCT_V3M:
+ case PRR_PRODUCT_V3M:
bl2_realtime_cpg_init_v3m();
break;
- case RCAR_PRODUCT_E3:
+ case PRR_PRODUCT_E3:
bl2_realtime_cpg_init_e3();
break;
- case RCAR_PRODUCT_D3:
+ case PRR_PRODUCT_D3:
bl2_realtime_cpg_init_d3();
break;
default:
@@ -381,25 +381,25 @@
void bl2_system_cpg_init(void)
{
#if RCAR_LSI == RCAR_AUTO
- uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
+ uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
switch (product) {
- case RCAR_PRODUCT_H3:
+ case PRR_PRODUCT_H3:
bl2_system_cpg_init_h3();
break;
- case RCAR_PRODUCT_M3:
+ case PRR_PRODUCT_M3:
bl2_system_cpg_init_m3();
break;
- case RCAR_PRODUCT_M3N:
+ case PRR_PRODUCT_M3N:
bl2_system_cpg_init_m3n();
break;
- case RCAR_PRODUCT_V3M:
+ case PRR_PRODUCT_V3M:
bl2_system_cpg_init_v3m();
break;
- case RCAR_PRODUCT_E3:
+ case PRR_PRODUCT_E3:
bl2_system_cpg_init_e3();
break;
- case RCAR_PRODUCT_D3:
+ case PRR_PRODUCT_D3:
bl2_system_cpg_init_d3();
break;
default:
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 3c9b56f..ebe6ddd 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -65,22 +65,22 @@
/* R-Car Gen3 product check */
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
-#define TARGET_PRODUCT RCAR_PRODUCT_H3
+#define TARGET_PRODUCT PRR_PRODUCT_H3
#define TARGET_NAME "R-Car H3"
#elif RCAR_LSI == RCAR_M3
-#define TARGET_PRODUCT RCAR_PRODUCT_M3
+#define TARGET_PRODUCT PRR_PRODUCT_M3
#define TARGET_NAME "R-Car M3"
#elif RCAR_LSI == RCAR_M3N
-#define TARGET_PRODUCT RCAR_PRODUCT_M3N
+#define TARGET_PRODUCT PRR_PRODUCT_M3N
#define TARGET_NAME "R-Car M3N"
#elif RCAR_LSI == RCAR_V3M
-#define TARGET_PRODUCT RCAR_PRODUCT_V3M
+#define TARGET_PRODUCT PRR_PRODUCT_V3M
#define TARGET_NAME "R-Car V3M"
#elif RCAR_LSI == RCAR_E3
-#define TARGET_PRODUCT RCAR_PRODUCT_E3
+#define TARGET_PRODUCT PRR_PRODUCT_E3
#define TARGET_NAME "R-Car E3"
#elif RCAR_LSI == RCAR_D3
-#define TARGET_PRODUCT RCAR_PRODUCT_D3
+#define TARGET_PRODUCT PRR_PRODUCT_D3
#define TARGET_NAME "R-Car D3"
#elif RCAR_LSI == RCAR_AUTO
#define TARGET_NAME "R-Car H3/M3/M3N/V3M"
@@ -238,17 +238,17 @@
bl2_secure_setting();
reg = mmio_read_32(RCAR_PRR);
- product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
- product = reg & RCAR_PRODUCT_MASK;
- cut = reg & RCAR_CUT_MASK;
+ product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+ product = reg & PRR_PRODUCT_MASK;
+ cut = reg & PRR_CUT_MASK;
- if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut)
+ if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
goto tlb;
- if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut)
+ if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
goto tlb;
- if (product == RCAR_PRODUCT_D3)
+ if (product == PRR_PRODUCT_D3)
goto tlb;
/* Disable MFIS write protection */
@@ -261,28 +261,28 @@
boot_cpu != MODEMR_BOOT_CPU_CA53)
goto mmu;
- if (product_cut == RCAR_PRODUCT_H3_CUT20) {
+ if (product_cut == PRR_PRODUCT_H3_CUT20) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
- } else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
- product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
+ } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
+ product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
- } else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) ||
- (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) {
+ } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
+ (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
}
- if (product_cut == (RCAR_PRODUCT_H3_CUT20) ||
- product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) ||
- product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) ||
- product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
+ if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
+ product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
+ product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
+ product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
@@ -458,28 +458,28 @@
}
reg = mmio_read_32(RCAR_PRR);
- switch (reg & RCAR_PRODUCT_MASK) {
- case RCAR_PRODUCT_H3:
+ switch (reg & PRR_PRODUCT_MASK) {
+ case PRR_PRODUCT_H3:
ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a7795");
break;
- case RCAR_PRODUCT_M3:
+ case PRR_PRODUCT_M3:
ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a7796");
break;
- case RCAR_PRODUCT_M3N:
+ case PRR_PRODUCT_M3N:
ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77965");
break;
- case RCAR_PRODUCT_V3M:
+ case PRR_PRODUCT_V3M:
ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77970");
break;
- case RCAR_PRODUCT_E3:
+ case PRR_PRODUCT_E3:
ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77990");
break;
- case RCAR_PRODUCT_D3:
+ case PRR_PRODUCT_D3:
ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77995");
break;
@@ -572,7 +572,7 @@
};
switch (product) {
- case RCAR_PRODUCT_H3:
+ case PRR_PRODUCT_H3:
#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
/* 4GB(1GBx4) */
dram_config[1] = 0x40000000ULL;
@@ -594,7 +594,7 @@
#endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
break;
- case RCAR_PRODUCT_M3:
+ case PRR_PRODUCT_M3:
#if (RCAR_GEN3_ULCB == 1)
/* 2GB(1GBx2 2ch split) */
dram_config[1] = 0x40000000ULL;
@@ -606,17 +606,17 @@
#endif
break;
- case RCAR_PRODUCT_M3N:
+ case PRR_PRODUCT_M3N:
/* 2GB(1GBx2) */
dram_config[1] = 0x80000000ULL;
break;
- case RCAR_PRODUCT_V3M:
+ case PRR_PRODUCT_V3M:
/* 1GB(512MBx2) */
dram_config[1] = 0x40000000ULL;
break;
- case RCAR_PRODUCT_E3:
+ case PRR_PRODUCT_E3:
#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
/* 1GB(512MBx2) */
dram_config[1] = 0x40000000ULL;
@@ -629,7 +629,7 @@
#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
break;
- case RCAR_PRODUCT_D3:
+ case PRR_PRODUCT_D3:
/* 512MB */
dram_config[1] = 0x20000000ULL;
break;
@@ -716,26 +716,26 @@
version_of_renesas);
reg = mmio_read_32(RCAR_PRR);
- product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
- product = reg & RCAR_PRODUCT_MASK;
+ product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
+ product = reg & PRR_PRODUCT_MASK;
switch (product) {
- case RCAR_PRODUCT_H3:
+ case PRR_PRODUCT_H3:
str = product_h3;
break;
- case RCAR_PRODUCT_M3:
+ case PRR_PRODUCT_M3:
str = product_m3;
break;
- case RCAR_PRODUCT_M3N:
+ case PRR_PRODUCT_M3N:
str = product_m3n;
break;
- case RCAR_PRODUCT_V3M:
+ case PRR_PRODUCT_V3M:
str = product_v3m;
break;
- case RCAR_PRODUCT_E3:
+ case PRR_PRODUCT_E3:
str = product_e3;
break;
- case RCAR_PRODUCT_D3:
+ case PRR_PRODUCT_D3:
str = product_d3;
break;
default:
@@ -743,9 +743,9 @@
break;
}
- if ((RCAR_PRODUCT_M3 == product) &&
- (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) {
- if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) {
+ if ((PRR_PRODUCT_M3 == product) &&
+ (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
+ if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
/* M3 Ver.1.1 or Ver.1.2 */
NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
str);
@@ -761,7 +761,7 @@
NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
}
- if (product == RCAR_PRODUCT_E3) {
+ if (product == PRR_PRODUCT_E3) {
reg = mmio_read_32(RCAR_MODEMR);
sscg = reg & RCAR_SSCG_MASK;
str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
@@ -930,7 +930,7 @@
mmio_write_32(CPG_CA53DBGRCR,
DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
- if (product_cut == RCAR_PRODUCT_H3_CUT10) {
+ if (product_cut == PRR_PRODUCT_H3_CUT10) {
reg = mmio_read_32(CPG_PLL2CR);
reg &= ~((uint32_t) 1 << 5);
mmio_write_32(CPG_PLL2CR, reg);
@@ -1016,7 +1016,7 @@
/* Set frequency data in CNTFID0 */
reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
- reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+ reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
switch (modemr_pll) {
case MD14_MD13_TYPE_0:
rcar_get_board_type(&board_type, &board_rev);
@@ -1025,7 +1025,7 @@
}
break;
case MD14_MD13_TYPE_3:
- if (RCAR_PRODUCT_H3_CUT10 == reg) {
+ if (PRR_PRODUCT_H3_CUT10 == reg) {
reg_cntfid = reg_cntfid >> 1U;
}
break;
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
index 4fff233..bd83c41 100644
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ b/plat/renesas/rcar/bl31_plat_setup.c
@@ -44,9 +44,9 @@
{
uint32_t prd;
- prd = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
+ prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
- if (RCAR_PRODUCT_H3_CUT10 == prd || RCAR_PRODUCT_H3_CUT11 == prd) {
+ if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) {
cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
}
diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h
index ac7dc17..a60f9b6 100644
--- a/plat/renesas/rcar/include/rcar_def.h
+++ b/plat/renesas/rcar/include/rcar_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -147,31 +147,34 @@
#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
/* Product register */
#define RCAR_PRR U(0xFFF00044)
-#define RCAR_PRODUCT_MASK U(0x00007F00)
-#define RCAR_CUT_MASK U(0x000000FF)
-#define RCAR_PRODUCT_H3 U(0x00004F00)
-#define RCAR_PRODUCT_M3 U(0x00005200)
-#define RCAR_PRODUCT_V3M U(0x00005400)
-#define RCAR_PRODUCT_M3N U(0x00005500)
-#define RCAR_PRODUCT_E3 U(0x00005700)
-#define RCAR_PRODUCT_D3 U(0x00005800)
-#define RCAR_CUT_VER10 U(0x00000000)
-#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
-#define RCAR_CUT_VER20 U(0x00000010)
-#define RCAR_CUT_VER30 U(0x00000020)
#define RCAR_MAJOR_MASK U(0x000000F0)
#define RCAR_MINOR_MASK U(0x0000000F)
-#define RCAR_PRODUCT_SHIFT U(8)
+#define PRR_PRODUCT_SHIFT U(8)
#define RCAR_MAJOR_SHIFT U(4)
#define RCAR_MINOR_SHIFT U(0)
#define RCAR_MAJOR_OFFSET U(1)
#define RCAR_M3_MINOR_OFFSET U(2)
-#define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | U(0x00)) /* 1.0 */
-#define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | U(0x01)) /* 1.1 */
-#define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */
-#define RCAR_PRODUCT_M3_CUT10 (RCAR_PRODUCT_M3 | U(0x00)) /* 1.0 */
-#define RCAR_PRODUCT_M3_CUT11 (RCAR_PRODUCT_M3 | U(0x10))
+#define PRR_PRODUCT_H3_CUT10 (PRR_PRODUCT_H3 | U(0x00)) /* 1.0 */
+#define PRR_PRODUCT_H3_CUT11 (PRR_PRODUCT_H3 | U(0x01)) /* 1.1 */
+#define PRR_PRODUCT_H3_CUT20 (PRR_PRODUCT_H3 | U(0x10)) /* 2.0 */
+#define PRR_PRODUCT_M3_CUT10 (PRR_PRODUCT_M3 | U(0x00)) /* 1.0 */
+#define PRR_PRODUCT_M3_CUT11 (PRR_PRODUCT_M3 | U(0x10))
+#define PRR 0xFFF00044U
+#define PRR_PRODUCT_MASK 0x00007F00U
+#define PRR_CUT_MASK 0x000000FFU
+#define PRR_PRODUCT_H3 0x00004F00U /* R-Car H3 */
+#define PRR_PRODUCT_M3 0x00005200U /* R-Car M3-W */
+#define PRR_PRODUCT_V3M 0x00005400U /* R-Car V3M */
+#define PRR_PRODUCT_M3N 0x00005500U /* R-Car M3-N */
+#define PRR_PRODUCT_V3H 0x00005600U /* R-Car V3H */
+#define PRR_PRODUCT_E3 0x00005700U /* R-Car E3 */
+#define PRR_PRODUCT_D3 0x00005800U /* R-Car D3 */
+#define PRR_PRODUCT_10 0x00U /* Ver.1.0 */
+#define PRR_PRODUCT_11 0x01U /* Ver.1.1 */
+#define PRR_PRODUCT_20 0x10U /* Ver.2.0 */
+#define PRR_PRODUCT_21 0x11U /* Ver.2.1 */
+#define PRR_PRODUCT_30 0x20U /* Ver.3.0 */
#define RCAR_CPU_MASK_CA57 U(0x80000000)
#define RCAR_CPU_MASK_CA53 U(0x04000000)
#define RCAR_CPU_HAVE_CA57 U(0x00000000)
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index a13ee49..c4a0359 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -14,7 +14,6 @@
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/ti/uart/uart_16550.h>
-#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <plat_private.h>
#include <plat/common/platform.h>
@@ -62,16 +61,10 @@
params_early_setup(arg1);
-#if COREBOOT
- if (coreboot_serial.type)
- console_16550_register(coreboot_serial.baseaddr,
- coreboot_serial.input_hertz,
- coreboot_serial.baud,
- &console);
-#else
- console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
- PLAT_RK_UART_BAUDRATE, &console);
-#endif
+ if (rockchip_get_uart_base() != 0)
+ console_16550_register(rockchip_get_uart_base(),
+ rockchip_get_uart_clock(),
+ rockchip_get_uart_baudrate(), &console);
VERBOSE("bl31_setup\n");
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 714a8bf..990d106 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -139,6 +139,8 @@
extern const mmap_region_t plat_rk_mmap[];
uint32_t rockchip_get_uart_base(void);
+uint32_t rockchip_get_uart_baudrate(void);
+uint32_t rockchip_get_uart_clock(void);
#endif /* __ASSEMBLER__ */
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index d0fea4f..8c2e5e9 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -26,12 +26,6 @@
static struct bl_aux_gpio_info suspend_gpio[10];
uint32_t suspend_gpio_cnt;
static struct bl_aux_rk_apio_info suspend_apio;
-static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
-
-uint32_t rockchip_get_uart_base(void)
-{
- return rk_uart_base;
-}
#if COREBOOT
static int dt_process_fdt(u_register_t param_from_bl2)
@@ -39,6 +33,9 @@
return -ENODEV;
}
#else
+static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
+static uint32_t rk_uart_baudrate = PLAT_RK_UART_BAUDRATE;
+static uint32_t rk_uart_clock = PLAT_RK_UART_CLOCK;
static uint8_t fdt_buffer[0x10000];
void *plat_get_fdt(void)
@@ -53,9 +50,12 @@
int node_offset;
int stdout_path_len;
const char *stdout_path;
+ const char *separator;
+ const char *baud_start;
char serial_char;
int serial_no;
uint32_t uart_base;
+ uint32_t baud;
node_offset = fdt_path_offset(fdt, path_name);
if (node_offset < 0)
@@ -68,7 +68,7 @@
/*
* We expect something like:
- * "serial0:...""
+ * "serial0:baudrate"
*/
if (strncmp("serial", stdout_path, 6) != 0)
return;
@@ -96,11 +96,38 @@
uart_base = UART4_BASE;
break;
#endif
+#ifdef UART5_BASE
+ case 5:
+ uart_base = UART5_BASE;
+ break;
+#endif
default:
return;
}
rk_uart_base = uart_base;
+
+ separator = strchr(stdout_path, ':');
+ if (!separator)
+ return;
+
+ baud = 0;
+ baud_start = separator + 1;
+ while (*baud_start != '\0') {
+ /*
+ * uart binding is <baud>{<parity>{<bits>{...}}}
+ * So the baudrate either is the whole string, or
+ * we end in the parity characters.
+ */
+ if (*baud_start == 'n' || *baud_start == 'o' ||
+ *baud_start == 'e')
+ break;
+
+ baud = baud * 10 + (*baud_start - '0');
+ baud_start++;
+ }
+
+ rk_uart_baudrate = baud;
}
static int dt_process_fdt(u_register_t param_from_bl2)
@@ -118,6 +145,33 @@
}
#endif
+uint32_t rockchip_get_uart_base(void)
+{
+#if COREBOOT
+ return coreboot_serial.baseaddr;
+#else
+ return rk_uart_base;
+#endif
+}
+
+uint32_t rockchip_get_uart_baudrate(void)
+{
+#if COREBOOT
+ return coreboot_serial.baud;
+#else
+ return rk_uart_baudrate;
+#endif
+}
+
+uint32_t rockchip_get_uart_clock(void)
+{
+#if COREBOOT
+ return coreboot_serial.input_hertz;
+#else
+ return rk_uart_clock;
+#endif
+}
+
struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
{
return &rst_gpio;
diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c
index 7b1a0b5..6d15075 100644
--- a/plat/rockchip/common/sp_min_plat_setup.c
+++ b/plat/rockchip/common/sp_min_plat_setup.c
@@ -15,7 +15,6 @@
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/ti/uart/uart_16550.h>
-#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <plat_private.h>
#include <plat/common/platform.h>
@@ -57,16 +56,11 @@
params_early_setup(arg1);
-#if COREBOOT
- if (coreboot_serial.type)
- console_16550_register(coreboot_serial.baseaddr,
- coreboot_serial.input_hertz,
- coreboot_serial.baud,
- &console);
-#else
- console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
- PLAT_RK_UART_BAUDRATE, &console);
-#endif
+ if (rockchip_get_uart_base() != 0)
+ console_16550_register(rockchip_get_uart_base(),
+ rockchip_get_uart_clock(),
+ rockchip_get_uart_baudrate(), &console);
+
VERBOSE("sp_min_setup\n");
bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);
diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h
index 021165a..9b8ccfc 100644
--- a/plat/rockchip/px30/px30_def.h
+++ b/plat/rockchip/px30/px30_def.h
@@ -54,6 +54,9 @@
#define UART2_BASE 0xff160000
#define UART2_SIZE SIZE_K(64)
+#define UART5_BASE 0xff178000
+#define UART5_SIZE SIZE_K(64)
+
#define I2C0_BASE 0xff180000
#define I2C0_SIZE SIZE_K(64)
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index a6b5973..30941fd 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1125,32 +1125,41 @@
void suspend_uart(void)
{
- uart_save.uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
- uart_save.uart_ier = mmio_read_32(PLAT_RK_UART_BASE + UART_IER);
- uart_save.uart_mcr = mmio_read_32(PLAT_RK_UART_BASE + UART_MCR);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
+ uint32_t uart_base = rockchip_get_uart_base();
+
+ if (uart_base == 0)
+ return;
+
+ uart_save.uart_lcr = mmio_read_32(uart_base + UART_LCR);
+ uart_save.uart_ier = mmio_read_32(uart_base + UART_IER);
+ uart_save.uart_mcr = mmio_read_32(uart_base + UART_MCR);
+ mmio_write_32(uart_base + UART_LCR,
uart_save.uart_lcr | UARTLCR_DLAB);
- uart_save.uart_dll = mmio_read_32(PLAT_RK_UART_BASE + UART_DLL);
- uart_save.uart_dlh = mmio_read_32(PLAT_RK_UART_BASE + UART_DLH);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
+ uart_save.uart_dll = mmio_read_32(uart_base + UART_DLL);
+ uart_save.uart_dlh = mmio_read_32(uart_base + UART_DLH);
+ mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
}
void resume_uart(void)
{
+ uint32_t uart_base = rockchip_get_uart_base();
uint32_t uart_lcr;
- mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
+ if (uart_base == 0)
+ return;
+
+ mmio_write_32(uart_base + UARTSRR,
XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET);
- uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
- mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
- mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
- mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
- mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
- mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
- mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
+ uart_lcr = mmio_read_32(uart_base + UART_LCR);
+ mmio_write_32(uart_base + UART_MCR, DIAGNOSTIC_MODE);
+ mmio_write_32(uart_base + UART_LCR, uart_lcr | UARTLCR_DLAB);
+ mmio_write_32(uart_base + UART_DLL, uart_save.uart_dll);
+ mmio_write_32(uart_base + UART_DLH, uart_save.uart_dlh);
+ mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
+ mmio_write_32(uart_base + UART_IER, uart_save.uart_ier);
+ mmio_write_32(uart_base + UART_FCR, UARTFCR_FIFOEN);
+ mmio_write_32(uart_base + UART_MCR, uart_save.uart_mcr);
}
void save_usbphy(void)
diff --git a/services/spd/opteed/opteed.mk b/services/spd/opteed/opteed.mk
index b1b2175..643b054 100644
--- a/services/spd/opteed/opteed.mk
+++ b/services/spd/opteed/opteed.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -13,3 +13,6 @@
services/spd/opteed/opteed_pm.c
NEED_BL32 := yes
+
+# required so that optee code can control access to the timer registers
+NS_TIMER_SWITCH := 1
diff --git a/services/std_svc/spm/spm_buffers.c b/services/std_svc/spm/spm_buffers.c
index 3e0c949..79398ba 100644
--- a/services/std_svc/spm/spm_buffers.c
+++ b/services/std_svc/spm/spm_buffers.c
@@ -38,6 +38,8 @@
struct sprt_response *resp = &(responses[i]);
if ((resp->is_valid == 1) && (resp->token == token)) {
+ spin_unlock(&responses_lock);
+
return -1;
}
}
diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c
index 055ddbf..57fb47d 100644
--- a/tools/cert_create/src/ext.c
+++ b/tools/cert_create/src/ext.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -284,6 +284,7 @@
ex = ext_new(nid, crit, p, sz);
/* Clean up */
+ BIO_free(mem);
OPENSSL_free(p);
return ex;
diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c
index 871f9ee..fece770 100644
--- a/tools/cert_create/src/key.c
+++ b/tools/cert_create/src/key.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -73,6 +73,7 @@
goto err;
}
+ BN_free(e);
return 1;
err:
RSA_free(rsa);
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index ed56620..0f588cc 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/