adding support to enable different personality of the same soc.
Same SoC has different personality by creating different number of:
- cores
- clusters.
As a result, the platform specific power domain tree will be created
after identify the personality of the SoC.
Hence, platform specific power domain tree may not be same for all the
personality of the soc.
Thus, psci library code will deduce the 'plat_core_count', while
populating the power domain tree topology and return the number of
cores.
PLATFORM_CORE_COUNT will still be valid for a SoC, such that
psci_plat_core_count <= PLATFORM_CORE_COUNT.
PLATFORM_CORE_COUNT will continued to be defined by platform to create
the data structures.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I1f5c47647631cae2dcdad540d64cf09757db7185
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 7c42be7..ea1a01d 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -43,6 +43,7 @@
static plat_local_state_t
psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
+unsigned int psci_plat_core_count;
/*******************************************************************************
* Arrays that hold the platform's power domain tree information for state
@@ -161,7 +162,7 @@
{
unsigned int cpu_idx, my_idx = plat_my_core_pos();
- for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT;
+ for (cpu_idx = 0; cpu_idx < psci_plat_core_count;
cpu_idx++) {
if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON);
@@ -208,7 +209,7 @@
{
assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
- (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
+ (cpu_idx < psci_plat_core_count)) {
psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
}
}
@@ -220,10 +221,10 @@
{
/* Initialize the requested state of all non CPU power domains as OFF */
unsigned int pwrlvl;
- int core;
+ unsigned int core;
for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) {
- for (core = 0; core < PLATFORM_CORE_COUNT; core++) {
+ for (core = 0; core < psci_plat_core_count; core++) {
psci_req_local_pwr_states[pwrlvl][core] =
PLAT_MAX_OFF_STATE;
}
@@ -244,7 +245,7 @@
assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
- (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
+ (cpu_idx < psci_plat_core_count)) {
return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
} else
return NULL;
@@ -888,7 +889,7 @@
void psci_print_power_domain_map(void)
{
#if LOG_LEVEL >= LOG_LEVEL_INFO
- int idx;
+ unsigned int idx;
plat_local_state_t state;
plat_local_state_type_t state_type;
@@ -900,7 +901,7 @@
};
INFO("PSCI Power Domain Map:\n");
- for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT);
+ for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - psci_plat_core_count);
idx++) {
state_type = find_local_state_type(
psci_non_cpu_pd_nodes[idx].local_state);
@@ -912,7 +913,7 @@
psci_non_cpu_pd_nodes[idx].local_state);
}
- for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) {
+ for (idx = 0; idx < psci_plat_core_count; idx++) {
state = psci_get_cpu_local_state_by_idx(idx);
state_type = find_local_state_type(state);
INFO(" CPU Node : MPID 0x%llx, parent_node %d,"
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index b49847c..0f25e65 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -251,6 +251,7 @@
extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
extern unsigned int psci_caps;
+extern unsigned int psci_plat_core_count;
/*******************************************************************************
* SPD's power management hooks registered with PSCI
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 853f915..becb547 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -84,11 +84,12 @@
*******************************************************************************/
static void __init psci_update_pwrlvl_limits(void)
{
- int j, cpu_idx;
+ unsigned int cpu_idx;
+ int j;
unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
unsigned int temp_index[PLAT_MAX_PWR_LVL];
- for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
+ for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
psci_get_parent_pwr_domain_nodes(cpu_idx,
(unsigned int)PLAT_MAX_PWR_LVL,
temp_index);
@@ -109,7 +110,8 @@
* informs the number of root power domains. The parent nodes of the root nodes
* will point to an invalid entry(-1).
******************************************************************************/
-static void __init populate_power_domain_tree(const unsigned char *topology)
+static unsigned int __init populate_power_domain_tree(const unsigned char
+ *topology)
{
unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
unsigned int node_index = 0U, num_children;
@@ -160,7 +162,8 @@
}
/* Validate the sanity of array exported by the platform */
- assert((int) j == PLATFORM_CORE_COUNT);
+ assert(j <= (unsigned int)PLATFORM_CORE_COUNT);
+ return j;
}
/*******************************************************************************
@@ -199,7 +202,7 @@
topology_tree = plat_get_power_domain_tree_desc();
/* Populate the power domain arrays using the platform topology map */
- populate_power_domain_tree(topology_tree);
+ psci_plat_core_count = populate_power_domain_tree(topology_tree);
/* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
psci_update_pwrlvl_limits();