diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index 60791d4..f617692 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -301,7 +301,7 @@
 	}
 
 	/* Clear phy isolation mode to make it work in normal mode */
-	offset =  COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
+	offset =  COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
 	comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE);
 
 	/* 0. Check the Polarity invert bits */
@@ -310,7 +310,7 @@
 	if (invert & COMPHY_POLARITY_RXD_INVERT)
 		data |= RXD_INVERT_BIT;
 
-	offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
+	offset = COMPHY_SYNC_PATTERN + SATAPHY_LANE2_REG_BASE_OFFSET;
 	comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
 				 RXD_INVERT_BIT);
 
@@ -524,7 +524,7 @@
 	if (invert & COMPHY_POLARITY_RXD_INVERT)
 		data |= RXD_INVERT_BIT;
 	mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
-	reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask);
+	reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN, sd_ip_addr), data, mask);
 
 	/*
 	 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
@@ -646,7 +646,7 @@
 	 */
 	mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
 		CFG_TX_ALIGN_POS_MASK;
-	usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
+	usb3_reg_set(reg_base, COMPHY_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
 		     mask);
 
 	/*
@@ -654,38 +654,38 @@
 	 *    Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
 	 *    Set BIT6: Tx detect Rx at HiZ mode
 	 *    Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
-	 *            together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register
+	 *            together with bit 0 of COMPHY_LANE_CFG0_ADDR register
 	 */
 	mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
 		TX_ELEC_IDLE_MODE_EN;
 	data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
-	usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask);
+	usb3_reg_set(reg_base, COMPHY_LANE_CFG1_ADDR, data, mask);
 
 	/*
 	 * 3. Set Spread Spectrum Clock Enabled
 	 */
-	usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR,
+	usb3_reg_set(reg_base, COMPHY_LANE_CFG4_ADDR,
 		     SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
 
 	/*
 	 * 4. Set Override Margining Controls From the MAC:
 	 *    Use margining signals from lane configuration
 	 */
-	usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR,
+	usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL_ADDR,
 		     MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK);
 
 	/*
 	 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
 	 *    set Mode Clock Source = PCLK is generated from REFCLK
 	 */
-	usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0,
+	usb3_reg_set(reg_base, COMPHY_GLOB_CLK_SRC_LO_ADDR, 0x0,
 		     (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
 		      BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
 
 	/*
 	 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K
 	 */
-	usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2,
+	usb3_reg_set(reg_base, COMPHY_GEN2_SET_2,
 		     G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK);
 
 	/*
@@ -694,7 +694,7 @@
 	 */
 	mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
 		RSVD_PH03FH_6_0_MASK;
-	usb3_reg_set(reg_base, COMPHY_REG_GEN3_SET_2,
+	usb3_reg_set(reg_base, COMPHY_GEN3_SET_2,
 		     G3_VREG_RXTX_MAS_ISET_60U, mask);
 
 	/*
@@ -721,13 +721,13 @@
 	mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
 		CFG_PM_RXDLOZ_WAIT_MASK;
 	data = CFG_PM_RXDEN_WAIT_1_UNIT  | cfg;
-	usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask);
+	usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1_ADDR, data, mask);
 
 	/*
 	 * 9. Enable idle sync
 	 */
 	data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
-	usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
+	usb3_reg_set(reg_base, COMPHY_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
 
 	/*
 	 * 10. Enable the output of 500M clock
@@ -759,32 +759,32 @@
 		data |= RXD_INVERT_BIT;
 	}
 	mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
-	usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask);
+	usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN, data, mask);
 
 	/*
 	 * 14. Set max speed generation to USB3.0 5Gbps
 	 */
-	usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_MAX_USB3_5G,
+	usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN, PHY_GEN_MAX_USB3_5G,
 		     PHY_GEN_MAX_MASK);
 
 	/*
 	 * 15. Set capacitor value for FFE gain peaking to 0xF
 	 */
-	usb3_reg_set(reg_base, COMPHY_REG_GEN2_SETTINGS_3,
+	usb3_reg_set(reg_base, COMPHY_GEN2_SETTINGS_3,
 		     COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK);
 
 	/*
 	 * 16. Release SW reset
 	 */
 	data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
-	usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data,
+	usb3_reg_set(reg_base, COMPHY_GLOB_PHY_CTRL0_ADDR, data,
 		     REG_16_BIT_MASK);
 
 	/* Wait for > 55 us to allow PCLK be enabled */
 	udelay(PLL_SET_DELAY_US);
 
 	if (comphy_index == COMPHY_LANE2) {
-		data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
+		data = COMPHY_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
 		mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
 			      data);
 
@@ -882,7 +882,7 @@
 		data |= RXD_INVERT_BIT;
 	}
 	mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
-	reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
+	reg_set16(SYNC_PATTERN_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
 
 	/* 11. Release SW reset */
 	data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;
@@ -962,7 +962,7 @@
 	debug_enter();
 
 	/* Set phy isolation mode */
-	offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
+	offset = COMPHY_ISOLATION_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
 	comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
 				 PHY_ISOLATE_MODE);
 
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 95b9e8f..9bc1a5d 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -82,32 +82,30 @@
 #define DATA_WIDTH_40BIT		(0x2 << SEL_DATA_WIDTH_OFFSET)
 #define PLL_READY_TX_BIT		BIT(4)
 
-#define COMPHY_SYNC_PATTERN_REG		0x24
-#define SYNC_PATTERN_REG_ADDR(unit)	(COMPHY_SYNC_PATTERN_REG * \
-					 PHY_SHFT(unit))
+#define COMPHY_SYNC_PATTERN		0x24
+#define SYNC_PATTERN_ADDR(unit)		(COMPHY_SYNC_PATTERN * PHY_SHFT(unit))
 #define TXD_INVERT_BIT			BIT(10)
 #define RXD_INVERT_BIT			BIT(11)
 
-#define COMPHY_SYNC_MASK_GEN_REG	0x25
+#define COMPHY_SYNC_MASK_GEN		0x25
 #define PHY_GEN_MAX_OFFSET		10
 #define PHY_GEN_MAX_MASK		(3 << PHY_GEN_MAX_OFFSET)
 #define PHY_GEN_MAX_USB3_5G		(1 << PHY_GEN_MAX_OFFSET)
 
-#define COMPHY_ISOLATION_CTRL_REG	0x26
-#define ISOLATION_CTRL_REG_ADDR(unit)	(COMPHY_ISOLATION_CTRL_REG * \
-					 PHY_SHFT(unit))
+#define COMPHY_ISOLATION_CTRL		0x26
+#define ISOLATION_CTRL_ADDR(unit)	(COMPHY_ISOLATION_REG * PHY_SHFT(unit))
 #define PHY_ISOLATE_MODE		BIT(15)
 
-#define COMPHY_REG_GEN2_SET_2	0x3e
-#define GEN2_SETTING_2_ADDR(unit)	(COMPHY_REG_GEN2_SET_2 * PHY_SHFT(unit))
+#define COMPHY_GEN2_SET_2		0x3e
+#define GEN2_SETTING_2_ADDR(unit)	(COMPHY_GEN2_SET_2 * PHY_SHFT(unit))
 #define G2_TX_SSC_AMP_VALUE_20		BIT(14)
 #define G2_TX_SSC_AMP_OFF		9
 #define G2_TX_SSC_AMP_LEN		7
 #define G2_TX_SSC_AMP_MASK		(((1 << G2_TX_SSC_AMP_LEN) - 1) << \
 					 G2_TX_SSC_AMP_OFF)
 
-#define COMPHY_REG_GEN3_SET_2	0x3f
-#define GEN3_SETTING_2_ADDR(unit)	(COMPHY_REG_GEN3_SET_2 * PHY_SHFT(unit))
+#define COMPHY_GEN3_SET_2		0x3f
+#define GEN3_SETTING_2_ADDR(unit)	(COMPHY_GEN3_SET_2 * PHY_SHFT(unit))
 #define G3_TX_SSC_AMP_OFF		9
 #define G3_TX_SSC_AMP_LEN		7
 #define G3_TX_SSC_AMP_MASK		(((1 << G2_TX_SSC_AMP_LEN) - 1) << \
@@ -123,9 +121,8 @@
 #define RSVD_PH03FH_6_0_MASK		(((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
 					 RSVD_PH03FH_6_0_OFF)
 
-#define COMPHY_REG_UNIT_CTRL_ADDR	0x48
-#define UNIT_CTRL_ADDR(unit)		(COMPHY_REG_UNIT_CTRL_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_UNIT_CTRL_ADDR		0x48
+#define UNIT_CTRL_ADDR(unit)		(COMPHY_UNIT_CTRL_ADDR * PHY_SHFT(unit))
 #define IDLE_SYNC_EN			BIT(12)
 #define UNIT_CTRL_DEFAULT_VALUE		0x60
 
@@ -141,21 +138,19 @@
 #define MISC_REG1_ADDR(unit)		(COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit))
 #define SEL_BITS_PCIE_FORCE		BIT(15)
 
-#define COMPHY_REG_GEN2_SETTINGS_3	0x112
+#define COMPHY_GEN2_SETTINGS_3		0x112
 #define COMPHY_GEN_FFE_CAP_SEL_MASK	0xF
 #define COMPHY_GEN_FFE_CAP_SEL_VALUE	0xF
 
-#define COMPHY_REG_LANE_CFG0_ADDR	0x180
-#define LANE_CFG0_ADDR(unit)		(COMPHY_REG_LANE_CFG0_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_LANE_CFG0_ADDR		0x180
+#define LANE_CFG0_ADDR(unit)		(COMPHY_LANE_CFG0_ADDR * PHY_SHFT(unit))
 #define PRD_TXDEEMPH0_MASK		BIT(0)
 #define PRD_TXMARGIN_MASK		(BIT(1) | BIT(2) | BIT(3))
 #define PRD_TXSWING_MASK		BIT(4)
 #define CFG_TX_ALIGN_POS_MASK		(BIT(5) | BIT(6) | BIT(7) | BIT(8))
 
-#define COMPHY_REG_LANE_CFG1_ADDR	0x181
-#define LANE_CFG1_ADDR(unit)		(COMPHY_REG_LANE_CFG1_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_LANE_CFG1_ADDR		0x181
+#define LANE_CFG1_ADDR(unit)		(COMPHY_LANE_CFG1_ADDR * PHY_SHFT(unit))
 #define PRD_TXDEEMPH1_MASK		BIT(15)
 #define USE_MAX_PLL_RATE_EN		BIT(9)
 #define TX_DET_RX_MODE			BIT(6)
@@ -163,18 +158,17 @@
 #define GEN2_TX_DATA_DLY_DEFT		(2 << 3)
 #define TX_ELEC_IDLE_MODE_EN		BIT(0)
 
-#define COMPHY_REG_LANE_STATUS1_ADDR	0x183
-#define LANE_STATUS1_ADDR(unit)		(COMPHY_REG_LANE_STATUS1_ADDR * \
+#define COMPHY_LANE_STATUS1_ADDR	0x183
+#define LANE_STATUS1_ADDR(unit)		(COMPHY_LANE_STATUS1_ADDR * \
 					 PHY_SHFT(unit))
 #define TXDCLK_PCLK_EN				BIT(0)
 
-#define COMPHY_REG_LANE_CFG4_ADDR	0x188
-#define LANE_CFG4_ADDR(unit)		(COMPHY_REG_LANE_CFG4_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_LANE_CFG4_ADDR		0x188
+#define LANE_CFG4_ADDR(unit)		(COMPHY_LANE_CFG4_ADDR * PHY_SHFT(unit))
 #define SPREAD_SPECTRUM_CLK_EN		BIT(7)
 
-#define COMPHY_REG_GLOB_PHY_CTRL0_ADDR	0x1C1
-#define GLOB_PHY_CTRL0_ADDR(unit)	(COMPHY_REG_GLOB_PHY_CTRL0_ADDR * \
+#define COMPHY_GLOB_PHY_CTRL0_ADDR	0x1C1
+#define GLOB_PHY_CTRL0_ADDR(unit)	(COMPHY_GLOB_PHY_CTRL0_ADDR * \
 					 PHY_SHFT(unit))
 #define SOFT_RESET			BIT(0)
 #define MODE_CORE_CLK_FREQ_SEL		BIT(9)
@@ -184,13 +178,13 @@
 #define MODE_REFDIV_MASK		(0x3 << MODE_REFDIV_OFFSET)
 #define MODE_REFDIV_BY_4		(0x2 << MODE_REFDIV_OFFSET)
 
-#define COMPHY_REG_TEST_MODE_CTRL_ADDR	0x1C2
-#define TEST_MODE_CTRL_ADDR(unit)	(COMPHY_REG_TEST_MODE_CTRL_ADDR * \
+#define COMPHY_TEST_MODE_CTRL_ADDR	0x1C2
+#define TEST_MODE_CTRL_ADDR(unit)	(COMPHY_TEST_MODE_CTRL_ADDR * \
 					 PHY_SHFT(unit))
 #define MODE_MARGIN_OVERRIDE		BIT(2)
 
-#define COMPHY_REG_GLOB_CLK_SRC_LO_ADDR	0x1C3
-#define GLOB_CLK_SRC_LO_ADDR(unit)	(COMPHY_REG_GLOB_CLK_SRC_LO_ADDR * \
+#define COMPHY_GLOB_CLK_SRC_LO_ADDR	0x1C3
+#define GLOB_CLK_SRC_LO_ADDR(unit)	(COMPHY_GLOB_CLK_SRC_LO_ADDR * \
 					 PHY_SHFT(unit))
 #define MODE_CLK_SRC			BIT(0)
 #define BUNDLE_PERIOD_SEL		BIT(1)
@@ -199,8 +193,8 @@
 #define PLL_READY_DLY			(BIT(5) | BIT(6) | BIT(7))
 #define CFG_SEL_20B			BIT(15)
 
-#define COMPHY_REG_PWR_MGM_TIM1_ADDR	0x1D0
-#define PWR_MGM_TIM1_ADDR(unit)		(COMPHY_REG_PWR_MGM_TIM1_ADDR * \
+#define COMPHY_PWR_MGM_TIM1_ADDR	0x1D0
+#define PWR_MGM_TIM1_ADDR(unit)		(COMPHY_PWR_MGM_TIM1_ADDR * \
 					 PHY_SHFT(unit))
 #define CFG_PM_OSCCLK_WAIT_OFF		12
 #define CFG_PM_OSCCLK_WAIT_LEN		4