refactor(drivers/marvell/comphy-3700): drop _REG prefixes and suffixes
Some register constants are defined with _REG suffix or REG_ prefix, but
others are not. Unify this by dropping these prefixes / suffixes.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I1ba331c0a4686093ee250bcaf3297349956ac9a8
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 95b9e8f..9bc1a5d 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -82,32 +82,30 @@
#define DATA_WIDTH_40BIT (0x2 << SEL_DATA_WIDTH_OFFSET)
#define PLL_READY_TX_BIT BIT(4)
-#define COMPHY_SYNC_PATTERN_REG 0x24
-#define SYNC_PATTERN_REG_ADDR(unit) (COMPHY_SYNC_PATTERN_REG * \
- PHY_SHFT(unit))
+#define COMPHY_SYNC_PATTERN 0x24
+#define SYNC_PATTERN_ADDR(unit) (COMPHY_SYNC_PATTERN * PHY_SHFT(unit))
#define TXD_INVERT_BIT BIT(10)
#define RXD_INVERT_BIT BIT(11)
-#define COMPHY_SYNC_MASK_GEN_REG 0x25
+#define COMPHY_SYNC_MASK_GEN 0x25
#define PHY_GEN_MAX_OFFSET 10
#define PHY_GEN_MAX_MASK (3 << PHY_GEN_MAX_OFFSET)
#define PHY_GEN_MAX_USB3_5G (1 << PHY_GEN_MAX_OFFSET)
-#define COMPHY_ISOLATION_CTRL_REG 0x26
-#define ISOLATION_CTRL_REG_ADDR(unit) (COMPHY_ISOLATION_CTRL_REG * \
- PHY_SHFT(unit))
+#define COMPHY_ISOLATION_CTRL 0x26
+#define ISOLATION_CTRL_ADDR(unit) (COMPHY_ISOLATION_REG * PHY_SHFT(unit))
#define PHY_ISOLATE_MODE BIT(15)
-#define COMPHY_REG_GEN2_SET_2 0x3e
-#define GEN2_SETTING_2_ADDR(unit) (COMPHY_REG_GEN2_SET_2 * PHY_SHFT(unit))
+#define COMPHY_GEN2_SET_2 0x3e
+#define GEN2_SETTING_2_ADDR(unit) (COMPHY_GEN2_SET_2 * PHY_SHFT(unit))
#define G2_TX_SSC_AMP_VALUE_20 BIT(14)
#define G2_TX_SSC_AMP_OFF 9
#define G2_TX_SSC_AMP_LEN 7
#define G2_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
G2_TX_SSC_AMP_OFF)
-#define COMPHY_REG_GEN3_SET_2 0x3f
-#define GEN3_SETTING_2_ADDR(unit) (COMPHY_REG_GEN3_SET_2 * PHY_SHFT(unit))
+#define COMPHY_GEN3_SET_2 0x3f
+#define GEN3_SETTING_2_ADDR(unit) (COMPHY_GEN3_SET_2 * PHY_SHFT(unit))
#define G3_TX_SSC_AMP_OFF 9
#define G3_TX_SSC_AMP_LEN 7
#define G3_TX_SSC_AMP_MASK (((1 << G2_TX_SSC_AMP_LEN) - 1) << \
@@ -123,9 +121,8 @@
#define RSVD_PH03FH_6_0_MASK (((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
RSVD_PH03FH_6_0_OFF)
-#define COMPHY_REG_UNIT_CTRL_ADDR 0x48
-#define UNIT_CTRL_ADDR(unit) (COMPHY_REG_UNIT_CTRL_ADDR * \
- PHY_SHFT(unit))
+#define COMPHY_UNIT_CTRL_ADDR 0x48
+#define UNIT_CTRL_ADDR(unit) (COMPHY_UNIT_CTRL_ADDR * PHY_SHFT(unit))
#define IDLE_SYNC_EN BIT(12)
#define UNIT_CTRL_DEFAULT_VALUE 0x60
@@ -141,21 +138,19 @@
#define MISC_REG1_ADDR(unit) (COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit))
#define SEL_BITS_PCIE_FORCE BIT(15)
-#define COMPHY_REG_GEN2_SETTINGS_3 0x112
+#define COMPHY_GEN2_SETTINGS_3 0x112
#define COMPHY_GEN_FFE_CAP_SEL_MASK 0xF
#define COMPHY_GEN_FFE_CAP_SEL_VALUE 0xF
-#define COMPHY_REG_LANE_CFG0_ADDR 0x180
-#define LANE_CFG0_ADDR(unit) (COMPHY_REG_LANE_CFG0_ADDR * \
- PHY_SHFT(unit))
+#define COMPHY_LANE_CFG0_ADDR 0x180
+#define LANE_CFG0_ADDR(unit) (COMPHY_LANE_CFG0_ADDR * PHY_SHFT(unit))
#define PRD_TXDEEMPH0_MASK BIT(0)
#define PRD_TXMARGIN_MASK (BIT(1) | BIT(2) | BIT(3))
#define PRD_TXSWING_MASK BIT(4)
#define CFG_TX_ALIGN_POS_MASK (BIT(5) | BIT(6) | BIT(7) | BIT(8))
-#define COMPHY_REG_LANE_CFG1_ADDR 0x181
-#define LANE_CFG1_ADDR(unit) (COMPHY_REG_LANE_CFG1_ADDR * \
- PHY_SHFT(unit))
+#define COMPHY_LANE_CFG1_ADDR 0x181
+#define LANE_CFG1_ADDR(unit) (COMPHY_LANE_CFG1_ADDR * PHY_SHFT(unit))
#define PRD_TXDEEMPH1_MASK BIT(15)
#define USE_MAX_PLL_RATE_EN BIT(9)
#define TX_DET_RX_MODE BIT(6)
@@ -163,18 +158,17 @@
#define GEN2_TX_DATA_DLY_DEFT (2 << 3)
#define TX_ELEC_IDLE_MODE_EN BIT(0)
-#define COMPHY_REG_LANE_STATUS1_ADDR 0x183
-#define LANE_STATUS1_ADDR(unit) (COMPHY_REG_LANE_STATUS1_ADDR * \
+#define COMPHY_LANE_STATUS1_ADDR 0x183
+#define LANE_STATUS1_ADDR(unit) (COMPHY_LANE_STATUS1_ADDR * \
PHY_SHFT(unit))
#define TXDCLK_PCLK_EN BIT(0)
-#define COMPHY_REG_LANE_CFG4_ADDR 0x188
-#define LANE_CFG4_ADDR(unit) (COMPHY_REG_LANE_CFG4_ADDR * \
- PHY_SHFT(unit))
+#define COMPHY_LANE_CFG4_ADDR 0x188
+#define LANE_CFG4_ADDR(unit) (COMPHY_LANE_CFG4_ADDR * PHY_SHFT(unit))
#define SPREAD_SPECTRUM_CLK_EN BIT(7)
-#define COMPHY_REG_GLOB_PHY_CTRL0_ADDR 0x1C1
-#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_REG_GLOB_PHY_CTRL0_ADDR * \
+#define COMPHY_GLOB_PHY_CTRL0_ADDR 0x1C1
+#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_GLOB_PHY_CTRL0_ADDR * \
PHY_SHFT(unit))
#define SOFT_RESET BIT(0)
#define MODE_CORE_CLK_FREQ_SEL BIT(9)
@@ -184,13 +178,13 @@
#define MODE_REFDIV_MASK (0x3 << MODE_REFDIV_OFFSET)
#define MODE_REFDIV_BY_4 (0x2 << MODE_REFDIV_OFFSET)
-#define COMPHY_REG_TEST_MODE_CTRL_ADDR 0x1C2
-#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_REG_TEST_MODE_CTRL_ADDR * \
+#define COMPHY_TEST_MODE_CTRL_ADDR 0x1C2
+#define TEST_MODE_CTRL_ADDR(unit) (COMPHY_TEST_MODE_CTRL_ADDR * \
PHY_SHFT(unit))
#define MODE_MARGIN_OVERRIDE BIT(2)
-#define COMPHY_REG_GLOB_CLK_SRC_LO_ADDR 0x1C3
-#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_REG_GLOB_CLK_SRC_LO_ADDR * \
+#define COMPHY_GLOB_CLK_SRC_LO_ADDR 0x1C3
+#define GLOB_CLK_SRC_LO_ADDR(unit) (COMPHY_GLOB_CLK_SRC_LO_ADDR * \
PHY_SHFT(unit))
#define MODE_CLK_SRC BIT(0)
#define BUNDLE_PERIOD_SEL BIT(1)
@@ -199,8 +193,8 @@
#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7))
#define CFG_SEL_20B BIT(15)
-#define COMPHY_REG_PWR_MGM_TIM1_ADDR 0x1D0
-#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_REG_PWR_MGM_TIM1_ADDR * \
+#define COMPHY_PWR_MGM_TIM1_ADDR 0x1D0
+#define PWR_MGM_TIM1_ADDR(unit) (COMPHY_PWR_MGM_TIM1_ADDR * \
PHY_SHFT(unit))
#define CFG_PM_OSCCLK_WAIT_OFF 12
#define CFG_PM_OSCCLK_WAIT_LEN 4