Merge changes I41001484,Ic734696a,I84741535,I85aaaf3a,Ibd5423b7, ... into integration
* changes:
feat(plat/mediatek/mt8186): add reboot function for PSCI
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
feat(plat/mediatek/mt8186): apply erratas for MT8186
feat(plat/mediatek/mt8186): add MCDI drivers
feat(plat/mediatek/mt8186): add CPU hotplug
feat(plat/mediatek/mt8186): add RTC drivers
fix(plat/mediatek/mt8186): extend MMU region size
feat(plat/mediatek/mt8186): add DCM driver
feat(plat/mediatek/mt8186): add pinctrl support
feat(plat/mediatek/mt8186): add sys_cirq support
feat(plat/mediatek/mt8186): initialize GIC
feat(plat/mediatek/mt8186): add SiP service
feat(plat/mediatek/mt8186): add pwrap and pmic driver
feat(plat/mediatek/mt8186): initialize delay_timer
feat(plat/mediatek/mt8186): initialize systimer
feat(plat/mediatek/mt8186): add EMI MPU basic driver
diff --git a/.cz.json b/.cz.json
index 5ac961e..3c28d3c 100644
--- a/.cz.json
+++ b/.cz.json
@@ -809,6 +809,10 @@
{
"title": "STM32 Image",
"scopes": ["stm32image", "tools/stm32image"]
+ },
+ {
+ "title": "fiptool",
+ "scopes": ["fiptool"]
}
]
},
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 08b6ba1..7075ca6 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -447,6 +447,10 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
it is still open.
+- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
+ CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
+ it is still open.
+
- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
index 3c315d5..bf1b460 100644
--- a/include/lib/cpus/aarch64/cortex_x2.h
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -15,6 +15,15 @@
#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
+ * CPU Extended Control register 2 specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
+
+#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
+#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
+#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
+
+/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index ab8d629..88116c3 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -56,6 +56,35 @@
endfunc check_errata_2002765
/* --------------------------------------------------
+ * Errata Workaround for Cortex X2 Errata #2058056.
+ * This applies to revisions r0p0, r1p0, and r2p0 and
+ * is open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0, x1, x17
+ * --------------------------------------------------
+ */
+func errata_cortex_x2_2058056_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_2058056
+ cbz x0, 1f
+
+ mrs x1, CORTEX_X2_CPUECTLR2_EL1
+ mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
+ msr CORTEX_X2_CPUECTLR2_EL1, x1
+
+1:
+ ret x17
+endfunc errata_cortex_x2_2058056_wa
+
+func check_errata_2058056
+ /* Applies to r0p0 - r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_2058056
+
+ /* --------------------------------------------------
* Errata Workaround for Cortex X2 Errata #2083908.
* This applies to revision r2p0 and is open.
* x0: variant[4:7] and revision[0:3] of current cpu.
@@ -115,6 +144,7 @@
* checking functions of each errata.
*/
report_errata ERRATA_X2_2002765, cortex_x2, 2002765
+ report_errata ERRATA_X2_2058056, cortex_x2, 2058056
report_errata ERRATA_X2_2083908, cortex_x2, 2083908
ldp x8, x30, [sp], #16
@@ -138,6 +168,11 @@
bl errata_cortex_x2_2002765_wa
#endif
+#if ERRATA_X2_2058056
+ mov x0, x18
+ bl errata_cortex_x2_2058056_wa
+#endif
+
#if ERRATA_X2_2083908
mov x0, x18
bl errata_cortex_x2_2083908_wa
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 98c78cd..dd06cb8 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -499,6 +499,10 @@
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
ERRATA_X2_2002765 ?=0
+# Flag to apply erratum 2058056 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
+ERRATA_X2_2058056 ?=0
+
# Flag to apply erratum 2083908 workaround during reset. This erratum applies
# to revision r2p0 of the Cortex-X2 cpu and is still open.
ERRATA_X2_2083908 ?=0
@@ -932,6 +936,10 @@
$(eval $(call assert_boolean,ERRATA_X2_2002765))
$(eval $(call add_define,ERRATA_X2_2002765))
+# Process ERRATA_X2_2058056 flag
+$(eval $(call assert_boolean,ERRATA_X2_2058056))
+$(eval $(call add_define,ERRATA_X2_2058056))
+
# Process ERRATA_X2_2083908 flag
$(eval $(call assert_boolean,ERRATA_X2_2083908))
$(eval $(call add_define,ERRATA_X2_2083908))
diff --git a/tools/fiptool/fiptool.c b/tools/fiptool/fiptool.c
index d92c31d..5c240b5 100644
--- a/tools/fiptool/fiptool.c
+++ b/tools/fiptool/fiptool.c
@@ -537,7 +537,7 @@
for (desc = image_desc_head; desc != NULL; desc = desc->next) {
image_t *image = desc->image;
- if (image == NULL)
+ if (image == NULL || (image->toc_e.size == 0ULL))
continue;
payload_size += image->toc_e.size;
entry_offset = (entry_offset + align - 1) & ~(align - 1);