Merge changes from topic "st_fixes" into integration
* changes:
fix(st): enable RTC clock before accessing nv counter
fix(st-crypto): use GENMASK_32 to define PKA registers masks
fix(st): update comment on encryption key
fix(st): allow crypto lib compilation in aarch64
fix(st-uart): allow 64 bit compilation
fix(st): reduce MMC block_buffer
fix(stm32mp13-fdts): cosmetic fixes in PLL nodes
fix(st): update dt_get_ddr_size() type
fix(nand): reset the SLC NAND
fix(st-crypto): do not read RNG data if it's not ready
diff --git a/drivers/mtd/nand/raw_nand.c b/drivers/mtd/nand/raw_nand.c
index 021e30b..3595c21 100644
--- a/drivers/mtd/nand/raw_nand.c
+++ b/drivers/mtd/nand/raw_nand.c
@@ -218,6 +218,18 @@
return -ETIMEDOUT;
}
+static int nand_reset(void)
+{
+ int ret;
+
+ ret = nand_send_cmd(NAND_CMD_RESET, NAND_TWB_MAX);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return nand_send_wait(PSEC_TO_MSEC(NAND_TRST_MAX), 0U);
+}
+
#if NAND_ONFI_DETECT
static uint16_t nand_check_crc(uint16_t crc, uint8_t *data_in,
unsigned int data_len)
@@ -265,18 +277,6 @@
return nand_read_data(id, size, true);
}
-static int nand_reset(void)
-{
- int ret;
-
- ret = nand_send_cmd(NAND_CMD_RESET, NAND_TWB_MAX);
- if (ret != 0) {
- return ret;
- }
-
- return nand_send_wait(PSEC_TO_MSEC(NAND_TRST_MAX), 0U);
-}
-
static int nand_read_param_page(void)
{
struct nand_param_page page;
@@ -346,11 +346,6 @@
int ret;
char id[4];
- ret = nand_reset();
- if (ret != 0) {
- return ret;
- }
-
ret = nand_read_id(ONFI_SIGNATURE_ADDR, (uint8_t *)id, sizeof(id));
if (ret != 0) {
return ret;
@@ -406,6 +401,8 @@
int nand_raw_init(unsigned long long *size, unsigned int *erase_size)
{
+ int ret;
+
rawnand_dev.nand_dev = get_nand_device();
if (rawnand_dev.nand_dev == NULL) {
return -EINVAL;
@@ -420,6 +417,11 @@
return -ENODEV;
}
+ ret = nand_reset();
+ if (ret != 0) {
+ return ret;
+ }
+
#if NAND_ONFI_DETECT
if (detect_onfi() != 0) {
WARN("Detect ONFI failed\n");
diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c
index 9124cf2..3054577 100644
--- a/drivers/st/crypto/stm32_pka.c
+++ b/drivers/st/crypto/stm32_pka.c
@@ -56,7 +56,7 @@
#define _PKA_IPIDR 0x1FF8U
/* PKA control register fields */
-#define _PKA_CR_MODE_MASK GENMASK(13, 8)
+#define _PKA_CR_MODE_MASK GENMASK_32(13, 8)
#define _PKA_CR_MODE_SHIFT 8U
#define _PKA_CR_MODE_ADD 0x9U
#define _PKA_CR_MODE_ECDSA_VERIF 0x26U
@@ -69,7 +69,7 @@
#define _PKA_SR_INITOK BIT(0)
/* PKA it flag fields (used in CR, SR and CLRFR) */
-#define _PKA_IT_MASK (GENMASK(21, 19) | BIT(17))
+#define _PKA_IT_MASK (GENMASK_32(21, 19) | BIT(17))
#define _PKA_IT_SHIFT 17U
#define _PKA_IT_OPERR BIT(21)
#define _PKA_IT_ADDRERR BIT(20)
@@ -77,9 +77,9 @@
#define _PKA_IT_PROCEND BIT(17)
/* PKA version register fields */
-#define _PKA_VERR_MAJREV_MASK GENMASK(7, 4)
+#define _PKA_VERR_MAJREV_MASK GENMASK_32(7, 4)
#define _PKA_VERR_MAJREV_SHIFT 4U
-#define _PKA_VERR_MINREV_MASK GENMASK(3, 0)
+#define _PKA_VERR_MINREV_MASK GENMASK_32(3, 0)
#define _PKA_VERR_MINREV_SHIFT 0U
/* RAM magic offset */
diff --git a/drivers/st/crypto/stm32_rng.c b/drivers/st/crypto/stm32_rng.c
index a9dc43f..1342fd4 100644
--- a/drivers/st/crypto/stm32_rng.c
+++ b/drivers/st/crypto/stm32_rng.c
@@ -187,6 +187,10 @@
count = 4U;
while (len != 0U) {
+ if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_DRDY) == 0U) {
+ break;
+ }
+
data32 = mmio_read_32(stm32_rng.base + RNG_DR);
count--;
diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts
index 0f06b67..1204692 100644
--- a/fdts/stm32mp135f-dk.dts
+++ b/fdts/stm32mp135f-dk.dts
@@ -223,20 +223,20 @@
};
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
- src = < CLK_PLL12_HSE >;
- divmn = < 2 65 >;
- frac = < 0x1400 >;
+ src = <CLK_PLL12_HSE>;
+ divmn = <2 65>;
+ frac = <0x1400>;
};
- pll3_vco_417_8Mhz: pll3-vco-417_8Mhz {
- src = < CLK_PLL3_HSE >;
- divmn = < 1 33 >;
- frac = < 0x1a04 >;
+ pll3_vco_417Mhz: pll3-vco-417Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 33>;
+ frac = <0x1a04>;
};
pll4_vco_600Mhz: pll4-vco-600Mhz {
- src = < CLK_PLL4_HSE >;
- divmn = < 1 49 >;
+ src = <CLK_PLL4_HSE>;
+ divmn = <1 49>;
};
};
@@ -258,11 +258,11 @@
compatible = "st,stm32mp1-pll";
reg = <1>;
- st,pll = < &pll2_cfg1 >;
+ st,pll = <&pll2_cfg1>;
pll2_cfg1: pll2_cfg1 {
- st,pll_vco = < &pll2_vco_1066Mhz >;
- st,pll_div_pqr = < 1 1 0 >;
+ st,pll_vco = <&pll2_vco_1066Mhz>;
+ st,pll_div_pqr = <1 1 0>;
};
};
@@ -271,11 +271,11 @@
compatible = "st,stm32mp1-pll";
reg = <2>;
- st,pll = < &pll3_cfg1 >;
+ st,pll = <&pll3_cfg1>;
pll3_cfg1: pll3_cfg1 {
- st,pll_vco = < &pll3_vco_417_8Mhz >;
- st,pll_div_pqr = < 1 16 1 >;
+ st,pll_vco = <&pll3_vco_417Mhz>;
+ st,pll_div_pqr = <1 16 1>;
};
};
@@ -284,11 +284,11 @@
compatible = "st,stm32mp1-pll";
reg = <3>;
- st,pll = < &pll4_cfg1 >;
+ st,pll = <&pll4_cfg1>;
pll4_cfg1: pll4_cfg1 {
- st,pll_vco = < &pll4_vco_600Mhz >;
- st,pll_div_pqr = < 11 59 5 >;
+ st,pll_vco = <&pll4_vco_600Mhz>;
+ st,pll_div_pqr = <11 59 5>;
};
};
};
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 0bcfece..86795d7 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -56,7 +56,7 @@
#if STM32MP_SDMMC || STM32MP_EMMC
static struct mmc_device_info mmc_info;
-static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
+static uint8_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
static io_block_dev_spec_t mmc_block_dev_spec = {
/* It's used as temp buffer in block driver */
diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h
index b7bf1d0..2d11653 100644
--- a/plat/st/common/include/stm32mp_dt.h
+++ b/plat/st/common/include/stm32mp_dt.h
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2020-2022, STMicroelectronics - All Rights Reserved
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -35,7 +35,7 @@
int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
int dt_get_stdout_uart_info(struct dt_node_info *info);
int dt_match_instance_by_compatible(const char *compatible, uintptr_t address);
-uint32_t dt_get_ddr_size(void);
+size_t dt_get_ddr_size(void);
uint32_t dt_get_pwr_vdd_voltage(void);
struct rdev *dt_get_vdd_regulator(void);
struct rdev *dt_get_cpu_regulator(void);
diff --git a/plat/st/common/stm32cubeprogrammer_uart.c b/plat/st/common/stm32cubeprogrammer_uart.c
index e4a5338..0916099 100644
--- a/plat/st/common/stm32cubeprogrammer_uart.c
+++ b/plat/st/common/stm32cubeprogrammer_uart.c
@@ -409,7 +409,7 @@
handle.addr = (uint8_t *)buffer;
handle.len = length;
- INFO("UART: read phase %u at 0x%lx size 0x%x\n",
+ INFO("UART: read phase %u at 0x%lx size 0x%zx\n",
id, buffer, length);
while (!start_done) {
ret = uart_receive_command(&command);
diff --git a/plat/st/common/stm32mp_crypto_lib.c b/plat/st/common/stm32mp_crypto_lib.c
index ea2b8db..e282115 100644
--- a/plat/st/common/stm32mp_crypto_lib.c
+++ b/plat/st/common/stm32mp_crypto_lib.c
@@ -80,7 +80,7 @@
}
static int get_plain_pk_from_asn1(void *pk_ptr, unsigned int pk_len, void **plain_pk,
- unsigned int *len, int *pk_alg)
+ size_t *len, int *pk_alg)
{
int ret;
mbedtls_pk_context mbedtls_pk = {0};
@@ -170,7 +170,15 @@
static int crypto_convert_pk(void *full_pk_ptr, unsigned int full_pk_len,
void **hashed_pk_ptr, unsigned int *hashed_pk_len)
{
- return get_plain_pk_from_asn1(full_pk_ptr, full_pk_len, hashed_pk_ptr, hashed_pk_len, NULL);
+ size_t len;
+ int ret;
+
+ ret = get_plain_pk_from_asn1(full_pk_ptr, full_pk_len, hashed_pk_ptr, &len, NULL);
+ if (ret == 0) {
+ *hashed_pk_len = (unsigned int)len;
+ }
+
+ return ret;
}
#else /* STM32MP_CRYPTO_ROM_LIB*/
static uint32_t verify_signature(uint8_t *hash_in, uint8_t *pubkey_in,
@@ -226,7 +234,7 @@
static uint8_t st_pk[CRYPTO_PUBKEY_MAX_SIZE + sizeof(uint32_t)];
int ret;
void *plain_pk;
- unsigned int len;
+ size_t len;
int curve_id;
uint32_t cid;
@@ -241,7 +249,7 @@
memcpy(st_pk + sizeof(cid), plain_pk, len);
*hashed_pk_ptr = st_pk;
- *hashed_pk_len = len + sizeof(cid);
+ *hashed_pk_len = (unsigned int)(len + sizeof(cid));
return 0;
}
@@ -339,15 +347,15 @@
return CRYPTO_ERR_SIGNATURE;
}
- ret = get_plain_pk_from_asn1(pk_ptr, pk_len, &pk_ptr, &pk_len, &curve_id);
+ ret = get_plain_pk_from_asn1(pk_ptr, pk_len, &pk_ptr, &len, &curve_id);
if (ret != 0) {
VERBOSE("%s: get_plain_pk_from_asn1 (%d)\n", __func__, ret);
return CRYPTO_ERR_SIGNATURE;
}
/* We expect a known pk_len */
- if (pk_len != sizeof(my_pk)) {
- VERBOSE("%s: pk_len=%u sizeof(my_pk)=%zu)\n", __func__, pk_len, sizeof(my_pk));
+ if (len != sizeof(my_pk)) {
+ VERBOSE("%s: pk_len=%zu sizeof(my_pk)=%zu)\n", __func__, len, sizeof(my_pk));
return CRYPTO_ERR_SIGNATURE;
}
@@ -483,7 +491,7 @@
/*
* Not a real derivation yet
*
- * But we expect a 32 bytes key, and OTP is only 16 bytes
+ * We expect a 32 bytes key, if OTP is only 16 bytes
* => duplicate.
*/
for (i = 0U, j = len; j < 32U;
@@ -517,7 +525,7 @@
}
if (otp_len > (*key_len * CHAR_BIT)) {
- VERBOSE("%s: length Error otp_len=%u key_len=%u\n", __func__,
+ VERBOSE("%s: length Error otp_len=%u key_len=%zu\n", __func__,
otp_len, *key_len * CHAR_BIT);
return -EINVAL;
}
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 34d52e1..1cbf51b 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -228,9 +228,9 @@
* This function gets DDR size information from the DT.
* Returns value in bytes on success, and 0 on failure.
******************************************************************************/
-uint32_t dt_get_ddr_size(void)
+size_t dt_get_ddr_size(void)
{
- static uint32_t size;
+ static size_t size;
int node;
if (size != 0U) {
@@ -240,12 +240,12 @@
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read DDR node in DT\n", __func__);
- return 0;
+ return 0U;
}
- size = fdt_read_uint32_default(fdt, node, "st,mem-size", 0U);
+ size = (size_t)fdt_read_uint32_default(fdt, node, "st,mem-size", 0U);
- flush_dcache_range((uintptr_t)&size, sizeof(uint32_t));
+ flush_dcache_range((uintptr_t)&size, sizeof(size_t));
return size;
}
diff --git a/plat/st/common/stm32mp_trusted_boot.c b/plat/st/common/stm32mp_trusted_boot.c
index 051d6fc..6d89290 100644
--- a/plat/st/common/stm32mp_trusted_boot.c
+++ b/plat/st/common/stm32mp_trusted_boot.c
@@ -10,6 +10,7 @@
#include <common/debug.h>
#include <common/tbbr/cot_def.h>
+#include <drivers/clk.h>
#include <drivers/st/stm32_hash.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
@@ -171,16 +172,20 @@
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
{
+ clk_enable(TAMP_BKP_REG_CLK);
*nv_ctr = mmio_read_32(TAMP_BASE + TAMP_COUNTR);
+ clk_disable(TAMP_BKP_REG_CLK);
return 0;
}
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
{
+ clk_enable(TAMP_BKP_REG_CLK);
while (mmio_read_32(TAMP_BASE + TAMP_COUNTR) != nv_ctr) {
mmio_write_32(TAMP_BASE + TAMP_COUNTR, 1U);
}
+ clk_disable(TAMP_BKP_REG_CLK);
return 0;
}