diff --git a/plat/hisilicon/hikey/hikey_ddr.c b/plat/hisilicon/hikey/hikey_ddr.c
index e688c15..cd9e9a2 100644
--- a/plat/hisilicon/hikey/hikey_ddr.c
+++ b/plat/hisilicon/hikey/hikey_ddr.c
@@ -138,7 +138,7 @@
 	mmio_write_32((0xf6504000 + 0x06c), data);
 
 	data = mmio_read_32((0xf6504000 + 0x06c));
-	data &= ~(0xffffff << 8);
+	data &= ~(0xffffffu << 8);
 	data |= 0xc7a << 8;
 	mmio_write_32((0xf6504000 + 0x06c), data);
 
diff --git a/plat/hisilicon/hikey/include/hi6220_regs_ao.h b/plat/hisilicon/hikey/include/hi6220_regs_ao.h
index 132f33c..614eba2 100644
--- a/plat/hisilicon/hikey/include/hi6220_regs_ao.h
+++ b/plat/hisilicon/hikey/include/hi6220_regs_ao.h
@@ -222,14 +222,14 @@
 #define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK		(1 << 27)
 #define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK			(1 << 28)
 #define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK			(1 << 29)
-#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK			(1 << 31)
+#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK			(1U << 31)
 
 #define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR			(1 << 26)
 #define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR			(1 << 27)
 #define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR			(1 << 28)
 #define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR			(1 << 29)
 #define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR			(1 << 30)
-#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR			(1 << 31)
+#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR			(1U << 31)
 
 #define AO_SC_SYS_STAT0_MCU_RST_STAT				(1 << 25)
 #define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT			(1 << 26)
@@ -237,7 +237,7 @@
 #define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT			(1 << 28)
 #define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT			(1 << 29)
 #define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT			(1 << 30)
-#define AO_SC_SYS_STAT0_GLB_SRST_STAT				(1 << 31)
+#define AO_SC_SYS_STAT0_GLB_SRST_STAT				(1U << 31)
 
 #define AO_SC_SYS_STAT1_MODE_STATUS				(1 << 0)
 #define AO_SC_SYS_STAT1_BOOT_SEL_LOCK				(1 << 16)
@@ -308,7 +308,7 @@
 #define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH			(1 << 28)
 #define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON			(1 << 29)
 #define AO_SC_PERIPH_CLKEN4_CLK_PDM				(1 << 30)
-#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD				(1 << 31)
+#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD				(1U << 31)
 
 #define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU			(1 << 0)
 #define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU			(1 << 1)
diff --git a/plat/hisilicon/hikey/include/hi6220_regs_peri.h b/plat/hisilicon/hikey/include/hi6220_regs_peri.h
index 8711ae4..77236e8 100644
--- a/plat/hisilicon/hikey/include/hi6220_regs_peri.h
+++ b/plat/hisilicon/hikey/include/hi6220_regs_peri.h
@@ -134,7 +134,7 @@
 #define PERI_CTRL4_OTG_SESSEND			(1 << 28)
 #define PERI_CTRL4_OTG_BVALID			(1 << 29)
 #define PERI_CTRL4_OTG_AVALID			(1 << 30)
-#define PERI_CTRL4_OTG_VBUSVALID		(1 << 31)
+#define PERI_CTRL4_OTG_VBUSVALID		(1U << 31)
 
 /* PERI_SC_PERIPH_CTRL5 */
 #define PERI_CTRL5_USBOTG_RES_SEL		(1 << 3)
diff --git a/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c b/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
index bcf6865..91d8033 100644
--- a/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
+++ b/plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c
@@ -23,7 +23,7 @@
 #define RES2_LOCK_BASE		(SOC_PCTRL_RESOURCE2_LOCK_ADDR(PCTRL_BASE))
 
 #define LOCK_BIT			(0x1 << 28)
-#define LOCK_ID_MASK			(0x7 << 29)
+#define LOCK_ID_MASK			(0x7u << 29)
 #define CPUIDLE_LOCK_ID(core)		(0x6 - (core))
 #define LOCK_UNLOCK_OFFSET		0x4
 #define LOCK_STAT_OFFSET		0x8
diff --git a/plat/hisilicon/hikey960/include/hi3660.h b/plat/hisilicon/hikey960/include/hi3660.h
index 5b9305a..7cc1ee0 100644
--- a/plat/hisilicon/hikey960/include/hi3660.h
+++ b/plat/hisilicon/hikey960/include/hi3660.h
@@ -67,7 +67,7 @@
 #define SCTRL_SCPERDIS1_REG		(SCTRL_REG_BASE + 0x174)
 #define SCTRL_SCPEREN1_REG		(SCTRL_REG_BASE + 0x170)
 #define SCTRL_SCPERDIS1_REG		(SCTRL_REG_BASE + 0x174)
-#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS	(1 << 31)
+#define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS	(1u << 31)
 #define SCPEREN_GT_PCLK_MMBUFCFG	(1 << 25)
 #define SCPEREN_GT_PCLK_MMBUF		(1 << 23)
 #define SCPEREN_GT_ACLK_MMBUF		(1 << 22)
diff --git a/plat/hisilicon/hikey960/include/hi3660_crg.h b/plat/hisilicon/hikey960/include/hi3660_crg.h
index ec587aa..eb5a6c5 100644
--- a/plat/hisilicon/hikey960/include/hi3660_crg.h
+++ b/plat/hisilicon/hikey960/include/hi3660_crg.h
@@ -11,7 +11,7 @@
 #define CRG_PEREN0_REG			(CRG_REG_BASE + 0x000)
 #define CRG_PERDIS0_REG			(CRG_REG_BASE + 0x004)
 #define CRG_PERSTAT0_REG		(CRG_REG_BASE + 0x008)
-#define PEREN0_GT_CLK_AOMM		(1 << 31)
+#define PEREN0_GT_CLK_AOMM		(1U << 31)
 
 #define CRG_PEREN1_REG			(CRG_REG_BASE + 0x010)
 #define CRG_PERDIS1_REG			(CRG_REG_BASE + 0x014)
@@ -62,7 +62,7 @@
 #define CRG_PERRSTSTAT5_REG		(CRG_REG_BASE + 0x0A4)
 
 /* bit fields in CRG_PERI */
-#define PERI_PCLK_PCTRL_BIT		(1 << 31)
+#define PERI_PCLK_PCTRL_BIT		(1U << 31)
 #define PERI_TIMER12_BIT		(1 << 25)
 #define PERI_TIMER11_BIT		(1 << 24)
 #define PERI_TIMER10_BIT		(1 << 23)
diff --git a/plat/hisilicon/hikey960/include/hi3660_hkadc.h b/plat/hisilicon/hikey960/include/hi3660_hkadc.h
index 4d2de4a..dc9e813 100644
--- a/plat/hisilicon/hikey960/include/hi3660_hkadc.h
+++ b/plat/hisilicon/hikey960/include/hi3660_hkadc.h
@@ -13,7 +13,7 @@
 #define HKADC_DSP_START_CLR_REG			(HKADC_SSI_REG_BASE + 0x01C)
 #define HKADC_WR01_DATA_REG			(HKADC_SSI_REG_BASE + 0x020)
 
-#define WR1_WRITE_MODE				(1 << 31)
+#define WR1_WRITE_MODE				(1U << 31)
 #define WR1_READ_MODE				(0 << 31)
 #define WR1_ADDR(x)				(((x) & 0x7F) << 24)
 #define WR1_DATA(x)				(((x) & 0xFF) << 16)
@@ -47,7 +47,7 @@
 
 #define HKADC_WR01_VALUE			((HKADC_START_ADDR << 24) | \
 						 (0x1 << 16))
-#define HKADC_WR23_VALUE			((0x1 << 31) |		\
+#define HKADC_WR23_VALUE			((0x1u << 31) |		\
 						 (HKADC_DATA0_ADDR << 24) | \
 						 (1 << 15) |		\
 						 (HKADC_DATA1_ADDR << 8))