Update hisilicon drivers to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.
Change-Id: I67984b6c48c08af61e95a4dbd18047e2c3151f9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
diff --git a/plat/hisilicon/hikey/hikey_ddr.c b/plat/hisilicon/hikey/hikey_ddr.c
index e688c15..cd9e9a2 100644
--- a/plat/hisilicon/hikey/hikey_ddr.c
+++ b/plat/hisilicon/hikey/hikey_ddr.c
@@ -138,7 +138,7 @@
mmio_write_32((0xf6504000 + 0x06c), data);
data = mmio_read_32((0xf6504000 + 0x06c));
- data &= ~(0xffffff << 8);
+ data &= ~(0xffffffu << 8);
data |= 0xc7a << 8;
mmio_write_32((0xf6504000 + 0x06c), data);
diff --git a/plat/hisilicon/hikey/include/hi6220_regs_ao.h b/plat/hisilicon/hikey/include/hi6220_regs_ao.h
index 132f33c..614eba2 100644
--- a/plat/hisilicon/hikey/include/hi6220_regs_ao.h
+++ b/plat/hisilicon/hikey/include/hi6220_regs_ao.h
@@ -222,14 +222,14 @@
#define AO_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
#define AO_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
#define AO_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
-#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
+#define AO_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1U << 31)
#define AO_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
#define AO_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
#define AO_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
#define AO_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
#define AO_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
-#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
+#define AO_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1U << 31)
#define AO_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
#define AO_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
@@ -237,7 +237,7 @@
#define AO_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
#define AO_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
#define AO_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
-#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
+#define AO_SC_SYS_STAT0_GLB_SRST_STAT (1U << 31)
#define AO_SC_SYS_STAT1_MODE_STATUS (1 << 0)
#define AO_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
@@ -308,7 +308,7 @@
#define AO_SC_PERIPH_CLKEN4_CLK_JTAG_AUTH (1 << 28)
#define AO_SC_PERIPH_CLKEN4_CLK_CS_DAPB_ON (1 << 29)
#define AO_SC_PERIPH_CLKEN4_CLK_PDM (1 << 30)
-#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1 << 31)
+#define AO_SC_PERIPH_CLKEN4_CLK_SSI_PAD (1U << 31)
#define AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU (1 << 0)
#define AO_SC_PERIPH_CLKEN5_PCLK_EFUSEC_CCPU (1 << 1)
diff --git a/plat/hisilicon/hikey/include/hi6220_regs_peri.h b/plat/hisilicon/hikey/include/hi6220_regs_peri.h
index 8711ae4..77236e8 100644
--- a/plat/hisilicon/hikey/include/hi6220_regs_peri.h
+++ b/plat/hisilicon/hikey/include/hi6220_regs_peri.h
@@ -134,7 +134,7 @@
#define PERI_CTRL4_OTG_SESSEND (1 << 28)
#define PERI_CTRL4_OTG_BVALID (1 << 29)
#define PERI_CTRL4_OTG_AVALID (1 << 30)
-#define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
+#define PERI_CTRL4_OTG_VBUSVALID (1U << 31)
/* PERI_SC_PERIPH_CTRL5 */
#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)