Merge "plat: marvell: armada: a3k: improve 4GB DRAM usage from 3.375 GB to 3.75 GB" into integration
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index 712b162..74cf78a 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2018-2020 Marvell International Ltd.
+# Copyright (C) 2018-2021 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
@@ -38,7 +38,6 @@
-I$/drivers/arm/gic/common/
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
- $(MARVELL_COMMON_BASE)/marvell_cci.c \
$(MARVELL_DRV_BASE)/uart/a3700_console.S
BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
@@ -50,12 +49,14 @@
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
+ $(PLAT_COMMON_BASE)/plat_cci.c \
$(PLAT_COMMON_BASE)/plat_pm.c \
$(PLAT_COMMON_BASE)/dram_win.c \
$(PLAT_COMMON_BASE)/io_addr_dec.c \
$(PLAT_COMMON_BASE)/marvell_plat_config.c \
$(PLAT_COMMON_BASE)/a3700_ea.c \
$(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \
+ $(MARVELL_COMMON_BASE)/marvell_cci.c \
$(MARVELL_COMMON_BASE)/marvell_ddr_info.c \
$(MARVELL_COMMON_BASE)/marvell_gicv3.c \
$(MARVELL_GIC_SOURCES) \
diff --git a/plat/marvell/armada/a3k/common/dram_win.c b/plat/marvell/armada/a3k/common/dram_win.c
index 694f6d4..e89f295 100644
--- a/plat/marvell/armada/a3k/common/dram_win.c
+++ b/plat/marvell/armada/a3k/common/dram_win.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -92,33 +92,35 @@
},
/*
- * If total dram size is more than 2GB, now there is only one case - 4GB
- * dram; we will use below cpu windows configurations:
- * - Internal Regs, CCI-400, Boot Rom and PCIe windows are kept as
- * default;
- * - Use 4 CPU decode windows for DRAM, which cover 3.375GB DRAM;
- * DDR window 0 is configured in tim header with 2GB size, no need to
- * configure it again here;
+ * If total DRAM size is more than 2GB, now there is only one case:
+ * 4GB of DRAM; to better utilize address space (for maximization of
+ * DRAM usage), we will use the configuration of CPU windows below:
+ * - Internal Regs and Boot ROM windows are kept as default;
+ * - CCI-400 is moved from its default address to another address
+ * (this is actually done even if DRAM size is not more than 2 GB,
+ * because the firmware is compiled with that address as a
+ * constant);
+ * - PCIe window is moved to another address;
+ * - Use 4 CPU decode windows for DRAM, which cover 3.75GB DRAM;
+ * DDR window 0 is configured in tim header with 2G B size, no need
+ * to configure it again here;
*
- * 0xFFFFFFFF ---> |-----------------------|
- * | Boot ROM | 64KB
+ * 0xFFFFFFFF ---> +-----------------------+
+ * | Boot ROM | 64 KB
* 0xFFF00000 ---> +-----------------------+
* : :
- * 0xF0000000 ---> |-----------------------|
- * | PCIE | 128 MB
- * 0xE8000000 ---> |-----------------------|
- * | DDR window 3 | 128 MB
- * 0xE0000000 ---> +-----------------------+
+ * 0xFE010000 ---> +-----------------------+
+ * | CCI Regs | 64 KB
+ * 0xFE000000 ---> +-----------------------+
* : :
- * 0xD8010000 ---> |-----------------------|
- * | CCI Regs | 64 KB
- * 0xD8000000 ---> +-----------------------+
- * : :
- * : :
+ * 0xFA000000 ---> +-----------------------+
+ * | PCIE | 128 MB
+ * 0xF2000000 ---> +-----------------------+
+ * | DDR window 3 | 512 MB
* 0xD2000000 ---> +-----------------------+
- * | Internal Regs | 32MB
+ * | Internal Regs | 32 MB
* 0xD0000000 ---> |-----------------------|
- * | DDR window 2 | 256 MB
+ * | DDR window 2 | 256 MB
* 0xC0000000 ---> |-----------------------|
* | |
* | DDR window 1 | 1 GB
@@ -155,14 +157,14 @@
0xc0000000},
{CPU_WIN_ENABLED,
CPU_WIN_TARGET_DRAM,
- 0xe0000000,
- 0x08000000,
- 0xe0000000},
+ 0xd2000000,
+ 0x20000000,
+ 0xd2000000},
{CPU_WIN_ENABLED,
CPU_WIN_TARGET_PCIE,
- 0xe8000000,
+ 0xf2000000,
0x08000000,
- 0xe8000000},
+ 0xf2000000},
},
};
diff --git a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
index d23f5be..83d9561 100644
--- a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2020 Marvell International Ltd.
+ * Copyright (C) 2018-2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -41,8 +41,14 @@
#define MVEBU_GICR_BASE 0x1D40000
#define MVEBU_GICC_BASE 0x1D80000
-/* CCI-400 */
-#define MVEBU_CCI_BASE 0x8000000
+/*
+ * CCI-400 base address
+ * This address is absolute, not relative to MVEBU_REGS_BASE.
+ * This is not the default CCI base address (that would be 0xD8000000).
+ * Rather we remap CCI to this address to better utilize the address space.
+ * (The remapping is done in plat/marvell/armada/a3k/common/plat_cci.c)
+ */
+#define MVEBU_CCI_BASE 0xFE000000
/*****************************************************************************
* North and south bridge register base
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index 3d839f8..057ee2e 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2016-2019 Marvell International Ltd.
+ * Copyright (C) 2016-2021 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -148,7 +148,7 @@
#define PLAT_MARVELL_SHARED_RAM_CACHED 1
/* CCI related constants */
-#define PLAT_MARVELL_CCI_BASE (MVEBU_REGS_BASE + MVEBU_CCI_BASE)
+#define PLAT_MARVELL_CCI_BASE MVEBU_CCI_BASE
#define PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX 3
#define PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX 4
@@ -227,6 +227,8 @@
#define CPU_DEC_RLR_REMAP_LOW_MASK \
(0xffff << CPU_DEC_BR_BASE_OFFS)
+#define CPU_DEC_CCI_BASE_REG (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
+
/* Securities */
#define IRQ_SEC_OS_TICK_INT MARVELL_IRQ_SEC_PHY_TIMER
diff --git a/plat/marvell/armada/a3k/common/plat_cci.c b/plat/marvell/armada/a3k/common/plat_cci.c
new file mode 100644
index 0000000..56f091f
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/plat_cci.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2021 Marek Behun <marek.behun@nic.cz>
+ *
+ * Based on plat/marvell/armada/common/marvell_cci.c
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <drivers/arm/cci.h>
+#include <lib/mmio.h>
+
+#include <plat_marvell.h>
+
+static const int cci_map[] = {
+ PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX,
+ PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX
+};
+
+/*
+ * This redefines the weak definition in
+ * plat/marvell/armada/common/marvell_cci.c
+ */
+void plat_marvell_interconnect_init(void)
+{
+ /*
+ * To better utilize the address space, we remap CCI base address from
+ * the default (0xD8000000) to MVEBU_CCI_BASE.
+ * This has to be done here, rather than in cpu_wins_init(), because
+ * cpu_wins_init() is called later.
+ */
+ mmio_write_32(CPU_DEC_CCI_BASE_REG, MVEBU_CCI_BASE >> 20);
+
+ cci_init(PLAT_MARVELL_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
+}