tree 9501cb13945c36cde5055faccc905d1c0076da2f
parent f270d6bfaecd1c576be2852cd95ac60fea3cf55f
author Andre Przywara <andre.przywara@arm.com> 1475769293 +0100
committer Andre Przywara <andre.przywara@arm.com> 1490007466 +0000

Add workaround for ARM Cortex-A53 erratum 855873

ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and invalidate" instructions.
For core revisions of r0p3 and later this can be done by setting a bit
in the CPUACTLR_EL1 register, so that hardware takes care of the promotion.
As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3,
we set the bit in firmware.
Also we dump this register upon crashing to provide more debug
information.

Enable the workaround for the Juno boards.

Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>