Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration
* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2
diff --git a/Makefile b/Makefile
index 6b1f47c..d73fc87 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 2
-VERSION_MINOR := 10
+VERSION_MINOR := 11
# VERSION_PATCH is only used for LTS releases
VERSION_PATCH := 0
VERSION := ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
@@ -35,6 +35,17 @@
# Configure the toolchains used to build TF-A and its tools
################################################################################
+#
+# The clean and check targets do not behave correctly if the user's environment
+# does not appropriately configure a toolchain. While we try to find a permanent
+# solution to this, do not try to detect any toolchains if we are building
+# exclusively with targets which do not use any toolchain tools.
+#
+
+ifeq ($(filter-out check% %clean doc %tool,$(or $(MAKECMDGOALS),all)),)
+ toolchains :=
+endif
+
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
# Assertions enabled for DEBUG builds by default
@@ -299,7 +310,7 @@
-fsanitize-undefined-trap-on-error
endif #(${SANITIZE_UB},trap)
-GCC_V_OUTPUT := $(shell $($(ARCH)-cc) -v 2>&1)
+GCC_V_OUTPUT := $(if $($(ARCH)-cc),$(shell $($(ARCH)-cc) -v 2>&1))
TF_LDFLAGS += -z noexecstack
@@ -372,6 +383,15 @@
################################################################################
include lib/compiler-rt/compiler-rt.mk
+# Allow overriding the timestamp, for example for reproducible builds, or to
+# synchronize timestamps across multiple projects.
+# This must be set to a C string (including quotes where applicable).
+BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
+
+DEFINES += -DBUILD_MESSAGE_TIMESTAMP='$(BUILD_MESSAGE_TIMESTAMP)'
+DEFINES += -DBUILD_MESSAGE_VERSION_STRING='"$(VERSION_STRING)"'
+DEFINES += -DBUILD_MESSAGE_VERSION='"$(VERSION)"'
+
BL_COMMON_SOURCES += common/bl_common.c \
common/tf_log.c \
common/${ARCH}/debug.S \
@@ -898,10 +918,6 @@
endif
endif #(CTX_INCLUDE_PAUTH_REGS)
-ifeq ($(PSA_FWU_SUPPORT),1)
- $(info PSA_FWU_SUPPORT is an experimental feature)
-endif #(PSA_FWU_SUPPORT)
-
ifeq ($(FEATURE_DETECTION),1)
$(info FEATURE_DETECTION is an experimental feature)
endif #(FEATURE_DETECTION)
@@ -1008,6 +1024,10 @@
$(info PSA_CRYPTO is an experimental feature)
endif
+ifeq ($(DICE_PROTECTION_ENVIRONMENT),1)
+ $(info DICE_PROTECTION_ENVIRONMENT is an experimental feature)
+endif
+
################################################################################
# Process platform overrideable behaviour
################################################################################
@@ -1197,6 +1217,8 @@
ENABLE_CONSOLE_GETC \
INIT_UNUSED_NS_EL2 \
PLATFORM_REPORT_CTX_MEM_USE \
+ EARLY_CONSOLE \
+ PRESERVE_DSU_PMU_REGS \
)))
# Numeric_Flags
@@ -1320,6 +1342,8 @@
PSCI_EXTENDED_STATE_ID \
PSCI_OS_INIT_MODE \
RESET_TO_BL31 \
+ RME_GPT_BITLOCK_BLOCK \
+ RME_GPT_MAX_BLOCK \
SEPARATE_CODE_AND_RODATA \
SEPARATE_BL2_NOLOAD_REGION \
SEPARATE_NOBITS_REGION \
@@ -1394,6 +1418,8 @@
ENABLE_CONSOLE_GETC \
INIT_UNUSED_NS_EL2 \
PLATFORM_REPORT_CTX_MEM_USE \
+ EARLY_CONSOLE \
+ PRESERVE_DSU_PMU_REGS \
)))
ifeq (${PLATFORM_REPORT_CTX_MEM_USE}, 1)
@@ -1682,7 +1708,7 @@
endif #(UNIX_MK)
romlib.bin: libraries FORCE
- ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
+ ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES=$(call escape-shell,$(INCLUDES)) DEFINES=$(call escape-shell,$(DEFINES)) --no-print-directory -C ${ROMLIBPATH} all
memmap: all
ifdef UNIX_MK
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 6fe5511..2b3a827 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#include <arch_helpers.h>
#include <bl1/bl1.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
#include <drivers/auth/crypto_mod.h>
@@ -39,31 +40,13 @@
#endif
/*******************************************************************************
- * Helper utility to calculate the BL2 memory layout taking into consideration
- * the BL1 RW data assuming that it is at the top of the memory layout.
- ******************************************************************************/
-void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
-
- /*
- * Remove BL1 RW data from the scope of memory visible to BL2.
- * This is assuming BL1 RW data is at the top of bl1_mem_layout.
- */
- assert(BL1_RW_BASE > bl1_mem_layout->total_base);
- bl2_mem_layout->total_base = bl1_mem_layout->total_base;
- bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
-
- flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
-}
-
-/*******************************************************************************
* Setup function for BL1.
******************************************************************************/
void bl1_setup(void)
{
+ /* Enable early console if EARLY_CONSOLE flag is enabled */
+ plat_setup_early_console();
+
/* Perform early platform-specific setup */
bl1_early_platform_setup();
@@ -94,7 +77,7 @@
/* Announce our arrival */
NOTICE(FIRMWARE_WELCOME_STR);
- NOTICE("BL1: %s\n", version_string);
+ NOTICE("BL1: %s\n", build_version_string);
NOTICE("BL1: %s\n", build_message);
INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 923a554..f12c1a5 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <bl1/bl1.h>
#include <bl2/bl2.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
#include <drivers/auth/crypto_mod.h>
@@ -41,6 +42,9 @@
void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
{
+ /* Enable early console if EARLY_CONSOLE flag is enabled */
+ plat_setup_early_console();
+
/* Perform early platform-specific setup */
bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3);
@@ -63,6 +67,9 @@
void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
{
+ /* Enable early console if EARLY_CONSOLE flag is enabled */
+ plat_setup_early_console();
+
/* Perform early platform-specific setup */
bl2_early_platform_setup2(arg0, arg1, arg2, arg3);
@@ -92,7 +99,7 @@
PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_ENTRY, PMF_CACHE_MAINT);
#endif
- NOTICE("BL2: %s\n", version_string);
+ NOTICE("BL2: %s\n", build_version_string);
NOTICE("BL2: %s\n", build_message);
/* Perform remaining generic architectural setup in S-EL1 */
diff --git a/bl2u/bl2u_main.c b/bl2u/bl2u_main.c
index fcb73b9..cd13def 100644
--- a/bl2u/bl2u_main.c
+++ b/bl2u/bl2u_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <bl1/bl1.h>
#include <bl2u/bl2u.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
#include <drivers/console.h>
@@ -27,7 +28,7 @@
******************************************************************************/
void bl2u_main(void)
{
- NOTICE("BL2U: %s\n", version_string);
+ NOTICE("BL2U: %s\n", build_version_string);
NOTICE("BL2U: %s\n", build_message);
#if SCP_BL2U_BASE
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 962c362..e47b082 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -450,7 +450,7 @@
*
* handler = (base + off) + (index << log2(size))
*/
- adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
+ adr_l x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
lsl w10, w15, #RT_SVC_SIZE_LOG2
ldr x15, [x11, w10, uxtw]
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index cd61d01..40add91 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -52,13 +52,17 @@
${SPMC_SOURCES} \
${SPM_SOURCES}
+VENDOR_EL3_SRCS += services/el3/ven_el3_svc.c
+
ifeq (${ENABLE_PMF}, 1)
-BL31_SOURCES += lib/pmf/pmf_main.c
+BL31_SOURCES += lib/pmf/pmf_main.c \
+ ${VENDOR_EL3_SRCS}
endif
include lib/debugfs/debugfs.mk
ifeq (${USE_DEBUGFS},1)
- BL31_SOURCES += $(DEBUGFS_SRCS)
+BL31_SOURCES += ${DEBUGFS_SRCS} \
+ ${VENDOR_EL3_SRCS}
endif
ifeq (${PLATFORM_REPORT_CTX_MEM_USE},1)
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 9807817..83be0f6 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#include <bl31/bl31.h>
#include <bl31/ehf.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <common/feat_detect.h>
#include <common/runtime_svc.h>
@@ -94,6 +95,9 @@
void bl31_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
u_register_t arg3)
{
+ /* Enable early console if EARLY_CONSOLE flag is enabled */
+ plat_setup_early_console();
+
/* Perform early platform-specific setup */
bl31_early_platform_setup2(arg0, arg1, arg2, arg3);
@@ -128,7 +132,7 @@
/* Init per-world context registers for non-secure world */
manage_extensions_nonsecure_per_world();
- NOTICE("BL31: %s\n", version_string);
+ NOTICE("BL31: %s\n", build_version_string);
NOTICE("BL31: %s\n", build_message);
#if FEATURE_DETECTION
@@ -211,8 +215,6 @@
*/
bl31_prepare_next_image_entry();
- console_flush();
-
/*
* Perform any platform specific runtime setup prior to cold boot exit
* from BL31
@@ -220,9 +222,12 @@
bl31_plat_runtime_setup();
#if ENABLE_RUNTIME_INSTRUMENTATION
- PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_EXIT, PMF_CACHE_MAINT);
console_flush();
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_EXIT, PMF_CACHE_MAINT);
#endif
+
+ console_flush();
+ console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/*******************************************************************************
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index 474b4d5..47a555a 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -36,7 +36,7 @@
{
u_register_t hcr_el2 = read_hcr_el2();
- return ((read_feat_vhe_id_field() != 0U) && ((hcr_el2 & HCR_TGE_BIT) != 0U));
+ return ((is_feat_vhe_present()) && ((hcr_el2 & HCR_TGE_BIT) != 0U));
}
/*
@@ -116,7 +116,7 @@
/* If FEAT_BTI is present, clear BTYPE bits */
new_spsr |= old_spsr & (SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
- if (is_armv8_5_bti_present()) {
+ if (is_feat_bti_present()) {
new_spsr &= ~(SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
}
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index 693dd4b..ba9d90d 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -118,8 +118,7 @@
mov r1, r10
mov r2, r11
mov r3, r12
- bl sp_min_early_platform_setup2
- bl sp_min_plat_arch_setup
+ bl sp_min_setup
/* Jump to the main function */
bl sp_min_main
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index 427e39b..b1f4343 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -13,16 +13,17 @@
INCLUDES += -Iinclude/bl32/sp_min
-BL32_SOURCES += bl32/sp_min/sp_min_main.c \
- bl32/sp_min/aarch32/entrypoint.S \
- common/runtime_svc.c \
- plat/common/aarch32/plat_sp_min_common.c\
+BL32_SOURCES += bl32/sp_min/sp_min_main.c \
+ bl32/sp_min/aarch32/entrypoint.S \
+ common/runtime_svc.c \
+ plat/common/aarch32/plat_sp_min_common.c \
services/arm_arch_svc/arm_arch_svc_setup.c \
- services/std_svc/std_svc_setup.c \
+ services/std_svc/std_svc_setup.c \
${PSCI_LIB_SOURCES}
ifeq (${ENABLE_PMF}, 1)
-BL32_SOURCES += lib/pmf/pmf_main.c
+BL32_SOURCES += services/el3/ven_el3_svc.c \
+ lib/pmf/pmf_main.c
endif
ifneq (${ENABLE_FEAT_AMU},0)
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c
index 26cf207..a26910c 100644
--- a/bl32/sp_min/sp_min_main.c
+++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <context.h>
@@ -170,12 +171,26 @@
}
/******************************************************************************
+ * The SP_MIN setup function. Calls platforms init functions
+ *****************************************************************************/
+void sp_min_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
+ u_register_t arg3)
+{
+ /* Enable early console if EARLY_CONSOLE flag is enabled */
+ plat_setup_early_console();
+
+ /* Perform early platform-specific setup */
+ sp_min_early_platform_setup2(arg0, arg1, arg2, arg3);
+ sp_min_plat_arch_setup();
+}
+
+/******************************************************************************
* The SP_MIN main function. Do the platform and PSCI Library setup. Also
* initialize the runtime service framework.
*****************************************************************************/
void sp_min_main(void)
{
- NOTICE("SP_MIN: %s\n", version_string);
+ NOTICE("SP_MIN: %s\n", build_version_string);
NOTICE("SP_MIN: %s\n", build_message);
/* Perform the SP_MIN platform setup */
diff --git a/bl32/sp_min/sp_min_private.h b/bl32/sp_min/sp_min_private.h
index 628581a..9c6b5fb 100644
--- a/bl32/sp_min/sp_min_private.h
+++ b/bl32/sp_min/sp_min_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,10 @@
#ifndef SP_MIN_PRIVATE_H
#define SP_MIN_PRIVATE_H
+#include <stdint.h>
+
+void sp_min_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
+ u_register_t arg3);
void sp_min_main(void);
void sp_min_warm_boot(void);
void sp_min_fiq(void);
diff --git a/bl32/tsp/tsp_common.c b/bl32/tsp/tsp_common.c
index 908b4ff..3a6c9d9 100644
--- a/bl32/tsp/tsp_common.c
+++ b/bl32/tsp/tsp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,6 +66,9 @@
******************************************************************************/
void tsp_setup(void)
{
+ /* Enable early console if EARLY_CONSOLE flag is enabled */
+ plat_setup_early_console();
+
/* Perform early platform-specific setup. */
tsp_early_platform_setup();
diff --git a/bl32/tsp/tsp_ffa_main.c b/bl32/tsp/tsp_ffa_main.c
index 1c8c68f..8273060 100644
--- a/bl32/tsp/tsp_ffa_main.c
+++ b/bl32/tsp/tsp_ffa_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <arch_helpers.h>
#include <bl32/tsp/tsp.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include "ffa_helpers.h"
#include <lib/psci/psci.h>
@@ -554,7 +555,7 @@
{
smc_args_t smc_args = {0};
- NOTICE("TSP: %s\n", version_string);
+ NOTICE("TSP: %s\n", build_version_string);
NOTICE("TSP: %s\n", build_message);
INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE);
INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE);
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 805575a..ae38d69 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -12,6 +12,7 @@
#include <arch_helpers.h>
#include <bl32/tsp/tsp.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <lib/spinlock.h>
#include <plat/common/platform.h>
@@ -27,7 +28,7 @@
******************************************************************************/
uint64_t tsp_main(void)
{
- NOTICE("TSP: %s\n", version_string);
+ NOTICE("TSP: %s\n", build_version_string);
NOTICE("TSP: %s\n", build_message);
INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE);
INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE);
diff --git a/changelog.yaml b/changelog.yaml
index bfcfcdb..6f2458e 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -152,11 +152,15 @@
- title: Self-hosted Trace Extensions (FEAT_TRF)
scope: trf
+ - title: DynamIQ Shared Unit (DSU)
+ scope: dsu
+
- title: Platforms
scope: platforms
deprecated:
- plat/common
+ - plat
subsections:
- title: Allwinner
@@ -222,6 +226,9 @@
- title: SGI-575
scope: sgi575
+ - title: RD-E1-Edge
+ scope: rde1edge
+
- title: RD-N1-Edge
scope: rdn1edge
@@ -237,6 +244,9 @@
deprecated:
- board/rdn2
+ deprecated:
+ - neoverse
+
- title: TC
scope: tc
@@ -504,6 +514,13 @@
- title: LS1088AQDS
scope: ls1088aqds
+ - title: S32G274A
+ scope: s32g274a
+
+ subsections:
+ - title: S32G274ARDB
+ scope: s32g274ardb
+
- title: QEMU
scope: qemu
@@ -644,12 +661,11 @@
- plat/xilinx/versal
- plat/versal
- subsections:
- - title: Versal NET
- scope: versal-net
+ - title: Versal NET
+ scope: versal-net
- deprecated:
- - versal_net
+ deprecated:
+ - versal_net
- title: ZynqMP
scope: zynqmp
@@ -745,6 +761,9 @@
deprecated:
- errata_abi
+ - title: ChromeOS
+ scope: cros
+
- title: Libraries
scope: lib
@@ -827,6 +846,9 @@
- title: Firmware Handoff
scope: handoff
+ - title: Exception Handling Framework (EHF)
+ scope: ehf
+
- title: Drivers
subsections:
@@ -957,11 +979,12 @@
deprecated:
- drivers/arm/mhu
- - title: RSS
- scope: rss
+ - title: RSE
+ scope: rse
deprecated:
- drivers/arm/rss
+ - rss
- title: TZC
scope: tzc
diff --git a/common/bl_common.c b/common/bl_common.c
index 8fce02f..fe4de0a 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,7 @@
#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
#include <drivers/io/io_storage.h>
@@ -275,6 +276,5 @@
*/
const char *get_version(void)
{
- extern const char version[];
- return version;
+ return build_version;
}
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 7f01037..09088c9 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -70,37 +70,187 @@
#endif
}
-/****************************************************
- * Feature : FEAT_BTI (Branch Target Identification)
- ***************************************************/
-static void read_feat_bti(void)
+static unsigned int read_feat_rng_trap_id_field(void)
{
-#if (ENABLE_BTI == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_5_bti_present(), "BTI");
-#endif
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
+ ID_AA64PFR1_EL1_RNDR_TRAP_MASK);
}
-/**************************************************
- * Feature : FEAT_RME (Realm Management Extension)
- *************************************************/
-static void read_feat_rme(void)
+static unsigned int read_feat_bti_id_field(void)
{
-#if (ENABLE_RME == FEAT_STATE_ALWAYS)
- feat_detect_panic((get_armv9_2_feat_rme_support() !=
- ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED), "RME");
-#endif
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT,
+ ID_AA64PFR1_EL1_BT_MASK);
}
-/******************************************************************
- * Feature : FEAT_RNG_TRAP (Trapping support for RNDR/RNDRRS)
- *****************************************************************/
-static void read_feat_rng_trap(void)
+static unsigned int read_feat_sb_id_field(void)
{
-#if (ENABLE_FEAT_RNG_TRAP == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_feat_rng_trap_present(), "RNG_TRAP");
-#endif
+ return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT,
+ ID_AA64ISAR1_SB_MASK);
}
+static unsigned int read_feat_csv2_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT,
+ ID_AA64PFR0_CSV2_MASK);
+}
+
+static unsigned int read_feat_pmuv3_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT,
+ ID_AA64DFR0_PMUVER_MASK);
+}
+
+static unsigned int read_feat_vhe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT,
+ ID_AA64MMFR1_EL1_VHE_MASK);
+}
+
+static unsigned int read_feat_sve_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT,
+ ID_AA64PFR0_SVE_MASK);
+}
+
+static unsigned int read_feat_ras_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT,
+ ID_AA64PFR0_RAS_MASK);
+}
+
+static unsigned int read_feat_dit_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT,
+ ID_AA64PFR0_DIT_MASK);
+}
+
+static unsigned int read_feat_amu_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT,
+ ID_AA64PFR0_AMU_MASK);
+}
+
+static unsigned int read_feat_mpam_version(void)
+{
+ return (unsigned int)((((read_id_aa64pfr0_el1() >>
+ ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
+ ((read_id_aa64pfr1_el1() >>
+ ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
+}
+
+static unsigned int read_feat_nv_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT,
+ ID_AA64MMFR2_EL1_NV_MASK);
+}
+
+static unsigned int read_feat_sel2_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT,
+ ID_AA64PFR0_SEL2_MASK);
+}
+
+static unsigned int read_feat_trf_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT,
+ ID_AA64DFR0_TRACEFILT_MASK);
+}
+static unsigned int get_armv8_5_mte_support(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT,
+ ID_AA64PFR1_EL1_MTE_MASK);
+}
+static unsigned int read_feat_rng_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT,
+ ID_AA64ISAR0_RNDR_MASK);
+}
+static unsigned int read_feat_fgt_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT,
+ ID_AA64MMFR0_EL1_FGT_MASK);
+}
+static unsigned int read_feat_ecv_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT,
+ ID_AA64MMFR0_EL1_ECV_MASK);
+}
+static unsigned int read_feat_twed_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT,
+ ID_AA64MMFR1_EL1_TWED_MASK);
+}
+
+static unsigned int read_feat_hcx_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT,
+ ID_AA64MMFR1_EL1_HCX_MASK);
+}
+static unsigned int read_feat_tcr2_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT,
+ ID_AA64MMFR3_EL1_TCRX_MASK);
+}
+static unsigned int read_feat_s2pie_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT,
+ ID_AA64MMFR3_EL1_S2PIE_MASK);
+}
+static unsigned int read_feat_s1pie_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT,
+ ID_AA64MMFR3_EL1_S1PIE_MASK);
+}
+static unsigned int read_feat_s2poe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT,
+ ID_AA64MMFR3_EL1_S2POE_MASK);
+}
+static unsigned int read_feat_s1poe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT,
+ ID_AA64MMFR3_EL1_S1POE_MASK);
+}
+static unsigned int read_feat_brbe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT,
+ ID_AA64DFR0_BRBE_MASK);
+}
+static unsigned int read_feat_trbe_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT,
+ ID_AA64DFR0_TRACEBUFFER_MASK);
+}
+static unsigned int read_feat_sme_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT,
+ ID_AA64PFR1_EL1_SME_MASK);
+}
+static unsigned int read_feat_gcs_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT,
+ ID_AA64PFR1_EL1_GCS_MASK);
+}
+
+static unsigned int read_feat_rme_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT,
+ ID_AA64PFR0_FEAT_RME_MASK);
+}
+
+static unsigned int read_feat_pan_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT,
+ ID_AA64MMFR1_EL1_PAN_MASK);
+}
+
+static unsigned int read_feat_mtpmu_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
+ ID_AA64DFR0_MTPMU_MASK);
+
+}
+
/***********************************************************************************
* TF-A supports many Arm architectural features starting from arch version
* (8.0 till 8.7+). These features are mostly enabled through build flags. This
@@ -151,6 +301,7 @@
check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2);
/* v8.3 features */
+ /* TODO: Pauth yet to convert to tri-state feat detect logic */
read_feat_pauth();
/* v8.4 features */
@@ -170,8 +321,9 @@
check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), "MTE2",
MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), "RNG", 1, 1);
- read_feat_bti();
- read_feat_rng_trap();
+ check_feature(ENABLE_BTI, read_feat_bti_id_field(), "BTI", 1, 1);
+ check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
+ "RNG_TRAP", 1, 1);
/* v8.6 features */
check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
@@ -219,8 +371,7 @@
/* v9.4 features */
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);
-
- read_feat_rme();
+ check_feature(ENABLE_RME, read_feat_rme_id_field(), "RME", 1, 1);
if (tainted) {
panic();
diff --git a/docs/about/features.rst b/docs/about/features.rst
index c12509d..9b7bdf9 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -128,7 +128,7 @@
in a platform:
- MPU translation library ``lib/xlat_mpu``
-- RSS comms driver ``drivers/arm/rss``
+- RSE comms driver ``drivers/arm/rse``
Still to come
-------------
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 4a8169b..85cc612 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -63,8 +63,8 @@
:|G|: `bipinravi-arm`_
:|M|: Joanna Farley <joanna.farley@arm.com>
:|G|: `joannafarley-arm`_
-:|M|: Okash Khawaja <okash@google.com>
-:|G|: `bytefire`_
+:|M|: Jidong Sun <jidong@google.com>
+:|G|: `jidongsun`_
:|M|: Varun Wadekar <vwadekar@nvidia.com>
:|G|: `vwadekar`_
:|M|: Yann Gautier <yann.gautier@st.com>
@@ -114,6 +114,8 @@
:|M|: Marc Bonnici <marc.bonnici@arm.com>
:|G|: `marcbonnici`_
:|F|: services/std_svc/spm/el3_spmc/\*
+:|F|: include/services/el3_spmc\_\*
+:|F|: include/services/spmc_svc.h
Secure Partition Manager Dispatcher (SPMD)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -121,7 +123,13 @@
:|G|: `odeprez`_
:|M|: Joao Alves <Joao.Alves@arm.com>
:|G|: `J-Alves`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
:|F|: services/std_svc/spmd/\*
+:|F|: plat/common/plat_spmd_manifest.c
+:|F|: include/services/ffa_svc.h
+:|F|: include/services/el3_spmd_logical_sp.h
+:|F|: include/services/spmd_svc.h
Exception Handling Framework (EHF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -131,6 +139,16 @@
:|G|: `manish-pandey-arm`_
:|F|: bl31/ehf.c
+Runtime Exceptions and Interrupt Management
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: bl31/aarch64/
+:|F|: bl31/interrupt_mgmt.c
+:|F|: include/bl31/interrupt_mgmt.h
+
Realm Management Monitor Dispatcher (RMMD)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
@@ -216,12 +234,14 @@
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
:|F|: lib/psci/
+:|F|: include/lib/psci/
DebugFS
^^^^^^^
:|M|: Olivier Deprez <olivier.deprez@arm.com>
:|G|: `odeprez`_
:|F|: lib/debugfs/
+:|F|: include/lib/debugfs.h
Firmware Configuration Framework (FCONF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -232,6 +252,10 @@
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
:|F|: lib/fconf/
+:|F|: plat/arm/common/fconf/
+:|F|: include/lib/fconf/
+:|F|: include/plat/arm/common/arm_fconf\_\*
+:|F|: include/plat/arm/common/fconf\_\*
Performance Measurement Framework (PMF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -253,6 +277,7 @@
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
:|F|: lib/cpus/
+:|F|: include/lib/cpus/
Reliability Availability Serviceabilty (RAS) framework
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -337,12 +362,12 @@
:|F|: include/drivers/arm/mhu.h
:|F|: drivers/arm/mhu
-Runtime Security Subsystem (RSS) comms driver
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Runtime Security Engine (RSE) comms driver
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: David Vincze <david.vincze@arm.com>
:|G|: `davidvincze`_
-:|F|: include/drivers/arm/rss_comms.h
-:|F|: drivers/arm/rss
+:|F|: include/drivers/arm/rse_comms.h
+:|F|: drivers/arm/rse
Libfdt wrappers
^^^^^^^^^^^^^^^
@@ -380,6 +405,8 @@
:|M|: Manish Pandey <manish.pandey2@arm.com>
:|G|: `manish-pandey-arm`_
:|F|: services/std_svc/drtm
+:|F|: include/plat/common/plat_drtm.h
+:|F|: include/services/drtm_svc.h
PSA Firmware Update
^^^^^^^^^^^^^^^^^^^
@@ -433,6 +460,32 @@
:|F|: lib/transfer_list
:|F|: include/lib/transfer_list.h
+Context Management
+^^^^^^^^^^^^^^^^^^
+:|M|: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
+:|G|: `jayanthchidanand-arm`_
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: bl1/aarch32/bl1_context_mgmt.c
+:|F|: bl1/aarch64/bl1_context_mgmt.c
+:|F|: bl31/bl31_context_mgmt.c
+:|F|: lib/el3_runtime/
+:|F|: include/lib/el3_runtime/
+
+Runtime Services
+^^^^^^^^^^^^^^^^
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: services/std_svc/std_svc_setup.c
+:|F|: common/runtime_svc.c
+:|F|: include/common/runtime_svc.h
+:|F|: include/services/arm_arch_svc.h
+:|F|: include/services/std_svc.h
+
Platform Ports
~~~~~~~~~~~~~~
@@ -577,8 +630,6 @@
MediaTek platform ports
^^^^^^^^^^^^^^^^^^^^^^^
-:|M|: Rex-BC Chen <rex-bc.chen@mediatek.com>
-:|G|: `mtk-rex-bc-chen`_
:|M|: Leon Chen <leon.chen@mediatek.com>
:|G|: `leon-chen-mtk`_
:|M|: Jason-CH Chen <jason-ch.chen@mediatek.com>
@@ -606,7 +657,6 @@
:|M|: Avi Fishman <avi.fishman@nuvoton.com>
:|G|: `avifishman`_
:|F|: docs/plat/npcm845x.rst
-:|F|: drivers/nuvoton/
:|F|: include/drivers/nuvoton/
:|F|: include/plat/nuvoton/
:|F|: plat/nuvoton/
@@ -712,6 +762,15 @@
:|F|: plat/nxp/soc-ls1088a/ls1088ardb
:|F|: plat/nxp/soc-ls1088a/ls1088aqds
+NXP SoC Part S32G274A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
+:|G|: `gprocopciucnxp`_
+:|F|: docs/plat/s32g274a.rst
+:|F|: drivers/nxp/console/linflex_console.S
+:|F|: include/drivers/nxp/console/linflex.h
+:|F|: plat/nxp/s32
+
QEMU platform port
^^^^^^^^^^^^^^^^^^
:|M|: Jens Wiklander <jens.wiklander@linaro.org>
@@ -976,7 +1035,7 @@
.. _bijucdas: https://github.com/bijucdas
.. _bipinravi-arm: https://github.com/bipinravi-arm
.. _bryanodonoghue: https://github.com/bryanodonoghue
-.. _bytefire: https://github.com/bytefire
+.. _jidongsun: https://github.com/jidongsun
.. _carlocaione: https://github.com/carlocaione
.. _chandnich: https://github.com/chandnich
.. _ChiaweiW: https://github.com/chiaweiw
@@ -985,6 +1044,7 @@
.. _davidvincze: https://github.com/davidvincze
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
+.. _gprocopciucnxp: https://github.com/gprocopciucnxp
.. _grandpaul: https://github.com/grandpaul
.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
@@ -1020,7 +1080,6 @@
.. _michalsimek: https://github.com/michalsimek
.. _mmind: https://github.com/mmind
.. _MrVan: https://github.com/MrVan
-.. _mtk-rex-bc-chen: https://github.com/mtk-rex-bc-chen
.. _Neal-liu: https://github.com/neal-liu
.. _niej: https://github.com/niej
.. _nmenon: https://github.com/nmenon
@@ -1054,3 +1113,7 @@
.. _vwadekar: https://github.com/vwadekar
.. _xueliang-zhong-arm: https://github.com/xueliang-zhong-arm
.. _Yann-lms: https://github.com/Yann-lms
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/change-log.md b/docs/change-log.md
index cfc8c56..1e6647f 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,6 +3,924 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+## [2.11.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.10.0..refs/tags/v2.11.0) (2024-05-17)
+
+### âš BREAKING CHANGES
+
+- **Architecture**
+
+ - **Memory Tagging Extension2**
+
+ - Any platform or downstream code trying to use
+ SCR_EL3.ATA bit(26) will see failures as this is now moved to be
+ used only with FEAT_MTE2 with
+ commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2
+
+ **See:** remove mte, mte_perm ([c282384](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c282384dbb45b6185b4aba14efebbad110d18e49))
+
+- **Services**
+
+ - **SPM**
+
+ - **SPMD**
+
+ - Given the optimizations made in TF-A SPMD to simplify NS EL1 context
+ management, platform integrators must use SPMC binaries built by
+ picking commits after 2fc6dcfa97e05159f95859fcf68db3031586f8c7 from
+ hafnium repository.
+
+ **See:** skip NS EL1 context save & restore operations ([2d960a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d960a11601be6e7f24c38d84b2a4fdbb52efb9b))
+
+- **Drivers**
+
+ - **Arm**
+
+ - **RSE**
+
+ - remove PLAT_RSS_NOT_SUPPORTED build option
+
+ **See:** remove PLAT_RSS_NOT_SUPPORTED build option ([878354a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/878354a845cbc51c198b879d3d92ed472e21889c))
+
+ - **FWU**
+
+ - add a config flag for including image info in the FWU metadata ([11d05a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11d05a77295885f27530cf07029ebc2b36f49918))
+ - add a function to obtain an alternate FWU bank to boot ([26aab79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26aab79560a2281c4207b01102495459c2bddefc))
+ - add some sanity checks for the FWU metadata ([d2566cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2566cfb896672ea07c31c37e7acd9ef77abc4fb))
+ - document the config flag for including image info in the FWU metadata ([7ae1619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ae16196cc73a580f298734bb98f2ccb210e3ba9))
+ - migrate FWU metadata structure to version 2 ([a89d58b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a89d58bb204c00db260225859bce0b55aa5e2385))
+
+### New Features
+
+- **Architecture**
+
+ - **CPU feature / ID register handling in general**
+
+ - add cortex-a35 l2 extended control register ([a727d59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a727d59d9c1ef5ecf2f221ce289506da2011dda1))
+ - add feature detection for FEAT_CSV2_3 ([30019d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30019d8698b219d4a642dc59e7178006f59654ff))
+ - added few helper functions ([30f05b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30f05b4f5db605ddc1a3ca0ae0cbd13ed0e728b6))
+
+ - **DynamIQ Shared Unit (DSU)**
+
+ - save/restore DSU PMU register ([f99a69c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f99a69c386ce5448edfc47eaf146d1a20ac8216e))
+
+ - **Memory Tagging Extension2**
+
+ - add mte2 feat ([8e39788](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e3978899a481484d8c60bf276be503aebd43afb))
+
+- **Platforms**
+
+ - update SZ_* macros ([6d511a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d511a8c31f0d792695566ae75c8f7b08b3b7236))
+
+ - **Arm**
+
+ - add COT_DESC_IN_DTB option for CCA CoT ([b76a43c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b76a43c9382e85969cac896cd4d5d6774d0d1553))
+ - add trusty_sp_fw_config build option ([0686a01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0686a01b0cacb9aab840a5c334409b5739a95a97))
+ - move GPT setup to common BL source ([341df6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/341df6af6eb911ffd175e129f61fc59efcf9fcea))
+ - retrieve GPT related data from platform ([86e4859](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86e4859a05614b40ff3cf38f8bd4efc856c546fe))
+ - support FW handoff b/w BL1 & BL2 ([9c11ed7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c11ed7e3e5536ad1fcb9190560e0368da9c5ab5))
+ - support FW handoff b/w BL2 & BL31 ([a5566f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5566f65fd1be689ca5c63baa1f5b61b40960c8d))
+ - add platform API that gets cluster ID ([e6ae019](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6ae019a84c4d2ad2d2825b32fbcbe304752e3ae))
+
+ - **CSS**
+
+ - initialise generic timer early in the boot ([3447ba1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3447ba1f0405a8590ec31e4b79737efe151c3d5b))
+
+ - **FVP**
+
+ - add CCA CoT in DTB support ([4c79b86](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c79b86ed6a36b572cf9e96f0269eb5dd0b46d5f))
+ - add stdout-path ([8c30a0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c30a0c7fe0162de0618b26fb34cc91ea582e5f7))
+ - add support for virto-net, virtio-9p and virtio-rng ([51b8b9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/51b8b9c3c46cec87ebb7b484727c80ff29d73057))
+ - added calls to unprotect/protect memory ([6873088](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6873088c2cd6983025b6777d4c3bde912eade571))
+ - delegate FFH RAS handling to SP ([d07d4d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d07d4d63374b0d155b9281f9fcaf6b44f18117c8))
+ - remove left-over RSS usage ([a1726fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1726fa7ffecdcc8f8f4d09bd0bdc97ef3b72f11))
+
+ - **Neoverse-RD**
+
+ - add scope for RD-V1 ([86a4949](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86a4949fd012a9912c8bf909d14e20657bba2240))
+ - add scope for RD-V1-MC ([6fb16da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fb16dac6e6672040ec80f85f2f337f52cf3f3d3))
+ - add scope for SGI-575 ([18b5070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18b50707f7732a8b3deb46d8d011566199711c0b))
+ - disable SPMD_SPM_AT_SEL2 for A75/V1/N1 platforms ([b9c3273](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9c32730e5b7efe5170ed3c0dda7ab9db397c478))
+ - disable SPMD_SPM_AT_SEL2 for N2/V2 platforms ([301c017](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/301c01748ea717d0f2cf3ba1f0a2fe389b6fb155))
+ - enable AMU if supported by the platform ([fed9368](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fed9368529e5bc2c9111ac5a743688166661fd8f))
+ - remove unused SGI_PLAT build-option ([2d32517](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d32517ce64886f154c6d509f80d0fcde05dc498))
+
+ - **SGI-575**
+
+ - remove SGI-575 from deprecated list ([f104eec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f104eecdea209af87de43c62811a0a9456f2838c))
+
+ - **RD-E1-Edge**
+
+ - remove support for RD-E1-Edge ([c69253c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c69253cc3ad3063380c8f905125fe85f6d942d09))
+
+ - **RD-N1-Edge**
+
+ - remove RD-N1-Edge from deprecated list ([78b7939](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/78b793956f3a86a3dd62394c858ae9ee41379b8b))
+
+ - **RD-N2**
+
+ - enable NEOVERSE_Nx_EXTERNAL_LLC flag ([ab2b363](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab2b3632171dd5488952ba3f68693e490857e9dc))
+ - add dts for secure partition ([49df726](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49df7261be44d5199a930c95667edb6b878355d1))
+ - enable AMU if present on the platform ([2cfedfa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2cfedfad9c2c59316adf17d4f0ee561b50a041b6))
+ - enable MTE2 if present on the platform ([3a5b375](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a5b3753033561cb5d7cd7aace634cc66eab0fa7))
+ - update power message value to 0 ([08f6398](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/08f6398b2b9566812cd110498e3135dfc2e3e494))
+
+ - **TC**
+
+ - add arm_ffa node in dts ([4fc4e9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fc4e9c969930d83f1144441199301d3b4b34a5a))
+ - add DPE backend to the measured boot framework ([e7f1181](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7f1181f8a7729acb07ebac86944e36932bcd09e))
+ - add DPE context handle node to device tree ([1f47a71](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f47a7133f7fe7fb038aca97fc93533964b2b429))
+ - add dummy TRNG support to be able to boot pVMs ([7be391d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7be391d1ce5683c717fcf2be584f3d294ebc2bf3))
+ - add firmware update secure partition ([d062872](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0628728a627ee11c97839640d404221a74c3a65))
+ - add memory node in the device tree ([5ee4deb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ee4deb8e69175f57fa51519ef37e3674aa6b9a0))
+ - add PMU entry ([553b06b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/553b06b5d4f7ec8e49796e0ffdf081bf5cf30d53))
+ - add RSS SDS region right after SCMI payload ([6f503e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6f503e0eea23a2663ed5cbfe9b925e1e0d65c236))
+ - add save/restore DSU PMU register support ([b87d7ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b87d7ab13f4b03f872c3c4a3dd7c755baf3a38d3))
+ - add SCMI power domain and IOMMU toggles ([a658b46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a658b46dc74ceaa51d119bd7bd9eccdefb0cc455))
+ - add spmc manifest with trusty sp ([ba197f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba197f5f708fe8e033971c6f4d5b25f6783aaa45))
+ - add TC3 platform definitions ([62320dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62320dc4fd2c13d9f4b227fe73cad2a79bdba42c))
+ - allow booting from DRAM ([18f754a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18f754a275083ea66823b1c9f39e234cf430140e))
+ - choose the DPU address and irq based on the target ([8e94163](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e94163ec041f2d7df41c2dfd8625c06655ba08e))
+ - enable gpu/dpu scmi power domain and also gpu perf domain ([127eabe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/127eabeddfc4fb596a1b499fe68ee6f7e5b5b6d5))
+ - factor in FVP/FPGA differences ([1b8ed09](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b8ed0993fc5c04f76d949df7e2851e67040bbf9))
+ - get the parent component provided DPE context_handle ([467bdf2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/467bdf26b64a38cfbfb3bf8ab915eb97eb6b3037))
+ - group components into certificates ([6df8d76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6df8d7647dad5c347d363554d25e590d24eb05e5))
+ - interrupt numbers for `smmu_700` ([2c406dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c406ddaf700e0f1c80535e309a2245b9e0bee92))
+ - introduce an FPGA subvariant and TC3 CPUs ([a02bb36](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a02bb36caa521259ae57a904dedb7fd4e6a51340))
+ - pass the DTB address to BL33 in R0 ([638e4a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/638e4a92d80346b4d46ef2cc5fbb7941d1b7fd31))
+ - provide a mock mbedtls-random generation function ([a877818](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8778185d2fd2b80cee8af7879ecb92be1aa3898))
+ - share DPE context handle with child component ([03d388d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03d388d8e3eb5c6cce65afba060a16fae83d4d12))
+
+ - **Intel**
+
+ - add in QSPI ECC for Linux ([4d122e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d122e5f199ad1531650ae11de5121057cfc0855))
+ - enable query of fip offset on RSU ([6cbe2c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cbe2c5d19c4af0ba6bbba049962bf55454da8bb))
+ - enable SDMMC frontdoor load for ATF->Linux ([32a87d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32a87d440087e0a71765a61ec341af7cfcfbda97))
+ - increase bl2 size limit ([2d46b2e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d46b2e46189120b6779cd27ec6bd6ec9901f72c))
+ - restructure watchdog ([47ca43b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47ca43bcb4565a992bf527f68e1ff60fc036fd12))
+ - support QSPI ECC Linux for Agilex ([d6ae69c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6ae69c8c69016d05d64752538aad53f319b88a2))
+ - support QSPI ECC Linux for N5X ([6cf16b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cf16b36821b9f2a60ed9abbaa593ef62b8b9f2b))
+ - support QSPI ECC Linux for Stratix10 ([8be16e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8be16e44cf0143e8651090d80bd14194aa78b1f2))
+ - support query of fip offset using RSU ([62be2a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62be2a1ae3efcba0bb8b7ec8ef73b2a0f5a437e3))
+ - support SDM mailbox safe inject seu error for Linux ([fffcb25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fffcb25c3c2171624c582d92173154f570708a9a))
+ - support wipe DDR after calibration ([68bb3e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68bb3e836e93b271f9f1c05787025dd3f04dd788))
+
+ - **MediaTek**
+
+ - remove bl32 flag for mtk_bl ([9c41cc1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c41cc182dd7acf541565ab3df7a4261fb7eaf1b))
+
+ - **MT8188**
+
+ - add secure iommu support ([5fb5ff5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5fb5ff5694c1bcf0ddfc972600b69d7494ca6645))
+ - remove apusys kernel handler usage constraints ([0c77651](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c77651fb47c7ffd4b1b37a74aea77373179ab5d))
+
+ - **NXP**
+
+ - **i.MX**
+
+ - **i.MX 8M**
+
+ - add 3600 MTps DDR PLL rate ([f1bb459](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1bb459c3192eb6b3fc6b9b77658d82227eae2d5))
+ - add defines for csu_sa access security ([81de503](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81de50372c9192098118fc8bddaf086a620add87))
+ - add imx csu_sa enum type defines for imx8m ([2ac4909](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ac4909a5ec0a50a75cab9bb587fb1b8e592794d))
+ - make bl33 start configurable via PRELOADED_BL33_BASE ([9260a8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9260a8c818aadbf513b2744cad978c18d0f65a8e))
+ - obtain boot image set for imx8mn/mp ([6d2c502](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d2c502afb845e7af94c610ab5a375b868c885ba))
+
+ - **i.MX 8M Mini**
+
+ - restrict peripheral access to secure world ([1156c76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1156c76361c170c83c6b9a9dd7c22aa401a4ce2e))
+ - set and lock almost all peripherals as non-secure ([f4b11e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4b11e59b81af3e485e6992b10b50b362902eee1))
+
+ - **i.MX 8M Plus**
+
+ - restrict peripheral access to secure world ([0324081](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0324081af0105af536992c8ced2caa5a1928010f))
+ - set and lock almost all peripherals as non-secure ([cba7daa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cba7daa10576684670e06d05ff02888a5b4f16bf))
+
+ - **i.MX 8Q**
+
+ - detect console base address during runtime ([52ee817](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52ee8173041c46aafcfa43f004029dddbfa9f9b5))
+
+ - **i.MX 8ULP**
+
+ - add a flag check for the ddr status ([4fafccb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fafccb9a8f7b35406b08743f6d9c9b519b01c61))
+ - add APD power down mode(PD) support in system suspend ([478af8d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/478af8d3c34576793a820733ddba6449c2cf2fac))
+ - add i.MX8ULP basic support ([fcd41e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcd41e8692ce8e8fc98d069bc131820cbf83c55c))
+ - add memory region policy ([5fd0642](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5fd06421f8bf9f5b67e73828281534f14f302630))
+ - add OPTEE support ([e7b82a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7b82a7d2fa1fc3f32724e6836b8f6078d20c103))
+ - add some delay before cmc1 access ([c514d3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c514d3cfa7640313c4d78674df9d7cbe9227420b))
+ - add system power off support ([891c547](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/891c547e9658c1827559d8da5e3b87de5a2e9f6a))
+ - add the basic support for idle & system suspned ([daa4478](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/daa4478a3cb2f86501c37e5a301cd4d6a6e60ee6))
+ - add the initial XRDC support ([ac5d69b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac5d69b628736f66f72e99532656105fdc07a3fe))
+ - add trusty support ([e853041](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e853041920b15b77839027ab802d0cd9a08c7c35))
+ - adjust the dram mapped region ([8d50c91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d50c91b476474cc403c30eb6de6af28cb246e5a))
+ - adjust the voltage when sys dvfs enabled ([416c443](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/416c4433f0047a86165e450e60f93020c561151b))
+ - allocated caam did for the non secure world ([7c5eedc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c5eedca4c7f176448e6b92eb5c22ee2ea45e70a))
+ - allow RTD to reset APD through MU ([ea1f7a2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea1f7a2e109181f19f5bdeb71533e7dfda753df7))
+ - ddrc switch auto low power and software interface ([ee25e6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee25e6a51bf20c92471e737ccba98af4a74d1383))
+ - enable 512KB cache after resume on imx8ulp ([bcca70b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcca70b9688c5effa0731f39e2b209071f54be2c))
+ - enable the DDR frequency scaling support ([caee273](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/caee2733ba4e7a09ea656b0be85f150a275cc57c))
+ - give HIFI4 DSP access to more resources ([351976b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/351976bb063cca7866e214a6bda9302f9ab018b3))
+ - not power off LPAV PD when LPAV owner is RTD ([ab787db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab787dba7726bdf58c15626e5cc9a3525aade8a3))
+ - protect TEE region for secure access only ([ff5e179](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff5e1793b95ed4297deae72cdb665178e6e72e44))
+ - update the upower config for power optimization ([36af80c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36af80c2b420cb32ff57273eda0d7d0e93b49153))
+ - update XRDC for ELE to access DDR with CA35 DID ([d159c00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d159c00532afe50686dd92215de9b420d60502f6))
+
+ - **S32G274A**
+
+ - add S32G274ARDB2 board support ([8b81a39](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b81a39e28a087e1123271a42c04a7ce3b496a58))
+ - enable BL31 stage ([e73c3c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e73c3c3a6cbc1e81de4c9d73a5d713e6b37ae3b2))
+
+ - **QEMU**
+
+ - allow ARM_ARCH_MAJOR/MINOR override ([e769f83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e769f830d3116f49ed82769d9d731c4dca8f6188))
+ - enable FEAT_ECV when present ([1b694c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b694c77c497cb8272c97417ef1fa4f5f9c869c1))
+ - enable transfer list to BL31/32 ([305825b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/305825b490a77e5b0ee816ea29c53bc6444a1d63))
+ - load and run RMM image ([8ffe0b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ffe0b2edea6b00c9fe7d9ecaeca43c734d3764d))
+ - setup Granule Protection Table ([6cd113f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cd113fe06fdaa67a8457391eb6bcffd295f87fd))
+ - setup memory map for RME ([cd75693](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd75693f5ed303c1366fdff9b392d766848b6b67))
+ - support TRP for RME ([ebe82a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ebe82a392f06aa0adddf9cc5caa7af8f561b2fb4))
+ - update mapping types for RME ([a5ab1ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5ab1ef7febb2dc931cd8f7fcd76caac04d628cd))
+ - update to manifest v0.3 ([762a1c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/762a1c44b985b71495a90bc3484b576d28c8511a))
+ - use mock attestation functions for RME ([c69e95e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c69e95eed0491b481971b48f5df855402ed5392a))
+
+ - **SBSA**
+
+ - handle CPU information ([42925c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42925c15bee09162c6dfc8c2204843ffac6201c1))
+ - handle memory information ([8b7dd83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b7dd8397dd017b61ecda8447e8956a1d9d6d5d3))
+ - mpidr needs to be present ([4fc54c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fc54c99d08926c2d42173902c8aaf3862722c84))
+
+ - **Raspberry Pi**
+
+ - add Raspberry Pi 5 support ([f834b64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f834b64f889c1c4e03e590d44a6a52e3ac79cf42))
+
+ - **Renesas**
+
+ - **R-Car**
+
+ - **R-Car 3**
+
+ - add cache operations to boot process ([7e06b06](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e06b06753b12d567b6f48b6e60d6d0a56cf72e5))
+ - change CAM setting to improve bus latency of R-Car Gen3 ([e366f8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e366f8cf3349189daafb7ac2ab74d98931757a60))
+ - change MMU configurations ([5e8c2d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e8c2d8e23ca0760bca7e5b692ee95dd2871ec89))
+ - enable the stack protection ([cfa466a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cfa466ab733ff021771b94b4a98d22bfdd246139))
+ - update IPL and Secure Monitor Rev.4.0.0 ([516a98e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/516a98ef277626aa1858d9a4018d13ab2aeb39e7))
+
+ - **ST**
+
+ - add a function to clear the FWU trial state counter ([6e99fee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e99fee43efa256bdac3b38864206c94bd9ae3c8))
+ - add logic to boot the platform from an alternate bank ([6166051](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6166051426638087b5433eff1739d26478313dff))
+ - do not directly call BSEC functions in common code ([3007c72](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3007c72844c72e0911721e499dbab37b3eca1cdc))
+ - get the state of the active bank directly ([588b01b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/588b01b5e4726cd4a6d235e9f566a546ef17f631))
+ - use stm32_get_otp_value_from_idx() in BL31 ([189db94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/189db9486ddd949f279faa970bfc1dd9cc0e3623))
+
+ - **STM32MP1**
+
+ - only fuse monotonic counter on closed devices ([d6bb94f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6bb94f3a14ddbcf44c667134ed302eff054954c))
+
+ - **STM32MP2**
+
+ - add BSEC and OTP support ([197ac78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/197ac780d73c3421c4643e0bc02d112ceffd248f))
+ - add ddr-fw parameter for fiptool ([e494afc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e494afc05f8562455e09b4f131f2699990a744f8))
+ - add plat_my_core_pos ([d1c85da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1c85da8ef23a99387823272b03399a07e3a00da))
+ - add STM32MP_USB_PROGRAMMER compilation ([2e905c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e905c0682b4e6d2cfdbd42e41f6097b16967ff5))
+ - put back core 1 in wfi after debugger's halt ([2331a34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2331a34f783b29a9a1fe86f5142d0a359cacb259))
+ - use early traces ([47ea303](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47ea303389f6d0ac81617366973ece9d93dc49c9))
+
+ - **Xilinx**
+
+ - add handler for power down req sgi irq ([ade92a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ade92a64e4d2fbb5f246e6ad891465d10e0d9b26))
+ - add new state to identify cpu power down ([5949701](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5949701600c7f3c3a6589d0efd743615156c34b6))
+ - add wrapper to handle cpu power down req ([3dd118c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3dd118cf9d60e1eab97af505eb63a2cdc044d747))
+ - power down all cores on receiving cpu pwrdwn req ([c3280df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3280df1bb95ed09b5d5f91f8977bbe99c6a923b))
+ - request cpu power down from reset ([88ee081](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88ee0816a7429689890659f69b895ac84e48f141))
+ - send SGI to mailbox driver ([9a7f892](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9a7f892e29ea81c67f6f6b1342a367234e125b63))
+
+ - **Versal**
+
+ - enable errata management feature ([d766f99](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d766f994d2bd00c538f66e95686fc47b45ccbdb9))
+ - extend platform address space sizes ([663f024](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/663f024f207bddb7b80167e661c094d77955e292))
+
+ - **Versal NET**
+
+ - add bufferless IPI Support ([511e4a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/511e4a48ccd5e74af338041be238f5df12fffe3e))
+
+ - **ZynqMP**
+
+ - remove unused pm_get_proc_by_node() ([b03ba48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b03ba4801d39da1d5acc7a58d9c7736e57efc099))
+
+- **Bootloader Images**
+
+ - **BL32**
+
+ - create an sp_min_setup function ([a1255c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1255c758593f9f6fb85b70165fad21de7491e1e))
+
+- **Services**
+
+ - **FF-A**
+
+ - update FF-A version to v1.2 ([e830e4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e830e4cdee3d2238314326ef8c259b35d1c4f167))
+
+ - **RME**
+
+ - build TF-A with ENABLE_RME for Armv9.2 ([7d5fc98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d5fc98f5483efb942f7cbe4c04bf546a9a8598c))
+ - pass console info via RMM-EL3 ifc ([3290447](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32904472cc55a4bc9d8181a389ce3419033e0101))
+
+ - **SPM**
+
+ - **EL3 SPMC**
+
+ - add support for FFA_CONSOLE_LOG ([638a6f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/638a6f8e04c543649369374492524f2952f8d6b6))
+ - add support for FFA_MEM_PERM_GET and SET ABIs ([1f6b2b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f6b2b26535d5254d998239f232d997972d0475b))
+ - add support to handle power mgmt calls for s-el0 sp ([5917379](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59173793f47e27a66c871a0e8237e0f0d462080d))
+ - add support to map S-EL0 SP device regions ([727ab1c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/727ab1c4ab1e5ce1559fa6efec510114ce51fdf8))
+ - add support to map S-EL0 SP memory regions ([83c3da7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83c3da7711a246e04f4d0a64593fc0ab46f08bad))
+ - add support to setup S-EL0 context ([48db2b0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48db2b0120d1726208ff38a0edf6962f55a988bf))
+ - synchronize access to the s-el0 sp context ([5ed8e25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ed8e255096bd34d12bc6621e48cf9139bf414b2))
+
+ - **SPMD**
+
+ - add FFA_MSG_SEND_DIR_REQ2 ([cc6047b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc6047b3de52e412988f321723f67077a409e27d))
+ - add FFA_MSG_SEND_DIR_RESP2 ([0651b7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0651b7beb7e08a01c6e28be61026b053d53308fa))
+ - initialize SCR_EL3.EEL2 bit at RESET ([8815cda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8815cdaf57806901cfd388b8ee8c7979a8a2fe15))
+ - pass SMCCCv1.3 SVE hint to lower EL ([c925867](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c925867ec1be039abb72a7d65bff1b6a85b3d67a))
+
+ - **DRTM**
+
+ - add ACPI table region size to the DLME header ([5dde96b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5dde96b02490829d023b37931737c2ba2a6ed431))
+ - add additional return codes ([89f5c75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/89f5c753af8e5b8091543e8b1cae4d37e345ed7f))
+ - for TPM features fw hash algorithm should be 16-bits ([c86cfa3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c86cfa35975542d25d2192b81908074195aafe96))
+ - update DRTM version to 1.0 ([9c36b90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c36b900f904642f41e201024df584c0eaef9fc5))
+ - update references to DRTM beta0 ([b94d590](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b94d59099f0addb32389952dc6ecf35136a23859))
+ - update return code if secondary PE is not off ([bc9064a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc9064ae5c983aaca56102c2c0d3513ed022fd46))
+
+ - **ChromeOS**
+
+ - add ChromeOS widevine SMC handler ([b22e689](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b22e6898e1493eb00d0f0de6d48655d744264cb6))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - add support for Poseidon V CPU ([b77f55d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b77f55d6c7e51025d6c7ada1b4aa9506a046cf0f))
+ - support to update External LLC presence in Neoverse N3 ([6fbc98b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fbc98b15d92d881c4fbb74fd1344f0ef3f128ad))
+ - support to update External LLC presence in Neoverse V2 ([6aa5d1b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6aa5d1b3ab7b29c85ffe05942f2991da869e7fed))
+
+ - **EL3 Runtime**
+
+ - introduce UNDEF injection to lower EL ([3c789bf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3c789bfccca548ebcbdafbc7ecb07461d9368bea))
+
+ - **FCONF**
+
+ - support signing-key in root cert node ([04ac0b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04ac0b3c2711a4cb2f35983e91ff0ee842b52bbd))
+
+ - **OP-TEE**
+
+ - enable transfer list in opteed ([0e8def9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e8def996e73673d3e2c3d755a84e2b759ab3052))
+
+ - **PSCI**
+
+ - add psci_do_manage_extensions API ([160e843](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/160e8434baa48cc19d69913b00d2a643c788caec))
+
+ - **GPT**
+
+ - validate CRC of GPT partition entries ([7a9e9f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a9e9f6e96a93617abd33ef48734b65ad792ec13))
+
+ - **SMCCC**
+
+ - add vendor specific el3 id ([be5b1e2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be5b1e22346c6d8ce4b0c56604c99f7a9d3676cc))
+ - add vendor-specific el3 service ([de6b79d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/de6b79d8b5e15262b328051095e15ad4c67518eb))
+ - add version FID for PMF ([42cbefc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42cbefc72721a9cbf68a70d81cbcb141a2d085f1))
+
+ - **C Standard Library**
+
+ - add printf support for space padding ([0926d2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0926d2df7a5606c2b7c341d51f04a396084c39f2))
+
+ - **Locks**
+
+ - add bitlock ([222f885](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/222f885df38c3abd34ee239a721654155609631b))
+
+ - **DICE Protection Environment (Experimental)**
+
+ - add cert_id argument to dpe_derive_context() ([6a415bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a415bd1e71ac944c0ac67507b01f251e63361c3))
+ - add client API for DICE Protection Environment ([b03fe8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b03fe8c025f1c8025e70e7289339ecbc6cf83aae))
+ - add DPE driver to measured boot ([0ae9c63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ae9c631eaa32a30df3ff10cb4f0abafccb6c409))
+ - add QCBOR library as a dependency of DPE ([c19977b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c19977be0c3654e12accd51d4aef7059411106a6))
+ - add typedefs from the Open DICE repo ([584052c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/584052c7f80b406666b9597447eeccef4d6deca4))
+
+ - **Context Management**
+
+ - report context memory usage ([bfef8b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfef8b908e3a3cc29656c1d30a6b53490c79539b))
+ - add documentation for context management library ([4efd219](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4efd2193621ab7b933f4edfa28888379f3e03cbd))
+
+ - **Firmware Handoff**
+
+ - add additional TE tags ([a312bfb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a312bfb34487774a0e3244266ee45f63af86e2e8))
+ - add support for RESET_TO_BL2 ([f019c80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f019c8013e9c5efeb85eec7792fe901543a5832c))
+ - add TE's for BL1 handoff interface ([0646c9b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0646c9b293a2d8cdfd4626d15395385b5c1c2a6c))
+ - add TL source files to BL1 ([469b1d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/469b1d8412a748819f8c1bf51f695f2cb9f20489))
+ - enhance transfer list library ([40fd755](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40fd755bad9411d1e9e55984107186dde4137635))
+
+- **Drivers**
+
+ - **Authentication**
+
+ - add explicit entries for key OIDs ([2b53106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b53106a0e91e0865bf855935de04b24ef1cfa02))
+
+ - **mbedTLS**
+
+ - update config for 3.6.0 ([55aed7d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55aed7d798f3d48d6aa08d58eb46c4cda318bcfb))
+
+ - **Console**
+
+ - introduce EARLY_CONSOLE ([ae770fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae770fedf459d5643125d29f48659e3e936ebd2d))
+
+ - **FWU**
+
+ - modify the check for getting the FWU bank's state ([56724d0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56724d09c2c55ee2b8486b7c706f5fb9d980df88))
+ - update the URL links for the FWU specification ([e106a78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e106a78ef00df4c70a1594a89520af07b939cd92))
+
+ - **SCMI**
+
+ - add scmi sensor support ([e63819f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e63819f2bc307e7a42d43151242009f91ceeb06b))
+
+ - **Arm**
+
+ - **SMMU**
+
+ - fix to perform INV_ALL before enabling GPC ([70d849c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70d849c14de99e7320cc381b441af8bfe2a38375))
+ - separate out smmuv3_security_init from smmuv3_init ([a23710b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a23710b4b943a15a418a5d41236b2b57bd071de6))
+
+ - **MHU**
+
+ - add MHUv3 doorbell driver ([bc17476](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc174764f0daa82128bf60163653fc20db9a7e87))
+ - add MHUv3 wrapper APIs for RSS comm driver ([4b4f850](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b4f8505e7c58ba80a00c47a11f5feaf6d6f44f2))
+ - use compile flag to choose mhu version ([996b3af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/996b3af84cc6aeca90bc0dd3559abffd8bdc0ed7))
+
+ - **RSE**
+
+ - add defines for 'type' range and use them in psa_call() ([002b106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/002b10604ba0b90ac6e85d445ce2184cab52e39b))
+ - adjust parameter packing to match TF-M changes ([5abcc83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5abcc83991770a2fdbcb57dfc01000c6354da915))
+
+ - **NXP**
+
+ - add Linflex driver ([306946b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/306946b01490cfe0675300412cf738840bd099ef))
+
+ - **ST**
+
+ - **BSEC**
+
+ - add driver for the new IP version BSEC3 ([ae6542f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae6542f6c7ac9224843448424d3a539733bd651b))
+ - use early traces ([cf237f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf237f8d55255da1aad4f8dccb3110bab6060eba))
+
+ - **Clock**
+
+ - add function to control MCU subsystem ([77b4ca0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77b4ca0b2fd2c35e3bcb516078e1d9e3573172b3))
+
+ - **SDMMC2**
+
+ - set FIFO size to 1024 on STM32MP25 ([d5b4d5d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5b4d5d2e62e57acdcb2dbbcd4fe208bde92dc4c))
+
+- **Miscellaneous**
+
+ - **AArch64**
+
+ - add functions for TLBI RPALOS ([8754cc5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8754cc5d1c1b33d645b321f465bcfe61bc3915d6))
+
+ - **DT Bindings**
+
+ - introduce CCA CoT, rename TBBR ([c4b35ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4b35cebffb0d034aa7bdba7cfdb65ba93939e35))
+
+ - **FDTs**
+
+ - **STM32MP2**
+
+ - add board ID OTP in STM32MP257F-EV1 ([88528f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88528f55771fdc0a94b2ddd7f49f495a83044a24))
+ - add OTP nodes in STM32MP251 SoC DT file ([c238a46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c238a46a76660cbfa9ed40da4b1d0e5d477c3dd7))
+
+ - **Security**
+
+ - add support for SLS mitigation ([538516f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/538516f5d3db6e2c30dfa9f0b82859389f529e78))
+
+- **Documentation**
+
+ - update maintainer list for neoverse_rd ([2d7902d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d7902d9bf0bafceee9f571225862c476de0cdce))
+
+- **Build System**
+
+ - check that .text section starts at page boundary ([3d6edc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d6edc325c52082ab63ffd003c55a4ed875a52c5))
+ - redirect stdin to nul during toolchain detection ([b9014f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9014f858d1fd963a466228ec15572b0892a8490))
+
+- **Tools**
+
+ - **Memory Mapping Tool**
+
+ - add RELA section display ([a6462e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a6462e05cf1cd55da44002cdede04053a928cf0a))
+
+### Resolved Issues
+
+- **Architecture**
+
+ - **Memory Tagging Extension2**
+
+ - remove CTX_INCLUDE_MTE_REGS usage ([30788a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30788a8455779b70aebd38d53afc8aa19d776c6c))
+ - use ATA bit with FEAT_MTE2 ([ef0d0e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef0d0e5478a3f19cbe70a378b9b184036db38fe2))
+
+ - **Performance Monitors Extension (FEAT_PMUv3)**
+
+ - fix breakage on ARMv7 CPUs with SP_min as BL32 ([e6f8fc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6f8fc7437f6b9483ea0463315809d7ff6d5c0ec))
+
+ - **Statistical profiling Extension (FEAT_SPE)**
+
+ - invoke spe_disable during power domain off/suspend ([777f1f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/777f1f6897b57fe98c70d17c0d318aab3b86e119))
+
+- **Platforms**
+
+ - **Arm**
+
+ - move console flush/switch in common function ([6bdc856](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6bdc856bc9135db420196683501b4f201b30ae3a))
+ - only expose `arm_bl2_dyn_cfg_init` to BL2 ([3b48ca1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b48ca17f350d8b0999e89e8d9215993701e16a0))
+
+ - **FVP**
+
+ - added ranges for linux ([b7491c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7491c77d7ad2991b8c7c01f0311ebb3b0eca397))
+ - don't check MPIDRs with the power controller in BL1 ([6d8546f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d8546f9fc49a03a817b15b20a9d62fadda74b9c))
+ - permit enabling SME for SPD=spmd ([0b0fd0b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b0fd0b47616b706e2f07c6da548cdc913fecd17))
+
+ - **FPGA**
+
+ - halve number of PEs per core ([70b9204](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70b9204e6f98f1ec4f0529e8c1c88e8ece490d22))
+
+ - **Neoverse-RD**
+
+ - **SGI**
+
+ - align to misra rule for braces ([cacee06](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cacee0605684a75bbe8783c74fddba97b9abcffa))
+ - apply workarounds for N2 CPU erratum ([7934b68](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7934b68af6b446783823a114f25c3be06244c0e4))
+ - increase BL31 carveout size ([0737bd3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0737bd33faba5c9e6a0e98969e015430e2782332))
+ - reduce cper buffer carveout size ([f10d3e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f10d3e4953741eb3be1f9e4c09e7420554a0f050))
+ - update spi_id max for sgi multichip platforms ([89d8577](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/89d857780c50bddf94db26f158c008b4cc846edf))
+
+ - **RD-N1-Edge**
+
+ - update RD-N1-Edge's changelog title ([d239ede](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d239edea5644657ac72458cc13e3ce6bb5754ff8))
+
+ - **RD-N2**
+
+ - populate TOS_CONFIG only when SPMC_AT_EL3 is enabled ([10dcffe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10dcffedb36a658cf8a3389fbdeb499d4e7e4446))
+
+ - **TC**
+
+ - correct interrupts ([d2e44e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2e44e7d71863e3b302b5e72c8262bb0f3964fe6))
+ - do not enable MPMM and Aux AMU counters always ([fc42f84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fc42f84560d33c53b248e14913bbd6a69a8d310a))
+ - do not use r0 for HW_CONFIG ([a5a966b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5a966b12d9fe51a337db3204e7463ad95ba99c6))
+ - enable FEAT_MTE2 ([154eb0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/154eb0a22fa0a88d1f46e3674e3979626a83e063))
+ - guard PSA crypto headers under TF-M test-suite define ([d2ce6aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2ce6aa066ce1539908726de0d94a59c16634c4a))
+ - increase BL2 maximum size limit ([19258a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19258a5839cae9a81fb7256fbea34ff118220161))
+ - increase stack size when TRUSTED_BOARD_BOOT=0 ([44ddee6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44ddee6f0a993ed5b3409e6626c0c70b7ed7d7a2))
+ - missing device regions in spmc manifest ([5e47112](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e4711208db622ff6150e69c87962b506742a544))
+ - remove timer interrupt from G1S ([9bf31a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9bf31a59d187f6537066f05677972d9767e96c82))
+
+ - **Intel**
+
+ - add HPS remapper to remap base address for SDM ([b727664](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b727664e0dcf62be39552521c451ecde02091917))
+ - bl31 overwrite OCRAM configuration ([cfbac59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cfbac59590056e6b639aed56a1da480cd46f6f3e))
+ - fix hardcoded mpu frequency ticks ([150d2be](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/150d2be0d2d440011c91c9bf8013a1ab602b464c))
+ - read QSPI bank buffer data in bytes ([2f17ac0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2f17ac01adf28edb90a5ec8f446be1be76971b5c))
+ - revert back to use L4 clock ([d0e400b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0e400b3c626be647b9a20bc4f4869e20cc15dde))
+ - revert sys counter to 400MHz ([460692a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/460692afb5b934720b69c410e3b02c540a3b1ddf))
+ - temporarily workaround for Zephyr SMP ([68820f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68820f642191cef67df38516ef1c2ed1411c579f))
+ - update DDR range checking for Agilex5 ([f4aaa9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4aaa9fd6e6b4edd03976680b94e1c24aa582a68))
+ - update fcs crypto init code to check for mode ([b0f4478](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0f447897d3e2ddd72b291cb450165f4d220663e))
+ - update fcs functions to check ddr range ([e8a3454](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8a3454cb74a9b55c0cb678d47a8553ece660439))
+ - update from INFO to VERBOSE when print debug message ([56c8d02](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56c8d022b00ba212f3e21dcfab20c14f3a44eec4))
+ - update HPS bridges for Agilex5 SoC FPGA ([2973054](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2973054d9b4ba4fbcad7e04303ce8e0838b2f2b3))
+ - update individual return result for hps and fpga bridges ([82752c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82752c412362607549068d1c10cf7688f309d249))
+ - update nand driver to match GHRD design ([a773f41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a773f4121b3064fba24631e980c6226f23378e06))
+ - update stream id to non-secure for SDM ([8fbd307](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8fbd3073cacfc7a23efdfda4eecfaf6607515306))
+ - update system counter back to 400MHz ([a72f86a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a72f86ac4208e2aae5da83229cdd9ac97f651e36))
+
+ - **NXP**
+
+ - **i.MX**
+
+ - **i.MX 8M**
+
+ - align 3200 MTps rate with U-Boot ([060fe63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/060fe63337097c6cadea76ef5d2d383f0d90ef01))
+ - fix CSU_SA_REG to work with all sa registers ([c13016b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c13016bac6a6960acbbfb3e0176e1894a7e9fa3a))
+ - handle 3734 in addition to 3733 and 3732 MTps rates ([cb60a87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb60a876efc156c87afcd5ec53b9cf356f30211d))
+
+ - **i.MX 8M Plus**
+
+ - uncondtionally enable only the USB power domain ([ae6ce19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae6ce196df5b932f38c543cd8c6d8d86ee600009))
+
+ - **i.MX 8ULP**
+
+ - add sw workaround for csi/hotplug test hang ([e1d5c3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e1d5c3c8f435424394367e2ff19240b1b8a3073c))
+ - fix suspend/resume issue when DBD owner is s400 only ([68f132b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68f132b88bb24277ee34d5c3c94d16c26d7d4545))
+ - increase the mmap region num ([047d7d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/047d7d1ba2fc84d8377156f7f45d2d69c3cb5f84))
+
+ - **QEMU**
+
+ - disable FEAT_SB ([59bdb42](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59bdb426d300a6350334523a8dbc3fa6ae9f3bfc))
+ - increase max FIP size ([f465ac2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f465ac221001f82bed907be356917675645d92eb))
+
+ - **Raspberry Pi**
+
+ - consider MT when calculating core index from MPIDR ([6744d07](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6744d07d9475adb49352fa57aa72fce17a95d757))
+
+ - **Renesas**
+
+ - **R-Car**
+
+ - fix implicit rule invocations in tools ([e068a7c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e068a7ca860f35a171f608d55fb8a2a00ebd7561))
+
+ - **R-Car 3**
+
+ - change RAM protection configurations ([e9afde1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9afde1a2e311df0197a8e9102ef535382aef228))
+ - fix load address range check ([4f7e0fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f7e0fa38fdb6a25b07afafff492985bcc4e63a0))
+
+ - **Rockchip**
+
+ - add support for building with LTO enabled ([e5e9ccd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5e9ccdb0c070d3066e7d778e5e2b563acd7ba98))
+ - fix documentation in how build bl31 in AARCH64 ([6611e81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6611e81e14ed4aa16844e3865fd8a9f6fa99a074))
+
+ - **RK3328**
+
+ - apply ERRATA_A53_1530924 erratum ([dd2c888](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd2c888606dcdd638354c6345e08d4415d9d09fd))
+
+ - **ST**
+
+ - **STM32MP2**
+
+ - add missing include ([cb0d6b5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb0d6b5b5f7530335eac3c387bbb82d86608b0ea))
+ - correct early/crash console init ([4da462d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4da462dcdc2e435c8b732f3ceff4c94ca28b4c43))
+
+ - **Texas Instruments**
+
+ - do not stop non-secure timer on world switch ([d2e1f6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2e1f6a8811e52505556f7b91156499d82488751))
+
+ - **K3**
+
+ - increment while reading trail bytes ([0bdaf5c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bdaf5c804f852fe21f6172e436524157c9f6919))
+
+ - **Xilinx**
+
+ - add console_flush() before shutdown ([7ec53af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ec53afaade308b35f546480990dbc9304e06e7d))
+ - add FIT image check in DT console ([e2d9dfe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2d9dfe2bffe4fde28f2714058c8c882ea90102a))
+ - add FIT image check in prepare_dtb ([046e130](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/046e1304721e8bbf3d304dac22aa290bcbb0d10c))
+ - check proc variable before use ([652c1ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/652c1ab1526877d3505218f87ea96e6a9b2ccc11))
+ - deprecate SiP service count query ([6a80c20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a80c20eff74054c28273b42f3fe8e1a8fc5add4))
+ - fix sending sgi to linux ([427e46d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/427e46ddea1e528d4c57b1d8215482055bd79c3e))
+ - follow MISRA-C standards for condition check ([655e62a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/655e62aa5bede7ace8f8c6df571707aca9d6e14f))
+ - rename macros to align with ARM ([7995319](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79953190bc856ac3f47281029a80e5129bb4437d))
+ - update correct return types ([8eb6a1d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8eb6a1da1229b8f0bff33293cbb86ce20d09259d))
+
+ - **Versal**
+
+ - initialize cntfrq_el0 register ([f000744](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f000744e0f501c89fb2240b47e91c261e3082249))
+
+ - **Versal NET**
+
+ - setup counter frequency ([07625d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07625d9dd42d81c0e15f101fc0b6efa1c784b6f4))
+ - use arm common GIC handlers ([b225926](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b2259261815961042d2a994401929bc76a0d3ee9))
+
+ - **ZynqMP**
+
+ - resolve null pointer dereferencing ([20fa9fc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20fa9fc82334c67834eb22e20a3f4a07bcbe069d))
+
+ - **Nuvoton**
+
+ - gfx frame buffer memory corruption during secondary boot ([ae2b4a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae2b4a5494f9b4985fc2434e543ab0921e3b5a34))
+ - prevent changing clock frequency ([fe8cc55](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe8cc55a0cb5e47a0c0e28b147ee3e8dfdae07b2))
+
+- **Bootloader Images**
+
+ - **BL1**
+
+ - add missing `__RW_{START,END}__` symbols ([d701b48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d701b48eef4bb4b4b13ce5ef4091a37047e49a0b))
+ - add missing spinlock dependency ([e40b563](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e40b563e87fd4ff58474a289909a1827c8d2bca7))
+
+ - **BL2**
+
+ - make BL2 SRAM footprint flexible ([e0e03a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0e03a8d8b7eac45606812d1f2a9685b51e44515))
+
+- **Services**
+
+ - **FF-A**
+
+ - add NS memory node to fvp_spmc_optee_sp manifest ([92bba3e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/92bba3e711a21f2d31842bee64a1bd87e4b65414))
+
+ - **RME**
+
+ - **RMMD**
+
+ - avoid TRP when external RMM is defined ([57bc3c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57bc3c40560285e6029742b7360f8a0d0ac2346c))
+ - fix bug, raised by coverity, when zeroing manifest struct ([83a4e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83a4e8e0c69c64219e4d9de6c7f51fb10e3adc5a))
+
+ - **SPM**
+
+ - add device-regions used in tf-a-tests ([45716e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45716e377ecb30c17aa3b375ce1e232d15492b9c))
+ - not defining load-address in SP config ([04e7f80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04e7f80823e8a083138dd25963a5509bacd93257))
+ - reduce verbosity on passing tf-a-tests ([29872eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29872eb330201334fcb8e418b7dc7ae8ff0dc192))
+ - silence warning in sp_mk_generator ([6a3225e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a3225e2277df18e5c3aceb6173579cccefece51))
+
+ - **EL3 SPMC**
+
+ - add datastore linker script markers ([ba33528](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba33528a00bb83f5562918131cb37574fc287193))
+ - fix dangling pointer in FFA_CONSOLE_LOG ([83129bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83129bcd8e75f1ffbfc9a3bae3d60749b1d22fe3))
+
+ - **SPMD**
+
+ - register group0 handler only if supported ([fca5f0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fca5f0ebe5c2b5cf1c9d5096db6001a60ff7e089))
+ - skip NS EL1 context save & restore operations ([2d960a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d960a11601be6e7f24c38d84b2a4fdbb52efb9b))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - workaround for Cortex-A520 erratum 2630792 ([f03bfc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f03bfc304599540d859c4a07ac85d1bd9ae2c4f0))
+ - workaround for Cortex-A520 erratum 2858100 ([34db353](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34db3531ba085f111274b3b8e18476c4a392c245))
+ - workaround for Cortex-A710 erratum 2778471 ([c9508d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9508d6a1062ec3de4baaa3bd79ceed13eb972ad))
+ - workaround for Cortex-A715 erratum 2331818 ([53b3cd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53b3cd2532dbdb794ddfedcc8a3985d2404eb6f7))
+ - workaround for Cortex-A715 erratum 2344187 ([33c665a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33c665ae955fe5f5ae255f56ef6cdf073a9f601f))
+ - workaround for Cortex-A715 erratum 2413290 ([15a0461](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15a04615bb6834d93ab0077b89726dc17e3ba8b0))
+ - workaround for Cortex-A715 erratum 2420947 ([1f73247](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f732471320cee7b4f355ecff7dcfab7018e48ae))
+ - workaround for Cortex-A715 erratum 2429384 ([262dc9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/262dc9f76086970dab3dc43815890bed0ea29c79))
+ - workaround for Cortex-A715 erratum 2561034 ([6a6b282](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a6b282378340dc61cf088ff5a06770cf68f44d8))
+ - workaround for Cortex-A715 erratum 2728106 ([10134e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10134e3556ca61e670017e681eb637889b1bd4f8))
+ - workaround for Cortex-A720 erratum 2926083 ([152f4cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/152f4cfa16bc3d2786f598390450af38f4b2d0be))
+ - workaround for Cortex-A720 erratum 2940794 ([7385213](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7385213e602465d27530015a9b28ebc36a77b1c1))
+ - workaround for Cortex-A78C erratum 2683027 ([68cac6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68cac6a0f273dbe4f44563b467c996fafef07016))
+ - workaround for Cortex-A78C erratum 2743232 ([81d4094](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81d4094d637871ff34ddd7c2e2b3e842915f30f5))
+ - workaround for Cortex-X2 erratum 2778471 ([b01a93d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b01a93d7789a794ef0635e0a7b0e7e53cc8519e5))
+ - workaround for Cortex-X3 erratum 2266875 ([a65c5ba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65c5ba351178e6119299fa935a3576453cf900b))
+ - workaround for Cortex-X3 erratum 2302506 ([3f9df2c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f9df2c6ad053172c5dab74cd12d82a5b2c93c34))
+ - workaround for Cortex-X3 erratum 2372204 ([7f69a40](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f69a40697c3cc64e3fc553f6b50c72b97238dc9))
+ - workaround for Cortex X3 erratum 2641945 ([c1aa3fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b))
+ - workaround for Cortex X3 erratum 2743088 ([f43e9f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f43e9f57dc37a806bcd5e25a46b9f9bb1f365a64))
+ - workaround for Cortex-X3 erratum 2779509 ([355ce0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/355ce0a43abc1559b072b9cd9905f5194a6f0b86))
+ - workaround for Cortex-X4 erratum 2701112 ([cc41b56](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc41b56f41af14b00ce9f5c802e2f883786cef38))
+ - workaround for Cortex-X4 erratum 2740089 ([c833ca6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c833ca66a6fecbc54e038164e466be677559ec4e))
+ - workaround for Cortex-X4 erratum 2763018 ([4731211](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47312115dea140dd7ba26cf0512856a41f3e3067))
+ - workaround for Neoverse V1 erratum 2348377 ([71ed917](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ed91733140c82a392161c81869fcadb445c01a))
+ - workaround for Neoverse V2 erratum 2618597 ([c0f8ce5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0f8ce5379a77e61e89d91e225784801e5bbd3e0))
+ - workaround for Neoverse V2 erratum 2662553 ([912c409](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/912c4090fff207b445dde4bff72cc9b6e057e8b7))
+ - workaround for Neoverse V2 erratum 3099206 ([8815cda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8815cdaf57806901cfd388b8ee8c7979a8a2fe15))
+ - add Cortex-A520 definitions ([ae19093](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae19093f2aa6dd95cc7819accb0d05c0ebe4eeb3))
+ - workaround for Cortex-A715 erratum 2413290 re-factored with ENABLE_SPE_FOR_NS=1 ([bd2f7d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd2f7d325826f75acd729d4ee2719fd6130a7c5e))
+ - fix a defect in Cortex-A715 erratum 2561034 ([57ab6d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57ab6d897656f71d229268d80e41b26e62179400))
+ - add erratum 2701951 to Cortex-X3's list ([106c428](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/106c4283a564e4f37976ebc7dd8bc7d35f6592e4))
+ - update status of Cortex-X3 erratum 2615812 ([f589a2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f589a2a5f1b032ff3a09a419e49db0b97ccd8595))
+ - fix incorrect AMU trap settings for N2 CPU ([54b86d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54b86d47eb05f09330df57519b7d04b9968890e5))
+ - correct variant name for default Poseidon CPU ([61a2968](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/61a29682c66d0437806f81fb8ab0e3ff321dfe04))
+ - check for SCU before accessing DSU ([5b5562b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b5562b2e5855f949f1fc0579d7aff15e6b274ef))
+
+ - **EL3 Runtime**
+
+ - **Context Management**
+
+ - add more feature registers to EL1 context mgmt ([d6c76e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6c76e6c65429326e7572e10f521dd9108a3a1e3))
+ - add more system registers to EL1 context mgmt ([ed9bb82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed9bb824e4a3815e60acaa69ed66796279f4afbf))
+ - hide `cm_init_context_by_index` from BL1 ([a6b3643](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a6b3643c2a1a95146e93c8b6f07c2e491a1230d6))
+ - remove ENABLE_FEAT_MTE usage ([a796d5a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a796d5aa11b25622841cd2283630ff9348eed699))
+ - save guarded control stack registers ([6aae3ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6aae3acfd0d48e49e2367e6cd883dda7dca974c8))
+ - update gic el2 sysregs save/restore mechanism ([937d6fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/937d6fdb70cd24602fd2638a5dbd5c46d32559c1))
+ - couple el2 registers with dependent feature flags ([d6af234](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6af23443179f6d2239c7f5f190f0d8828bd68cf))
+ - move EL1 save/restore routines into C ([59f8882](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59f8882b44845ab865e354eeda8ce653f5d5fcf3))
+
+ - **FCONF**
+
+ - boot fails using ARM_ARCH_MINOR=8 ([0c86a84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c86a846d9149ee5af7e1ee4bb185c532ed9d0f8))
+
+ - **OP-TEE**
+
+ - set interrupt handler before kernel boot ([0ec69a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ec69a5bfbfcdf4566db8e96adaf29ad847d3d58))
+
+ - **PSCI**
+
+ - fix parent_idx in psci_validate_state_coordination ([412d92f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/412d92fdfd28d2f850a48e5f0aee95faa894a556))
+ - mask the Last in Level nibble in StateId ([0a9c244](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0a9c244b05ef2d2d4b946ba81bb9b9584b479b48))
+
+ - **GPT**
+
+ - declare gpt_tlbi_by_pa_ll() ([832e4ed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/832e4ed520d5ed7e64249fe98c1ffb4550db5eca))
+ - unify logging messages ([b99926e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b99926ef7b287738c4b4a87ee7ab4eaed1e4038f))
+ - use DC CIGDPAPA when MTE2 is implemented ([62d6465](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62d64652134ca1d3ea68da65ea9e4ae136f6c44e))
+
+ - **C Standard Library**
+
+ - add memcpy_s source file to libc_asm mk ([99db13b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99db13bfaa5b11345730937c2e0e56cb670c01a5))
+ - memset inclusion to libc makefiles ([84eb3ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/84eb3ef6c9f596e968b4f9b83a3a01deda2a8a9d))
+
+ - **PSA**
+
+ - fix static check failure ([bc0ff02](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc0ff02cbb046388eff1a95efd0043757d6ac317))
+
+ - **Context Management**
+
+ - align the memory address of EL2 context registers ([8c56a78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c56a78894ddc69167bc093fe19f173feced720c))
+
+ - **Firmware Handoff**
+
+ - correct representation of tag_id ([d594ace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d594ace68d4fa62cf2f1d5d13503b737b85924e5))
+
+ - **Exception Handling Framework (EHF)**
+
+ - restrict secure world FIQ routing model to SPM_MM ([7671008](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7671008fcfc826dbc3166ff1bdbb9cd7fbc7f68b))
+
+ - **SMCCC**
+
+ - correctly find pmf version ([62865b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62865b4ee455806e37a9c5bd52255b8c09cf1a1a))
+
+- **Drivers**
+
+ - **Measured Boot**
+
+ - add missing image identifier string ([a8a09e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8a09e3141354b159e7699d7c9c325bdd817b1f5))
+
+ - **SCMI**
+
+ - induce a delay in monitoring SCMI channel status ([af1ac2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af1ac2d7db47717bc69afd69b56f398aa34b2fb6))
+
+ - **Arm**
+
+ - **GIC**
+
+ - **GICv3**
+
+ - **GIC-600**
+
+ - workaround for Part 1 of GIC600 erratum 2384374 ([24a4a0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24a4a0a5ec25e179f2e567a6e13a9b5c87db1b81))
+
+ - **GICv2**
+
+ - fix SGIR_NSATT bitshift ([eef240c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eef240cfdedcc59f09dd5cd942448c5dcecc75d6))
+
+ - **MHU**
+
+ - use MHUv2 if PLAT_MHU_VERSION undefined ([c34dd06](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c34dd06a843d71cdba2fa1c3c9067f6f130a0c73))
+ - provide only the usable size of memory ([5cd1084](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cd10848be4f6ac19daa66803c3d512e3eea4266))
+
+ - **RSE**
+
+ - fix bound check during protocol selection ([f754bd4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f754bd466749a9338561f991bfb85140dd034e03))
+
+ - **Renesas**
+
+ - **R-Car3**
+
+ - add integer overflow check ([ef38fb1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef38fb1f5a5f2bdb897158e4244a1eddd2396eeb))
+ - add integer overflow check ([93b8952](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93b8952eefa14141c142070a71fc017736c8910c))
+ - check "rcar_image_number" variable before use ([b469880](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b469880e3b6b26849c3d43d3fe88a755a25249bc))
+ - check for length underflow ([9778b27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9778b270e29bac3e16f57f9557098c45858c05de))
+ - check loaded NS image area ([ae4860b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae4860b0f5c283aeca4def1449f0293ef22ff508))
+
+ - **USB**
+
+ - add missing include ([f84f21f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f84f21fa8d17662dcdc6b0b8b0caca4a45cd9ccd))
+
+- **Miscellaneous**
+
+ - **TBBR**
+
+ - move rotpk definitions out of arm_def.h ([0f0fd49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f0fd499dedd799e19279f0aa1f4f686085a944a))
+
+ - code coverage optimization fix ([152ad11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/152ad112d73402523302f3cb252aee0efc145736))
+ - fix MISRA defects ([c42d0d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c42d0d8754ae8818a7e7a63e873ca7699a7f102b))
+ - static checks on spmc dts ([c35299d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c35299d6b4e8b2757e47dc4c5a3b2e0836f89a7d))
+
+- **Documentation**
+
+ - revise the description of REGISTER_CRYPTO_LIB ([5710229](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5710229f9e837f28e4bafee6b51e828f901bf3f1))
+ - typo in the romlib design ([3b57ae2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b57ae23e0891e44d5b648575b80cbad4fc10405))
+
+- **Build System**
+
+ - add forgotten BL_LDFLAGS to lto command line ([49ba1df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49ba1df52204e721f06a6da76ef0f8692ce1b2f8))
+ - don't generate build-id ([304ad94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/304ad94b34c2117823169a199558e7484139caa1))
+ - don't rely on that gcc-ar is in the same directory as gcc ([7ef0b83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ef0b8377fa7fb3697dda5adfa44dafd7e14150f))
+ - enforce single partition for LTO build ([31f80ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31f80efeefaee2c59db50a46cabe2b5fdf20e4ae))
+ - march handling with arch-features ([7275ac2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7275ac2af86277e2442ef4b0fee6c35cbe830056))
+ - move comment for VERSION_PATCH ([c25d1cc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c25d1ccf1e205b2781ecd0de91e91d35e57b79bc))
+ - mute sp_mk_generator from build log ([fbd32ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbd32ac081c421929728f454427b7839235d2075))
+ - properly manage versions in .versionrc.js ([7f74030](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f74030b89136a1673e2a949564403709bc48f5d))
+ - wrap toolchain paths in double quotes ([4731c00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4731c00bb60915c0d4b29c082a752e9925a244b4))
+
+- **Tools**
+
+ - **Certificate Creation Tool**
+
+ - add guardrails around brainpool usage ([c0c280d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0c280dfda7322dcaebb5c6341c0880bdf524e13))
+ - use a salt length equal to digest length for RSA-PSS ([e639ad2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e639ad23c8c7a1b320af9ebd519420ae7d431531))
+
+ - **Memory Mapping Tool**
+
+ - fix footprint free space calculation ([9e72d01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9e72d01ed29c350dfc0567c59bc482901211634b))
+ - fix memory map dump when SEPARATE_CODE_AND_RODATA=0 ([6dc8ee6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dc8ee61ffeee8ea5aafdbef3121fa4e82b57932))
+
+ - **Marvell Tools**
+
+ - include mbedtls/version.h before use ([8eb4efe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8eb4efe70bd5b03917e2063ab8ff5646de88922a))
+
## [2.10.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.9.0..refs/tags/v2.10.0) (2023-11-21)
### âš BREAKING CHANGES
@@ -2667,11 +3585,11 @@
- route GIC IPI interrupts during setup ([04cc91b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04cc91b43c1d10fcba563e18f06336987e6e3a24))
- use only one space for indentation ([dee5885](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dee588591328b96d9b9ef908869c8b42bd2632f2))
- - **Versal NET**
+ - **Versal NET**
- - Enable a78 errata workarounds ([bcc6e4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcc6e4a02a88056b9c45ff28f405e09444433528))
- - add default values for silicon ([faa22d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/faa22d48d9929d57975b84ab76cb595afdcf57f4))
- - use api_id directly without FUNCID_MASK ([b0eb6d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0eb6d124b1764264778d17b1519bfe62b7b9337))
+ - Enable a78 errata workarounds ([bcc6e4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcc6e4a02a88056b9c45ff28f405e09444433528))
+ - add default values for silicon ([faa22d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/faa22d48d9929d57975b84ab76cb595afdcf57f4))
+ - use api_id directly without FUNCID_MASK ([b0eb6d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0eb6d124b1764264778d17b1519bfe62b7b9337))
- **ZynqMP**
@@ -8839,7 +9757,7 @@
______________________________________________________________________
-*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
[mbed tls releases]: https://tls.mbed.org/tech-updates/releases
[pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
diff --git a/docs/components/arm-sip-service.rst b/docs/components/arm-sip-service.rst
index b51a94d..74a40a3 100644
--- a/docs/components/arm-sip-service.rst
+++ b/docs/components/arm-sip-service.rst
@@ -15,19 +15,20 @@
The Arm SiP implementation offers the following services:
-- Performance Measurement Framework (PMF)
- Execution State Switching service
-- DebugFS interface
Source definitions for Arm SiP service are located in the ``arm_sip_svc.h`` header
file.
-Performance Measurement Framework (PMF)
----------------------------------------
++----------------------------+----------------------------+---------------------------------------+
+| ARM_SIP_SVC_VERSION_MAJOR | ARM_SIP_SVC_VERSION_MINOR | Changes |
++============================+============================+=======================================+
+| 1 | 0 | Move DebugFS and PMF to the new vendor|
+| | | specific FID range. The old FID range |
+| | | for these services are deprecated |
++----------------------------+----------------------------+---------------------------------------+
-The :ref:`Performance Measurement Framework <firmware_design_pmf>`
-allows callers to retrieve timestamps captured at various paths in TF-A
-execution.
+*Table 1: Showing different versions of arm-sip-service and changes done with each version*
Execution State Switching service
---------------------------------
@@ -88,348 +89,8 @@
and 1 populated with the supplied *Cookie hi* and *Cookie lo* values,
respectively.
-DebugFS interface
------------------
-
-The optional DebugFS interface is accessed through an SMC SiP service. Refer
-to the component documentation for details.
-
-String parameters are passed through a shared buffer using a specific union:
-
-.. code:: c
-
- union debugfs_parms {
- struct {
- char fname[MAX_PATH_LEN];
- } open;
-
- struct mount {
- char srv[MAX_PATH_LEN];
- char where[MAX_PATH_LEN];
- char spec[MAX_PATH_LEN];
- } mount;
-
- struct {
- char path[MAX_PATH_LEN];
- dir_t dir;
- } stat;
-
- struct {
- char oldpath[MAX_PATH_LEN];
- char newpath[MAX_PATH_LEN];
- } bind;
- };
-
-Format of the dir_t structure as such:
-
-.. code:: c
-
- typedef struct {
- char name[NAMELEN];
- long length;
- unsigned char mode;
- unsigned char index;
- unsigned char dev;
- qid_t qid;
- } dir_t;
-
-
-* Identifiers
-
-======================== =============================================
-SMC_OK 0
-SMC_UNK -1
-DEBUGFS_E_INVALID_PARAMS -2
-======================== =============================================
-
-======================== =============================================
-MOUNT 0
-CREATE 1
-OPEN 2
-CLOSE 3
-READ 4
-WRITE 5
-SEEK 6
-BIND 7
-STAT 8
-INIT 10
-VERSION 11
-======================== =============================================
-
-MOUNT
-~~~~~
-
-Description
-^^^^^^^^^^^
-This operation mounts a blob of data pointed to by path stored in `src`, at
-filesystem location pointed to by path stored in `where`, using driver pointed
-to by path in `spec`.
-
-Parameters
-^^^^^^^^^^
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``MOUNT``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if mount operation failed
-=============== ==========================================================
-
-OPEN
-~~~~
-
-Description
-^^^^^^^^^^^
-This operation opens the file path pointed to by `fname`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``OPEN``
-uint32_t mode
-======== ============================================================
-
-mode can be one of:
-
-.. code:: c
-
- enum mode {
- O_READ = 1 << 0,
- O_WRITE = 1 << 1,
- O_RDWR = 1 << 2,
- O_BIND = 1 << 3,
- O_DIR = 1 << 4,
- O_STAT = 1 << 5
- };
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if open operation failed
-
-uint32_t w1: file descriptor id on success.
-=============== ==========================================================
-
-CLOSE
-~~~~~
-
-Description
-^^^^^^^^^^^
-
-This operation closes a file described by a file descriptor obtained by a
-previous call to OPEN.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``CLOSE``
-uint32_t File descriptor id returned by OPEN
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if close operation failed
-=============== ==========================================================
-
-READ
-~~~~
-
-Description
-^^^^^^^^^^^
-
-This operation reads a number of bytes from a file descriptor obtained by
-a previous call to OPEN.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``READ``
-uint32_t File descriptor id returned by OPEN
-uint32_t Number of bytes to read
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-On success, the read data is retrieved from the shared buffer after the
-operation.
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if read operation failed
-
-uint32_t w1: number of bytes read on success.
-=============== ==========================================================
-
-SEEK
-~~~~
-
-Description
-^^^^^^^^^^^
-
-Move file pointer for file described by given `file descriptor` of given
-`offset` related to `whence`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``SEEK``
-uint32_t File descriptor id returned by OPEN
-sint32_t offset in the file relative to whence
-uint32_t whence
-======== ============================================================
-
-whence can be one of:
-
-========= ============================================================
-KSEEK_SET 0
-KSEEK_CUR 1
-KSEEK_END 2
-========= ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if seek operation failed
-=============== ==========================================================
-
-BIND
-~~~~
-
-Description
-^^^^^^^^^^^
-
-Create a link from `oldpath` to `newpath`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``BIND``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if bind operation failed
-=============== ==========================================================
-
-STAT
-~~~~
-
-Description
-^^^^^^^^^^^
-
-Perform a stat operation on provided file `name` and returns the directory
-entry statistics into `dir`.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``STAT``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ==========================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if stat operation failed
-=============== ==========================================================
-
-INIT
-~~~~
-
-Description
-^^^^^^^^^^^
-Initial call to setup the shared exchange buffer. Notice if successful once,
-subsequent calls fail after a first initialization. The caller maps the same
-page frame in its virtual space and uses this buffer to exchange string
-parameters with filesystem primitives.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``INIT``
-uint64_t Physical address of the shared buffer.
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ======================================================
-int32_t w0 == SMC_OK on success
-
- w0 == DEBUGFS_E_INVALID_PARAMS if already initialized,
- or internal error occurred.
-=============== ======================================================
-
-VERSION
-~~~~~~~
-
-Description
-^^^^^^^^^^^
-Returns the debugfs interface version if implemented in TF-A.
-
-Parameters
-^^^^^^^^^^
-
-======== ============================================================
-uint32_t FunctionID (0x82000030 / 0xC2000030)
-uint32_t ``VERSION``
-======== ============================================================
-
-Return values
-^^^^^^^^^^^^^
-
-=============== ======================================================
-int32_t w0 == SMC_OK on success
-
- w0 == SMC_UNK if interface is not implemented
-
-uint32_t w1: On success, debugfs interface version, 32 bits
- value with major version number in upper 16 bits and
- minor version in lower 16 bits.
-=============== ======================================================
-
-* CREATE(1) and WRITE (5) command identifiers are unimplemented and
- return `SMC_UNK`.
-
--------------
-*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.*
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
diff --git a/docs/components/context-management-library.rst b/docs/components/context-management-library.rst
new file mode 100644
index 0000000..56ba2ec
--- /dev/null
+++ b/docs/components/context-management-library.rst
@@ -0,0 +1,501 @@
+Context Management Library
+**************************
+
+This document provides an overview of the Context Management library implementation
+in Trusted Firmware-A (TF-A). It enumerates and describes the APIs implemented
+and their accessibility from other components at EL3.
+
+Overview
+========
+
+Arm TrustZone architecture facilitates hardware-enforced isolation between
+software running in various security states (Secure/Non-Secure/Realm).
+The general-purpose registers, most of the system registers and vector registers
+are not banked per world. When moving between the security states it is the
+responsibility of the secure monitor software (BL31(AArch64) / BL32(Aarch32))
+in TF-A, not the hardware, to save and restore register state.
+Refer to `Trustzone for AArch64`_ for more details.
+
+EL3 Runtime Firmware, also termed as secure monitor firmware, is integrated
+with a context management library to handle the context of the CPU, managing the
+saving and restoring of register states across the worlds.
+
+TF-A Context
+============
+
+In TF-A, the context is represented as a data structure used by the EL3 firmware
+to preserve the state of the CPU at the next lower exception level (EL) in a given
+security state and save enough EL3 metadata to be able to return to that exception
+level and security state. The memory for the context data structures are allocated
+in BSS section of EL3 firmware.
+
+In a trusted system at any instance, a given CPU could be executing in one of the
+security states (Non-Secure, Secure, Realm). Each world must have its
+configuration of system registers independent of other security states to access
+and execute any of the architectural features.
+
+If the CPU switches across security states (for example: from Non-secure to Secure
+or vice versa), the register contents, especially the ones that are not banked
+(EL2/EL1, vector, general-purpose registers), will be overwritten, as the software
+running in either state has the privileges to access them. Additionally, some of
+the architectural features enabled in the former security state will be unconditionally
+accessible in the latter security state as well. This can be a major concern when
+dealing with security-specific bits, as they need to be explicitly enabled or
+disabled in each state to prevent data leakage across the worlds.
+
+In general, an ideal trusted system should have Secure world-specific configurations
+that are not influenced by Normal World operations. Therefore, for each CPU, we
+need to maintain world-specific context to ensure that register entries from one
+world do not leak or impact the execution of the CPU in other worlds.
+This will help ensure the integrity and security of the system, preventing any
+unauthorized access or data corruption between the different security states.
+
+Design
+======
+
+The Context Management library in TF-A is designed to cover all the requirements
+for maintaining world-specific context essential for a trusted system.
+This includes implementing CPU context initialization and management routines,
+as well as other helper APIs that are required by dispatcher components in EL3
+firmware, which are collectively referred to as CPU Context Management.
+The APIs and their usecases are listed in detail under the :ref:`Library APIs`
+section.
+
+Originally, the Context Management library in TF-A was designed to cater for a
+two-world system, comprising of Non-Secure and Secure Worlds. In this case, the
+EL3 Firmware is assumed to be running in Secure World.
+With introduction of Realm Management Extension (RME), from Armv9.2 a system
+can have four distinct worlds (Non-Secure, Secure, Realm, Root).
+RME isolates EL3 from all other Security states and moves it into its own security
+state called root. EL3 firmware now runs at Root World and thereby is
+trusted from software in Non-secure, Secure, and Realm states.
+Refer to `Security States with RME`_ for more details.
+
+Key principles followed in designing the context management library :
+
+1. **EL3 should only initialize immediate used lower EL**
+
+Context Management library running at EL3 should only initialize and monitor the
+immediate used lower EL. This implies that, when S-EL2 is present in the system,
+EL3 should initialise and monitor S-EL2 registers only. S-EL1 registers should
+not be the concern of EL3 while S-EL2 is in place. In systems where S-EL2 is
+absent, S-EL1 registers should be initialised from EL3.
+
+2. **Decentralized model for context management**
+
+Each world (Non-Secure, Secure, and Realm) should have their separate component
+in EL3 responsible for their respective world context management.
+Both the Secure and Realm world have associated dispatcher components in EL3
+firmware to allow management of the respective worlds. For the Non-Secure world,
+PSCI Library (BL31)/context management library provides routines to help
+initialize the Non-Secure world context.
+
+3. **Flexibility for Dispatchers to select desired feature set to save and restore**
+
+Each feature is supported with a helper function ``is_feature_supported(void)``,
+to detect its presence at runtime. This helps dispatchers to select the desired
+feature set, and thereby save and restore the configuration associated with them.
+
+4. **Dynamic discovery of Feature enablement by EL3**
+
+TF-A supports three states for feature enablement at EL3, to make them available
+for lower exception levels.
+
+.. code:: c
+
+ #define FEAT_STATE_DISABLED 0
+ #define FEAT_STATE_ENABLED 1
+ #define FEAT_STATE_CHECK 2
+
+A pattern is established for feature enablement behavior.
+Each feature must support the 3 possible values with rigid semantics.
+
+- **FEAT_STATE_DISABLED** - all code relating to this feature is always skipped.
+ Firmware is unaware of this feature.
+
+- **FEAT_STATE_ALWAYS** - all code relating to this feature is always executed.
+ Firmware expects this feature to be present in hardware.
+
+- **FEAT_STATE_CHECK** - same as ``FEAT_STATE_ALWAYS`` except that the feature's
+ existence will be checked at runtime. Default on dynamic platforms (example: FVP).
+
+.. note::
+ ``FEAT_RAS`` is an exception here, as it impacts the execution of EL3 and
+ it is essential to know its presence at compile time. Refer to ``ENABLE_FEAT``
+ macro under :ref:`Build Options` section for more details.
+
+Code Structure
+==============
+
+`lib/el3_runtime/(aarch32/aarch64)`_ - Context library code directory.
+
+Source Files
+~~~~~~~~~~~~
+
+#. ``context_mgmt.c`` : consists of core functions that setup, save and restore
+ context for different security states alongside high level feature enablement
+ APIs for individual worlds.
+
+#. ``cpu_data_array.c`` : contains per_cpu_data structure instantiation.
+
+#. ``context.S`` : consists of functions that save and restore some of the context
+ structure members in assembly code.
+
+#. ``cpu_data.S`` : consists of helper functions to initialise per_cpu_data pointers.
+
+#. ``el3_common_macros.S`` : consists of macros to facilitate actions to be performed
+ during cold and warmboot and el3 registers initialisation in assembly code.
+
+Header Files
+~~~~~~~~~~~~
+
+#. ``context_mgmt.h`` : contains the public interface to Context Management Library.
+
+#. ``context.h`` : contains the helper macros and definitions for context entries.
+
+#. ``cpu_data.h`` : contains the public interface to Per CPU data structure.
+
+#. ``context_debug.h`` : contains public interface to report context memory
+ utilisation across the security states.
+
+#. ``context_el2.h`` : internal header consisting of helper macros to access EL2
+ context entries. Used by ``context.h``.
+
+Apart from these files, we have some context related source files under ``BL1``
+and ``BL31`` directory. ``bl1_context_mgmt.c`` ``bl31_context_mgmt.c``
+
+Bootloader Images utilizing Context Management Library
+======================================================
+
++-------------------------------------------+-----------------------------+
+| Bootloader | Context Management Library |
++-------------------------------------------+-----------------------------+
+| BL1 | Yes |
++-------------------------------------------+-----------------------------+
+| BL2 | No |
++-------------------------------------------+-----------------------------+
+| BL31 (Aarch64- EL3runtime firmware) | Yes |
++-------------------------------------------+-----------------------------+
+| BL32 (Aarch32- EL3runtime firmware) | Yes |
++-------------------------------------------+-----------------------------+
+
+CPU Data Structure
+==================
+For a given system, depending on the CPU count, the platform statically
+allocates memory for the CPU data structure.
+
+.. code:: c
+
+ /* The per_cpu_ptr_cache_t space allocation */
+ cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
+
+This CPU data structure has a member element with an array of pointers to hold
+the Non-Secure, Realm and Secure security state context structures as listed below.
+
+.. code:: c
+
+ typedef struct cpu_data {
+ #ifdef __aarch64__
+ void *cpu_context[CPU_DATA_CONTEXT_NUM];
+ #endif
+
+ ....
+ ....
+
+ }cpu_data_t;
+
+|CPU Data Structure|
+
+At runtime, ``cpu_context[CPU_DATA_CONTEXT_NUM]`` array will be intitialised with
+the Secure, Non-Secure and Realm context structure addresses to ensure proper
+handling of the register state.
+See :ref:`Library APIs` section for more details.
+
+CPU Context and Memory allocation
+=================================
+
+CPU Context
+~~~~~~~~~~~
+The members of the context structure used by the EL3 firmware to preserve the
+state of CPU across exception levels for a given security state are listed below.
+
+.. code:: c
+
+ typedef struct cpu_context {
+ gp_regs_t gpregs_ctx;
+ el3_state_t el3state_ctx;
+ el1_sysregs_t el1_sysregs_ctx;
+
+ #if CTX_INCLUDE_EL2_REGS
+ el2_sysregs_t el2_sysregs_ctx;
+ #endif
+
+ #if CTX_INCLUDE_FPREGS
+ fp_regs_t fpregs_ctx;
+ #endif
+
+ cve_2018_3639_t cve_2018_3639_ctx;
+ #if CTX_INCLUDE_PAUTH_REGS
+ pauth_t pauth_ctx;
+ #endif
+
+ #if CTX_INCLUDE_MPAM_REGS
+ mpam_t mpam_ctx;
+ #endif
+
+ } cpu_context_t;
+
+Context Memory Allocation
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+CPUs maintain their context per world. The individual context memory allocation
+for each CPU per world is allocated by the world-specific dispatcher components
+at compile time as shown below.
+
+|Context memory allocation|
+
+NS-Context Memory
+~~~~~~~~~~~~~~~~~
+It's important to note that the Normal world doesn't possess the dispatcher
+component found in the Secure and Realm worlds. Instead, the PSCI library at EL3
+handles memory allocation for ``Non-Secure`` world context for all CPUs.
+
+.. code:: c
+
+ static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
+
+Secure-Context Memory
+~~~~~~~~~~~~~~~~~~~~~
+Secure World dispatcher (such as SPMD) at EL3 allocates the memory for ``Secure``
+world context of all CPUs.
+
+.. code:: c
+
+ static spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT];
+
+Realm-Context Memory
+~~~~~~~~~~~~~~~~~~~~
+Realm World dispatcher (RMMD) at EL3 allocates the memory for ``Realm`` world
+context of all CPUs.
+
+.. code:: c
+
+ rmmd_rmm_context_t rmm_context[PLATFORM_CORE_COUNT];
+
+To summarize, the world-specific context structures are synchronized with
+per-CPU data structures, which means that each CPU will have an array of pointers
+to individual worlds. The figure below illustrates the same.
+
+|CPU Context Memory Configuration|
+
+Context Setup/Initialization
+============================
+
+The CPU has been assigned context structures for every security state, which include
+Non-Secure, Secure and Realm. It is crucial to initialize each of these structures
+during the bootup of every CPU before they enter any security state for the
+first time. This section explains the specifics of how the initialization of
+every CPU context takes place during both cold and warm boot paths.
+
+Context Setup during Cold boot
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The cold boot path is mainly executed by the primary CPU, other than essential
+CPU initialization executed by all CPUs. After executing BL1 and BL2, the Primary
+CPU jumps to the BL31 image for runtime services initialization.
+During this process, the per_cpu_data structure gets initialized with statically
+allocated world-specific context memory.
+
+Later in the cold boot sequence, the BL31 image at EL3 checks for the presence
+of a Secure world image at S-EL2. If detected, it invokes the secure context
+initialization sequence under SPMD. Additionally, based on RME enablement,
+the Realm context gets initialized from the RMMD at EL3. Finally, before exiting
+to the normal world, the Non-Secure context gets initialized via the context
+management library. At this stage, all Primary CPU contexts are initialized
+and the CPU exits EL3 to enter the Normal world.
+
+|Context Init ColdBoot|
+
+.. note::
+ The figure above illustrates a scenario on FVP for one of the build
+ configurations with TFTF component at NS-EL2.
+
+Context Setup during Warmboot
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+During a warm boot sequence, the primary CPU is responsible for powering on the
+secondary CPUs. Refer to :ref:`CPU Reset` and :ref:`Firmware Design` sections for
+more details on the warm boot.
+
+|Context Init WarmBoot|
+
+The primary CPU initializes the Non-Secure context for the secondary CPU while
+restoring re-entry information for the Non-Secure world.
+It initialises via ``cm_init_context_by_index(target_idx, ep )``.
+
+``psci_warmboot_entrypoint()`` is the warm boot entrypoint procedure.
+During the warm bootup process, secondary CPUs have their secure context
+initialized through SPMD at EL3. Upon successful SP initialization, the SPD
+power management operations become shared with the PSCI library. During this
+process, the SPMD duly registers its handlers with the PSCI library.
+
+.. code:: c
+
+ file: psci_common.c
+ const spd_pm_ops_t *psci_spd_pm;
+
+ file: spmd_pm.c
+ const spd_pm_ops_t spmd_pm = {
+ .svc_on_finish = spmd_cpu_on_finish_handler,
+ .svc_off = spmd_cpu_off_handler
+ }
+
+Secondary CPUs during their bootup in the ``psci_cpu_on_finish()`` routine get
+their secure context initialised via the registered SPMD handler
+``spmd_cpu_on_finish_handler()`` at EL3.
+The figure above illustrates the same with reference of Primary CPU running at
+NS-EL2.
+
+.. _Library APIs:
+
+Library APIs
+============
+
+The public APIs and types can be found in ``include/lib/el3_runtime/context_management.h``
+and this section is intended to provide additional details and clarifications.
+
+Context Initialization for Individual Worlds
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The library implements high level APIs for the CPUs in setting up their individual
+context for each world (Non-Secure, Secure and Realm).
+
+.. c:function:: static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep);
+
+This function is responsible for the general context initialization that applies
+to all worlds. It will be invoked first, before calling the individual
+world-specific context setup APIs.
+
+.. c:function:: static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep);
+.. c:function:: static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep);
+.. c:function:: static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep);
+
+Depending on the security state that the CPU needs to enter, the respective
+world-specific context setup handlers listed above will be invoked once per-CPU
+to set up the context for their execution.
+
+.. c:function:: void cm_manage_extensions_el3(void)
+
+This function initializes all EL3 registers whose values do not change during the
+lifetime of EL3 runtime firmware. It is invoked from each CPU via the cold boot
+path ``bl31_main()`` and in the WarmBoot entry path ``void psci_warmboot_entrypoint()``.
+
+Runtime Save and Restore of Registers
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+EL1 Registers
+-------------
+
+.. c:function:: void cm_el1_sysregs_context_save(uint32_t security_state);
+.. c:function:: void cm_el1_sysregs_context_restore(uint32_t security_state);
+
+These functions are utilized by the world-specific dispatcher components running
+at EL3 to facilitate the saving and restoration of the EL1 system registers
+during a world switch.
+
+EL2 Registers
+-------------
+
+.. c:function:: void cm_el2_sysregs_context_save(uint32_t security_state);
+.. c:function:: void cm_el2_sysregs_context_restore(uint32_t security_state);
+
+These functions are utilized by the world-specific dispatcher components running
+at EL3 to facilitate the saving and restoration of the EL2 system registers
+during a world switch.
+
+Pauth Registers
+---------------
+
+Pointer Authentication feature is enabled by default for Non-Secure world and
+disabled for Secure and Realm worlds. In this case, we don't need to explicitly
+save and restore the Pauth registers during world switch.
+However, ``CTX_INCLUDE_PAUTH_REGS`` flag is explicitly used to enable Pauth for
+lower exception levels of Secure and Realm worlds. In this scenario, we save the
+general purpose and Pauth registers while we enter EL3 from lower ELs via
+``prepare_el3_entry`` and restore them back while we exit EL3 to lower ELs
+via ``el3_exit``.
+
+.. code:: c
+
+ .macro save_gp_pmcr_pauth_regs
+ func restore_gp_pmcr_pauth_regs
+
+Feature Enablement for Individual Worlds
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. c:function:: static void manage_extensions_nonsecure(cpu_context_t *ctx);
+.. c:function:: static void manage_extensions_secure(cpu_context_t *ctx);
+.. c:function:: static void manage_extensions_realm(cpu_context_t *ctx)
+
+Functions that allow the enabling and disabling of architectural features for
+each security state. These functions are invoked from the top-level setup APIs
+during context initialization.
+
+Further, a pattern is established for feature enablement code (AArch64).
+Each feature implements following APIs as applicable:
+Note: (``xxx`` is the name of the feature in the APIs)
+
+- ``is_feat_xxx_supported()`` and ``is_feat_xxx_present()`` - mandatory for all features.
+
+- ``xxx_enable(cpu_context * )`` and ``xxx_disable(cpu_context * )`` - optional
+ functions to enable the feature for the passed context only. To be called in
+ the respective world's setup_context to select behaviour.
+
+- ``xxx_init_el3()`` - optional function to enable the feature in-place in any EL3
+ registers that are never context switched. The values they write must never
+ change, otherwise the functions mentioned in previous point should be used.
+ Invoked from ``cm_manage_extensions_el3()``.
+
+- ``xxx_init_el2_unused()`` - optional function to enable the feature in-place
+ in any EL2 registers that are necessary for execution in EL1 with no EL2 present.
+
+The above mentioned rules, followed for ``FEAT_SME`` is shown below:
+
+.. code:: c
+
+ void sme_enable(cpu_context_t *context);
+ void sme_init_el3(void);
+ void sme_init_el2_unused(void);
+ void sme_disable(cpu_context_t *context);
+
+Per-world Context
+=================
+
+Apart from the CPU context structure, we have another structure to manage some
+of the EL3 system registers whose values are identical across all the CPUs
+referred to as ``per_world_context_t``.
+The Per-world context structure is intended for managing EL3 system registers with
+identical values across all CPUs, requiring only a singular context entry for each
+individual world. This structure operates independently of the CPU context
+structure and is intended to manage specific EL3 registers.
+
+.. code-block:: c
+
+ typedef struct per_world_context {
+ uint64_t ctx_cptr_el3;
+ uint64_t ctx_zcr_el3;
+ uint64_t ctx_mpam3_el3;
+ } per_world_context_t;
+
+These functions facilitate the activation of architectural extensions that possess
+identical values across all cores for the individual Non-secure, Secure, and
+Realm worlds.
+
+*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
+
+.. |Context Memory Allocation| image:: ../resources/diagrams/context_memory_allocation.png
+.. |CPU Context Memory Configuration| image:: ../resources/diagrams/cpu_data_config_context_memory.png
+.. |CPU Data Structure| image:: ../resources/diagrams/percpu-data-struct.png
+.. |Context Init ColdBoot| image:: ../resources/diagrams/context_init_coldboot.png
+.. |Context Init WarmBoot| image:: ../resources/diagrams/context_init_warmboot.png
+.. _Trustzone for AArch64: https://developer.arm.com/documentation/102418/0101/TrustZone-in-the-processor/Switching-between-Security-states
+.. _Security States with RME: https://developer.arm.com/documentation/den0126/0100/Security-states
+.. _lib/el3_runtime/(aarch32/aarch64): https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime
\ No newline at end of file
diff --git a/docs/components/index.rst b/docs/components/index.rst
index 30d80fc..3697026 100644
--- a/docs/components/index.rst
+++ b/docs/components/index.rst
@@ -26,3 +26,6 @@
realm-management-extension
rmm-el3-comms-spec
granule-protection-tables-design
+ ven-el3-service
+ ven-el3-debugfs
+ context-management-library
diff --git a/docs/components/ven-el3-debugfs.rst b/docs/components/ven-el3-debugfs.rst
new file mode 100644
index 0000000..8629d70
--- /dev/null
+++ b/docs/components/ven-el3-debugfs.rst
@@ -0,0 +1,343 @@
+DebugFS interface
+=================
+
+The optional DebugFS interface is accessed through a Vendor specific EL3 service. Refer
+to the component documentation for details.
+
+String parameters are passed through a shared buffer using a specific union:
+
+.. code:: c
+
+ union debugfs_parms {
+ struct {
+ char fname[MAX_PATH_LEN];
+ } open;
+
+ struct mount {
+ char srv[MAX_PATH_LEN];
+ char where[MAX_PATH_LEN];
+ char spec[MAX_PATH_LEN];
+ } mount;
+
+ struct {
+ char path[MAX_PATH_LEN];
+ dir_t dir;
+ } stat;
+
+ struct {
+ char oldpath[MAX_PATH_LEN];
+ char newpath[MAX_PATH_LEN];
+ } bind;
+ };
+
+Format of the dir_t structure as such:
+
+.. code:: c
+
+ typedef struct {
+ char name[NAMELEN];
+ long length;
+ unsigned char mode;
+ unsigned char index;
+ unsigned char dev;
+ qid_t qid;
+ } dir_t;
+
+
+* Identifiers
+
+======================== =============================================
+SMC_OK 0
+SMC_UNK -1
+DEBUGFS_E_INVALID_PARAMS -2
+======================== =============================================
+
+======================== =============================================
+MOUNT 0
+CREATE 1
+OPEN 2
+CLOSE 3
+READ 4
+WRITE 5
+SEEK 6
+BIND 7
+STAT 8
+INIT 10
+VERSION 11
+======================== =============================================
+
+MOUNT
+~~~~~
+
+Description
+^^^^^^^^^^^
+This operation mounts a blob of data pointed to by path stored in `src`, at
+filesystem location pointed to by path stored in `where`, using driver pointed
+to by path in `spec`.
+
+Parameters
+^^^^^^^^^^
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``MOUNT``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if mount operation failed
+=============== ==========================================================
+
+OPEN
+~~~~
+
+Description
+^^^^^^^^^^^
+This operation opens the file path pointed to by `fname`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``OPEN``
+uint32_t mode
+======== ============================================================
+
+mode can be one of:
+
+.. code:: c
+
+ enum mode {
+ O_READ = 1 << 0,
+ O_WRITE = 1 << 1,
+ O_RDWR = 1 << 2,
+ O_BIND = 1 << 3,
+ O_DIR = 1 << 4,
+ O_STAT = 1 << 5
+ };
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if open operation failed
+
+uint32_t w1: file descriptor id on success.
+=============== ==========================================================
+
+CLOSE
+~~~~~
+
+Description
+^^^^^^^^^^^
+
+This operation closes a file described by a file descriptor obtained by a
+previous call to OPEN.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``CLOSE``
+uint32_t File descriptor id returned by OPEN
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if close operation failed
+=============== ==========================================================
+
+READ
+~~~~
+
+Description
+^^^^^^^^^^^
+
+This operation reads a number of bytes from a file descriptor obtained by
+a previous call to OPEN.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``READ``
+uint32_t File descriptor id returned by OPEN
+uint32_t Number of bytes to read
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+On success, the read data is retrieved from the shared buffer after the
+operation.
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if read operation failed
+
+uint32_t w1: number of bytes read on success.
+=============== ==========================================================
+
+SEEK
+~~~~
+
+Description
+^^^^^^^^^^^
+
+Move file pointer for file described by given `file descriptor` of given
+`offset` related to `whence`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``SEEK``
+uint32_t File descriptor id returned by OPEN
+sint32_t offset in the file relative to whence
+uint32_t whence
+======== ============================================================
+
+whence can be one of:
+
+========= ============================================================
+KSEEK_SET 0
+KSEEK_CUR 1
+KSEEK_END 2
+========= ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if seek operation failed
+=============== ==========================================================
+
+BIND
+~~~~
+
+Description
+^^^^^^^^^^^
+
+Create a link from `oldpath` to `newpath`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``BIND``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if bind operation failed
+=============== ==========================================================
+
+STAT
+~~~~
+
+Description
+^^^^^^^^^^^
+
+Perform a stat operation on provided file `name` and returns the directory
+entry statistics into `dir`.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``STAT``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ==========================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if stat operation failed
+=============== ==========================================================
+
+INIT
+~~~~
+
+Description
+^^^^^^^^^^^
+Initial call to setup the shared exchange buffer. Notice if successful once,
+subsequent calls fail after a first initialization. The caller maps the same
+page frame in its virtual space and uses this buffer to exchange string
+parameters with filesystem primitives.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``INIT``
+uint64_t Physical address of the shared buffer.
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ======================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == DEBUGFS_E_INVALID_PARAMS if already initialized,
+ or internal error occurred.
+=============== ======================================================
+
+VERSION
+~~~~~~~
+
+Description
+^^^^^^^^^^^
+Returns the debugfs interface version if implemented in TF-A.
+
+Parameters
+^^^^^^^^^^
+
+======== ============================================================
+uint32_t FunctionID (0x87000010 / 0xC7000010)
+uint32_t ``VERSION``
+======== ============================================================
+
+Return values
+^^^^^^^^^^^^^
+
+=============== ======================================================
+int32_t w0 == SMC_OK on success
+
+ w0 == SMC_UNK if interface is not implemented
+
+uint32_t w1: On success, debugfs interface version, 32 bits
+ value with major version number in upper 16 bits and
+ minor version in lower 16 bits.
+=============== ======================================================
+
+* CREATE(1) and WRITE (5) command identifiers are unimplemented and
+ return `SMC_UNK`.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/ven-el3-service.rst b/docs/components/ven-el3-service.rst
new file mode 100644
index 0000000..13449ba
--- /dev/null
+++ b/docs/components/ven-el3-service.rst
@@ -0,0 +1,78 @@
+Vendor Specific EL3 Monitor Service Calls
+=========================================
+
+This document enumerates and describes the Vendor Specific EL3 Monitor Service
+Calls.
+
+These are Service Calls defined by the vendor of the EL3 Monitor.
+They are accessed via ``SMC`` ("SMC calls") instruction executed from Exception
+Levels below EL3. SMC calls for Vendor Specific EL3 Monitor Services:
+
+- Follow `SMC Calling Convention`_;
+- Use SMC function IDs that fall in the vendor-specific EL3 range, which are
+
++---------------------------+--------------------------------------------------+
+| SMC Function Identifier | Service Type |
++===========================+==================================================+
+| 0x87000000 - 0x8700FFFF | SMC32: Vendor Specific EL3 Monitor Service Calls |
++---------------------------+--------------------------------------------------+
+| 0xC7000000 - 0xC700FFFF | SMC64: Vendor Specific EL3 Monitor Service Calls |
++---------------------------+--------------------------------------------------+
+
+Vendor-specific EL3 monitor services are as follows:
+
++-----------------------------------+-----------------------+---------------------------------------------+
+| SMC Function Identifier | Service Type | FID's Usage |
++===================================+=======================+=============================================+
+| 0x87000010 - 0x8700001F (SMC32) | DebugFS Interface | | 0 - 11 are in use. |
++-----------------------------------+ | | 12 - 15 are reserved for future expansion.|
+| 0xC7000010 - 0xC700001F (SMC64) | | |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000020 - 0x8700002F (SMC32) | Performance | | 0,1 is in use. |
++-----------------------------------+ Measurement Framework | | 2 - 15 are reserved for future expansion. |
+| 0xC7000020 - 0xC700002F (SMC64) | (PMF) | |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000030 - 0x8700FFFF (SMC32) | Reserved | | reserved for future expansion |
++-----------------------------------+ | |
+| 0xC7000030 - 0xC700FFFF (SMC64) | | |
++-----------------------------------+-----------------------+---------------------------------------------+
+
+Source definitions for vendor-specific EL3 Monitor Service Calls used by TF-A are located in
+the ``ven_el3_svc.h`` header file.
+
++----------------------------+----------------------------+--------------------------------+
+| VEN_EL3_SVC_VERSION_MAJOR | VEN_EL3_SVC_VERSION_MINOR | Changes |
++============================+============================+================================+
+| 1 | 0 | Added Debugfs and PMF services.|
++----------------------------+----------------------------+--------------------------------+
+
+*Table 1: Showing different versions of Vendor-specific service and changes done with each version*
+
+Each sub service will have its own version, one FID allocated for sub service version.
+
+Some ground rules when one should update top level version.
+ - VEN_EL3_SVC_VERSION_MAJOR is incremented when any of the sub service version discovery
+ FID changes or the FID that was allocated for discovery changes. So any breaking subfeature
+ discovery changes will lead to major version update.
+ - VEN_EL3_SVC_VERSION_MINOR is incremented when we add a new FID or a new sub service.
+ For example adding an new monitor service at 0x30, Debugfs starts at 0x10 and PMF
+ starts at 0x20 next one will start at 0x30, this will need a update to minor version.
+
+Performance Measurement Framework (PMF)
+---------------------------------------
+
+The :ref:`Performance Measurement Framework <firmware_design_pmf>`
+allows callers to retrieve timestamps captured at various paths in TF-A
+execution.
+
+DebugFS interface
+-----------------
+
+The optional DebugFS interface is accessed through Vendor specific EL3 service. Refer
+to :ref:`DebugFS interface` documentation for further details and usage.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
+
+.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
diff --git a/docs/conf.py b/docs/conf.py
index d4e5423..3f9655b 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -14,8 +14,8 @@
project = "Trusted Firmware-A"
author = "Trusted Firmware-A contributors"
-version = "2.10.0"
-release = "2.10.0"
+version = "2.11.0"
+release = "2.11.0"
# -- General configuration ---------------------------------------------------
diff --git a/docs/design_documents/cmake_framework.rst b/docs/design_documents/cmake_framework.rst
index d88942e..f946b2e 100644
--- a/docs/design_documents/cmake_framework.rst
+++ b/docs/design_documents/cmake_framework.rst
@@ -11,11 +11,7 @@
Abstract
--------
This document presents a proposal for a new buildsystem for TF-A using CMake,
-and as part of this a reusable CMake framework for embedded projects. For a
-summary about the proposal, please see the `Phabricator wiki page
-<https://developer.trustedfirmware.org/w/tf_a/cmake-buildsystem-proposal/>`_. As
-mentioned there, the proposal consists of two phases. The subject of this
-document is the first phase only.
+and as part of this a reusable CMake framework for embedded projects.
Introduction
------------
@@ -162,4 +158,4 @@
--------------
-*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/design_documents/context_mgmt_rework.rst b/docs/design_documents/context_mgmt_rework.rst
index 59f9d4e..b086e3c 100644
--- a/docs/design_documents/context_mgmt_rework.rst
+++ b/docs/design_documents/context_mgmt_rework.rst
@@ -4,7 +4,7 @@
:Authors: Soby Mathew & Zelalem Aweke
:Organization: Arm Limited
:Contact: Soby Mathew <soby.mathew@arm.com> & Zelalem Aweke <zelalem.aweke@arm.com>
-:Status: RFC
+:Status: Implementation is ongoing. Refer to :ref:`Context Management Library` for more details.
.. contents:: Table of Contents
@@ -194,4 +194,4 @@
--------------
-*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/design_documents/index.rst b/docs/design_documents/index.rst
index ecc68b2..ac982e0 100644
--- a/docs/design_documents/index.rst
+++ b/docs/design_documents/index.rst
@@ -9,7 +9,7 @@
context_mgmt_rework
measured_boot_poc
drtm_poc
- rss
+ rse
psci_osi_mode
measured_boot
diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst
index 8a2ab2d..9dfe494 100644
--- a/docs/design_documents/measured_boot.rst
+++ b/docs/design_documents/measured_boot.rst
@@ -91,10 +91,10 @@
and the variable length crypto agile structure called TCG_PCR_EVENT2. Event
Log driver implemented in TF-A covers later part.
-#. RSS
+#. RSE
It is one of physical backend to extend the measurements. Please refer this
- document :ref:`Runtime Security Subsystem (RSS)` for more details.
+ document :ref:`Runtime Security Engine (RSE)` for more details.
Platform Interface
------------------
@@ -121,7 +121,7 @@
void bl2_plat_mboot_init(void);
Initialise all Measured Boot backends supported by the platform
- (e.g. Event Log buffer, RSS). As these functions do not return any value,
+ (e.g. Event Log buffer, RSE). As these functions do not return any value,
the platform should deal with error management, such as logging the error
somewhere, or panicking the system if this is considered a fatal error.
@@ -147,7 +147,7 @@
- If it is Event Log backend, then record the measurement in TCG Event Log
format.
- - If it is a secure crypto-processor (like RSS), then extend the designated
+ - If it is a secure crypto-processor (like RSE), then extend the designated
PCR (or slot) with the given measurement.
- This function must return 0 on success, a signed integer error code
otherwise.
@@ -223,7 +223,7 @@
- This function must return 0 on success, a signed integer error code
otherwise.
- In TC2 platform, this function is used to calculate the hash of the given
- key and forward this hash to RSS alongside the measurement of the image
+ key and forward this hash to RSE alongside the measurement of the image
which the key signs.
--------------
diff --git a/docs/design_documents/rss.rst b/docs/design_documents/rse.rst
similarity index 88%
rename from docs/design_documents/rss.rst
rename to docs/design_documents/rse.rst
index 18d5436..7296a45 100644
--- a/docs/design_documents/rss.rst
+++ b/docs/design_documents/rse.rst
@@ -1,45 +1,45 @@
-Runtime Security Subsystem (RSS)
-================================
+Runtime Security Engine (RSE)
+=============================
-This document focuses on the relationship between the Runtime Security Subsystem
-(RSS) and the application processor (AP). According to the ARM reference design
-the RSS is an independent core next to the AP and the SCP on the same die. It
+This document focuses on the relationship between the Runtime Security Engine
+(RSE) and the application processor (AP). According to the ARM reference design
+the RSE is an independent core next to the AP and the SCP on the same die. It
provides fundamental security guarantees and runtime services for the rest of
the system (e.g.: trusted boot, measured boot, platform attestation,
key management, and key derivation).
-At power up RSS boots first from its private ROM code. It validates and loads
+At power up RSE boots first from its private ROM code. It validates and loads
its own images and the initial images of SCP and AP. When AP and SCP are
released from reset and their initial code is loaded then they continue their
-own boot process, which is the same as on non-RSS systems. Please refer to the
-``RSS documentation`` [1]_ for more details about the RSS boot flow.
+own boot process, which is the same as on non-RSE systems. Please refer to the
+``RSE documentation`` [1]_ for more details about the RSE boot flow.
-The last stage of the RSS firmware is a persistent, runtime component. Much
+The last stage of the RSE firmware is a persistent, runtime component. Much
like AP_BL31, this is a passive entity which has no periodical task to do and
-just waits for external requests from other subsystems. RSS and other
-subsystems can communicate with each other over message exchange. RSS waits
+just waits for external requests from other subsystems. RSE and other
+subsystems can communicate with each other over message exchange. RSE waits
in idle for the incoming request, handles them, and sends a response then goes
back to idle.
-RSS communication layer
+RSE communication layer
-----------------------
-The communication between RSS and other subsystems are primarily relying on the
-Message Handling Unit (MHU) module. The number of MHU interfaces between RSS
+The communication between RSE and other subsystems are primarily relying on the
+Message Handling Unit (MHU) module. The number of MHU interfaces between RSE
and other cores is IMPDEF. Besides MHU other modules also could take part in
-the communication. RSS is capable of mapping the AP memory to its address space.
-Thereby either RSS core itself or a DMA engine if it is present, can move the
-data between memory belonging to RSS or AP. In this way, a bigger amount of data
+the communication. RSE is capable of mapping the AP memory to its address space.
+Thereby either RSE core itself or a DMA engine if it is present, can move the
+data between memory belonging to RSE or AP. In this way, a bigger amount of data
can be transferred in a short time.
The MHU comes in pairs. There is a sender and receiver side. They are connected
to each other. An MHU interface consists of two pairs of MHUs, one sender and
one receiver on both sides. Bidirectional communication is possible over an
-interface. One pair provides message sending from AP to RSS and the other pair
-from RSS to AP. The sender and receiver are connected via channels. There is an
+interface. One pair provides message sending from AP to RSE and the other pair
+from RSE to AP. The sender and receiver are connected via channels. There is an
IMPDEF number of channels (e.g: 4-16) between a sender and a receiver module.
-The RSS communication layer provides two ways for message exchange:
+The RSE communication layer provides two ways for message exchange:
- ``Embedded messaging``: The full message, including header and payload, are
exchanged over the MHU channels. A channel is capable of delivering a single
@@ -55,16 +55,16 @@
- ``Pointer-access messaging``: The message header and the payload are
separated and they are conveyed in different ways. The header is sent
over the channels, similar to the embedded messaging but the payload is
- copied over by RSS core (or by DMA) between the sender and the receiver. This
+ copied over by RSE core (or by DMA) between the sender and the receiver. This
could be useful in the case of long messages because transaction time is less
- compared to the embedded messaging mode. Small payloads are copied by the RSS
+ compared to the embedded messaging mode. Small payloads are copied by the RSE
core because setting up DMA would require more CPU cycles. The payload is
- either copied into an internal buffer or directly read-written by RSS. Actual
- behavior depends on RSS setup, whether the partition supports memory-mapped
+ either copied into an internal buffer or directly read-written by RSE. Actual
+ behavior depends on RSE setup, whether the partition supports memory-mapped
``iovec``. Therefore, the sender must handle both cases and prevent access to
- the memory, where payload data lives, while the RSS handles the request.
+ the memory, where payload data lives, while the RSE handles the request.
-The RSS communication layer supports both ways of messaging in parallel. It is
+The RSE communication layer supports both ways of messaging in parallel. It is
decided at runtime based on the message size which way to transfer the message.
.. code-block:: bash
@@ -93,25 +93,25 @@
V | | | V V
+----------------------------------------------+ | | +-------------------+
| |--+-+ | |
- | RSS | | SRAM |
+ | RSE | | SRAM |
| | | |
+----------------------------------------------+ +-------------------+
.. Note::
- The RSS communication layer is not prepared for concurrent execution. The
+ The RSE communication layer is not prepared for concurrent execution. The
current use case only requires message exchange during the boot phase. In
the boot phase, only a single core is running and the rest of the cores are
in reset.
Message structure
^^^^^^^^^^^^^^^^^
-A description of the message format can be found in the ``RSS communication
+A description of the message format can be found in the ``RSE communication
design`` [2]_ document.
Source files
^^^^^^^^^^^^
-- RSS comms: ``drivers/arm/rss``
+- RSE comms: ``drivers/arm/rse``
- MHU driver: ``drivers/arm/mhu``
@@ -119,29 +119,29 @@
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The API is defined in these header files:
-- ``include/drivers/arm/rss_comms.h``
+- ``include/drivers/arm/rse_comms.h``
- ``include/drivers/arm/mhu.h``
-RSS provided runtime services
+RSE provided runtime services
-----------------------------
-RSS provides the following runtime services:
+RSE provides the following runtime services:
- ``Measured boot``: Securely store the firmware measurements which were
computed during the boot process and the associated metadata (image
description, measurement algorithm, etc.). More info on measured boot service
- in RSS can be found in the ``measured_boot_integration_guide`` [3]_ .
+ in RSE can be found in the ``measured_boot_integration_guide`` [3]_ .
- ``Delegated attestation``: Query the platform attestation token and derive a
delegated attestation key. More info on the delegated attestation service
- in RSS can be found in the ``delegated_attestation_integration_guide`` [4]_ .
+ in RSE can be found in the ``delegated_attestation_integration_guide`` [4]_ .
- ``OTP assets management``: Public keys used by AP during the trusted boot
- process can be requested from RSS. Furthermore, AP can request RSS to
+ process can be requested from RSE. Furthermore, AP can request RSE to
increase a non-volatile counter. Please refer to the
- ``RSS key management`` [5]_ document for more details.
+ ``RSE key management`` [5]_ document for more details.
Runtime service API
^^^^^^^^^^^^^^^^^^^
-The RSS provided runtime services implement a PSA aligned API. The parameter
+The RSE provided runtime services implement a PSA aligned API. The parameter
encoding follows the PSA client protocol described in the
``Firmware Framework for M`` [6]_ document in chapter 4.4. The implementation is
restricted to the static handle use case therefore only the ``psa_call`` API is
@@ -168,7 +168,7 @@
| |
V V
+------------------------------------------------+
- | RSS communication protocol |
+ | RSE communication protocol |
+------------------------------------------------+
| ^
| mhu_send_data() | mhu_receive_data()
@@ -188,7 +188,7 @@
|
V
+------------------------------------------------+
- | MHU HW on RSS side |
+ | MHU HW on RSE side |
+------------------------------------------------+
| ^
| IRQ | Register access
@@ -204,17 +204,17 @@
+---------------+ +------------------------+
-RSS based Measured Boot
+RSE based Measured Boot
-----------------------
Measured Boot is the process of cryptographically measuring (computing the hash
value of a binary) the code and critical data used at boot time. The
measurement must be stored in a tamper-resistant way, so the security state
-of the device can be attested later to an external party. RSS provides a runtime
+of the device can be attested later to an external party. RSE provides a runtime
service which is meant to store measurements and associated metadata alongside.
Data is stored in internal SRAM which is only accessible by the secure runtime
-firmware of RSS. Data is stored in so-called measurement slots. A platform has
+firmware of RSE. Data is stored in so-called measurement slots. A platform has
IMPDEF number of measurement slots. The measurement storage follows extend
semantics. This means that measurements are not stored directly (as it was
taken) instead they contribute to the current value of the measurement slot.
@@ -236,7 +236,7 @@
.. code-block:: c
psa_status_t
- rss_measured_boot_extend_measurement(uint8_t index,
+ rse_measured_boot_extend_measurement(uint8_t index,
const uint8_t *signer_id,
size_t signer_id_size,
const uint8_t *version,
@@ -291,27 +291,27 @@
.. Note::
Extending multiple measurements in the same slot leads to some metadata
- information loss. Since RSS is not constrained on special HW resources to
+ information loss. Since RSE is not constrained on special HW resources to
store the measurements and metadata, therefore it is worth considering to
store all of them one by one in distinct slots. However, they are one-by-one
included in the platform attestation token. So, the number of distinct
firmware image measurements has an impact on the size of the attestation
token.
-The allocation of the measurement slot among RSS, Root and Realm worlds is
+The allocation of the measurement slot among RSE, Root and Realm worlds is
platform dependent. The platform must provide an allocation of the measurement
slot at build time. An example can be found in
``tf-a/plat/arm/board/tc/tc_bl1_measured_boot.c``
Furthermore, the memory, which holds the metadata is also statically allocated
-in RSS memory. Some of the fields have a static value (measurement algorithm),
+in RSE memory. Some of the fields have a static value (measurement algorithm),
and some of the values have a dynamic value (measurement value) which is updated
by the bootloaders when the firmware image is loaded and measured. The metadata
structure is defined in
-``include/drivers/measured_boot/rss/rss_measured_boot.h``.
+``include/drivers/measured_boot/rse/rse_measured_boot.h``.
.. code-block:: c
- struct rss_mboot_metadata {
+ struct rse_mboot_metadata {
unsigned int id;
uint8_t slot;
uint8_t signer_id[SIGNER_ID_MAX_SIZE];
@@ -328,24 +328,24 @@
^^^^^^^^^^^^^
This function calculates the hash of a public key (signer-ID) using the
-``Measurement algorithm`` and stores it in the ``rss_mboot_metadata`` field
+``Measurement algorithm`` and stores it in the ``rse_mboot_metadata`` field
named ``signer_id``.
Prior to calling this function, the caller must ensure that the ``signer_id``
field points to the zero-filled buffer.
Defined here:
-- ``include/drivers/measured_boot/rss/rss_measured_boot.h``
+- ``include/drivers/measured_boot/rse/rse_measured_boot.h``
.. code-block:: c
- int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+ int rse_mboot_set_signer_id(struct rse_mboot_metadata *metadata_ptr,
const void *pk_oid,
const void *pk_ptr,
size_t pk_len)
-- First parameter is the pointer to the ``rss_mboot_metadata`` structure.
+- First parameter is the pointer to the ``rse_mboot_metadata`` structure.
- Second parameter is the pointer to the key-OID of the public key.
- Third parameter is the pointer to the public key buffer.
- Fourth parameter is the size of public key buffer.
@@ -356,15 +356,15 @@
^^^^^^^^^^^^^^^^^^^^^^^^^
- ``MEASURED_BOOT``: Enable measured boot. It depends on the platform
- implementation whether RSS or TPM (or both) backend based measured boot is
+ implementation whether RSE or TPM (or both) backend based measured boot is
enabled.
-- ``MBOOT_RSS_HASH_ALG``: Determine the hash algorithm to measure the images.
+- ``MBOOT_RSE_HASH_ALG``: Determine the hash algorithm to measure the images.
The default value is sha-256.
Measured boot flow
^^^^^^^^^^^^^^^^^^
-.. figure:: ../resources/diagrams/rss_measured_boot_flow.svg
+.. figure:: ../resources/diagrams/rse_measured_boot_flow.svg
:align: center
Sample console log
@@ -425,15 +425,15 @@
the ``Delegated Attestation Service Integration Guide`` [4]_ document.
In the CCA use case, the Realm Management Monitor (RMM) relies on the delegated
-attestation service of the RSS to get a realm attestation key and the CCA
+attestation service of the RSE to get a realm attestation key and the CCA
platform token. BL31 does not use the service for its own purpose, only calls
-it on behalf of RMM. The access to MHU interface and thereby to RSS is
+it on behalf of RMM. The access to MHU interface and thereby to RSE is
restricted to BL31 only. Therefore, RMM does not have direct access, all calls
need to go through BL31. The RMM dispatcher module of the BL31 is responsible
for delivering the calls between the two parties.
.. Note::
- Currently the connection between the RMM dispatcher and the PSA/RSS layer
+ Currently the connection between the RMM dispatcher and the PSA/RSE layer
is not yet implemented. RMM dispatcher just returns hard coded data.
Delegated Attestation API
@@ -445,7 +445,7 @@
.. code-block:: c
psa_status_t
- rss_delegated_attest_get_delegated_key(uint8_t ecc_curve,
+ rse_delegated_attest_get_delegated_key(uint8_t ecc_curve,
uint32_t key_bits,
uint8_t *key_buf,
size_t key_buf_size,
@@ -453,7 +453,7 @@
uint32_t hash_algo);
psa_status_t
- rss_delegated_attest_get_token(const uint8_t *dak_pub_hash,
+ rse_delegated_attest_get_token(const uint8_t *dak_pub_hash,
size_t dak_pub_hash_size,
uint8_t *token_buf,
size_t token_buf_size,
@@ -462,7 +462,7 @@
Attestation flow
^^^^^^^^^^^^^^^^
-.. figure:: ../resources/diagrams/rss_attestation_flow.svg
+.. figure:: ../resources/diagrams/rse_attestation_flow.svg
:align: center
Sample attestation token
@@ -623,27 +623,27 @@
"CCA_PLATFORM_VERIFICATION_SERVICE": "www.trustedfirmware.org"
}
-RSS OTP Assets Management
+RSE OTP Assets Management
-------------------------
-RSS provides access for AP to assets in OTP, which include keys for image
+RSE provides access for AP to assets in OTP, which include keys for image
signature verification and non-volatile counters for anti-rollback protection.
Non-Volatile Counter API
^^^^^^^^^^^^^^^^^^^^^^^^
-AP/RSS interface for retrieving and incrementing non-volatile counters API is
+AP/RSE interface for retrieving and incrementing non-volatile counters API is
as follows.
Defined here:
-- ``include/lib/psa/rss_platform_api.h``
+- ``include/lib/psa/rse_platform_api.h``
.. code-block:: c
- psa_status_t rss_platform_nv_counter_increment(uint32_t counter_id)
+ psa_status_t rse_platform_nv_counter_increment(uint32_t counter_id)
- psa_status_t rss_platform_nv_counter_read(uint32_t counter_id,
+ psa_status_t rse_platform_nv_counter_read(uint32_t counter_id,
uint32_t size, uint8_t *val)
Through this service, we can read/increment any of the 3 non-volatile
@@ -656,15 +656,15 @@
Public Key API
^^^^^^^^^^^^^^
-AP/RSS interface for reading the ROTPK is as follows.
+AP/RSE interface for reading the ROTPK is as follows.
Defined here:
-- ``include/lib/psa/rss_platform_api.h``
+- ``include/lib/psa/rse_platform_api.h``
.. code-block:: c
- psa_status_t rss_platform_key_read(enum rss_key_id_builtin_t key,
+ psa_status_t rse_platform_key_read(enum rse_key_id_builtin_t key,
uint8_t *data, size_t data_size, size_t *data_length)
Through this service, we can read any of the 3 ROTPKs used on an
@@ -677,11 +677,11 @@
References
----------
-.. [1] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rss/readme.html
-.. [2] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rss/rss_comms.html
+.. [1] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rse/readme.html
+.. [2] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rse/rse_comms.html
.. [3] https://git.trustedfirmware.org/TF-M/tf-m-extras.git/tree/partitions/measured_boot/measured_boot_integration_guide.rst
.. [4] https://git.trustedfirmware.org/TF-M/tf-m-extras.git/tree/partitions/delegated_attestation/delegated_attest_integration_guide.rst
-.. [5] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rss/rss_key_management.html
+.. [5] https://tf-m-user-guide.trustedfirmware.org/platform/arm/rse/rse_key_management.html
.. [6] https://developer.arm.com/-/media/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf?revision=2d1429fa-4b5b-461a-a60e-4ef3d8f7f4b4&hash=3BFD6F3E687F324672F18E5BE9F08EDC48087C93
.. [7] https://developer.arm.com/documentation/DEN0096/A_a/?lang=en
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index c18c155..52a9317 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -230,6 +230,13 @@
contributions are still expected to build with ``W=0`` and ``E=1`` (the
default).
+- ``EARLY_CONSOLE``: This option is used to enable early traces before default
+ console is properly setup. It introduces EARLY_* traces macros, that will
+ use the non-EARLY traces macros if the flag is enabled, or do nothing
+ otherwise. To use this feature, platforms will have to create the function
+ plat_setup_early_console().
+ Default is 0 (disabled)
+
- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
the normal boot flow. It must specify the entry point address of the EL3
payload. Please refer to the "Booting an EL3 payload" section for more
@@ -694,13 +701,6 @@
This option defaults to 0.
-- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot
- backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When
- set to ``1`` then measurements and additional metadata collected during the
- measured boot process are sent to the DICE Protection Environment for storage
- and processing. A certificate chain, which represents the boot state of the
- device, can be queried from the DPE.
-
- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build
options to the compiler. An example usage:
@@ -761,6 +761,11 @@
``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
over ``PRELOADED_BL33_BASE``.
+- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to
+ save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU)
+ registers when the cluster goes through a power cycle. This is disabled by
+ default and platforms that require this feature have to enable them.
+
- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
vector address can be programmed or is fixed on the platform. It can take
either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
@@ -800,6 +805,21 @@
instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
+- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB
+- blocks) covered by a single bit of the bitlock structure during RME GPT
+- operations. The lower the block size, the better opportunity for
+- parallelising GPT operations but at the cost of more bits being needed
+- for the bitlock structure. This numeric parameter can take the values
+- from 0 to 512 and must be a power of 2. The value of 0 is special and
+- and it chooses a single spinlock for all GPT L1 table entries. Default
+- value is 1 which corresponds to block size of 512MB per bit of bitlock
+- structure.
+
+- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of
+ supported contiguous blocks in GPT Library. This parameter can take the
+ values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious
+ descriptors. Default value is 2.
+
- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
file that contains the ROT private key in PEM format or a PKCS11 URI and
enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is
@@ -1245,6 +1265,13 @@
Common build options
~~~~~~~~~~~~~~~~~~~~
+- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot
+ backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When
+ set to ``1`` then measurements and additional metadata collected during the
+ measured boot process are sent to the DICE Protection Environment for storage
+ and processing. A certificate chain, which represents the boot state of the
+ device, can be queried from the DPE.
+
- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
for Measurement (DRTM). This feature has trust dependency on BL31 for taking
the measurements and recording them as per `PSA DRTM specification`_. For
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 3498ac5..6a0241f 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -8,32 +8,53 @@
different from those listed below, however only the software described in this
document can be officially supported.
-Build Host
-----------
+Getting the TF-A Source
+-----------------------
-|TF-A| can be compiled on both Linux and Windows-based machines.
-However, we strongly recommend using a UNIX-compatible build environment.
+Source code for |TF-A| is maintained in a Git repository hosted on
+`TrustedFirmware.org`_. To clone this repository from the server, run the following
+in your shell:
-Testing is performed using Ubuntu 22.04 LTS (64-bit), but other distributions
-should also work, provided the necessary tools and libraries are installed.
+.. code:: shell
+
+ git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
-.. _prerequisites_toolchain:
-Toolchain
----------
+Requirements
+------------
-|TF-A| can be built with any of the following *cross-compiler* toolchains that
-target the Armv7-A or Armv8-A architectures:
+======================== =====================
+ Program Min supported version
+======================== =====================
+Arm Compiler 6.18
+Arm GNU Compiler 13.2
+Clang/LLVM 11.0.0
+Device Tree Compiler 1.4.7
+GNU make 3.81
+mbed TLS\ [#f1]_ 3.6.0
+Node.js [#f2]_ 16
+OpenSSL 1.0.0
+Poetry [#f2]_ 1.3.2
+QCBOR\ [#f3]_ 1.2
+Sphinx\ [#f2]_ 2.4.4
+======================== =====================
-- TF-A has been tested with version 13.2.Rel1 (gcc 13.2) from the `Arm Developer website`_
+.. [#f1] Required for Trusted Board Boot and Measured Boot.
+.. [#f2] Required only for building TF-A documentation.
+.. [#f3] Required only when enabling DICE Protection Environment support.
- You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for
- AArch32 and AArch64 builds respectively.
+Toolchain
+^^^^^^^^^
-- Clang == 14.0.0
-- Arm Compiler == 6.18
+|TF-A| can be compiled using any cross-compiler toolchain specified in the
+preceding table that target Armv7-A or Armv8-A. For AArch32 and
+AArch64 builds, the respective targets required are ``arm-none-eabi`` and
+``aarch64-none-elf``.
-In addition, a native compiler is required to build the supporting tools.
+Testing has been performed with version 13.2.Rel1 (gcc 13.2) of the Arm
+GNU compiler, which can be installed from the `Arm Developer website`_.
+
+In addition, a native compiler is required to build supporting tools.
.. note::
Versions greater than the ones specified are likely but not guaranteed to
@@ -45,74 +66,63 @@
For instructions on how to select the cross compiler refer to
:ref:`Performing an Initial Build`.
-.. _prerequisites_software_and_libraries:
-
-Software and Libraries
-----------------------
-
-The following tools are required to obtain and build |TF-A|:
-
-- An appropriate toolchain (see :ref:`prerequisites_toolchain`)
-- GNU Make
-- Git
-
-The following libraries must be available to build one or more components or
-supporting tools:
-
-- OpenSSL >= 1.0.0 (1.0.x, v3.0.0 to v3.0.6 highly discouraged due to security issues)
+OpenSSL
+^^^^^^^
- Required to build the cert_create, encrypt_fw, and fiptool tools.
+OpenSSL is required to build the cert_create, encrypt_fw, and fiptool tools.
- .. note::
+If using OpenSSL 3, older Linux versions may require it to be built from
+source code, as it may not be available in the default package repositories.
+Please refer to the OpenSSL project documentation for more information.
- If using OpenSSL 3, older Linux versions may require it to be built from
- source code, as it may not be available in the default package repositories.
- Please refer to the OpenSSL project documentation for more information.
+.. warning::
+ Versions 1.0.x and from v3.0.0 up to v3.0.6 are strongly advised against due
+ to concerns regarding security vulnerabilities!
-The following libraries are required for Trusted Board Boot and Measured Boot
-support:
+Device Tree Compiler (DTC)
+^^^^^^^^^^^^^^^^^^^^^^^^^^
-- mbed TLS == 3.4.1 (tag: ``mbedtls-3.4.1``)
+Needed if you want to rebuild the provided Flattened Device Tree (FDT)
+source files (``.dts`` files). DTC is available for Linux through the package
+repositories of most distributions.
-The following libraries are required for DICE Protection Environment support:
+Arm Development Studio (`Arm-DS`_)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- QCBOR == 1.2 (tag: ``v1.2``)
+The standard software package used for debugging software on Arm development
+platforms and |FVP| models.
-These tools are optional:
+Node.js
+^^^^^^^
-- Device Tree Compiler (DTC) >= 1.4.7
+Highly recommended, and necessary in order to install and use the packaged
+Git hooks and helper tools. Without these tools you will need to rely on the
+CI for feedback on commit message conformance.
- Needed if you want to rebuild the provided Flattened Device Tree (FDT)
- source files (``.dts`` files). DTC is available for Linux through the package
- repositories of most distributions.
+Poetry
+^^^^^^
-- Arm `Development Studio (Arm-DS)`_
+Required for managing Python dependencies, this will allow you to reliably
+reproduce a Python environment to build documentation and run analysis tools.
+Most importantly, it ensures your system environment will not be affected by
+dependencies in the Python scripts.
- The standard software package used for debugging software on Arm development
- platforms and |FVP| models.
-
-- Node.js >= 16
-
- Highly recommended, and necessary in order to install and use the packaged
- Git hooks and helper tools. Without these tools you will need to rely on the
- CI for feedback on commit message conformance.
+.. _prerequisites_software_and_libraries:
-- Poetry >= 1.3.2
+Package Installation (Linux)
+----------------------------
- Required for managing Python dependencies, this will allow you to reliably
- reproduce a Python environment to build documentation and run analysis tools.
- Most importantly, it ensures your system environment will not be affected by
- dependencies in the Python scripts.
+|TF-A| can be compiled on both Linux and Windows-based machines.
+However, we strongly recommend using a UNIX-compatible build environment.
-Package Installation (Linux)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Testing is performed using Ubuntu 22.04 LTS (64-bit), but other distributions
+should also work, provided the necessary tools and libraries are installed.
-If you are using the recommended Ubuntu distribution then you can install the
-required packages with the following command:
+The following are steps to install the required packages:
.. code:: shell
- sudo apt install build-essential git
+ sudo apt install build-essential
The optional packages can be installed using:
@@ -141,17 +151,6 @@
.. _prerequisites_get_source:
-Getting the TF-A Source
------------------------
-
-Source code for |TF-A| is maintained in a Git repository hosted on
-TrustedFirmware.org. To clone this repository from the server, run the following
-in your shell:
-
-.. code:: shell
-
- git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
-
Additional Steps for Contributors
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -189,5 +188,6 @@
.. _Gerrit Code Review: https://www.gerritcodereview.com/
.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
-.. _Development Studio (Arm-DS): https://developer.arm.com/Tools%20and%20Software/Arm%20Development%20Studio
+.. _Arm-DS: https://developer.arm.com/Tools%20and%20Software/Arm%20Development%20Studio
.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
+.. _TrustedFirmware.org: https://www.trustedfirmware.org/
diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst
index fe64558..4d4ec22 100644
--- a/docs/getting_started/rt-svc-writers-guide.rst
+++ b/docs/getting_started/rt-svc-writers-guide.rst
@@ -49,8 +49,11 @@
Fast 1 CPU Service calls
Fast 2 SiP Service calls
Fast 3 OEM Service calls
- Fast 4 Standard Service calls
- Fast 5-47 Reserved for future use
+ Fast 4 Standard Secure Service calls
+ Fast 5 Standard Hypervisor Service Calls
+ Fast 6 Vendor Specific Hypervisor Service Calls
+ Fast 7 Vendor Specific EL3 Monitor Calls
+ Fast 8-47 Reserved for future use
Fast 48-49 Trusted Application calls
Fast 50-63 Trusted OS calls
@@ -312,9 +315,17 @@
the BL31 support for these services. Or a reference to the document that will
provide this information....
+Additional References:
+----------------------
+
+#. :ref:`ARM SiP Services <arm sip services>`
+#. :ref:`Vendor Specific EL3 Monitor Service Calls`
+
--------------
-*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.*
.. _SMCCC: https://developer.arm.com/docs/den0028/latest
.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
+.. _ARM SiP Services: arm-sip-service.rst
+.. _Vendor Specific EL3 Monitor Service Calls: ven-el3-service.rst
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index bab1086..43a7d59 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -31,8 +31,8 @@
The following source trees and binaries were used:
-- TF-A [`v2.9-rc0`_]
-- TFTF [`v2.9-rc0`_]
+- `TF-A v2.11-rc0`_
+- `TFTF v2.11-rc0`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
<Runtime Instrumentation Methodology>`
@@ -73,23 +73,23 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- parallel (v2.9)
+ parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 104.58 | 241.20 | 5.26 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 384.24 | 22.50 | 138.76 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 244.56 | 22.18 | 5.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 670.56 | 18.58 | 4.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 809.36 | 269.28 | 4.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 984.96 | 219.70 | 79.62 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-------------------+--------------------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-------------------+--------------------+-------------+
+ | 0 | 0 | 112.98 (-53.44%) | 26.16 (-89.33%) | 5.48 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 0 | 1 | 411.18 | 438.88 (+1572.56%) | 138.54 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 0 | 261.82 (+150.88%) | 474.06 (+1649.30%) | 5.6 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 1 | 714.76 (+86.84%) | 26.44 | 4.48 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 2 | 862.66 | 149.34 (-45.00%) | 4.38 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 3 | 1045.12 | 98.12 (-55.76%) | 79.74 |
+ +---------+------+-------------------+--------------------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
parallel (v2.10)
@@ -111,22 +111,22 @@
+---------+------+-------------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- serial (v2.9)
+ serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 236.56 | 23.24 | 138.18 |
+ | 0 | 0 | 244.42 | 27.42 | 138.12 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 236.86 | 23.28 | 138.10 |
+ | 0 | 1 | 245.02 | 27.34 | 138.08 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 281.04 | 22.80 | 77.24 |
+ | 1 | 0 | 297.66 | 26.2 | 77.68 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 100.28 | 18.52 | 4.54 |
+ | 1 | 1 | 108.02 | 21.94 | 4.52 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 100.12 | 18.78 | 4.50 |
+ | 1 | 2 | 107.48 | 21.88 | 4.46 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 100.36 | 18.94 | 4.44 |
+ | 1 | 3 | 107.52 | 21.86 | 4.46 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
@@ -152,23 +152,23 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
- parallel (v2.9)
+ parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 662.34 | 15.22 | 8.08 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 802.00 | 15.50 | 8.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 385.22 | 15.74 | 7.88 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 106.16 | 16.06 | 7.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 524.38 | 15.64 | 7.34 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 246.00 | 15.78 | 7.72 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-------------------+--------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-------------------+--------+-------------+
+ | 0 | 0 | 704.46 | 19.28 | 7.86 |
+ +---------+------+-------------------+--------+-------------+
+ | 0 | 1 | 853.66 | 18.78 | 7.82 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 0 | 556.52 (+425.51%) | 19.06 | 7.82 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 1 | 113.28 (-70.47%) | 19.28 | 7.48 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 2 | 260.62 (-50.22%) | 19.8 | 7.26 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 3 | 408.16 (+66.94%) | 19.82 | 7.38 |
+ +---------+------+-------------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
parallel (v2.10)
@@ -189,22 +189,22 @@
| 1 | 3 | 244.5 | 20.16 | 7.56 |
+---------+------+-------------------+--------+-------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 99.80 | 15.94 | 5.42 |
+ | 0 | 0 | 106.78 | 19.2 | 5.32 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 99.76 | 15.80 | 5.24 |
+ | 0 | 1 | 107.44 | 19.64 | 5.44 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 278.26 | 16.16 | 4.58 |
+ | 1 | 0 | 295.82 | 19.14 | 4.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 96.88 | 16.00 | 4.52 |
+ | 1 | 1 | 104.34 | 19.18 | 4.28 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 96.80 | 16.12 | 4.54 |
+ | 1 | 2 | 103.96 | 19.34 | 4.4 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 96.88 | 16.12 | 4.54 |
+ | 1 | 3 | 104.32 | 19.18 | 4.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
@@ -231,22 +231,22 @@
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9)
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 235.76 | 26.14 | 137.80 |
+ | 0 | 0 | 243.62 | 29.84 | 137.66 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 235.40 | 25.72 | 137.62 |
+ | 0 | 1 | 243.88 | 29.54 | 137.8 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 174.70 | 22.40 | 77.26 |
+ | 1 | 0 | 183.26 | 26.22 | 77.76 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 100.92 | 24.04 | 4.52 |
+ | 1 | 1 | 107.64 | 26.74 | 4.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 100.68 | 22.44 | 4.36 |
+ | 1 | 2 | 107.52 | 25.9 | 4.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 101.36 | 22.70 | 4.52 |
+ | 1 | 3 | 107.74 | 25.8 | 4.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10)
@@ -272,23 +272,23 @@
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.9)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.11)
- +-------------+--------+-------------+
- | Cluster | Core | Latency |
- +-------------+--------+-------------+
- | 0 | 0 | 1.48 |
- +-------------+--------+-------------+
- | 0 | 1 | 1.04 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.56 |
- +-------------+--------+-------------+
- | 1 | 1 | 0.92 |
- +-------------+--------+-------------+
- | 1 | 2 | 0.96 |
- +-------------+--------+-------------+
- | 1 | 3 | 0.96 |
- +-------------+--------+-------------+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +-------------+--------+--------------+
+ | 0 | 0 | 1.26 |
+ +-------------+--------+--------------+
+ | 0 | 1 | 0.96 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.54 |
+ +-------------+--------+--------------+
+ | 1 | 1 | 0.94 |
+ +-------------+--------+--------------+
+ | 1 | 2 | 0.92 |
+ +-------------+--------+--------------+
+ | 1 | 3 | 1.02 |
+ +-------------+--------+--------------+
.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.10)
@@ -526,8 +526,9 @@
--------------
-*Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
.. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
-.. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0
+.. _TF-A v2.11-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.11-rc0
+.. _TFTF v2.11-rc0: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/?h=v2.11-rc0
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index fd3c9c9..c1c4dd6 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -6,8 +6,8 @@
The following source trees and binaries were used:
-- TF-A [`v2.9-rc0-16-g666aec401`_]
-- TFTF [`v2.9-rc0`_]
+- `TF-A v2.11-rc0`_
+- `TFTF v2.11-rc0`_
- SCP/MCP `Prebuilt Images`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
@@ -92,20 +92,19 @@
``CPU_SUSPEND`` to deepest power level
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- parallel (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.80 | 10.08 | 0.80 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 4.14 | 15.92 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 3.68 | 12.96 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 3.36 | 18.58 | 0.18 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+----------------+--------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+--------+----------------+
+ | 0 | 0 | 3.0 (+41.51%) | 23.14 | 1.2 (+185.71%) |
+ +---------+------+----------------+--------+----------------+
+ | 0 | 0 | 4.6 | 35.86 | 0.3 |
+ +---------+------+----------------+--------+----------------+
+ | 1 | 0 | 3.68 (+33.33%) | 33.36 | 0.3 |
+ +---------+------+----------------+--------+----------------+
+ | 1 | 0 | 3.7 (+40.15%) | 38.1 | 0.28 |
+ +---------+------+----------------+--------+----------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
parallel (v2.10)
@@ -122,19 +121,18 @@
| 1 | 0 | 2.64 | 44.56 (+139.83%) | 0.36 (+100.00%) |
+---------+------+----------------+------------------+-----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.86 | 9.92 | 0.32 |
+ | 0 | 0 | 1.7 | 22.46 | 0.3 |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.70 | 10.48 | 0.36 |
+ | 0 | 0 | 2.28 | 22.5 | 0.3 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.78 | 9.72 | 0.16 |
+ | 1 | 0 | 2.14 | 21.5 | 0.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.94 | 10.44 | 0.16 |
+ | 1 | 0 | 2.24 | 22.66 | 0.3 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
@@ -155,22 +153,19 @@
``CPU_SUSPEND`` to power level 0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
- parallel (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.11)
- +---------------------------------------------------+
- | test_rt_instr_cpu_susp_parallel |
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 0.88 | 12.32 | 0.26 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.12 | 14.62 | 0.26 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.86 | 14.14 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.92 | 9.44 | 0.18 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+----------------+--------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+--------+-------------+
+ | 0 | 0 | 0.94 (-37.33%) | 30.36 | 0.3 |
+ +---------+------+----------------+--------+-------------+
+ | 0 | 0 | 2.12 | 33.12 | 0.28 |
+ +---------+------+----------------+--------+-------------+
+ | 1 | 0 | 2.08 | 32.56 | 0.3 |
+ +---------+------+----------------+--------+-------------+
+ | 1 | 0 | 2.14 | 21.92 | 0.28 |
+ +---------+------+----------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
parallel (v2.10)
@@ -187,20 +182,18 @@
| 1 | 0 | 2.04 | 23.1 (+144.70%) | 0.24 |
+---------+------+---------------+------------------+----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
- +---------------------------------------------------+
- | test_rt_instr_cpu_susp_serial |
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.52 | 9.40 | 0.30 |
+ | 0 | 0 | 1.64 | 21.88 | 0.34 |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.92 | 9.80 | 0.18 |
+ | 0 | 0 | 2.42 | 21.76 | 0.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 2.20 | 9.60 | 0.14 |
+ | 1 | 0 | 2.02 | 21.14 | 0.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.82 | 9.78 | 0.18 |
+ | 1 | 0 | 2.18 | 22.3 | 0.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
@@ -223,19 +216,19 @@
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9)
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.84 | 9.94 | 0.32 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 14.20 | 13.10 | 0.50 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 13.88 | 12.36 | 0.42 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 14.40 | 13.26 | 0.52 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-----------+--------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-----------+--------+----------------+
+ | 0 | 0 | 1.96 | 22.44 | 0.38 |
+ +---------+------+-----------+--------+----------------+
+ | 0 | 0 | 13.76 | 30.34 | 0.26 |
+ +---------+------+-----------+--------+----------------+
+ | 1 | 0 | 13.46 | 28.28 | 0.24 |
+ +---------+------+-----------+--------+----------------+
+ | 1 | 0 | 13.84 | 30.06 | 0.28 (-60.00%) |
+ +---------+------+-----------+--------+----------------+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10)
@@ -254,21 +247,19 @@
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.9)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.11)
- +------------------------------------+
- | test_rt_instr_psci_version_parallel|
- +-------------+--------+-------------+
- | Cluster | Core | Latency |
- +-------------+--------+-------------+
- | 0 | 0 | 0.08 |
- +-------------+--------+-------------+
- | 0 | 0 | 0.26 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.20 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.26 |
- +-------------+--------+-------------+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +-------------+--------+--------------+
+ | 0 | 0 | 0.12 |
+ +-------------+--------+--------------+
+ | 0 | 0 | 0.24 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.2 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.26 |
+ +-------------+--------+--------------+
.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.10)
@@ -288,10 +279,10 @@
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
-.. _v2.9-rc0-16-g666aec401: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/heads/v2.9-rc0-16-g666aec401
-.. _v2.9-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.9-rc0
+.. _TF-A v2.11-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.11-rc0
+.. _TFTF v2.11-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.11-rc0
.. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
.. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/
.. _N1SDP: https://developer.arm.com/documentation/101489/latest
diff --git a/docs/plat/arm/fvp/fvp-aemv8-base.rst b/docs/plat/arm/fvp/fvp-aemv8-base.rst
new file mode 100644
index 0000000..6dd35e5
--- /dev/null
+++ b/docs/plat/arm/fvp/fvp-aemv8-base.rst
@@ -0,0 +1,154 @@
+Running on the AEMv8 Base FVP
+=============================
+
+AArch64 with reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_RevC-2xAEMv8A \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cluster0.NUM_CORES=4 \
+ -C cluster1.NUM_CORES=4 \
+ -C cache_state_modelled=1 \
+ -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
+ -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+.. note::
+ The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
+ a specific DTS for all the CPUs to be loaded.
+
+AArch32 with reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_AEMv8A-AEMv8A \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cluster0.NUM_CORES=4 \
+ -C cluster1.NUM_CORES=4 \
+ -C cache_state_modelled=1 \
+ -C cluster0.cpu0.CONFIG64=0 \
+ -C cluster0.cpu1.CONFIG64=0 \
+ -C cluster0.cpu2.CONFIG64=0 \
+ -C cluster0.cpu3.CONFIG64=0 \
+ -C cluster1.cpu0.CONFIG64=0 \
+ -C cluster1.cpu1.CONFIG64=0 \
+ -C cluster1.cpu2.CONFIG64=0 \
+ -C cluster1.cpu3.CONFIG64=0 \
+ -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
+ -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+AArch64 with reset to BL31 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_RevC-2xAEMv8A \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cluster0.NUM_CORES=4 \
+ -C cluster1.NUM_CORES=4 \
+ -C cache_state_modelled=1 \
+ -C cluster0.cpu0.RVBAR=0x04010000 \
+ -C cluster0.cpu1.RVBAR=0x04010000 \
+ -C cluster0.cpu2.RVBAR=0x04010000 \
+ -C cluster0.cpu3.RVBAR=0x04010000 \
+ -C cluster1.cpu0.RVBAR=0x04010000 \
+ -C cluster1.cpu1.RVBAR=0x04010000 \
+ -C cluster1.cpu2.RVBAR=0x04010000 \
+ -C cluster1.cpu3.RVBAR=0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
+ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+Notes:
+
+- Position Independent Executable (PIE) support is enabled in this
+ config allowing BL31 to be loaded at any valid address for execution.
+
+- Since a FIP is not loaded when using BL31 as reset entrypoint, the
+ ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
+ parameter is needed to load the individual bootloader images in memory.
+ BL32 image is only needed if BL31 has been built to expect a Secure-EL1
+ Payload. For the same reason, the FDT needs to be compiled from the DT source
+ and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
+ parameter.
+
+- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
+ specific DTS for all the CPUs to be loaded.
+
+- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
+ X and Y are the cluster and CPU numbers respectively, is used to set the
+ reset vector for each core.
+
+- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
+ changing the value of
+ ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
+ ``BL32_BASE``.
+
+AArch32 with reset to SP_MIN entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_AEMv8A-AEMv8A \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cluster0.NUM_CORES=4 \
+ -C cluster1.NUM_CORES=4 \
+ -C cache_state_modelled=1 \
+ -C cluster0.cpu0.CONFIG64=0 \
+ -C cluster0.cpu1.CONFIG64=0 \
+ -C cluster0.cpu2.CONFIG64=0 \
+ -C cluster0.cpu3.CONFIG64=0 \
+ -C cluster1.cpu0.CONFIG64=0 \
+ -C cluster1.cpu1.CONFIG64=0 \
+ -C cluster1.cpu2.CONFIG64=0 \
+ -C cluster1.cpu3.CONFIG64=0 \
+ -C cluster0.cpu0.RVBAR=0x04002000 \
+ -C cluster0.cpu1.RVBAR=0x04002000 \
+ -C cluster0.cpu2.RVBAR=0x04002000 \
+ -C cluster0.cpu3.RVBAR=0x04002000 \
+ -C cluster1.cpu0.RVBAR=0x04002000 \
+ -C cluster1.cpu1.RVBAR=0x04002000 \
+ -C cluster1.cpu2.RVBAR=0x04002000 \
+ -C cluster1.cpu3.RVBAR=0x04002000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
+ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+.. note::
+ Position Independent Executable (PIE) support is enabled in this
+ config allowing SP_MIN to be loaded at any valid address for execution.
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/fvp-build-options.rst b/docs/plat/arm/fvp/fvp-build-options.rst
new file mode 100644
index 0000000..b0359fa
--- /dev/null
+++ b/docs/plat/arm/fvp/fvp-build-options.rst
@@ -0,0 +1,51 @@
+.. _build_options_arm_fvp_platform:
+
+Arm FVP Platform Specific Build Options
+---------------------------------------
+
+- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
+ build the topology tree within TF-A. By default TF-A is configured for dual
+ cluster topology and this option can be used to override the default value.
+
+- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
+ default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
+ explained in the options below:
+
+ - ``FVP_CCI`` : The CCI driver is selected. This is the default
+ if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
+ - ``FVP_CCN`` : The CCN driver is selected. This is the default
+ if ``FVP_CLUSTER_COUNT`` > 2.
+
+- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
+ a single cluster. This option defaults to 4.
+
+- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
+ in the system. This option defaults to 1. Note that the build option
+ ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
+
+- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
+
+ - ``FVP_GICV2`` : The GICv2 only driver is selected
+ - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
+
+- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
+ to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
+ details on HW_CONFIG. By default, this is initialized to a sensible DTS
+ file in ``fdts/`` folder depending on other build options. But some cases,
+ like shifted affinity format for MPIDR, cannot be detected at build time
+ and this option is needed to specify the appropriate DTS file.
+
+- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
+ FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
+ similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
+ HW_CONFIG blob instead of the DTS file. This option is useful to override
+ the default HW_CONFIG selected by the build system.
+
+- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
+ inactive/fused CPU cores as read-only. The default value of this option
+ is ``0``, which means the redistributor pages of all CPU cores are marked
+ as read and write.
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/fvp-cortex-a32.rst b/docs/plat/arm/fvp/fvp-cortex-a32.rst
new file mode 100644
index 0000000..df17eed
--- /dev/null
+++ b/docs/plat/arm/fvp/fvp-cortex-a32.rst
@@ -0,0 +1,47 @@
+Running on the Cortex-A32 Base FVP (AArch32)
+============================================
+
+With reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
+boot Linux with 4 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_Cortex-A32x4 \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cache_state_modelled=1 \
+ -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
+ -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+With reset to SP_MIN entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
+boot Linux with 4 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_Cortex-A32x4 \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cache_state_modelled=1 \
+ -C cluster0.cpu0.RVBARADDR=0x04002000 \
+ -C cluster0.cpu1.RVBARADDR=0x04002000 \
+ -C cluster0.cpu2.RVBARADDR=0x04002000 \
+ -C cluster0.cpu3.RVBARADDR=0x04002000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
+ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/fvp-cortex-a57-a53.rst b/docs/plat/arm/fvp/fvp-cortex-a57-a53.rst
new file mode 100644
index 0000000..8f54114
--- /dev/null
+++ b/docs/plat/arm/fvp/fvp-cortex-a57-a53.rst
@@ -0,0 +1,52 @@
+Running on the Cortex-A57-A53 Base FVP
+======================================
+
+With reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
+boot Linux with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cache_state_modelled=1 \
+ -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
+ -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+With reset to BL31 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
+boot Linux with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cache_state_modelled=1 \
+ -C cluster0.cpu0.RVBARADDR=0x04010000 \
+ -C cluster0.cpu1.RVBARADDR=0x04010000 \
+ -C cluster0.cpu2.RVBARADDR=0x04010000 \
+ -C cluster0.cpu3.RVBARADDR=0x04010000 \
+ -C cluster1.cpu0.RVBARADDR=0x04010000 \
+ -C cluster1.cpu1.RVBARADDR=0x04010000 \
+ -C cluster1.cpu2.RVBARADDR=0x04010000 \
+ -C cluster1.cpu3.RVBARADDR=0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
+ --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/fvp-foundation.rst b/docs/plat/arm/fvp/fvp-foundation.rst
new file mode 100644
index 0000000..dd6f9dc
--- /dev/null
+++ b/docs/plat/arm/fvp/fvp-foundation.rst
@@ -0,0 +1,42 @@
+Running on the Foundation FVP
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``Foundation_Platform`` parameters should be used to boot Linux with
+4 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+ <path-to>/Foundation_Platform \
+ --cores=4 \
+ --arm-v8.0 \
+ --secure-memory \
+ --visualization \
+ --gicv3 \
+ --data="<path-to>/<bl1-binary>"@0x0 \
+ --data="<path-to>/<FIP-binary>"@0x08000000 \
+ --data="<path-to>/<kernel-binary>"@0x80080000 \
+ --data="<path-to>/<ramdisk-binary>"@0x84000000
+
+Notes:
+
+- BL1 is loaded at the start of the Trusted ROM.
+- The Firmware Image Package is loaded at the start of NOR FLASH0.
+- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
+ is specified via the ``load-address`` property in the ``hw-config`` node of
+ `FW_CONFIG for FVP`_.
+- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
+ and enable the GICv3 device in the model. Note that without this option,
+ the Foundation FVP defaults to legacy (Versatile Express) memory map which
+ is not supported by TF-A.
+- In order for TF-A to run correctly on the Foundation FVP, the architecture
+ versions must match. The Foundation FVP defaults to the highest v8.x
+ version it supports but the default build for TF-A is for v8.0. To avoid
+ issues either start the Foundation FVP to use v8.0 architecture using the
+ ``--arm-v8.0`` option, or build TF-A with an appropriate value for
+ ``ARM_ARCH_MINOR``.
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+
+.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts
diff --git a/docs/plat/arm/fvp/fvp-specific-configs.rst b/docs/plat/arm/fvp/fvp-specific-configs.rst
new file mode 100644
index 0000000..63b3c31
--- /dev/null
+++ b/docs/plat/arm/fvp/fvp-specific-configs.rst
@@ -0,0 +1,209 @@
+Booting Firmware Update images
+------------------------------
+
+When Firmware Update (FWU) is enabled there are at least 2 new images
+that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
+FWU FIP.
+
+The additional fip images must be loaded with:
+
+::
+
+ --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
+ --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
+
+The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
+In the same way, the address ns_bl2u_base_address is the value of
+NS_BL2U_BASE.
+
+Booting an EL3 payload
+----------------------
+
+The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
+the secondary CPUs holding pen to work properly. Unfortunately, its reset value
+is undefined on the FVP platform and the FVP platform code doesn't clear it.
+Therefore, one must modify the way the model is normally invoked in order to
+clear the mailbox at start-up.
+
+One way to do that is to create an 8-byte file containing all zero bytes using
+the following command:
+
+.. code:: shell
+
+ dd if=/dev/zero of=mailbox.dat bs=1 count=8
+
+and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
+using the following model parameters:
+
+::
+
+ --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
+ --data=mailbox.dat@0x04000000 [Foundation FVP]
+
+To provide the model with the EL3 payload image, the following methods may be
+used:
+
+#. If the EL3 payload is able to execute in place, it may be programmed into
+ flash memory. On Base Cortex and AEM FVPs, the following model parameter
+ loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
+ used for the FIP):
+
+ ::
+
+ -C bp.flashloader1.fname="<path-to>/<el3-payload>"
+
+ On Foundation FVP, there is no flash loader component and the EL3 payload
+ may be programmed anywhere in flash using method 3 below.
+
+#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
+ command may be used to load the EL3 payload ELF image over JTAG:
+
+ ::
+
+ load <path-to>/el3-payload.elf
+
+#. The EL3 payload may be pre-loaded in volatile memory using the following
+ model parameters:
+
+ ::
+
+ --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
+ --data="<path-to>/<el3-payload>"@address [Foundation FVP]
+
+ The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
+ used when building TF-A.
+
+Booting a preloaded kernel image (Base FVP)
+-------------------------------------------
+
+The following example uses a simplified boot flow by directly jumping from the
+TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
+useful if both the kernel and the device tree blob (DTB) are already present in
+memory (like in FVP).
+
+For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
+address ``0x82000000``, the firmware can be built like this:
+
+.. code:: shell
+
+ CROSS_COMPILE=aarch64-none-elf- \
+ make PLAT=fvp DEBUG=1 \
+ RESET_TO_BL31=1 \
+ ARM_LINUX_KERNEL_AS_BL33=1 \
+ PRELOADED_BL33_BASE=0x80080000 \
+ ARM_PRELOADED_DTB_BASE=0x82000000 \
+ all fip
+
+Now, it is needed to modify the DTB so that the kernel knows the address of the
+ramdisk. The following script generates a patched DTB from the provided one,
+assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
+script assumes that the user is using a ramdisk image prepared for U-Boot, like
+the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
+offset in ``INITRD_START`` has to be removed.
+
+.. code:: bash
+
+ #!/bin/bash
+
+ # Path to the input DTB
+ KERNEL_DTB=<path-to>/<fdt>
+ # Path to the output DTB
+ PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
+ # Base address of the ramdisk
+ INITRD_BASE=0x84000000
+ # Path to the ramdisk
+ INITRD=<path-to>/<ramdisk.img>
+
+ # Skip uboot header (64 bytes)
+ INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
+ INITRD_SIZE=$(stat -Lc %s ${INITRD})
+ INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
+
+ CHOSEN_NODE=$(echo \
+ "/ { \
+ chosen { \
+ linux,initrd-start = <${INITRD_START}>; \
+ linux,initrd-end = <${INITRD_END}>; \
+ }; \
+ };")
+
+ echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
+ dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
+
+And the FVP binary can be run with the following command:
+
+.. code:: shell
+
+ <path-to>/FVP_Base_AEMv8A-AEMv8A \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C cluster0.NUM_CORES=4 \
+ -C cluster1.NUM_CORES=4 \
+ -C cache_state_modelled=1 \
+ -C cluster0.cpu0.RVBAR=0x04001000 \
+ -C cluster0.cpu1.RVBAR=0x04001000 \
+ -C cluster0.cpu2.RVBAR=0x04001000 \
+ -C cluster0.cpu3.RVBAR=0x04001000 \
+ -C cluster1.cpu0.RVBAR=0x04001000 \
+ -C cluster1.cpu1.RVBAR=0x04001000 \
+ -C cluster1.cpu2.RVBAR=0x04001000 \
+ -C cluster1.cpu3.RVBAR=0x04001000 \
+ --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \
+ --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+ --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
+
+Obtaining the Flattened Device Trees
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Depending on the FVP configuration and Linux configuration used, different
+FDT files are required. FDT source files for the Foundation and Base FVPs can
+be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
+a subset of the Base FVP components. For example, the Foundation FVP lacks
+CLCD and MMC support, and has only one CPU cluster.
+
+.. note::
+ It is not recommended to use the FDTs built along the kernel because not
+ all FDTs are available from there.
+
+The dynamic configuration capability is enabled in the firmware for FVPs.
+This means that the firmware can authenticate and load the FDT if present in
+FIP. A default FDT is packaged into FIP during the build based on
+the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
+or ``FVP_HW_CONFIG_DTS`` build options (refer to
+:ref:`build_options_arm_fvp_platform` for details on the options).
+
+- ``fvp-base-gicv2-psci.dts``
+
+ For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
+ without shifted affinities and with Base memory map configuration.
+
+- ``fvp-base-gicv3-psci.dts``
+
+ For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
+ without shifted affinities and with Base memory map configuration and
+ Linux GICv3 support.
+
+- ``fvp-base-gicv3-psci-1t.dts``
+
+ For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
+ single threaded CPUs, Base memory map configuration and Linux GICv3 support.
+
+- ``fvp-base-gicv3-psci-dynamiq.dts``
+
+ For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
+ single cluster, single threaded CPUs, Base memory map configuration and Linux
+ GICv3 support.
+
+- ``fvp-foundation-gicv2-psci.dts``
+
+ For use with Foundation FVP with Base memory map configuration.
+
+- ``fvp-foundation-gicv3-psci.dts``
+
+ (Default) For use with Foundation FVP with Base memory map configuration
+ and Linux GICv3 support.
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
new file mode 100644
index 0000000..cc1b500
--- /dev/null
+++ b/docs/plat/arm/fvp/fvp-support.rst
@@ -0,0 +1,105 @@
+Fixed Virtual Platform (FVP) Support
+------------------------------------
+
+This section lists the supported Arm |FVP| platforms. Please refer to the FVP
+documentation for a detailed description of the model parameter options.
+
+The latest version of the AArch64 build of TF-A has been tested on the following
+Arm FVPs without shifted affinities, and that do not support threaded CPU cores
+(64-bit host machine only).
+
+.. note::
+ The FVP models used are Version 11.22 Build 14, unless otherwise stated.
+
+- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21)
+- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
+- ``FVP_Base_AEMvA``
+- ``FVP_Base_AEMvA-AEMvA``
+- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38)
+- ``FVP_Base_Cortex-A35x4``
+- ``FVP_Base_Cortex-A53x4``
+- ``FVP_Base_Cortex-A55``
+- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
+- ``FVP_Base_Cortex-A55x4+Cortex-A76x2``
+- ``FVP_Base_Cortex-A57x1-A53x1``
+- ``FVP_Base_Cortex-A57x2-A53x4``
+- ``FVP_Base_Cortex-A57x4``
+- ``FVP_Base_Cortex-A57x4-A53x4``
+- ``FVP_Base_Cortex-A65``
+- ``FVP_Base_Cortex-A65AE``
+- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21)
+- ``FVP_Base_Cortex-A72x4``
+- ``FVP_Base_Cortex-A72x4-A53x4``
+- ``FVP_Base_Cortex-A73x4``
+- ``FVP_Base_Cortex-A73x4-A53x4``
+- ``FVP_Base_Cortex-A75``
+- ``FVP_Base_Cortex-A76``
+- ``FVP_Base_Cortex-A76AE``
+- ``FVP_Base_Cortex-A77``
+- ``FVP_Base_Cortex-A78``
+- ``FVP_Base_Cortex-A78AE``
+- ``FVP_Base_Cortex-A78C``
+- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21)
+- ``FVP_Base_Neoverse-E1``
+- ``FVP_Base_Neoverse-N1``
+- ``FVP_Base_Neoverse-V1``
+- ``FVP_Base_RevC-2xAEMv8A``
+- ``FVP_BaseR_AEMv8R``
+- ``FVP_Morello`` (Version 0.11/33)
+- ``FVP_RD_V1``
+- ``FVP_TC1``
+- ``FVP_TC2`` (Version 11.23/17)
+
+The latest version of the AArch32 build of TF-A has been tested on the
+following Arm FVPs without shifted affinities, and that do not support threaded
+CPU cores (64-bit host machine only).
+
+- ``FVP_Base_AEMvA``
+- ``FVP_Base_AEMvA-AEMvA``
+- ``FVP_Base_Cortex-A32x4``
+
+.. note::
+ The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
+ is not compatible with legacy GIC configurations. Therefore this FVP does not
+ support these legacy GIC configurations.
+
+The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
+FVP website`_. The Cortex-A models listed above are also available to download
+from `Arm's website`_.
+
+.. note::
+ The build numbers quoted above are those reported by launching the FVP
+ with the ``--version`` parameter.
+
+.. note::
+ Linaro provides a ramdisk image in prebuilt FVP configurations and full
+ file systems that can be downloaded separately. To run an FVP with a virtio
+ file system image an additional FVP configuration option
+ ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
+ used.
+
+.. note::
+ The software will not work on Version 1.0 of the Foundation FVP.
+ The commands below would report an ``unhandled argument`` error in this case.
+
+.. note::
+ FVPs can be launched with ``--cadi-server`` option such that a
+ CADI-compliant debugger (for example, Arm DS-5) can connect to and control
+ its execution.
+
+.. warning::
+ Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
+ the internal synchronisation timings changed compared to older versions of
+ the models. The models can be launched with ``-Q 100`` option if they are
+ required to match the run time characteristics of the older versions.
+
+All the above platforms have been tested with `Linaro Release 20.01`_.
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+
+.. _Arm's website: `FVP models`_
+.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
+.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index 55cefe1..088beec 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -1,638 +1,31 @@
Arm Fixed Virtual Platforms (FVP)
=================================
-Fixed Virtual Platform (FVP) Support
-------------------------------------
+Arm |FVP|\s are complete simulations of an Arm system, including processor,
+memory and peripherals. They enable software development without the need for
+real hardware.
-This section lists the supported Arm |FVP| platforms. Please refer to the FVP
-documentation for a detailed description of the model parameter options.
+There exists many types of FVPs. This page provides details on how to build and
+run TF-A on some of these FVPs.
-The latest version of the AArch64 build of TF-A has been tested on the following
-Arm FVPs without shifted affinities, and that do not support threaded CPU cores
-(64-bit host machine only).
+Please also refer to the TF-A CI scripts under the `model/`_ directory for an
+exhaustive list of |FVP|\s which TF-A is regularly tested on as part of our
+continuous integration strategy.
-.. note::
- The FVP models used are Version 11.22 Build 14, unless otherwise stated.
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
-- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21)
-- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
-- ``FVP_Base_AEMvA``
-- ``FVP_Base_AEMvA-AEMvA``
-- ``FVP_Base_Cortex-A32x4`` (Version 11.12/38)
-- ``FVP_Base_Cortex-A35x4``
-- ``FVP_Base_Cortex-A53x4``
-- ``FVP_Base_Cortex-A55``
-- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
-- ``FVP_Base_Cortex-A55x4+Cortex-A76x2``
-- ``FVP_Base_Cortex-A57x1-A53x1``
-- ``FVP_Base_Cortex-A57x2-A53x4``
-- ``FVP_Base_Cortex-A57x4``
-- ``FVP_Base_Cortex-A57x4-A53x4``
-- ``FVP_Base_Cortex-A65``
-- ``FVP_Base_Cortex-A65AE``
-- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21)
-- ``FVP_Base_Cortex-A72x4``
-- ``FVP_Base_Cortex-A72x4-A53x4``
-- ``FVP_Base_Cortex-A73x4``
-- ``FVP_Base_Cortex-A73x4-A53x4``
-- ``FVP_Base_Cortex-A75``
-- ``FVP_Base_Cortex-A76``
-- ``FVP_Base_Cortex-A76AE``
-- ``FVP_Base_Cortex-A77``
-- ``FVP_Base_Cortex-A78``
-- ``FVP_Base_Cortex-A78AE``
-- ``FVP_Base_Cortex-A78C``
-- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21)
-- ``FVP_Base_Neoverse-E1``
-- ``FVP_Base_Neoverse-N1``
-- ``FVP_Base_Neoverse-V1``
-- ``FVP_Base_RevC-2xAEMvA``
-- ``FVP_BaseR_AEMv8R``
-- ``FVP_Morello`` (Version 0.11/33)
-- ``FVP_RD_V1``
-- ``FVP_TC1``
-- ``FVP_TC2`` (Version 11.23/17)
-
-The latest version of the AArch32 build of TF-A has been tested on the
-following Arm FVPs without shifted affinities, and that do not support threaded
-CPU cores (64-bit host machine only).
-
-- ``FVP_Base_AEMvA``
-- ``FVP_Base_AEMvA-AEMvA``
-- ``FVP_Base_Cortex-A32x4``
-
-.. note::
- The ``FVP_Base_RevC-2xAEMvA`` FVP only supports shifted affinities, which
- is not compatible with legacy GIC configurations. Therefore this FVP does not
- support these legacy GIC configurations.
-
-The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
-FVP website`_. The Cortex-A models listed above are also available to download
-from `Arm's website`_.
-
-.. note::
- The build numbers quoted above are those reported by launching the FVP
- with the ``--version`` parameter.
-
-.. note::
- Linaro provides a ramdisk image in prebuilt FVP configurations and full
- file systems that can be downloaded separately. To run an FVP with a virtio
- file system image an additional FVP configuration option
- ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
- used.
-
-.. note::
- The software will not work on Version 1.0 of the Foundation FVP.
- The commands below would report an ``unhandled argument`` error in this case.
-
-.. note::
- FVPs can be launched with ``--cadi-server`` option such that a
- CADI-compliant debugger (for example, Arm DS-5) can connect to and control
- its execution.
-
-.. warning::
- Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
- the internal synchronisation timings changed compared to older versions of
- the models. The models can be launched with ``-Q 100`` option if they are
- required to match the run time characteristics of the older versions.
-
-All the above platforms have been tested with `Linaro Release 20.01`_.
-
-.. _build_options_arm_fvp_platform:
-
-Arm FVP Platform Specific Build Options
----------------------------------------
-
-- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
- build the topology tree within TF-A. By default TF-A is configured for dual
- cluster topology and this option can be used to override the default value.
-
-- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
- default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
- explained in the options below:
-
- - ``FVP_CCI`` : The CCI driver is selected. This is the default
- if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
- - ``FVP_CCN`` : The CCN driver is selected. This is the default
- if ``FVP_CLUSTER_COUNT`` > 2.
-
-- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
- a single cluster. This option defaults to 4.
-
-- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
- in the system. This option defaults to 1. Note that the build option
- ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
-
-- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
-
- - ``FVP_GICV2`` : The GICv2 only driver is selected
- - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
-
-- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
- to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
- details on HW_CONFIG. By default, this is initialized to a sensible DTS
- file in ``fdts/`` folder depending on other build options. But some cases,
- like shifted affinity format for MPIDR, cannot be detected at build time
- and this option is needed to specify the appropriate DTS file.
-
-- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
- FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
- similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
- HW_CONFIG blob instead of the DTS file. This option is useful to override
- the default HW_CONFIG selected by the build system.
-
-- ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
- inactive/fused CPU cores as read-only. The default value of this option
- is ``0``, which means the redistributor pages of all CPU cores are marked
- as read and write.
-
-Booting Firmware Update images
-------------------------------
-
-When Firmware Update (FWU) is enabled there are at least 2 new images
-that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
-FWU FIP.
-
-The additional fip images must be loaded with:
-
-::
-
- --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
- --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
-
-The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
-In the same way, the address ns_bl2u_base_address is the value of
-NS_BL2U_BASE.
-
-Booting an EL3 payload
-----------------------
-
-The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
-the secondary CPUs holding pen to work properly. Unfortunately, its reset value
-is undefined on the FVP platform and the FVP platform code doesn't clear it.
-Therefore, one must modify the way the model is normally invoked in order to
-clear the mailbox at start-up.
-
-One way to do that is to create an 8-byte file containing all zero bytes using
-the following command:
-
-.. code:: shell
-
- dd if=/dev/zero of=mailbox.dat bs=1 count=8
-
-and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
-using the following model parameters:
-
-::
-
- --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
- --data=mailbox.dat@0x04000000 [Foundation FVP]
-
-To provide the model with the EL3 payload image, the following methods may be
-used:
-
-#. If the EL3 payload is able to execute in place, it may be programmed into
- flash memory. On Base Cortex and AEM FVPs, the following model parameter
- loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
- used for the FIP):
-
- ::
-
- -C bp.flashloader1.fname="<path-to>/<el3-payload>"
-
- On Foundation FVP, there is no flash loader component and the EL3 payload
- may be programmed anywhere in flash using method 3 below.
-
-#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
- command may be used to load the EL3 payload ELF image over JTAG:
-
- ::
-
- load <path-to>/el3-payload.elf
-
-#. The EL3 payload may be pre-loaded in volatile memory using the following
- model parameters:
-
- ::
-
- --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
- --data="<path-to>/<el3-payload>"@address [Foundation FVP]
-
- The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
- used when building TF-A.
-
-Booting a preloaded kernel image (Base FVP)
--------------------------------------------
-
-The following example uses a simplified boot flow by directly jumping from the
-TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
-useful if both the kernel and the device tree blob (DTB) are already present in
-memory (like in FVP).
-
-For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
-address ``0x82000000``, the firmware can be built like this:
-
-.. code:: shell
-
- CROSS_COMPILE=aarch64-none-elf- \
- make PLAT=fvp DEBUG=1 \
- RESET_TO_BL31=1 \
- ARM_LINUX_KERNEL_AS_BL33=1 \
- PRELOADED_BL33_BASE=0x80080000 \
- ARM_PRELOADED_DTB_BASE=0x82000000 \
- all fip
-
-Now, it is needed to modify the DTB so that the kernel knows the address of the
-ramdisk. The following script generates a patched DTB from the provided one,
-assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
-script assumes that the user is using a ramdisk image prepared for U-Boot, like
-the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
-offset in ``INITRD_START`` has to be removed.
-
-.. code:: bash
-
- #!/bin/bash
-
- # Path to the input DTB
- KERNEL_DTB=<path-to>/<fdt>
- # Path to the output DTB
- PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
- # Base address of the ramdisk
- INITRD_BASE=0x84000000
- # Path to the ramdisk
- INITRD=<path-to>/<ramdisk.img>
-
- # Skip uboot header (64 bytes)
- INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
- INITRD_SIZE=$(stat -Lc %s ${INITRD})
- INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
-
- CHOSEN_NODE=$(echo \
- "/ { \
- chosen { \
- linux,initrd-start = <${INITRD_START}>; \
- linux,initrd-end = <${INITRD_END}>; \
- }; \
- };")
-
- echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
- dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
-
-And the FVP binary can be run with the following command:
-
-.. code:: shell
-
- <path-to>/FVP_Base_AEMv8A-AEMv8A \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C cluster0.NUM_CORES=4 \
- -C cluster1.NUM_CORES=4 \
- -C cache_state_modelled=1 \
- -C cluster0.cpu0.RVBAR=0x04001000 \
- -C cluster0.cpu1.RVBAR=0x04001000 \
- -C cluster0.cpu2.RVBAR=0x04001000 \
- -C cluster0.cpu3.RVBAR=0x04001000 \
- -C cluster1.cpu0.RVBAR=0x04001000 \
- -C cluster1.cpu1.RVBAR=0x04001000 \
- -C cluster1.cpu2.RVBAR=0x04001000 \
- -C cluster1.cpu3.RVBAR=0x04001000 \
- --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \
- --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
-
-Obtaining the Flattened Device Trees
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Depending on the FVP configuration and Linux configuration used, different
-FDT files are required. FDT source files for the Foundation and Base FVPs can
-be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
-a subset of the Base FVP components. For example, the Foundation FVP lacks
-CLCD and MMC support, and has only one CPU cluster.
-
-.. note::
- It is not recommended to use the FDTs built along the kernel because not
- all FDTs are available from there.
-
-The dynamic configuration capability is enabled in the firmware for FVPs.
-This means that the firmware can authenticate and load the FDT if present in
-FIP. A default FDT is packaged into FIP during the build based on
-the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
-or ``FVP_HW_CONFIG_DTS`` build options (refer to
-:ref:`build_options_arm_fvp_platform` for details on the options).
-
-- ``fvp-base-gicv2-psci.dts``
-
- For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
- without shifted affinities and with Base memory map configuration.
-
-- ``fvp-base-gicv3-psci.dts``
-
- For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
- without shifted affinities and with Base memory map configuration and
- Linux GICv3 support.
-
-- ``fvp-base-gicv3-psci-1t.dts``
-
- For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
- single threaded CPUs, Base memory map configuration and Linux GICv3 support.
-
-- ``fvp-base-gicv3-psci-dynamiq.dts``
-
- For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
- single cluster, single threaded CPUs, Base memory map configuration and Linux
- GICv3 support.
-
-- ``fvp-foundation-gicv2-psci.dts``
-
- For use with Foundation FVP with Base memory map configuration.
-
-- ``fvp-foundation-gicv3-psci.dts``
-
- (Default) For use with Foundation FVP with Base memory map configuration
- and Linux GICv3 support.
-
-
-Running on the Foundation FVP with reset to BL1 entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``Foundation_Platform`` parameters should be used to boot Linux with
-4 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
- <path-to>/Foundation_Platform \
- --cores=4 \
- --arm-v8.0 \
- --secure-memory \
- --visualization \
- --gicv3 \
- --data="<path-to>/<bl1-binary>"@0x0 \
- --data="<path-to>/<FIP-binary>"@0x08000000 \
- --data="<path-to>/<kernel-binary>"@0x80080000 \
- --data="<path-to>/<ramdisk-binary>"@0x84000000
-
-Notes:
-
-- BL1 is loaded at the start of the Trusted ROM.
-- The Firmware Image Package is loaded at the start of NOR FLASH0.
-- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
- is specified via the ``load-address`` property in the ``hw-config`` node of
- `FW_CONFIG for FVP`_.
-- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
- and enable the GICv3 device in the model. Note that without this option,
- the Foundation FVP defaults to legacy (Versatile Express) memory map which
- is not supported by TF-A.
-- In order for TF-A to run correctly on the Foundation FVP, the architecture
- versions must match. The Foundation FVP defaults to the highest v8.x
- version it supports but the default build for TF-A is for v8.0. To avoid
- issues either start the Foundation FVP to use v8.0 architecture using the
- ``--arm-v8.0`` option, or build TF-A with an appropriate value for
- ``ARM_ARCH_MINOR``.
-
-Running on the AEMv8 Base FVP with reset to BL1 entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_RevC-2xAEMv8A \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cluster0.NUM_CORES=4 \
- -C cluster1.NUM_CORES=4 \
- -C cache_state_modelled=1 \
- -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
- -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-.. note::
- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
- a specific DTS for all the CPUs to be loaded.
-
-Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_AEMv8A-AEMv8A \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cluster0.NUM_CORES=4 \
- -C cluster1.NUM_CORES=4 \
- -C cache_state_modelled=1 \
- -C cluster0.cpu0.CONFIG64=0 \
- -C cluster0.cpu1.CONFIG64=0 \
- -C cluster0.cpu2.CONFIG64=0 \
- -C cluster0.cpu3.CONFIG64=0 \
- -C cluster1.cpu0.CONFIG64=0 \
- -C cluster1.cpu1.CONFIG64=0 \
- -C cluster1.cpu2.CONFIG64=0 \
- -C cluster1.cpu3.CONFIG64=0 \
- -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
- -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
-boot Linux with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cache_state_modelled=1 \
- -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
- -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
-boot Linux with 4 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_Cortex-A32x4 \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cache_state_modelled=1 \
- -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
- -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-
-Running on the AEMv8 Base FVP with reset to BL31 entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_RevC-2xAEMv8A \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cluster0.NUM_CORES=4 \
- -C cluster1.NUM_CORES=4 \
- -C cache_state_modelled=1 \
- -C cluster0.cpu0.RVBAR=0x04010000 \
- -C cluster0.cpu1.RVBAR=0x04010000 \
- -C cluster0.cpu2.RVBAR=0x04010000 \
- -C cluster0.cpu3.RVBAR=0x04010000 \
- -C cluster1.cpu0.RVBAR=0x04010000 \
- -C cluster1.cpu1.RVBAR=0x04010000 \
- -C cluster1.cpu2.RVBAR=0x04010000 \
- -C cluster1.cpu3.RVBAR=0x04010000 \
- --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
- --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
- --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Notes:
-
-- Position Independent Executable (PIE) support is enabled in this
- config allowing BL31 to be loaded at any valid address for execution.
-
-- Since a FIP is not loaded when using BL31 as reset entrypoint, the
- ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
- parameter is needed to load the individual bootloader images in memory.
- BL32 image is only needed if BL31 has been built to expect a Secure-EL1
- Payload. For the same reason, the FDT needs to be compiled from the DT source
- and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
- parameter.
-
-- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
- specific DTS for all the CPUs to be loaded.
-
-- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
- X and Y are the cluster and CPU numbers respectively, is used to set the
- reset vector for each core.
-
-- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
- changing the value of
- ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
- ``BL32_BASE``.
-
-
-Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_AEMv8A-AEMv8A \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cluster0.NUM_CORES=4 \
- -C cluster1.NUM_CORES=4 \
- -C cache_state_modelled=1 \
- -C cluster0.cpu0.CONFIG64=0 \
- -C cluster0.cpu1.CONFIG64=0 \
- -C cluster0.cpu2.CONFIG64=0 \
- -C cluster0.cpu3.CONFIG64=0 \
- -C cluster1.cpu0.CONFIG64=0 \
- -C cluster1.cpu1.CONFIG64=0 \
- -C cluster1.cpu2.CONFIG64=0 \
- -C cluster1.cpu3.CONFIG64=0 \
- -C cluster0.cpu0.RVBAR=0x04002000 \
- -C cluster0.cpu1.RVBAR=0x04002000 \
- -C cluster0.cpu2.RVBAR=0x04002000 \
- -C cluster0.cpu3.RVBAR=0x04002000 \
- -C cluster1.cpu0.RVBAR=0x04002000 \
- -C cluster1.cpu1.RVBAR=0x04002000 \
- -C cluster1.cpu2.RVBAR=0x04002000 \
- -C cluster1.cpu3.RVBAR=0x04002000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
- --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
- --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-.. note::
- Position Independent Executable (PIE) support is enabled in this
- config allowing SP_MIN to be loaded at any valid address for execution.
-
-Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
-boot Linux with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cache_state_modelled=1 \
- -C cluster0.cpu0.RVBARADDR=0x04010000 \
- -C cluster0.cpu1.RVBARADDR=0x04010000 \
- -C cluster0.cpu2.RVBARADDR=0x04010000 \
- -C cluster0.cpu3.RVBARADDR=0x04010000 \
- -C cluster1.cpu0.RVBARADDR=0x04010000 \
- -C cluster1.cpu1.RVBARADDR=0x04010000 \
- -C cluster1.cpu2.RVBARADDR=0x04010000 \
- -C cluster1.cpu3.RVBARADDR=0x04010000 \
- --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
- --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
- --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
-boot Linux with 4 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
- <path-to>/FVP_Base_Cortex-A32x4 \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cache_state_modelled=1 \
- -C cluster0.cpu0.RVBARADDR=0x04002000 \
- -C cluster0.cpu1.RVBARADDR=0x04002000 \
- -C cluster0.cpu2.RVBARADDR=0x04002000 \
- -C cluster0.cpu3.RVBARADDR=0x04002000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
- --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
- --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
- --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
- --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+ fvp-support
+ fvp-build-options
+ fvp-foundation
+ fvp-aemv8-base
+ fvp-cortex-a57-a53
+ fvp-cortex-a32
+ fvp-specific-configs
--------------
*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
-.. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts
-.. _Arm's website: `FVP models`_
-.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
-.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _model/: https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/model
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 702726e..5c1ded0 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -29,6 +29,7 @@
imx8m
imx8ulp
imx9
+ s32g274a
npcm845x
nxp/index
poplar
diff --git a/docs/plat/s32g274a.rst b/docs/plat/s32g274a.rst
new file mode 100644
index 0000000..3aa858e
--- /dev/null
+++ b/docs/plat/s32g274a.rst
@@ -0,0 +1,99 @@
+NXP S32G274A
+============
+
+S32G2 is an NXP vehicle network processor combining ASIL D safety, hardware
+security, high-performance real-time and application processing and network
+acceleration. S32G2 supports the needs of new vehicle architectures:
+service-oriented gateways, domain controllers, zonal processors, safety
+processors and more. It is equipped with 4 Cortex-A53 cores operating at
+1.0GHz.
+
+The TF-A includes support for one single S32G2-based board called S32G274ARDB2.
+The S32G-VNP-RDB2 is a compact, highly optimized and integrated board
+engineering for vehicle service-oriented gateway (SoG), domain control
+applications, high-performance processing, safety and security applications.
+More details about this board can be found at `s32g274ardb2`_.
+
+Boot Flow
+---------
+
+::
+
+ BootROM -> BL2 (SRAM) -> BL31 (SRAM) -> BL33 (DDR - TODO)
+
+.. warning::
+ This boot flow is a preliminary version that will serve as a foundation for
+ upcoming S32G2 contributions. The execution will hang after the BL31 stage
+ due to U-Boot being deployed in SRAM instead of DDR. This issue will be
+ resolved with the addition of the DDR driver.
+
+Code Locations
+--------------
+
+- Downstream TF-A:
+ `link: <https://github.com/nxp-auto-linux/arm-trusted-firmware>`__
+
+- Downstream U-Boot:
+ `link <https://github.com/nxp-auto-linux/u-boot>`__
+
+- Downstream Linux:
+ `link <https://github.com/nxp-auto-linux/linux>`__
+
+How to build
+------------
+
+The port currently available on the S32G274ARDB2 platform is in its initial
+stage. This means that important drivers like DDR and storage are not yet
+available. Consequently, the boot process depends on BootROM to load all TF-A
+stages in SRAM. To create a bootable image, the script below should be used.
+This script makes use of the ``mkimage`` tool, which is part of the U-Boot drop
+for S32G274A SoCs.
+
+.. code:: bash
+
+ #!/bin/bash -xe
+ TF_A="${TF_A:-`pwd`}"
+ UBOOT="${UBOOT:-${TF_A}/../u-boot}"
+ DEBUG="${DEBUG:-1}"
+
+ FIP_BASE="0x34100000"
+
+ if [ "${DEBUG}" -eq "1" ]; then
+ BUILD="debug"
+ else
+ BUILD="release"
+ fi
+
+ BOOT_IMAGE="build/s32g274ardb2/${BUILD}/BOOT_IMAGE.bin"
+ BL2_BIN="build/s32g274ardb2/${BUILD}/bl2.bin"
+ FIP_BIN="build/s32g274ardb2/${BUILD}/fip.bin"
+
+ # Generate bl2, bl31 and fip image
+ make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \
+ BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" clean
+ make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \
+ BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" bl2
+ make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \
+ BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" fip
+
+ # Extract BL2 entry
+ BL2_START="0x$(poetry run memory -p s32g274ardb2 -b debug -f | \
+ grep BL2 | awk -F'|' '{print $3}' | xargs)"
+ # BL2 bin file size in bytes
+ BL2_SIZE="$(stat -c "%s" "${BL2_BIN}")"
+
+ # Pack bl2.bin and fip.bin by ensuring that the FIP image will start at FIP_BASE
+ cp -vf "${BL2_BIN}" "${BOOT_IMAGE}"
+ dd if="${FIP_BIN}" of="${BOOT_IMAGE}" seek="$((FIP_BASE - BL2_START))" bs=1
+
+ # Build a bootable image by appending the IVT
+ "${UBOOT}/tools/mkimage" \
+ -a "${BL2_START}" \
+ -e "${BL2_START}" \
+ -T s32ccimage \
+ -n "${UBOOT}/u-boot-s32.cfgout" \
+ -d "${BOOT_IMAGE}" \
+ fip.s32
+
+.. _s32g2: https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g2-processors-for-vehicle-networking:S32G2
+.. _s32g274ardb2: https://www.nxp.com/design/design-center/designs/s32g2-vehicle-networking-reference-design:S32G-VNP-RDB2
diff --git a/docs/plat/st/stm32mpus.rst b/docs/plat/st/stm32mpus.rst
index ab6d8fe..7b47112 100644
--- a/docs/plat/st/stm32mpus.rst
+++ b/docs/plat/st/stm32mpus.rst
@@ -54,8 +54,6 @@
| Default: stm32mp157c-ev1.dtb
- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP,
| default location (end of the first 128MB) is used when absent
-- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup.
- | Default: 0 (disabled)
- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2).
| Default: 0 (disabled)
- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate.
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 7c66d11..a7600ec 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -256,10 +256,10 @@
Defines the maximum address in secure RAM that the BL31 image can occupy.
-- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE**
+- **#define : PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE**
- Defines the maximum message size between AP and RSS. Need to define if
- platform supports RSS.
+ Defines the maximum message size between AP and RSE. Need to define if
+ platform supports RSE.
For every image, the platform must define individual identifiers that will be
used by BL1 or BL2 to load the corresponding image into memory from non-volatile
@@ -1712,6 +1712,18 @@
corresponding to ``image_id``. This function is invoked in BL1, both in cold
boot and FWU code path, before loading the image.
+Function : bl1_plat_calc_bl2_layout() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout
+ Return : void
+
+This utility function calculates the memory layout of BL2, representing it in a
+`meminfo_t` structure. The default implementation derives this layout from the
+positioning of BL1’s RW data at the top of the memory layout.
+
Function : bl1_plat_handle_post_image_load() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -3274,6 +3286,17 @@
data on the designated crash console. It should only use general purpose
registers x0 through x5 to do its work.
+Function : plat_setup_early_console [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : void
+ Return : void
+
+This API is used to setup the early console, it is required only if the flag
+``EARLY_CONSOLE`` is enabled.
+
.. _External Abort handling and RAS Support:
External Abort handling and RAS Support
@@ -3560,7 +3583,7 @@
--------------
-*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index 33b3533..11bec7e 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -4,8 +4,8 @@
Getting Started
===============
-- Make sure you have a Github account and you are logged on both
- `developer.trustedfirmware.org`_ and `review.trustedfirmware.org`_.
+- Make sure you have a Github account and you are logged on to
+ `review.trustedfirmware.org`_.
Also make sure that you have registered your full name and email address in
your `review.trustedfirmware.org`_ profile. Otherwise, the Gerrit server
@@ -334,7 +334,6 @@
*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
-.. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
.. _review.trustedfirmware.org: https://review.trustedfirmware.org
.. _Git guidelines: http://git-scm.com/book/ch5-2.html
.. _Gerrit Uploading Changes documentation: https://review.trustedfirmware.org/Documentation/user-upload.html
diff --git a/docs/resources/diagrams/context_init_coldboot.png b/docs/resources/diagrams/context_init_coldboot.png
new file mode 100644
index 0000000..85606e4
--- /dev/null
+++ b/docs/resources/diagrams/context_init_coldboot.png
Binary files differ
diff --git a/docs/resources/diagrams/context_init_warmboot.png b/docs/resources/diagrams/context_init_warmboot.png
new file mode 100644
index 0000000..19f11e3
--- /dev/null
+++ b/docs/resources/diagrams/context_init_warmboot.png
Binary files differ
diff --git a/docs/resources/diagrams/context_memory_allocation.png b/docs/resources/diagrams/context_memory_allocation.png
new file mode 100644
index 0000000..a2e6a8e
--- /dev/null
+++ b/docs/resources/diagrams/context_memory_allocation.png
Binary files differ
diff --git a/docs/resources/diagrams/cpu_data_config_context_memory.png b/docs/resources/diagrams/cpu_data_config_context_memory.png
new file mode 100644
index 0000000..3e64ddd
--- /dev/null
+++ b/docs/resources/diagrams/cpu_data_config_context_memory.png
Binary files differ
diff --git a/docs/resources/diagrams/percpu-data-struct.png b/docs/resources/diagrams/percpu-data-struct.png
new file mode 100644
index 0000000..d8977d5
--- /dev/null
+++ b/docs/resources/diagrams/percpu-data-struct.png
Binary files differ
diff --git a/docs/resources/diagrams/plantuml/rss_attestation_flow.puml b/docs/resources/diagrams/plantuml/rse_attestation_flow.puml
similarity index 99%
rename from docs/resources/diagrams/plantuml/rss_attestation_flow.puml
rename to docs/resources/diagrams/plantuml/rse_attestation_flow.puml
index aca5c01..9d7d780 100644
--- a/docs/resources/diagrams/plantuml/rss_attestation_flow.puml
+++ b/docs/resources/diagrams/plantuml/rse_attestation_flow.puml
@@ -5,7 +5,7 @@
participant RMM
participant BL31
endbox
-box RSS
+box RSE
participant DelegAttest
participant InitAttest
participant MeasuredBoot
diff --git a/docs/resources/diagrams/plantuml/rse_measured_boot_flow.puml b/docs/resources/diagrams/plantuml/rse_measured_boot_flow.puml
new file mode 100644
index 0000000..97af562
--- /dev/null
+++ b/docs/resources/diagrams/plantuml/rse_measured_boot_flow.puml
@@ -0,0 +1,79 @@
+@startuml
+skinparam ParticipantPadding 10
+skinparam BoxPadding 10
+box RSE
+participant RSE_BL1_1
+participant RSE_BL1_2
+participant RSE_BL2
+participant RSE_S
+endbox
+box SCP
+participant SCP_BL1
+endbox
+box AP
+participant AP_BL1
+participant AP_BL2
+participant AP_BL31
+endbox
+
+== RSE Boot phase ==
+-> RSE_BL1_1: Reset
+Rnote over RSE_BL1_1: ROM code, XIP
+Rnote over RSE_BL1_2: OTP code, XIP
+Rnote over RSE_BL2, AP_BL31: Stored in flash, loaded and executed in RAM
+activate RSE_BL1_1 #Green
+RSE_BL1_1 -->> RSE_BL1_2: Validate, measure
+Rnote over RSE_BL1_1: BL1_2 measurement\n\ saved to a shared buffer
+RSE_BL1_1 -> RSE_BL1_2: Pass execution
+deactivate RSE_BL1_1
+activate RSE_BL1_2 #Green
+RSE_BL1_2 -->> RSE_BL2: Validate, measure, load
+Rnote over RSE_BL1_2: RSE_BL2 measurement\n\ saved to a shared buffer
+RSE_BL1_2 -> RSE_BL2: Pass execution
+deactivate RSE_BL1_2
+activate RSE_BL2 #Green
+RSE_BL2 -->> RSE_S: Validate, measure, load
+RSE_BL2 -->> SCP_BL1: Validate, measure, load
+Rnote over RSE_BL2: RSE_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer
+RSE_BL2 -> SCP_BL1: Release from reset
+activate SCP_BL1 #Green
+Rnote over RSE_BL2, SCP_BL1: MHU init between RSE and SCP
+Rnote over SCP_BL1: Configure memory
+Rnote over RSE_BL2: Waits for SCP
+SCP_BL1 --> RSE_BL2: Done
+RSE_BL2 -->> AP_BL1: Validate, measure, load
+Rnote over RSE_BL2: AP_BL1 measurement\n\ saved to a shared buffer
+RSE_BL2 -> AP_BL1: Release from reset
+activate AP_BL1 #Green
+RSE_BL2 -> RSE_S: Pass execution
+deactivate RSE_BL2
+activate RSE_S #Green
+Rnote over RSE_S: Measurements read from\n\ shared buffer and saved by\n\
+Measured Boot service to\n\ measurement slots.
+
+== RSE Runtime / AP Boot phase ==
+Rnote over RSE_S, AP_BL1: MHU init between RSE and AP
+Rnote over AP_BL1: Measure and load:\n\ FW_CONFIG\n\ TB_FW_CONFIG
+AP_BL1 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL1 -->> AP_BL2: Validate, measure,load
+AP_BL1 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL1 -> AP_BL2: Pass execution
+deactivate AP_BL1
+activate AP_BL2 #Green
+Rnote over AP_BL2: Measure and load:\n\ HW_CONFIG
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL2 -->> AP_BL31: Validate, measure,load
+Rnote over AP_BL2: Measure and load:\n\ BL31
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+Rnote over AP_BL2: Measure and load:\n\ RMM
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
+AP_BL2 -> AP_BL31: Pass execution
+deactivate AP_BL2
+activate AP_BL31 #Green
+== RSE / AP Runtime ==
+@enduml
diff --git a/docs/resources/diagrams/plantuml/rss_measured_boot_flow.puml b/docs/resources/diagrams/plantuml/rss_measured_boot_flow.puml
deleted file mode 100644
index 1aeb1a9..0000000
--- a/docs/resources/diagrams/plantuml/rss_measured_boot_flow.puml
+++ /dev/null
@@ -1,79 +0,0 @@
-@startuml
-skinparam ParticipantPadding 10
-skinparam BoxPadding 10
-box RSS
-participant RSS_BL1_1
-participant RSS_BL1_2
-participant RSS_BL2
-participant RSS_S
-endbox
-box SCP
-participant SCP_BL1
-endbox
-box AP
-participant AP_BL1
-participant AP_BL2
-participant AP_BL31
-endbox
-
-== RSS Boot phase ==
--> RSS_BL1_1: Reset
-Rnote over RSS_BL1_1: ROM code, XIP
-Rnote over RSS_BL1_2: OTP code, XIP
-Rnote over RSS_BL2, AP_BL31: Stored in flash, loaded and executed in RAM
-activate RSS_BL1_1 #Green
-RSS_BL1_1 -->> RSS_BL1_2: Validate, measure
-Rnote over RSS_BL1_1: BL1_2 measurement\n\ saved to a shared buffer
-RSS_BL1_1 -> RSS_BL1_2: Pass execution
-deactivate RSS_BL1_1
-activate RSS_BL1_2 #Green
-RSS_BL1_2 -->> RSS_BL2: Validate, measure, load
-Rnote over RSS_BL1_2: RSS_BL2 measurement\n\ saved to a shared buffer
-RSS_BL1_2 -> RSS_BL2: Pass execution
-deactivate RSS_BL1_2
-activate RSS_BL2 #Green
-RSS_BL2 -->> RSS_S: Validate, measure, load
-RSS_BL2 -->> SCP_BL1: Validate, measure, load
-Rnote over RSS_BL2: RSS_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer
-RSS_BL2 -> SCP_BL1: Release from reset
-activate SCP_BL1 #Green
-Rnote over RSS_BL2, SCP_BL1: MHU init between RSS and SCP
-Rnote over SCP_BL1: Configure memory
-Rnote over RSS_BL2: Waits for SCP
-SCP_BL1 --> RSS_BL2: Done
-RSS_BL2 -->> AP_BL1: Validate, measure, load
-Rnote over RSS_BL2: AP_BL1 measurement\n\ saved to a shared buffer
-RSS_BL2 -> AP_BL1: Release from reset
-activate AP_BL1 #Green
-RSS_BL2 -> RSS_S: Pass execution
-deactivate RSS_BL2
-activate RSS_S #Green
-Rnote over RSS_S: Measurements read from\n\ shared buffer and saved by\n\
-Measured Boot service to\n\ measurement slots.
-
-== RSS Runtime / AP Boot phase ==
-Rnote over RSS_S, AP_BL1: MHU init between RSS and AP
-Rnote over AP_BL1: Measure and load:\n\ FW_CONFIG\n\ TB_FW_CONFIG
-AP_BL1 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL1 -->> AP_BL2: Validate, measure,load
-AP_BL1 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL1 -> AP_BL2: Pass execution
-deactivate AP_BL1
-activate AP_BL2 #Green
-Rnote over AP_BL2: Measure and load:\n\ HW_CONFIG
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL2 -->> AP_BL31: Validate, measure,load
-Rnote over AP_BL2: Measure and load:\n\ BL31
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-Rnote over AP_BL2: Measure and load:\n\ RMM
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
-AP_BL2 -> AP_BL31: Pass execution
-deactivate AP_BL2
-activate AP_BL31 #Green
-== RSS / AP Runtime ==
-@enduml
diff --git a/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml b/docs/resources/diagrams/plantuml/tfa_rse_dfd.puml
similarity index 89%
rename from docs/resources/diagrams/plantuml/tfa_rss_dfd.puml
rename to docs/resources/diagrams/plantuml/tfa_rse_dfd.puml
index a7e0ce5..68a80bf 100644
--- a/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml
+++ b/docs/resources/diagrams/plantuml/tfa_rse_dfd.puml
@@ -5,7 +5,7 @@
'/
/'
-TF-A Data Flow Diagram including RSS
+TF-A Data Flow Diagram including RSE
'/
@startuml
@@ -54,12 +54,12 @@
bl31 [label="TF-A Runtime\n(BL31)" fillcolor="#ddffb3"]
}
- # RSS cluster
- subgraph cluster_rss{
- label ="RSS";
+ # RSE cluster
+ subgraph cluster_rse{
+ label ="RSE";
graph [style=filled color="#000000" fillcolor="#faf9cd"]
- rss [label="Runtime Security\n\ Subsystem\n\ (RSS)" fillcolor="#ddffb3"]
+ rse [label="Runtime Security\n\ Subsystem\n\ (RSE)" fillcolor="#ddffb3"]
}
}
@@ -70,7 +70,7 @@
sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"]
nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"]
bl2 -> tzc [dir="both" ltail=cluster_tfa lhead=cluster_ip label="DF6" minlen=1]
- bl31 -> rss [dir="both" ltail=cluster_tfa lhead=cluster_rss label="DF7" minlen=1]
+ bl31 -> rse [dir="both" ltail=cluster_tfa lhead=cluster_rse label="DF7" minlen=1]
}
diff --git a/docs/resources/diagrams/rss_attestation_flow.svg b/docs/resources/diagrams/rse_attestation_flow.svg
similarity index 99%
rename from docs/resources/diagrams/rss_attestation_flow.svg
rename to docs/resources/diagrams/rse_attestation_flow.svg
index 3728c6f..7257576 100644
--- a/docs/resources/diagrams/rss_attestation_flow.svg
+++ b/docs/resources/diagrams/rse_attestation_flow.svg
@@ -1,4 +1,4 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentStyleType="text/css" height="1087px" preserveAspectRatio="none" style="width:900px;height:1087px;background:#FFFFFF;" version="1.1" viewBox="0 0 900 1087" width="900px" zoomAndPan="magnify"><defs/><g><rect fill="#DDDDDD" height="1075.1719" style="stroke:#181818;stroke-width:0.5;" width="261.5" x="44" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="20" x="164.75" y="18.0669">AP</text><rect fill="#DDDDDD" height="1075.1719" style="stroke:#181818;stroke-width:0.5;" width="502" x="364" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="28" x="601" y="18.0669">RSS</text><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="82" x2="82" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="266.5" x2="266.5" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="426" x2="426" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="553.5" x2="553.5" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="705" x2="705" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="822" x2="822" y1="56.4297" y2="1046.875"/><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="48" x="58" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="34" x="65" y="45.1279">RMM</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="48" x="58" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="34" x="65" y="1065.8701">RMM</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="49" x="242.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="35" x="249.5" y="45.1279">BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="49" x="242.5" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="35" x="249.5" y="1065.8701">BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="96" x="378" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="82" x="385" y="45.1279">DelegAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="96" x="378" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="82" x="385" y="1065.8701">DelegAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="516.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="523.5" y="45.1279">InitAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="516.5" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="523.5" y="1065.8701">InitAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="116" x="647" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="102" x="654" y="45.1279">MeasuredBoot</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="116" x="647" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="102" x="654" y="1065.8701">MeasuredBoot</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="59" x="793" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="45" x="800" y="45.1279">Crypto</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="59" x="793" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="45" x="800" y="1065.8701">Crypto</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="893" x="0" y="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="893" y1="86.9961" y2="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="893" y1="89.9961" y2="89.9961"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="144" x="374.5" y="76.4297"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="125" x="380.5" y="92.4966">RMM Boot phase</text><polygon fill="#181818" points="255,141.8281,265,145.8281,255,149.8281,259,145.8281" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="82" x2="261" y1="145.8281" y2="145.8281"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="99" x="89" y="125.6294">get_realm_key(</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="74" x="121" y="140.7622">hash_algo</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="25" x="195" y="140.7622">, ...)</text><polygon fill="#181818" points="414,170.9609,424,174.9609,414,178.9609,418,174.9609" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="267" x2="420" y1="174.9609" y2="174.9609"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="274" y="169.895">get_delegated_key</text><polygon fill="#181818" points="693,200.0938,703,204.0938,693,208.0938,697,204.0938" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="699" y1="204.0938" y2="204.0938"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="127" x="433" y="199.0278">read_measurement</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="167" x="342" y="217.0938"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="95" x="346" y="233.1606">Compute input</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="110" x="346" y="248.2935">for key derivation</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="159" x="346" y="263.4263">(hash of measurements)</text><polygon fill="#181818" points="810.5,292.625,820.5,296.625,810.5,300.625,814.5,296.625" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="816.5" y1="296.625" y2="296.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="68" x="433" y="291.5591">derive_key</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="150" x="351" y="309.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="126" x="355" y="325.6919">Compute public key</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="60" x="355" y="340.8247">hash with</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="74" x="419" y="340.8247">hash_algo</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="4" x="493" y="340.8247">.</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="132" x="756" y="357.8906"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="124" x="760" y="373.9575">Seed is provisioned</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="88" x="760" y="389.0903">in the factory.</text><polygon fill="#181818" points="278,418.2891,268,422.2891,278,426.2891,274,422.2891" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="272" x2="425" y1="422.2891" y2="422.2891"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="284" y="417.2231">get_delegated_key</text><polygon fill="#181818" points="93,447.4219,83,451.4219,93,455.4219,89,451.4219" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="87" x2="266" y1="451.4219" y2="451.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="94" x="99" y="446.356">get_realm_key</text><rect fill="#FEFFDD" height="129" style="stroke:#181818;stroke-width:0.5;" width="154" x="5" y="464.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="102" x="9" y="480.4888">Only private key</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="114" x="9" y="495.6216">is returned. Public</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="9" y="510.7544">key and its hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="126" x="9" y="525.8872">must be computed.</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="134" x="9" y="541.02">Public key is included</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="9" y="556.1528">in the realm token.</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="125" x="9" y="571.2856">Its hash is the input</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="146" x="9" y="586.4185">for get_platform_token</text><polygon fill="#181818" points="255,630.75,265,634.75,255,638.75,259,634.75" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="82" x2="261" y1="634.75" y2="634.75"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="130" x="89" y="614.5513">get_platform_token(</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="121" y="629.6841">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="25" x="225" y="629.6841">, ...)</text><polygon fill="#181818" points="414,659.8828,424,663.8828,414,667.8828,418,663.8828" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="267" x2="420" y1="663.8828" y2="663.8828"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="135" x="274" y="658.8169">get_delegated_token</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="155" x="348" y="676.8828"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="39" x="352" y="692.9497">Check</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="395" y="692.9497">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="352" y="708.0825">against derived key.</text><polygon fill="#181818" points="542,737.2813,552,741.2813,542,745.2813,546,741.2813" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="548" y1="741.2813" y2="741.2813"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="433" y="736.2153">get_initial_token</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="181" x="463" y="754.2813"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="168" x="467" y="770.3481">Create the token including</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="21" x="467" y="785.481">the</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="492" y="785.481">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="40" x="600" y="785.481">as the</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="99" x="467" y="800.6138">challenge claim</text><polygon fill="#181818" points="693,829.8125,703,833.8125,693,837.8125,697,833.8125" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="554" x2="699" y1="833.8125" y2="833.8125"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="127" x="561" y="828.7466">read_measurement</text><polygon fill="#181818" points="810.5,858.9453,820.5,862.9453,810.5,866.9453,814.5,862.9453" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="554" x2="816.5" y1="862.9453" y2="862.9453"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="69" x="561" y="857.8794">sign_token</text><polygon fill="#181818" points="437,888.0781,427,892.0781,437,896.0781,433,892.0781" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="431" x2="553" y1="892.0781" y2="892.0781"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="443" y="887.0122">get_initial_token</text><polygon fill="#181818" points="278,917.2109,268,921.2109,278,925.2109,274,921.2109" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="272" x2="425" y1="921.2109" y2="921.2109"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="135" x="284" y="916.145">get_delegated_token</text><polygon fill="#181818" points="93,946.3438,83,950.3438,93,954.3438,89,950.3438" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="87" x2="266" y1="950.3438" y2="950.3438"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="125" x="99" y="945.2778">get_platform_token</text><rect fill="#FEFFDD" height="68" style="stroke:#181818;stroke-width:0.5;" width="116" x="24" y="963.3438"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="108" x="28" y="979.4106">Platform token is</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="28" y="994.5435">cached. It is not</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="98" x="28" y="1009.6763">changing within</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="90" x="28" y="1024.8091">a power cycle.</text><!--MD5=[84fabec568a656165bea957fac178b53]
+<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentStyleType="text/css" height="1087px" preserveAspectRatio="none" style="width:900px;height:1087px;background:#FFFFFF;" version="1.1" viewBox="0 0 900 1087" width="900px" zoomAndPan="magnify"><defs/><g><rect fill="#DDDDDD" height="1075.1719" style="stroke:#181818;stroke-width:0.5;" width="261.5" x="44" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="20" x="164.75" y="18.0669">AP</text><rect fill="#DDDDDD" height="1075.1719" style="stroke:#181818;stroke-width:0.5;" width="502" x="364" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="28" x="601" y="18.0669">RSE</text><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="82" x2="82" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="266.5" x2="266.5" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="426" x2="426" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="553.5" x2="553.5" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="705" x2="705" y1="56.4297" y2="1046.875"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="822" x2="822" y1="56.4297" y2="1046.875"/><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="48" x="58" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="34" x="65" y="45.1279">RMM</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="48" x="58" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="34" x="65" y="1065.8701">RMM</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="49" x="242.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="35" x="249.5" y="45.1279">BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="49" x="242.5" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="35" x="249.5" y="1065.8701">BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="96" x="378" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="82" x="385" y="45.1279">DelegAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="96" x="378" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="82" x="385" y="1065.8701">DelegAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="516.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="523.5" y="45.1279">InitAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="516.5" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="523.5" y="1065.8701">InitAttest</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="116" x="647" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="102" x="654" y="45.1279">MeasuredBoot</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="116" x="647" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="102" x="654" y="1065.8701">MeasuredBoot</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="59" x="793" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="45" x="800" y="45.1279">Crypto</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="59" x="793" y="1045.875"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="45" x="800" y="1065.8701">Crypto</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="893" x="0" y="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="893" y1="86.9961" y2="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="893" y1="89.9961" y2="89.9961"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="144" x="374.5" y="76.4297"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="125" x="380.5" y="92.4966">RMM Boot phase</text><polygon fill="#181818" points="255,141.8281,265,145.8281,255,149.8281,259,145.8281" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="82" x2="261" y1="145.8281" y2="145.8281"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="99" x="89" y="125.6294">get_realm_key(</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="74" x="121" y="140.7622">hash_algo</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="25" x="195" y="140.7622">, ...)</text><polygon fill="#181818" points="414,170.9609,424,174.9609,414,178.9609,418,174.9609" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="267" x2="420" y1="174.9609" y2="174.9609"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="274" y="169.895">get_delegated_key</text><polygon fill="#181818" points="693,200.0938,703,204.0938,693,208.0938,697,204.0938" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="699" y1="204.0938" y2="204.0938"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="127" x="433" y="199.0278">read_measurement</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="167" x="342" y="217.0938"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="95" x="346" y="233.1606">Compute input</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="110" x="346" y="248.2935">for key derivation</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="159" x="346" y="263.4263">(hash of measurements)</text><polygon fill="#181818" points="810.5,292.625,820.5,296.625,810.5,300.625,814.5,296.625" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="816.5" y1="296.625" y2="296.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="68" x="433" y="291.5591">derive_key</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="150" x="351" y="309.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="126" x="355" y="325.6919">Compute public key</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="60" x="355" y="340.8247">hash with</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="74" x="419" y="340.8247">hash_algo</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="4" x="493" y="340.8247">.</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="132" x="756" y="357.8906"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="124" x="760" y="373.9575">Seed is provisioned</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="88" x="760" y="389.0903">in the factory.</text><polygon fill="#181818" points="278,418.2891,268,422.2891,278,426.2891,274,422.2891" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="272" x2="425" y1="422.2891" y2="422.2891"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="284" y="417.2231">get_delegated_key</text><polygon fill="#181818" points="93,447.4219,83,451.4219,93,455.4219,89,451.4219" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="87" x2="266" y1="451.4219" y2="451.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="94" x="99" y="446.356">get_realm_key</text><rect fill="#FEFFDD" height="129" style="stroke:#181818;stroke-width:0.5;" width="154" x="5" y="464.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="102" x="9" y="480.4888">Only private key</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="114" x="9" y="495.6216">is returned. Public</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="9" y="510.7544">key and its hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="126" x="9" y="525.8872">must be computed.</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="134" x="9" y="541.02">Public key is included</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="9" y="556.1528">in the realm token.</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="125" x="9" y="571.2856">Its hash is the input</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="146" x="9" y="586.4185">for get_platform_token</text><polygon fill="#181818" points="255,630.75,265,634.75,255,638.75,259,634.75" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="82" x2="261" y1="634.75" y2="634.75"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="130" x="89" y="614.5513">get_platform_token(</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="121" y="629.6841">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="25" x="225" y="629.6841">, ...)</text><polygon fill="#181818" points="414,659.8828,424,663.8828,414,667.8828,418,663.8828" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="267" x2="420" y1="663.8828" y2="663.8828"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="135" x="274" y="658.8169">get_delegated_token</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="155" x="348" y="676.8828"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="39" x="352" y="692.9497">Check</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="395" y="692.9497">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="352" y="708.0825">against derived key.</text><polygon fill="#181818" points="542,737.2813,552,741.2813,542,745.2813,546,741.2813" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="426" x2="548" y1="741.2813" y2="741.2813"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="433" y="736.2153">get_initial_token</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="181" x="463" y="754.2813"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="168" x="467" y="770.3481">Create the token including</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="21" x="467" y="785.481">the</text><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="104" x="492" y="785.481">pub_key_hash</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="40" x="600" y="785.481">as the</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="99" x="467" y="800.6138">challenge claim</text><polygon fill="#181818" points="693,829.8125,703,833.8125,693,837.8125,697,833.8125" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="554" x2="699" y1="833.8125" y2="833.8125"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="127" x="561" y="828.7466">read_measurement</text><polygon fill="#181818" points="810.5,858.9453,820.5,862.9453,810.5,866.9453,814.5,862.9453" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="554" x2="816.5" y1="862.9453" y2="862.9453"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="69" x="561" y="857.8794">sign_token</text><polygon fill="#181818" points="437,888.0781,427,892.0781,437,896.0781,433,892.0781" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="431" x2="553" y1="892.0781" y2="892.0781"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="104" x="443" y="887.0122">get_initial_token</text><polygon fill="#181818" points="278,917.2109,268,921.2109,278,925.2109,274,921.2109" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="272" x2="425" y1="921.2109" y2="921.2109"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="135" x="284" y="916.145">get_delegated_token</text><polygon fill="#181818" points="93,946.3438,83,950.3438,93,954.3438,89,950.3438" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="87" x2="266" y1="950.3438" y2="950.3438"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="125" x="99" y="945.2778">get_platform_token</text><rect fill="#FEFFDD" height="68" style="stroke:#181818;stroke-width:0.5;" width="116" x="24" y="963.3438"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="108" x="28" y="979.4106">Platform token is</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="28" y="994.5435">cached. It is not</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="98" x="28" y="1009.6763">changing within</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="90" x="28" y="1024.8091">a power cycle.</text><!--MD5=[84fabec568a656165bea957fac178b53]
@startuml
skinparam ParticipantPadding 10
skinparam BoxPadding 10
@@ -6,7 +6,7 @@
participant RMM
participant BL31
endbox
-box RSS
+box RSE
participant DelegAttest
participant InitAttest
participant MeasuredBoot
diff --git a/docs/resources/diagrams/rss_measured_boot_flow.svg b/docs/resources/diagrams/rse_measured_boot_flow.svg
similarity index 90%
rename from docs/resources/diagrams/rss_measured_boot_flow.svg
rename to docs/resources/diagrams/rse_measured_boot_flow.svg
index f5bf311..0ccfbc2 100644
--- a/docs/resources/diagrams/rss_measured_boot_flow.svg
+++ b/docs/resources/diagrams/rse_measured_boot_flow.svg
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentStyleType="text/css" height="1826px" preserveAspectRatio="none" style="width:1254px;height:1826px;background:#FFFFFF;" version="1.1" viewBox="0 0 1254 1826" width="1254px" zoomAndPan="magnify"><defs/><g><rect fill="#DDDDDD" height="1814.0938" style="stroke:#181818;stroke-width:0.5;" width="610.5" x="27" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="28" x="318.25" y="18.0669">RSS</text><rect fill="#DDDDDD" height="1814.0938" style="stroke:#181818;stroke-width:0.5;" width="103" x="659.5" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="29" x="696.5" y="18.0669">SCP</text><rect fill="#DDDDDD" height="1814.0938" style="stroke:#181818;stroke-width:0.5;" width="451.5" x="784.5" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="20" x="1000.25" y="18.0669">AP</text><rect fill="#008000" height="205.9297" style="stroke:#181818;stroke-width:1.0;" width="10" x="81.5" y="130.6953"/><rect fill="#008000" height="106.5313" style="stroke:#181818;stroke-width:1.0;" width="10" x="227.5" y="336.625"/><rect fill="#008000" height="414.9922" style="stroke:#181818;stroke-width:1.0;" width="10" x="408.5" y="443.1563"/><rect fill="#008000" height="918.6484" style="stroke:#181818;stroke-width:1.0;" width="10" x="589.5" y="858.1484"/><rect fill="#008000" height="1182.8438" style="stroke:#181818;stroke-width:1.0;" width="10" x="706" y="593.9531"/><rect fill="#008000" height="460.3906" style="stroke:#181818;stroke-width:1.0;" width="10" x="826" y="829.0156"/><rect fill="#008000" height="435.2578" style="stroke:#181818;stroke-width:1.0;" width="10" x="1003" y="1289.4063"/><rect fill="#008000" height="52.1328" style="stroke:#181818;stroke-width:1.0;" width="10" x="1180" y="1724.6641"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="86" x2="86" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="232" x2="232" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="413" x2="413" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="594.5" x2="594.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="710.5" x2="710.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="830.5" x2="830.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="1007.5" x2="1007.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="1185" x2="1185" y1="56.4297" y2="1785.7969"/><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="41" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="48" y="45.1279">RSS_BL1_1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="41" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="48" y="1804.792">RSS_BL1_1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="187" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="194" y="45.1279">RSS_BL1_2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="187" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="194" y="1804.792">RSS_BL1_2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="376" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="383" y="45.1279">RSS_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="376" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="383" y="1804.792">RSS_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="58" x="565.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="44" x="572.5" y="45.1279">RSS_S</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="58" x="565.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="44" x="572.5" y="1804.792">RSS_S</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="673.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="680.5" y="45.1279">SCP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="673.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="680.5" y="1804.792">SCP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="798.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="805.5" y="45.1279">AP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="798.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="805.5" y="1804.792">AP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="975.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="982.5" y="45.1279">AP_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="975.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="982.5" y="1804.792">AP_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="74" x="1148" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="60" x="1155" y="45.1279">AP_BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="74" x="1148" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="60" x="1155" y="1804.792">AP_BL31</text><rect fill="#008000" height="205.9297" style="stroke:#181818;stroke-width:1.0;" width="10" x="81.5" y="130.6953"/><rect fill="#008000" height="106.5313" style="stroke:#181818;stroke-width:1.0;" width="10" x="227.5" y="336.625"/><rect fill="#008000" height="414.9922" style="stroke:#181818;stroke-width:1.0;" width="10" x="408.5" y="443.1563"/><rect fill="#008000" height="918.6484" style="stroke:#181818;stroke-width:1.0;" width="10" x="589.5" y="858.1484"/><rect fill="#008000" height="1182.8438" style="stroke:#181818;stroke-width:1.0;" width="10" x="706" y="593.9531"/><rect fill="#008000" height="460.3906" style="stroke:#181818;stroke-width:1.0;" width="10" x="826" y="829.0156"/><rect fill="#008000" height="435.2578" style="stroke:#181818;stroke-width:1.0;" width="10" x="1003" y="1289.4063"/><rect fill="#008000" height="52.1328" style="stroke:#181818;stroke-width:1.0;" width="10" x="1180" y="1724.6641"/><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="1247" x="0" y="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="86.9961" y2="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="89.9961" y2="89.9961"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="136" x="555.5" y="76.4297"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="117" x="561.5" y="92.4966">RSS Boot phase</text><polygon fill="#181818" points="69.5,126.6953,79.5,130.6953,69.5,134.6953,73.5,130.6953" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="0" x2="75.5" y1="130.6953" y2="130.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="36" x="7" y="125.6294">Reset</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="99" x="37" y="143.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="91" x="41" y="159.7622">ROM code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="95" x="185" y="176.8281"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="87" x="189" y="192.895">OTP code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="861" x="368" y="209.9609"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="281" x="658" y="226.0278">Stored in flash, loaded and executed in RAM</text><line style="stroke:#181818;stroke-width:1.0;" x1="230.5" x2="220.5" y1="259.2266" y2="255.2266"/><line style="stroke:#181818;stroke-width:1.0;" x1="230.5" x2="220.5" y1="259.2266" y2="263.2266"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="91.5" x2="231.5" y1="259.2266" y2="259.2266"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="117" x="98.5" y="254.1606">Validate, measure</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="164" x="5" y="272.2266"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="134" x="9" y="288.2935">BL1_2 measurement</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="156" x="9" y="303.4263">saved to a shared buffer</text><polygon fill="#181818" points="215.5,332.625,225.5,336.625,215.5,340.625,219.5,336.625" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="86.5" x2="221.5" y1="336.625" y2="336.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="93.5" y="331.5591">Pass execution</text><line style="stroke:#181818;stroke-width:1.0;" x1="411.5" x2="401.5" y1="365.7578" y2="361.7578"/><line style="stroke:#181818;stroke-width:1.0;" x1="411.5" x2="401.5" y1="365.7578" y2="369.7578"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="237.5" x2="412.5" y1="365.7578" y2="365.7578"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="244.5" y="360.6919">Validate, measure, load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="164" x="150" y="378.7578"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="154" y="394.8247">RSS_BL2 measurement</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="156" x="154" y="409.9575">saved to a shared buffer</text><polygon fill="#181818" points="396.5,439.1563,406.5,443.1563,396.5,447.1563,400.5,443.1563" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="232.5" x2="402.5" y1="443.1563" y2="443.1563"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="239.5" y="438.0903">Pass execution</text><line style="stroke:#181818;stroke-width:1.0;" x1="592.5" x2="582.5" y1="472.2891" y2="468.2891"/><line style="stroke:#181818;stroke-width:1.0;" x1="592.5" x2="582.5" y1="472.2891" y2="476.2891"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="593.5" y1="472.2891" y2="472.2891"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="467.2231">Validate, measure, load</text><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="497.4219"/><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="505.4219"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="710" y1="501.4219" y2="501.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="496.356">Validate, measure, load</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="148" x="339" y="514.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="131" x="343" y="530.4888">RSS_S and SCP_BL1</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="140" x="343" y="545.6216">measurements saved</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="114" x="343" y="560.7544">to a shared buffer</text><polygon fill="#181818" points="694,589.9531,704,593.9531,694,597.9531,698,593.9531" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="418.5" x2="700" y1="593.9531" y2="593.9531"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="425.5" y="588.8872">Release from reset</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="387" x="368" y="606.9531"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="200" x="461.75" y="623.02">MHU init between RSS and SCP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="127" x="647" y="640.0859"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="119" x="651" y="656.1528">Configure memory</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="93" x="367" y="673.2188"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="85" x="371" y="689.2856">Waits for SCP</text><polygon fill="#181818" points="429.5,718.4844,419.5,722.4844,429.5,726.4844,425.5,722.4844" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="423.5" x2="705" y1="722.4844" y2="722.4844"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="34" x="435.5" y="717.4185">Done</text><line style="stroke:#181818;stroke-width:1.0;" x1="829" x2="819" y1="751.6172" y2="747.6172"/><line style="stroke:#181818;stroke-width:1.0;" x1="829" x2="819" y1="751.6172" y2="755.6172"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="830" y1="751.6172" y2="751.6172"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="746.5513">Validate, measure, load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="164" x="331" y="764.6172"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="143" x="335" y="780.6841">AP_BL1 measurement</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="156" x="335" y="795.8169">saved to a shared buffer</text><polygon fill="#181818" points="814,825.0156,824,829.0156,814,833.0156,818,829.0156" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="418.5" x2="820" y1="829.0156" y2="829.0156"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="425.5" y="823.9497">Release from reset</text><polygon fill="#181818" points="577.5,854.1484,587.5,858.1484,577.5,862.1484,581.5,858.1484" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="413.5" x2="583.5" y1="858.1484" y2="858.1484"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="420.5" y="853.0825">Pass execution</text><rect fill="#FEFFDD" height="68" style="stroke:#181818;stroke-width:0.5;" width="182" x="503" y="871.1484"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="163" x="507" y="887.2153">Measurements read from</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="174" x="507" y="902.3481">shared buffer and saved by</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="163" x="507" y="917.481">Measured Boot service to</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="129" x="507" y="932.6138">measurement slots.</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="1247" x="0" y="965.2461"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="965.2461" y2="965.2461"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="968.2461" y2="968.2461"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="237" x="505" y="954.6797"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="218" x="511" y="970.7466">RSS Runtime / AP Boot phase</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="313" x="556" y="992.8125"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="191" x="617" y="1008.8794">MHU init between RSS and AP</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="126" x="768" y="1025.9453"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="772" y="1042.0122">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="74" x="772" y="1057.145">FW_CONFIG</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="97" x="772" y="1072.2778">TB_FW_CONFIG</text><polygon fill="#181818" points="610.5,1101.4766,600.5,1105.4766,610.5,1109.4766,606.5,1105.4766" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="825" y1="1105.4766" y2="1105.4766"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1100.4106">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1118.4766"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1134.5435">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1149.6763">store measurement</text><line style="stroke:#181818;stroke-width:1.0;" x1="1006" x2="996" y1="1182.875" y2="1178.875"/><line style="stroke:#181818;stroke-width:1.0;" x1="1006" x2="996" y1="1182.875" y2="1186.875"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="836" x2="1007" y1="1182.875" y2="1182.875"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="148" x="843" y="1177.8091">Validate, measure,load</text><polygon fill="#181818" points="610.5,1208.0078,600.5,1212.0078,610.5,1216.0078,606.5,1212.0078" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="825" y1="1212.0078" y2="1212.0078"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1206.9419">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1225.0078"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1241.0747">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1256.2075">store measurement</text><polygon fill="#181818" points="991,1285.4063,1001,1289.4063,991,1293.4063,995,1289.4063" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="831" x2="997" y1="1289.4063" y2="1289.4063"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="838" y="1284.3403">Pass execution</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1302.4063"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1318.4731">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="77" x="949" y="1333.606">HW_CONFIG</text><polygon fill="#181818" points="610.5,1362.8047,600.5,1366.8047,610.5,1370.8047,606.5,1366.8047" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1366.8047" y2="1366.8047"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1361.7388">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1379.8047"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1395.8716">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1411.0044">store measurement</text><line style="stroke:#181818;stroke-width:1.0;" x1="1183" x2="1173" y1="1444.2031" y2="1440.2031"/><line style="stroke:#181818;stroke-width:1.0;" x1="1183" x2="1173" y1="1444.2031" y2="1448.2031"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="1013" x2="1184" y1="1444.2031" y2="1444.2031"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="148" x="1020" y="1439.1372">Validate, measure,load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1457.2031"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1473.27">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="32" x="949" y="1488.4028">BL31</text><polygon fill="#181818" points="610.5,1517.6016,600.5,1521.6016,610.5,1525.6016,606.5,1521.6016" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1521.6016" y2="1521.6016"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1516.5356">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1534.6016"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1550.6685">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1565.8013">store measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1582.8672"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1598.9341">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="30" x="949" y="1614.0669">RMM</text><polygon fill="#181818" points="610.5,1643.2656,600.5,1647.2656,610.5,1651.2656,606.5,1647.2656" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1647.2656" y2="1647.2656"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1642.1997">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1660.2656"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1676.3325">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1691.4653">store measurement</text><polygon fill="#181818" points="1168,1720.6641,1178,1724.6641,1168,1728.6641,1172,1724.6641" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="1008" x2="1174" y1="1724.6641" y2="1724.6641"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="1015" y="1719.5981">Pass execution</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="1247" x="0" y="1753.2305"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="1753.2305" y2="1753.2305"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="1756.2305" y2="1756.2305"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="148" x="549.5" y="1742.6641"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="129" x="555.5" y="1758.731">RSS / AP Runtime</text><!--MD5=[e3f0ee259d2a4aa9c2a97ff856de0312]
+<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentStyleType="text/css" height="1826px" preserveAspectRatio="none" style="width:1254px;height:1826px;background:#FFFFFF;" version="1.1" viewBox="0 0 1254 1826" width="1254px" zoomAndPan="magnify"><defs/><g><rect fill="#DDDDDD" height="1814.0938" style="stroke:#181818;stroke-width:0.5;" width="610.5" x="27" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="28" x="318.25" y="18.0669">RSE</text><rect fill="#DDDDDD" height="1814.0938" style="stroke:#181818;stroke-width:0.5;" width="103" x="659.5" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="29" x="696.5" y="18.0669">SCP</text><rect fill="#DDDDDD" height="1814.0938" style="stroke:#181818;stroke-width:0.5;" width="451.5" x="784.5" y="6"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="20" x="1000.25" y="18.0669">AP</text><rect fill="#008000" height="205.9297" style="stroke:#181818;stroke-width:1.0;" width="10" x="81.5" y="130.6953"/><rect fill="#008000" height="106.5313" style="stroke:#181818;stroke-width:1.0;" width="10" x="227.5" y="336.625"/><rect fill="#008000" height="414.9922" style="stroke:#181818;stroke-width:1.0;" width="10" x="408.5" y="443.1563"/><rect fill="#008000" height="918.6484" style="stroke:#181818;stroke-width:1.0;" width="10" x="589.5" y="858.1484"/><rect fill="#008000" height="1182.8438" style="stroke:#181818;stroke-width:1.0;" width="10" x="706" y="593.9531"/><rect fill="#008000" height="460.3906" style="stroke:#181818;stroke-width:1.0;" width="10" x="826" y="829.0156"/><rect fill="#008000" height="435.2578" style="stroke:#181818;stroke-width:1.0;" width="10" x="1003" y="1289.4063"/><rect fill="#008000" height="52.1328" style="stroke:#181818;stroke-width:1.0;" width="10" x="1180" y="1724.6641"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="86" x2="86" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="232" x2="232" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="413" x2="413" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="594.5" x2="594.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="710.5" x2="710.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="830.5" x2="830.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="1007.5" x2="1007.5" y1="56.4297" y2="1785.7969"/><line style="stroke:#181818;stroke-width:0.5;stroke-dasharray:5.0,5.0;" x1="1185" x2="1185" y1="56.4297" y2="1785.7969"/><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="41" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="48" y="45.1279">RSE_BL1_1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="41" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="48" y="1804.792">RSE_BL1_1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="187" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="194" y="45.1279">RSE_BL1_2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="91" x="187" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="77" x="194" y="1804.792">RSE_BL1_2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="376" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="383" y="45.1279">RSE_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="376" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="383" y="1804.792">RSE_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="58" x="565.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="44" x="572.5" y="45.1279">RSE_S</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="58" x="565.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="44" x="572.5" y="1804.792">RSE_S</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="673.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="680.5" y="45.1279">SCP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="75" x="673.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="61" x="680.5" y="1804.792">SCP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="798.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="805.5" y="45.1279">AP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="798.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="805.5" y="1804.792">AP_BL1</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="975.5" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="982.5" y="45.1279">AP_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="65" x="975.5" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="51" x="982.5" y="1804.792">AP_BL2</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="74" x="1148" y="25.1328"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="60" x="1155" y="45.1279">AP_BL31</text><rect fill="#E2E2F0" height="30.2969" rx="2.5" ry="2.5" style="stroke:#181818;stroke-width:0.5;" width="74" x="1148" y="1784.7969"/><text fill="#000000" font-family="sans-serif" font-size="14" lengthAdjust="spacing" textLength="60" x="1155" y="1804.792">AP_BL31</text><rect fill="#008000" height="205.9297" style="stroke:#181818;stroke-width:1.0;" width="10" x="81.5" y="130.6953"/><rect fill="#008000" height="106.5313" style="stroke:#181818;stroke-width:1.0;" width="10" x="227.5" y="336.625"/><rect fill="#008000" height="414.9922" style="stroke:#181818;stroke-width:1.0;" width="10" x="408.5" y="443.1563"/><rect fill="#008000" height="918.6484" style="stroke:#181818;stroke-width:1.0;" width="10" x="589.5" y="858.1484"/><rect fill="#008000" height="1182.8438" style="stroke:#181818;stroke-width:1.0;" width="10" x="706" y="593.9531"/><rect fill="#008000" height="460.3906" style="stroke:#181818;stroke-width:1.0;" width="10" x="826" y="829.0156"/><rect fill="#008000" height="435.2578" style="stroke:#181818;stroke-width:1.0;" width="10" x="1003" y="1289.4063"/><rect fill="#008000" height="52.1328" style="stroke:#181818;stroke-width:1.0;" width="10" x="1180" y="1724.6641"/><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="1247" x="0" y="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="86.9961" y2="86.9961"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="89.9961" y2="89.9961"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="136" x="555.5" y="76.4297"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="117" x="561.5" y="92.4966">RSE Boot phase</text><polygon fill="#181818" points="69.5,126.6953,79.5,130.6953,69.5,134.6953,73.5,130.6953" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="0" x2="75.5" y1="130.6953" y2="130.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="36" x="7" y="125.6294">Reset</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="99" x="37" y="143.6953"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="91" x="41" y="159.7622">ROM code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="95" x="185" y="176.8281"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="87" x="189" y="192.895">OTP code, XIP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="861" x="368" y="209.9609"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="281" x="658" y="226.0278">Stored in flash, loaded and executed in RAM</text><line style="stroke:#181818;stroke-width:1.0;" x1="230.5" x2="220.5" y1="259.2266" y2="255.2266"/><line style="stroke:#181818;stroke-width:1.0;" x1="230.5" x2="220.5" y1="259.2266" y2="263.2266"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="91.5" x2="231.5" y1="259.2266" y2="259.2266"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="117" x="98.5" y="254.1606">Validate, measure</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="164" x="5" y="272.2266"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="134" x="9" y="288.2935">BL1_2 measurement</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="156" x="9" y="303.4263">saved to a shared buffer</text><polygon fill="#181818" points="215.5,332.625,225.5,336.625,215.5,340.625,219.5,336.625" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="86.5" x2="221.5" y1="336.625" y2="336.625"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="93.5" y="331.5591">Pass execution</text><line style="stroke:#181818;stroke-width:1.0;" x1="411.5" x2="401.5" y1="365.7578" y2="361.7578"/><line style="stroke:#181818;stroke-width:1.0;" x1="411.5" x2="401.5" y1="365.7578" y2="369.7578"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="237.5" x2="412.5" y1="365.7578" y2="365.7578"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="244.5" y="360.6919">Validate, measure, load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="164" x="150" y="378.7578"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="154" y="394.8247">RSE_BL2 measurement</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="156" x="154" y="409.9575">saved to a shared buffer</text><polygon fill="#181818" points="396.5,439.1563,406.5,443.1563,396.5,447.1563,400.5,443.1563" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="232.5" x2="402.5" y1="443.1563" y2="443.1563"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="239.5" y="438.0903">Pass execution</text><line style="stroke:#181818;stroke-width:1.0;" x1="592.5" x2="582.5" y1="472.2891" y2="468.2891"/><line style="stroke:#181818;stroke-width:1.0;" x1="592.5" x2="582.5" y1="472.2891" y2="476.2891"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="593.5" y1="472.2891" y2="472.2891"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="467.2231">Validate, measure, load</text><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="497.4219"/><line style="stroke:#181818;stroke-width:1.0;" x1="709" x2="699" y1="501.4219" y2="505.4219"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="710" y1="501.4219" y2="501.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="496.356">Validate, measure, load</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="148" x="339" y="514.4219"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="131" x="343" y="530.4888">RSE_S and SCP_BL1</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="140" x="343" y="545.6216">measurements saved</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="114" x="343" y="560.7544">to a shared buffer</text><polygon fill="#181818" points="694,589.9531,704,593.9531,694,597.9531,698,593.9531" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="418.5" x2="700" y1="593.9531" y2="593.9531"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="425.5" y="588.8872">Release from reset</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="387" x="368" y="606.9531"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="200" x="461.75" y="623.02">MHU init between RSE and SCP</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="127" x="647" y="640.0859"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="119" x="651" y="656.1528">Configure memory</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="93" x="367" y="673.2188"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="85" x="371" y="689.2856">Waits for SCP</text><polygon fill="#181818" points="429.5,718.4844,419.5,722.4844,429.5,726.4844,425.5,722.4844" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="423.5" x2="705" y1="722.4844" y2="722.4844"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="34" x="435.5" y="717.4185">Done</text><line style="stroke:#181818;stroke-width:1.0;" x1="829" x2="819" y1="751.6172" y2="747.6172"/><line style="stroke:#181818;stroke-width:1.0;" x1="829" x2="819" y1="751.6172" y2="755.6172"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="418.5" x2="830" y1="751.6172" y2="751.6172"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="152" x="425.5" y="746.5513">Validate, measure, load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="164" x="331" y="764.6172"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="143" x="335" y="780.6841">AP_BL1 measurement</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="156" x="335" y="795.8169">saved to a shared buffer</text><polygon fill="#181818" points="814,825.0156,824,829.0156,814,833.0156,818,829.0156" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="418.5" x2="820" y1="829.0156" y2="829.0156"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="121" x="425.5" y="823.9497">Release from reset</text><polygon fill="#181818" points="577.5,854.1484,587.5,858.1484,577.5,862.1484,581.5,858.1484" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="413.5" x2="583.5" y1="858.1484" y2="858.1484"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="420.5" y="853.0825">Pass execution</text><rect fill="#FEFFDD" height="68" style="stroke:#181818;stroke-width:0.5;" width="182" x="503" y="871.1484"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="163" x="507" y="887.2153">Measurements read from</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="174" x="507" y="902.3481">shared buffer and saved by</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="163" x="507" y="917.481">Measured Boot service to</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="129" x="507" y="932.6138">measurement slots.</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="1247" x="0" y="965.2461"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="965.2461" y2="965.2461"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="968.2461" y2="968.2461"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="237" x="505" y="954.6797"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="218" x="511" y="970.7466">RSE Runtime / AP Boot phase</text><rect fill="#FEFFDD" height="23" style="stroke:#181818;stroke-width:0.5;" width="313" x="556" y="992.8125"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="191" x="617" y="1008.8794">MHU init between RSE and AP</text><rect fill="#FEFFDD" height="53" style="stroke:#181818;stroke-width:0.5;" width="126" x="768" y="1025.9453"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="772" y="1042.0122">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="74" x="772" y="1057.145">FW_CONFIG</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="97" x="772" y="1072.2778">TB_FW_CONFIG</text><polygon fill="#181818" points="610.5,1101.4766,600.5,1105.4766,610.5,1109.4766,606.5,1105.4766" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="825" y1="1105.4766" y2="1105.4766"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1100.4106">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1118.4766"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1134.5435">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1149.6763">store measurement</text><line style="stroke:#181818;stroke-width:1.0;" x1="1006" x2="996" y1="1182.875" y2="1178.875"/><line style="stroke:#181818;stroke-width:1.0;" x1="1006" x2="996" y1="1182.875" y2="1186.875"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="836" x2="1007" y1="1182.875" y2="1182.875"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="148" x="843" y="1177.8091">Validate, measure,load</text><polygon fill="#181818" points="610.5,1208.0078,600.5,1212.0078,610.5,1216.0078,606.5,1212.0078" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="825" y1="1212.0078" y2="1212.0078"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1206.9419">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1225.0078"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1241.0747">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1256.2075">store measurement</text><polygon fill="#181818" points="991,1285.4063,1001,1289.4063,991,1293.4063,995,1289.4063" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="831" x2="997" y1="1289.4063" y2="1289.4063"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="838" y="1284.3403">Pass execution</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1302.4063"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1318.4731">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="77" x="949" y="1333.606">HW_CONFIG</text><polygon fill="#181818" points="610.5,1362.8047,600.5,1366.8047,610.5,1370.8047,606.5,1366.8047" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1366.8047" y2="1366.8047"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1361.7388">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1379.8047"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1395.8716">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1411.0044">store measurement</text><line style="stroke:#181818;stroke-width:1.0;" x1="1183" x2="1173" y1="1444.2031" y2="1440.2031"/><line style="stroke:#181818;stroke-width:1.0;" x1="1183" x2="1173" y1="1444.2031" y2="1448.2031"/><line style="stroke:#181818;stroke-width:1.0;stroke-dasharray:2.0,2.0;" x1="1013" x2="1184" y1="1444.2031" y2="1444.2031"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="148" x="1020" y="1439.1372">Validate, measure,load</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1457.2031"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1473.27">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="32" x="949" y="1488.4028">BL31</text><polygon fill="#181818" points="610.5,1517.6016,600.5,1521.6016,610.5,1525.6016,606.5,1521.6016" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1521.6016" y2="1521.6016"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1516.5356">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1534.6016"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1550.6685">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1565.8013">store measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="126" x="945" y="1582.8672"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="118" x="949" y="1598.9341">Measure and load:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="30" x="949" y="1614.0669">RMM</text><polygon fill="#181818" points="610.5,1643.2656,600.5,1647.2656,610.5,1651.2656,606.5,1647.2656" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="604.5" x2="1002" y1="1647.2656" y2="1647.2656"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="139" x="616.5" y="1642.1997">Extend measurement</text><rect fill="#FEFFDD" height="38" style="stroke:#181818;stroke-width:0.5;" width="136" x="526" y="1660.2656"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="101" x="530" y="1676.3325">Measured Boot:</text><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="128" x="530" y="1691.4653">store measurement</text><polygon fill="#181818" points="1168,1720.6641,1178,1724.6641,1168,1728.6641,1172,1724.6641" style="stroke:#181818;stroke-width:1.0;"/><line style="stroke:#181818;stroke-width:1.0;" x1="1008" x2="1174" y1="1724.6641" y2="1724.6641"/><text fill="#000000" font-family="sans-serif" font-size="13" lengthAdjust="spacing" textLength="96" x="1015" y="1719.5981">Pass execution</text><rect fill="#EEEEEE" height="3" style="stroke:#EEEEEE;stroke-width:1.0;" width="1247" x="0" y="1753.2305"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="1753.2305" y2="1753.2305"/><line style="stroke:#000000;stroke-width:1.0;" x1="0" x2="1247" y1="1756.2305" y2="1756.2305"/><rect fill="#EEEEEE" height="23.1328" style="stroke:#000000;stroke-width:2.0;" width="148" x="549.5" y="1742.6641"/><text fill="#000000" font-family="sans-serif" font-size="13" font-weight="bold" lengthAdjust="spacing" textLength="129" x="555.5" y="1758.731">RSE / AP Runtime</text><!--MD5=[e3f0ee259d2a4aa9c2a97ff856de0312]
@startuml
skinparam ParticipantPadding 10
skinparam BoxPadding 10
-box RSS
-participant RSS_BL1_1
-participant RSS_BL1_2
-participant RSS_BL2
-participant RSS_S
+box RSE
+participant RSE_BL1_1
+participant RSE_BL1_2
+participant RSE_BL2
+participant RSE_S
endbox
box SCP
participant SCP_BL1
@@ -17,65 +17,65 @@
participant AP_BL31
endbox
-== RSS Boot phase ==
--> RSS_BL1_1: Reset
-Rnote over RSS_BL1_1: ROM code, XIP
-Rnote over RSS_BL1_2: OTP code, XIP
-Rnote over RSS_BL2, AP_BL31: Stored in flash, loaded and executed in RAM
-activate RSS_BL1_1 #Green
-RSS_BL1_1 - ->> RSS_BL1_2: Validate, measure
-Rnote over RSS_BL1_1: BL1_2 measurement\n\ saved to a shared buffer
-RSS_BL1_1 -> RSS_BL1_2: Pass execution
-deactivate RSS_BL1_1
-activate RSS_BL1_2 #Green
-RSS_BL1_2 - ->> RSS_BL2: Validate, measure, load
-Rnote over RSS_BL1_2: RSS_BL2 measurement\n\ saved to a shared buffer
-RSS_BL1_2 -> RSS_BL2: Pass execution
-deactivate RSS_BL1_2
-activate RSS_BL2 #Green
-RSS_BL2 - ->> RSS_S: Validate, measure, load
-RSS_BL2 - ->> SCP_BL1: Validate, measure, load
-Rnote over RSS_BL2: RSS_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer
-RSS_BL2 -> SCP_BL1: Release from reset
+== RSE Boot phase ==
+-> RSE_BL1_1: Reset
+Rnote over RSE_BL1_1: ROM code, XIP
+Rnote over RSE_BL1_2: OTP code, XIP
+Rnote over RSE_BL2, AP_BL31: Stored in flash, loaded and executed in RAM
+activate RSE_BL1_1 #Green
+RSE_BL1_1 - ->> RSE_BL1_2: Validate, measure
+Rnote over RSE_BL1_1: BL1_2 measurement\n\ saved to a shared buffer
+RSE_BL1_1 -> RSE_BL1_2: Pass execution
+deactivate RSE_BL1_1
+activate RSE_BL1_2 #Green
+RSE_BL1_2 - ->> RSE_BL2: Validate, measure, load
+Rnote over RSE_BL1_2: RSE_BL2 measurement\n\ saved to a shared buffer
+RSE_BL1_2 -> RSE_BL2: Pass execution
+deactivate RSE_BL1_2
+activate RSE_BL2 #Green
+RSE_BL2 - ->> RSE_S: Validate, measure, load
+RSE_BL2 - ->> SCP_BL1: Validate, measure, load
+Rnote over RSE_BL2: RSE_S and SCP_BL1\n\ measurements saved\n\ to a shared buffer
+RSE_BL2 -> SCP_BL1: Release from reset
activate SCP_BL1 #Green
-Rnote over RSS_BL2, SCP_BL1: MHU init between RSS and SCP
+Rnote over RSE_BL2, SCP_BL1: MHU init between RSE and SCP
Rnote over SCP_BL1: Configure memory
-Rnote over RSS_BL2: Waits for SCP
-SCP_BL1 - -> RSS_BL2: Done
-RSS_BL2 - ->> AP_BL1: Validate, measure, load
-Rnote over RSS_BL2: AP_BL1 measurement\n\ saved to a shared buffer
-RSS_BL2 -> AP_BL1: Release from reset
+Rnote over RSE_BL2: Waits for SCP
+SCP_BL1 - -> RSE_BL2: Done
+RSE_BL2 - ->> AP_BL1: Validate, measure, load
+Rnote over RSE_BL2: AP_BL1 measurement\n\ saved to a shared buffer
+RSE_BL2 -> AP_BL1: Release from reset
activate AP_BL1 #Green
-RSS_BL2 -> RSS_S: Pass execution
-deactivate RSS_BL2
-activate RSS_S #Green
-Rnote over RSS_S: Measurements read from\n\ shared buffer and saved by\nMeasured Boot service to\n\ measurement slots.
+RSE_BL2 -> RSE_S: Pass execution
+deactivate RSE_BL2
+activate RSE_S #Green
+Rnote over RSE_S: Measurements read from\n\ shared buffer and saved by\nMeasured Boot service to\n\ measurement slots.
-== RSS Runtime / AP Boot phase ==
-Rnote over RSS_S, AP_BL1: MHU init between RSS and AP
+== RSE Runtime / AP Boot phase ==
+Rnote over RSE_S, AP_BL1: MHU init between RSE and AP
Rnote over AP_BL1: Measure and load:\n\ FW_CONFIG\n\ TB_FW_CONFIG
-AP_BL1 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
+AP_BL1 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
AP_BL1 - ->> AP_BL2: Validate, measure,load
-AP_BL1 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
+AP_BL1 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
AP_BL1 -> AP_BL2: Pass execution
deactivate AP_BL1
activate AP_BL2 #Green
Rnote over AP_BL2: Measure and load:\n\ HW_CONFIG
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
AP_BL2 - ->> AP_BL31: Validate, measure,load
Rnote over AP_BL2: Measure and load:\n\ BL31
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
Rnote over AP_BL2: Measure and load:\n\ RMM
-AP_BL2 -> RSS_S: Extend measurement
-Rnote over RSS_S: Measured Boot:\n\ store measurement
+AP_BL2 -> RSE_S: Extend measurement
+Rnote over RSE_S: Measured Boot:\n\ store measurement
AP_BL2 -> AP_BL31: Pass execution
deactivate AP_BL2
activate AP_BL31 #Green
-== RSS / AP Runtime ==
+== RSE / AP Runtime ==
@enduml
PlantUML version 1.2022.7(Mon Aug 22 19:01:30 CEST 2022)
diff --git a/docs/threat_model/firmware_threat_model/index.rst b/docs/threat_model/firmware_threat_model/index.rst
index 05b6710..ce1752f 100644
--- a/docs/threat_model/firmware_threat_model/index.rst
+++ b/docs/threat_model/firmware_threat_model/index.rst
@@ -30,7 +30,7 @@
threat_model
threat_model_el3_spm
threat_model_fvp_r
- threat_model_rss_interface
+ threat_model_rse_interface
threat_model_arm_cca
threat_model_fw_update_and_recovery
diff --git a/docs/threat_model/firmware_threat_model/threat_model_rss_interface.rst b/docs/threat_model/firmware_threat_model/threat_model_rse_interface.rst
similarity index 74%
rename from docs/threat_model/firmware_threat_model/threat_model_rss_interface.rst
rename to docs/threat_model/firmware_threat_model/threat_model_rse_interface.rst
index 025d2d9..3b391c1 100644
--- a/docs/threat_model/firmware_threat_model/threat_model_rss_interface.rst
+++ b/docs/threat_model/firmware_threat_model/threat_model_rse_interface.rst
@@ -1,41 +1,41 @@
-Threat Model for RSS - AP interface
+Threat Model for RSE - AP interface
***********************************
************
Introduction
************
This document is an extension for the general TF-A threat-model. It considers
-those platforms where a Runtime Security Subsystem (RSS) is included in the SoC
+those platforms where a Runtime Security Engine (RSE) is included in the SoC
next to the Application Processor (AP).
********************
Target of Evaluation
********************
-The scope of this threat model only includes the interface between the RSS and
+The scope of this threat model only includes the interface between the RSE and
AP. Otherwise, the TF-A :ref:`Generic Threat Model` document is applicable for
-the AP core. The threat model for the RSS firmware will be provided by the RSS
+the AP core. The threat model for the RSE firmware will be provided by the RSE
firmware project in the future.
Data Flow Diagram
=================
This diagram is different only from the general TF-A data flow diagram in that
-it includes the RSS and highlights the interface between the AP and the RSS
-cores. The interface description only focuses on the AP-RSS interface the rest
+it includes the RSE and highlights the interface between the AP and the RSE
+cores. The interface description only focuses on the AP-RSE interface the rest
is the same as in the general TF-A threat-model document.
-.. uml:: ../../resources/diagrams/plantuml/tfa_rss_dfd.puml
- :caption: Figure 1: TF-A Data Flow Diagram including RSS
+.. uml:: ../../resources/diagrams/plantuml/tfa_rse_dfd.puml
+ :caption: Figure 1: TF-A Data Flow Diagram including RSE
-.. table:: Table 1: TF-A - RSS data flow diagram
+.. table:: Table 1: TF-A - RSE data flow diagram
+-----------------+--------------------------------------------------------+
| Diagram Element | Description |
+=================+========================================================+
- | DF7 | | Boot images interact with RSS over a communication |
+ | DF7 | | Boot images interact with RSE over a communication |
| | channel to record boot measurements and get image |
| | verification keys. At runtime, BL31 obtains the |
- | | realm world attestation signing key from RSS. |
+ | | realm world attestation signing key from RSE. |
+-----------------+--------------------------------------------------------+
Threat Assessment
@@ -44,12 +44,12 @@
threat-model document, :ref:`Generic Threat Model`. All the threats listed there
are applicable for the AP core, here only the differences are highlighted.
- - ID 11: The access to the communication interface between AP and RSS is
+ - ID 11: The access to the communication interface between AP and RSE is
allowed only for firmware running at EL3. Accidentally exposing this
- interface to NSCode can allow malicious code to interact with RSS and
+ interface to NSCode can allow malicious code to interact with RSE and
gain access to sensitive data.
- ID 13: Relevant in the context of the realm attestation key, which can be
- retrieved by BL31 through DF7. The RSS communication protocol layer
+ retrieved by BL31 through DF7. The RSE communication protocol layer
mitigates against this by clearing its internal buffer when reply is
received. The caller of the API must do the same if data is not needed
anymore.
diff --git a/docs/threat_model/supply_chain_threat_model.rst b/docs/threat_model/supply_chain_threat_model.rst
index 386a4b0..a0fed5c 100644
--- a/docs/threat_model/supply_chain_threat_model.rst
+++ b/docs/threat_model/supply_chain_threat_model.rst
@@ -115,7 +115,7 @@
- *EDK2 UEFI*: Normal world bootloader from the EDK2 project [7]_. We use EDK2
UEFI binaries hosted on tf.org servers for testing [8]_.
-Other software components used to test TF-A include U-Boot, Linux kernel, RSS,
+Other software components used to test TF-A include U-Boot, Linux kernel, RSE,
MCP, and file systems, all sourced from the Arm Reference Platforms teams.
TF-A Toolchain
diff --git a/drivers/arm/css/dsu/dsu.c b/drivers/arm/css/dsu/dsu.c
new file mode 100644
index 0000000..f0e8df1
--- /dev/null
+++ b/drivers/arm/css/dsu/dsu.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/arm/css/dsu.h>
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+/*
+ * Context structure that saves the state of DSU PMU registers
+ */
+cluster_pmu_state_t cluster_pmu_context[PLAT_ARM_CLUSTER_COUNT];
+
+/****************************************************************************
+ * This function, save_dsu_pmu_state, is designed to save the
+ * current state of the Performance Monitoring Unit (PMU) for a cluster.
+ *
+ * The function performs the following operations:
+ * 1. Saves the current values of several PMU registers
+ * (CLUSTERPMCR_EL1, CLUSTERPMCNTENSET_EL1, CLUSTERPMCCNTR_EL1,
+ * CLUSTERPMOVSSET_EL1, and CLUSTERPMSELR_EL1) into the cluster_pmu_state
+ * structure.
+ *
+ * 2. Disables the PMU event counting by
+ * clearing the E bit in the clusterpmcr_el1 register.
+ *
+ * 3. Iterates over the available PMU counters as
+ * determined by the read_cluster_eventctr_num() function.
+ * For each counter, it:
+ * a. Selects the counter by writing its index to CLUSTERPMSELR_EL1.
+ * b. Reads the current counter value (event count) and
+ * the event type being counted from CLUSTERPMXEVCNTR_EL1 and
+ * CLUSTERPMXEVTYPER_EL1 registers, respectively.
+ *
+ * This function is useful for preserving the DynamIQ Shared Unit's (DSU)
+ * PMU registers over a power cycle.
+ ***************************************************************************/
+
+void save_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_state)
+{
+ unsigned int idx = 0U;
+ unsigned int cluster_eventctr_num = read_cluster_eventctr_num();
+
+ assert(cluster_pmu_state != 0);
+
+ save_pmu_reg(cluster_pmu_state, clusterpmcr);
+
+ write_clusterpmcr(cluster_pmu_state->clusterpmcr &
+ ~(CLUSTERPMCR_E_BIT));
+
+ save_pmu_reg(cluster_pmu_state, clusterpmcntenset);
+
+ save_pmu_reg(cluster_pmu_state, clusterpmccntr);
+
+ save_pmu_reg(cluster_pmu_state, clusterpmovsset);
+
+ save_pmu_reg(cluster_pmu_state, clusterpmselr);
+
+ for (idx = 0U ; idx < cluster_eventctr_num ; idx++) {
+ write_clusterpmselr(idx);
+ cluster_pmu_state->counter_val[idx] = read_clusterpmxevcntr();
+ cluster_pmu_state->counter_type[idx] = read_clusterpmxevtyper();
+ }
+}
+
+void cluster_off_dsu_pmu_context_save(void)
+{
+ unsigned int cluster_pos;
+
+ cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1());
+
+ save_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
+}
+
+/*****************************************************************************
+ * This function, restore_dsu_pmu_state, restores the state of the
+ * Performance Monitoring Unit (PMU) from a previously saved state.
+ *
+ * The function performs the following operations:
+ * 1. Restores the CLUSTERPMCR_EL1 register with the
+ * saved value from the cluster_pmu_state structure.
+ * 2. Iterates over the available PMU counters as determined
+ * by the read_cluster_eventctr_num() function. For each counter, it:
+ * a. Selects the counter by writing its index to CLUSTERPMSELR_EL1.
+ * b. Restores the counter value (event count) and the event type to
+ * CLUSTERPMXEVCNTR_EL1 and CLUSTERPMXEVTYPER_EL1 registers, respectively
+ * 3. Restores several other PMU registers (CLUSTERPMSELR_EL1,
+ * CLUSTERPMOVSCLR_EL1, CLUSTERPMOVSSET_EL1, CLUSTERPMCCNTR_EL1,
+ * and CLUSTERPMCNTENSET_EL1) with their saved values.
+ *
+ *****************************************************************************/
+void restore_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_state)
+{
+ unsigned int idx = 0U;
+ unsigned int cluster_eventctr_num = read_cluster_eventctr_num();
+
+ assert(cluster_pmu_state != 0);
+
+ for (idx = 0U ; idx < cluster_eventctr_num ; idx++) {
+ write_clusterpmselr(idx);
+ write_clusterpmxevcntr(cluster_pmu_state->counter_val[idx]);
+ write_clusterpmxevtyper(cluster_pmu_state->counter_type[idx]);
+ }
+
+ restore_pmu_reg(cluster_pmu_state, clusterpmselr);
+
+ write_clusterpmovsclr(~(uint32_t)cluster_pmu_state->clusterpmovsset);
+
+ restore_pmu_reg(cluster_pmu_state, clusterpmovsset);
+
+ restore_pmu_reg(cluster_pmu_state, clusterpmccntr);
+
+ restore_pmu_reg(cluster_pmu_state, clusterpmcntenset);
+
+ write_clusterpmcr(cluster_pmu_state->clusterpmcr);
+}
+
+void cluster_on_dsu_pmu_context_restore(void)
+{
+ unsigned int cluster_pos;
+
+ cluster_pos = (unsigned int) plat_cluster_id_by_mpidr(read_mpidr_el1());
+
+ restore_dsu_pmu_state(&cluster_pmu_context[cluster_pos]);
+}
+
diff --git a/drivers/arm/rss/rss_comms.c b/drivers/arm/rse/rse_comms.c
similarity index 77%
rename from drivers/arm/rss/rss_comms.c
rename to drivers/arm/rse/rse_comms.c
index 332105f..cfc5a83 100644
--- a/drivers/arm/rss/rss_comms.c
+++ b/drivers/arm/rse/rse_comms.c
@@ -9,16 +9,16 @@
#include <common/debug.h>
#include <drivers/arm/mhu.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
#include <psa/client.h>
-#include <rss_comms_protocol.h>
+#include <rse_comms_protocol.h>
/* Union as message space and reply space are never used at the same time, and this saves space as
* we can overlap them.
*/
-union __packed __attribute__((aligned(4))) rss_comms_io_buffer_t {
- struct serialized_rss_comms_msg_t msg;
- struct serialized_rss_comms_reply_t reply;
+union __packed __attribute__((aligned(4))) rse_comms_io_buffer_t {
+ struct serialized_rse_comms_msg_t msg;
+ struct serialized_rse_comms_reply_t reply;
};
static uint8_t select_protocol_version(const psa_invec *in_vec, size_t in_len,
@@ -40,13 +40,13 @@
comms_mhu_msg_size = mhu_get_max_message_size();
- comms_embed_msg_min_size = sizeof(struct serialized_rss_comms_header_t) +
- sizeof(struct rss_embed_msg_t) -
- PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE;
+ comms_embed_msg_min_size = sizeof(struct serialized_rse_comms_header_t) +
+ sizeof(struct rse_embed_msg_t) -
+ PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE;
- comms_embed_reply_min_size = sizeof(struct serialized_rss_comms_header_t) +
- sizeof(struct rss_embed_reply_t) -
- PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE;
+ comms_embed_reply_min_size = sizeof(struct serialized_rse_comms_header_t) +
+ sizeof(struct rse_embed_reply_t) -
+ PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE;
/* Use embed if we can pack into one message and reply, else use
* pointer_access. The underlying MHU transport protocol uses a
@@ -63,9 +63,9 @@
comms_mhu_msg_size - sizeof(uint32_t)) ||
(comms_embed_reply_min_size + out_size_total >
comms_mhu_msg_size - sizeof(uint32_t))) {
- return RSS_COMMS_PROTOCOL_POINTER_ACCESS;
+ return RSE_COMMS_PROTOCOL_POINTER_ACCESS;
} else {
- return RSS_COMMS_PROTOCOL_EMBED;
+ return RSE_COMMS_PROTOCOL_EMBED;
}
}
@@ -75,7 +75,7 @@
/* Declared statically to avoid using huge amounts of stack space. Maybe revisit if
* functions not being reentrant becomes a problem.
*/
- static union rss_comms_io_buffer_t io_buf;
+ static union rse_comms_io_buffer_t io_buf;
enum mhu_error_t err;
psa_status_t status;
static uint8_t seq_num = 1U;
@@ -94,13 +94,13 @@
io_buf.msg.header.client_id = 1U,
io_buf.msg.header.protocol_ver = select_protocol_version(in_vec, in_len, out_vec, out_len);
- status = rss_protocol_serialize_msg(handle, type, in_vec, in_len, out_vec,
+ status = rse_protocol_serialize_msg(handle, type, in_vec, in_len, out_vec,
out_len, &io_buf.msg, &msg_size);
if (status != PSA_SUCCESS) {
return status;
}
- VERBOSE("[RSS-COMMS] Sending message\n");
+ VERBOSE("[RSE-COMMS] Sending message\n");
VERBOSE("protocol_ver=%u\n", io_buf.msg.header.protocol_ver);
VERBOSE("seq_num=%u\n", io_buf.msg.header.seq_num);
VERBOSE("client_id=%u\n", io_buf.msg.header.client_id);
@@ -117,7 +117,7 @@
#if DEBUG
/*
* Poisoning the message buffer (with a known pattern).
- * Helps in detecting hypothetical RSS communication bugs.
+ * Helps in detecting hypothetical RSE communication bugs.
*/
memset(&io_buf.msg, 0xA5, msg_size);
#endif
@@ -127,12 +127,12 @@
return PSA_ERROR_COMMUNICATION_FAILURE;
}
- VERBOSE("[RSS-COMMS] Received reply\n");
+ VERBOSE("[RSE-COMMS] Received reply\n");
VERBOSE("protocol_ver=%u\n", io_buf.reply.header.protocol_ver);
VERBOSE("seq_num=%u\n", io_buf.reply.header.seq_num);
VERBOSE("client_id=%u\n", io_buf.reply.header.client_id);
- status = rss_protocol_deserialize_reply(out_vec, out_len, &return_val,
+ status = rse_protocol_deserialize_reply(out_vec, out_len, &return_val,
&io_buf.reply, reply_size);
if (status != PSA_SUCCESS) {
return status;
@@ -152,16 +152,16 @@
return return_val;
}
-int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base)
+int rse_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base)
{
enum mhu_error_t err;
err = mhu_init_sender(mhu_sender_base);
if (err != MHU_ERR_NONE) {
if (err == MHU_ERR_ALREADY_INIT) {
- INFO("[RSS-COMMS] Host to RSS MHU driver already initialized\n");
+ INFO("[RSE-COMMS] Host to RSE MHU driver already initialized\n");
} else {
- ERROR("[RSS-COMMS] Host to RSS MHU driver initialization failed: %d\n", err);
+ ERROR("[RSE-COMMS] Host to RSE MHU driver initialization failed: %d\n", err);
return -1;
}
}
@@ -169,9 +169,9 @@
err = mhu_init_receiver(mhu_receiver_base);
if (err != MHU_ERR_NONE) {
if (err == MHU_ERR_ALREADY_INIT) {
- INFO("[RSS-COMMS] RSS to Host MHU driver already initialized\n");
+ INFO("[RSE-COMMS] RSE to Host MHU driver already initialized\n");
} else {
- ERROR("[RSS-COMMS] RSS to Host MHU driver initialization failed: %d\n", err);
+ ERROR("[RSE-COMMS] RSE to Host MHU driver initialization failed: %d\n", err);
return -1;
}
}
diff --git a/drivers/arm/rse/rse_comms.mk b/drivers/arm/rse/rse_comms.mk
new file mode 100644
index 0000000..a1abc6a
--- /dev/null
+++ b/drivers/arm/rse/rse_comms.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+$(warning "RSE driver is an experimental feature")
+
+RSE_COMMS_SOURCES := $(addprefix drivers/arm/rse/, \
+ rse_comms.c \
+ rse_comms_protocol.c \
+ rse_comms_protocol_embed.c \
+ rse_comms_protocol_pointer_access.c \
+ )
+
+# Default to MHUv2 if PLAT_MHU_VERSION undefined
+PLAT_MHU_VERSION ?= 2
+
+ifeq (${PLAT_MHU_VERSION}, 3)
+RSE_COMMS_SOURCES += $(addprefix drivers/arm/mhu/, \
+ mhu_v3_x.c \
+ mhu_wrapper_v3_x.c \
+ )
+else ifeq (${PLAT_MHU_VERSION}, 2)
+RSE_COMMS_SOURCES += $(addprefix drivers/arm/mhu/, \
+ mhu_v2_x.c \
+ mhu_wrapper_v2_x.c \
+ )
+else
+$(error Unsupported MHU version)
+endif
+
+PLAT_INCLUDES += -Idrivers/arm/rse \
+ -Idrivers/arm/mhu
diff --git a/drivers/arm/rss/rss_comms_protocol.c b/drivers/arm/rse/rse_comms_protocol.c
similarity index 62%
rename from drivers/arm/rss/rss_comms_protocol.c
rename to drivers/arm/rse/rse_comms_protocol.c
index a1b1b58..3eb7eaa 100644
--- a/drivers/arm/rss/rss_comms_protocol.c
+++ b/drivers/arm/rse/rse_comms_protocol.c
@@ -7,15 +7,15 @@
#include <assert.h>
#include <common/debug.h>
-#include "rss_comms_protocol.h"
+#include "rse_comms_protocol.h"
-psa_status_t rss_protocol_serialize_msg(psa_handle_t handle,
+psa_status_t rse_protocol_serialize_msg(psa_handle_t handle,
int16_t type,
const psa_invec *in_vec,
uint8_t in_len,
const psa_outvec *out_vec,
uint8_t out_len,
- struct serialized_rss_comms_msg_t *msg,
+ struct serialized_rse_comms_msg_t *msg,
size_t *msg_len)
{
psa_status_t status;
@@ -25,15 +25,15 @@
assert(in_vec != NULL);
switch (msg->header.protocol_ver) {
- case RSS_COMMS_PROTOCOL_EMBED:
- status = rss_protocol_embed_serialize_msg(handle, type, in_vec, in_len, out_vec,
+ case RSE_COMMS_PROTOCOL_EMBED:
+ status = rse_protocol_embed_serialize_msg(handle, type, in_vec, in_len, out_vec,
out_len, &msg->msg.embed, msg_len);
if (status != PSA_SUCCESS) {
return status;
}
break;
- case RSS_COMMS_PROTOCOL_POINTER_ACCESS:
- status = rss_protocol_pointer_access_serialize_msg(handle, type, in_vec, in_len,
+ case RSE_COMMS_PROTOCOL_POINTER_ACCESS:
+ status = rse_protocol_pointer_access_serialize_msg(handle, type, in_vec, in_len,
out_vec, out_len,
&msg->msg.pointer_access,
msg_len);
@@ -45,26 +45,26 @@
return PSA_ERROR_NOT_SUPPORTED;
}
- *msg_len += sizeof(struct serialized_rss_comms_header_t);
+ *msg_len += sizeof(struct serialized_rse_comms_header_t);
return PSA_SUCCESS;
}
-psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec,
+psa_status_t rse_protocol_deserialize_reply(psa_outvec *out_vec,
uint8_t out_len,
psa_status_t *return_val,
- const struct serialized_rss_comms_reply_t *reply,
+ const struct serialized_rse_comms_reply_t *reply,
size_t reply_size)
{
assert(reply != NULL);
assert(return_val != NULL);
switch (reply->header.protocol_ver) {
- case RSS_COMMS_PROTOCOL_EMBED:
- return rss_protocol_embed_deserialize_reply(out_vec, out_len, return_val,
+ case RSE_COMMS_PROTOCOL_EMBED:
+ return rse_protocol_embed_deserialize_reply(out_vec, out_len, return_val,
&reply->reply.embed, reply_size);
- case RSS_COMMS_PROTOCOL_POINTER_ACCESS:
- return rss_protocol_pointer_access_deserialize_reply(out_vec, out_len, return_val,
+ case RSE_COMMS_PROTOCOL_POINTER_ACCESS:
+ return rse_protocol_pointer_access_deserialize_reply(out_vec, out_len, return_val,
&reply->reply.pointer_access,
reply_size);
default:
diff --git a/drivers/arm/rse/rse_comms_protocol.h b/drivers/arm/rse/rse_comms_protocol.h
new file mode 100644
index 0000000..24f3965
--- /dev/null
+++ b/drivers/arm/rse/rse_comms_protocol.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSE_COMMS_PROTOCOL_H__
+#define __RSE_COMMS_PROTOCOL_H__
+
+#include <cdefs.h>
+#include <stdint.h>
+
+#include <psa/client.h>
+#include "rse_comms_protocol_embed.h"
+#include "rse_comms_protocol_pointer_access.h"
+
+enum rse_comms_protocol_version_t {
+ RSE_COMMS_PROTOCOL_EMBED = 0,
+ RSE_COMMS_PROTOCOL_POINTER_ACCESS = 1,
+};
+
+struct __packed serialized_rse_comms_header_t {
+ uint8_t protocol_ver;
+ uint8_t seq_num;
+ uint16_t client_id;
+};
+
+/* MHU message passed from Host to RSE to deliver a PSA client call */
+struct __packed serialized_rse_comms_msg_t {
+ struct serialized_rse_comms_header_t header;
+ union __packed {
+ struct rse_embed_msg_t embed;
+ struct rse_pointer_access_msg_t pointer_access;
+ } msg;
+};
+
+/* MHU reply message to hold the PSA client reply result returned by RSE */
+struct __packed serialized_rse_comms_reply_t {
+ struct serialized_rse_comms_header_t header;
+ union __packed {
+ struct rse_embed_reply_t embed;
+ struct rse_pointer_access_reply_t pointer_access;
+ } reply;
+};
+
+/* in_len and out_len are uint8_ts, therefore if there are more than 255 iovecs
+ * an error may occur.
+ */
+CASSERT(PSA_MAX_IOVEC <= UINT8_MAX, assert_rse_comms_max_iovec_too_large);
+
+psa_status_t rse_protocol_serialize_msg(psa_handle_t handle,
+ int16_t type,
+ const psa_invec *in_vec,
+ uint8_t in_len,
+ const psa_outvec *out_vec,
+ uint8_t out_len,
+ struct serialized_rse_comms_msg_t *msg,
+ size_t *msg_len);
+
+psa_status_t rse_protocol_deserialize_reply(psa_outvec *out_vec,
+ uint8_t out_len,
+ psa_status_t *return_val,
+ const struct serialized_rse_comms_reply_t *reply,
+ size_t reply_size);
+
+#endif /* __RSE_COMMS_PROTOCOL_H__ */
diff --git a/drivers/arm/rss/rss_comms_protocol_common.h b/drivers/arm/rse/rse_comms_protocol_common.h
similarity index 89%
rename from drivers/arm/rss/rss_comms_protocol_common.h
rename to drivers/arm/rse/rse_comms_protocol_common.h
index 177d636..235ea92 100644
--- a/drivers/arm/rss/rss_comms_protocol_common.h
+++ b/drivers/arm/rse/rse_comms_protocol_common.h
@@ -17,8 +17,8 @@
* Res: Reserved.
*/
-#ifndef RSS_COMMS_PROTOCOL_COMMON
-#define RSS_COMMS_PROTOCOL_COMMON
+#ifndef RSE_COMMS_PROTOCOL_COMMON
+#define RSE_COMMS_PROTOCOL_COMMON
#define TYPE_OFFSET (0U)
#define TYPE_MASK (0xFFFFUL << TYPE_OFFSET)
@@ -32,4 +32,4 @@
((((uint32_t)(in_len)) << IN_LEN_OFFSET) & IN_LEN_MASK) | \
((((uint32_t)(out_len)) << OUT_LEN_OFFSET) & OUT_LEN_MASK))
-#endif /* RSS_COMMS_PROTOCOL_COMMON */
+#endif /* RSE_COMMS_PROTOCOL_COMMON */
diff --git a/drivers/arm/rss/rss_comms_protocol_embed.c b/drivers/arm/rse/rse_comms_protocol_embed.c
similarity index 85%
rename from drivers/arm/rss/rss_comms_protocol_embed.c
rename to drivers/arm/rse/rse_comms_protocol_embed.c
index 05628cc..d425257 100644
--- a/drivers/arm/rss/rss_comms_protocol_embed.c
+++ b/drivers/arm/rse/rse_comms_protocol_embed.c
@@ -9,16 +9,16 @@
#include <string.h>
#include <common/debug.h>
-#include "rss_comms_protocol_common.h"
-#include "rss_comms_protocol_embed.h"
+#include "rse_comms_protocol_common.h"
+#include "rse_comms_protocol_embed.h"
-psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle,
+psa_status_t rse_protocol_embed_serialize_msg(psa_handle_t handle,
int16_t type,
const psa_invec *in_vec,
uint8_t in_len,
const psa_outvec *out_vec,
uint8_t out_len,
- struct rss_embed_msg_t *msg,
+ struct rse_embed_msg_t *msg,
size_t *msg_len)
{
uint32_t payload_size = 0;
@@ -55,10 +55,10 @@
return PSA_SUCCESS;
}
-psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec,
+psa_status_t rse_protocol_embed_deserialize_reply(psa_outvec *out_vec,
uint8_t out_len,
psa_status_t *return_val,
- const struct rss_embed_reply_t *reply,
+ const struct rse_embed_reply_t *reply,
size_t reply_size)
{
uint32_t payload_offset = 0;
diff --git a/drivers/arm/rse/rse_comms_protocol_embed.h b/drivers/arm/rse/rse_comms_protocol_embed.h
new file mode 100644
index 0000000..165978d
--- /dev/null
+++ b/drivers/arm/rse/rse_comms_protocol_embed.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSE_COMMS_PROTOCOL_EMBED_H__
+#define __RSE_COMMS_PROTOCOL_EMBED_H__
+
+#include <cdefs.h>
+
+#include <psa/client.h>
+
+#include <platform_def.h>
+
+
+
+struct __packed rse_embed_msg_t {
+ psa_handle_t handle;
+ uint32_t ctrl_param; /* type, in_len, out_len */
+ uint16_t io_size[PSA_MAX_IOVEC];
+ uint8_t trailer[PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE];
+};
+
+struct __packed rse_embed_reply_t {
+ int32_t return_val;
+ uint16_t out_size[PSA_MAX_IOVEC];
+ uint8_t trailer[PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE];
+};
+
+psa_status_t rse_protocol_embed_serialize_msg(psa_handle_t handle,
+ int16_t type,
+ const psa_invec *in_vec,
+ uint8_t in_len,
+ const psa_outvec *out_vec,
+ uint8_t out_len,
+ struct rse_embed_msg_t *msg,
+ size_t *msg_len);
+
+psa_status_t rse_protocol_embed_deserialize_reply(psa_outvec *out_vec,
+ uint8_t out_len,
+ psa_status_t *return_val,
+ const struct rse_embed_reply_t *reply,
+ size_t reply_size);
+
+#endif /* __RSE_COMMS_PROTOCOL_EMBED_H__ */
diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.c b/drivers/arm/rse/rse_comms_protocol_pointer_access.c
similarity index 78%
rename from drivers/arm/rss/rss_comms_protocol_pointer_access.c
rename to drivers/arm/rse/rse_comms_protocol_pointer_access.c
index 3a10a98..63524eb 100644
--- a/drivers/arm/rss/rss_comms_protocol_pointer_access.c
+++ b/drivers/arm/rse/rse_comms_protocol_pointer_access.c
@@ -6,16 +6,16 @@
*/
#include <assert.h>
-#include "rss_comms_protocol_common.h"
-#include "rss_comms_protocol_pointer_access.h"
+#include "rse_comms_protocol_common.h"
+#include "rse_comms_protocol_pointer_access.h"
-psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle,
+psa_status_t rse_protocol_pointer_access_serialize_msg(psa_handle_t handle,
int16_t type,
const psa_invec *in_vec,
uint8_t in_len,
const psa_outvec *out_vec,
uint8_t out_len,
- struct rss_pointer_access_msg_t *msg,
+ struct rse_pointer_access_msg_t *msg,
size_t *msg_len)
{
unsigned int i;
@@ -42,10 +42,10 @@
return PSA_SUCCESS;
}
-psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
+psa_status_t rse_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
uint8_t out_len,
psa_status_t *return_val,
- const struct rss_pointer_access_reply_t *reply,
+ const struct rse_pointer_access_reply_t *reply,
size_t reply_size)
{
unsigned int i;
diff --git a/drivers/arm/rse/rse_comms_protocol_pointer_access.h b/drivers/arm/rse/rse_comms_protocol_pointer_access.h
new file mode 100644
index 0000000..e5935f3
--- /dev/null
+++ b/drivers/arm/rse/rse_comms_protocol_pointer_access.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __RSE_COMMS_PROTOCOL_POINTER_ACCESS_H__
+#define __RSE_COMMS_PROTOCOL_POINTER_ACCESS_H__
+
+#include <cdefs.h>
+
+#include <psa/client.h>
+
+struct __packed rse_pointer_access_msg_t {
+ psa_handle_t handle;
+ uint32_t ctrl_param;
+ uint32_t io_sizes[PSA_MAX_IOVEC];
+ uint64_t host_ptrs[PSA_MAX_IOVEC];
+};
+
+struct __packed rse_pointer_access_reply_t {
+ int32_t return_val;
+ uint32_t out_sizes[PSA_MAX_IOVEC];
+};
+
+psa_status_t rse_protocol_pointer_access_serialize_msg(psa_handle_t handle,
+ int16_t type,
+ const psa_invec *in_vec,
+ uint8_t in_len,
+ const psa_outvec *out_vec,
+ uint8_t out_len,
+ struct rse_pointer_access_msg_t *msg,
+ size_t *msg_len);
+
+psa_status_t rse_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
+ uint8_t out_len,
+ psa_status_t *return_val,
+ const struct rse_pointer_access_reply_t *reply,
+ size_t reply_size);
+
+#endif /* __RSE_COMMS_PROTOCOL_POINTER_ACCESS_H__ */
diff --git a/drivers/arm/rss/rss_comms.mk b/drivers/arm/rss/rss_comms.mk
deleted file mode 100644
index 0d1e308..0000000
--- a/drivers/arm/rss/rss_comms.mk
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# Copyright (c) 2022-2024, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-$(warning "RSS driver is an experimental feature")
-
-RSS_COMMS_SOURCES := $(addprefix drivers/arm/rss/, \
- rss_comms.c \
- rss_comms_protocol.c \
- rss_comms_protocol_embed.c \
- rss_comms_protocol_pointer_access.c \
- )
-
-# Default to MHUv2 if PLAT_MHU_VERSION undefined
-PLAT_MHU_VERSION ?= 2
-
-ifeq (${PLAT_MHU_VERSION}, 3)
-RSS_COMMS_SOURCES += $(addprefix drivers/arm/mhu/, \
- mhu_v3_x.c \
- mhu_wrapper_v3_x.c \
- )
-else ifeq (${PLAT_MHU_VERSION}, 2)
-RSS_COMMS_SOURCES += $(addprefix drivers/arm/mhu/, \
- mhu_v2_x.c \
- mhu_wrapper_v2_x.c \
- )
-else
-$(error Unsupported MHU version)
-endif
-
-PLAT_INCLUDES += -Idrivers/arm/rss \
- -Idrivers/arm/mhu
diff --git a/drivers/arm/rss/rss_comms_protocol.h b/drivers/arm/rss/rss_comms_protocol.h
deleted file mode 100644
index 9a38057..0000000
--- a/drivers/arm/rss/rss_comms_protocol.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __RSS_COMMS_PROTOCOL_H__
-#define __RSS_COMMS_PROTOCOL_H__
-
-#include <cdefs.h>
-#include <stdint.h>
-
-#include <psa/client.h>
-#include "rss_comms_protocol_embed.h"
-#include "rss_comms_protocol_pointer_access.h"
-
-enum rss_comms_protocol_version_t {
- RSS_COMMS_PROTOCOL_EMBED = 0,
- RSS_COMMS_PROTOCOL_POINTER_ACCESS = 1,
-};
-
-struct __packed serialized_rss_comms_header_t {
- uint8_t protocol_ver;
- uint8_t seq_num;
- uint16_t client_id;
-};
-
-/* MHU message passed from Host to RSS to deliver a PSA client call */
-struct __packed serialized_rss_comms_msg_t {
- struct serialized_rss_comms_header_t header;
- union __packed {
- struct rss_embed_msg_t embed;
- struct rss_pointer_access_msg_t pointer_access;
- } msg;
-};
-
-/* MHU reply message to hold the PSA client reply result returned by RSS */
-struct __packed serialized_rss_comms_reply_t {
- struct serialized_rss_comms_header_t header;
- union __packed {
- struct rss_embed_reply_t embed;
- struct rss_pointer_access_reply_t pointer_access;
- } reply;
-};
-
-/* in_len and out_len are uint8_ts, therefore if there are more than 255 iovecs
- * an error may occur.
- */
-CASSERT(PSA_MAX_IOVEC <= UINT8_MAX, assert_rss_comms_max_iovec_too_large);
-
-psa_status_t rss_protocol_serialize_msg(psa_handle_t handle,
- int16_t type,
- const psa_invec *in_vec,
- uint8_t in_len,
- const psa_outvec *out_vec,
- uint8_t out_len,
- struct serialized_rss_comms_msg_t *msg,
- size_t *msg_len);
-
-psa_status_t rss_protocol_deserialize_reply(psa_outvec *out_vec,
- uint8_t out_len,
- psa_status_t *return_val,
- const struct serialized_rss_comms_reply_t *reply,
- size_t reply_size);
-
-#endif /* __RSS_COMMS_PROTOCOL_H__ */
diff --git a/drivers/arm/rss/rss_comms_protocol_embed.h b/drivers/arm/rss/rss_comms_protocol_embed.h
deleted file mode 100644
index c81c795..0000000
--- a/drivers/arm/rss/rss_comms_protocol_embed.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __RSS_COMMS_PROTOCOL_EMBED_H__
-#define __RSS_COMMS_PROTOCOL_EMBED_H__
-
-#include <cdefs.h>
-
-#include <psa/client.h>
-
-#include <platform_def.h>
-
-
-
-struct __packed rss_embed_msg_t {
- psa_handle_t handle;
- uint32_t ctrl_param; /* type, in_len, out_len */
- uint16_t io_size[PSA_MAX_IOVEC];
- uint8_t trailer[PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE];
-};
-
-struct __packed rss_embed_reply_t {
- int32_t return_val;
- uint16_t out_size[PSA_MAX_IOVEC];
- uint8_t trailer[PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE];
-};
-
-psa_status_t rss_protocol_embed_serialize_msg(psa_handle_t handle,
- int16_t type,
- const psa_invec *in_vec,
- uint8_t in_len,
- const psa_outvec *out_vec,
- uint8_t out_len,
- struct rss_embed_msg_t *msg,
- size_t *msg_len);
-
-psa_status_t rss_protocol_embed_deserialize_reply(psa_outvec *out_vec,
- uint8_t out_len,
- psa_status_t *return_val,
- const struct rss_embed_reply_t *reply,
- size_t reply_size);
-
-#endif /* __RSS_COMMS_PROTOCOL_EMBED_H__ */
diff --git a/drivers/arm/rss/rss_comms_protocol_pointer_access.h b/drivers/arm/rss/rss_comms_protocol_pointer_access.h
deleted file mode 100644
index a4d054b..0000000
--- a/drivers/arm/rss/rss_comms_protocol_pointer_access.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__
-#define __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__
-
-#include <cdefs.h>
-
-#include <psa/client.h>
-
-struct __packed rss_pointer_access_msg_t {
- psa_handle_t handle;
- uint32_t ctrl_param;
- uint32_t io_sizes[PSA_MAX_IOVEC];
- uint64_t host_ptrs[PSA_MAX_IOVEC];
-};
-
-struct __packed rss_pointer_access_reply_t {
- int32_t return_val;
- uint32_t out_sizes[PSA_MAX_IOVEC];
-};
-
-psa_status_t rss_protocol_pointer_access_serialize_msg(psa_handle_t handle,
- int16_t type,
- const psa_invec *in_vec,
- uint8_t in_len,
- const psa_outvec *out_vec,
- uint8_t out_len,
- struct rss_pointer_access_msg_t *msg,
- size_t *msg_len);
-
-psa_status_t rss_protocol_pointer_access_deserialize_reply(psa_outvec *out_vec,
- uint8_t out_len,
- psa_status_t *return_val,
- const struct rss_pointer_access_reply_t *reply,
- size_t reply_size);
-
-#endif /* __RSS_COMMS_PROTOCOL_POINTER_ACCESS_H__ */
diff --git a/drivers/arm/smmu/smmu_v3.c b/drivers/arm/smmu/smmu_v3.c
index 6932e61..ef04c4d 100644
--- a/drivers/arm/smmu/smmu_v3.c
+++ b/drivers/arm/smmu/smmu_v3.c
@@ -97,7 +97,7 @@
#if ENABLE_RME
- if (get_armv9_2_feat_rme_support() != 0U) {
+ if (is_feat_rme_present()) {
if ((mmio_read_32(smmu_base + SMMU_ROOT_IDR0) &
SMMU_ROOT_IDR0_ROOT_IMPL) == 0U) {
WARN("Skip SMMU GPC configuration.\n");
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 2bb23f9..55ab935 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -41,7 +41,6 @@
cipher.c \
cipher_wrap.c \
constant_time.c \
- hash_info.c \
memory_buffer_alloc.c \
oid.c \
platform.c \
@@ -51,6 +50,7 @@
gcm.c \
md.c \
pk.c \
+ pk_ecc.c \
pk_wrap.c \
pkparse.c \
pkwrite.c \
@@ -65,22 +65,16 @@
x509_crt.c \
)
-# Currently on Mbedtls-3 there is outstanding bug due to usage
-# of redundant declaration[1], So disable redundant-decls
-# compilation flag to avoid compilation error when compiling with
-# Mbedtls-3.
-# [1]: https://github.com/Mbed-TLS/mbedtls/issues/6910
-LIBMBEDTLS_CFLAGS += -Wno-error=redundant-decls
-
ifeq (${PSA_CRYPTO},1)
+LIBMBEDTLS_CFLAGS += -Wno-error=unused-but-set-variable
LIBMBEDTLS_SRCS += $(addprefix ${MBEDTLS_DIR}/library/, \
psa_crypto.c \
psa_crypto_client.c \
- psa_crypto_driver_wrappers.c \
psa_crypto_hash.c \
psa_crypto_rsa.c \
psa_crypto_ecp.c \
psa_crypto_slot_management.c \
+ psa_util.c \
)
endif
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 230cec9..9bfcaac 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,6 +65,18 @@
#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \
CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
+
+
+/*
+ * NOTE: This has been made internal in mbedtls 3.6.0 and the mbedtls team has
+ * advised that it's better to copy out the declaration than it would be to
+ * update to 3.5.2, where this function is exposed.
+ */
+int mbedtls_x509_get_sig_alg(const mbedtls_x509_buf *sig_oid,
+ const mbedtls_x509_buf *sig_params,
+ mbedtls_md_type_t *md_alg,
+ mbedtls_pk_type_t *pk_alg,
+ void **sig_opts);
/*
* Verify a signature.
*
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 5891acf..99242e3 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <mbedtls/memory_buffer_alloc.h>
#include <mbedtls/oid.h>
#include <mbedtls/platform.h>
+#include <mbedtls/psa_util.h>
#include <mbedtls/version.h>
#include <mbedtls/x509.h>
#include <psa/crypto.h>
@@ -49,16 +50,6 @@
* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
*/
-static inline psa_algorithm_t mbedtls_md_psa_alg_from_type(
- mbedtls_md_type_t md_type)
-{
- assert((md_type == MBEDTLS_MD_SHA256) ||
- (md_type == MBEDTLS_MD_SHA384) ||
- (md_type == MBEDTLS_MD_SHA512));
-
- return PSA_ALG_CATEGORY_HASH | (psa_algorithm_t) (md_type + 0x5);
-}
-
/*
* AlgorithmIdentifier ::= SEQUENCE {
* algorithm OBJECT IDENTIFIER,
@@ -293,6 +284,62 @@
**/
/*
+ * This is a helper function that adjusts the start of the pk_start to point to
+ * the subjectPublicKey bytes within the SubjectPublicKeyInfo block.
+ *
+ * SubjectPublicKeyInfo ::= SEQUENCE {
+ * algorithm AlgorithmIdentifier,
+ * subjectPublicKey BIT STRING }
+ *
+ * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure,
+ * otherwise success(0).
+ **/
+static int pk_bytes_from_subpubkey(unsigned char **pk_start,
+ unsigned int *pk_len)
+{
+ mbedtls_asn1_buf alg_oid, alg_params;
+ int rc;
+ unsigned char *pk_end;
+ size_t len;
+ unsigned char *pk_ptr = *pk_start;
+
+ pk_end = pk_ptr + *pk_len;
+ rc = mbedtls_asn1_get_tag(&pk_ptr, pk_end, &len,
+ MBEDTLS_ASN1_CONSTRUCTED |
+ MBEDTLS_ASN1_SEQUENCE);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ pk_end = pk_ptr + len;
+ rc = mbedtls_asn1_get_alg(&pk_ptr, pk_end, &alg_oid, &alg_params);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+ pk_end = pk_ptr + len - (alg_oid.len + alg_params.len +
+ 2 * (SIZE_OF_ASN1_LEN + SIZE_OF_ASN1_TAG));
+ rc = mbedtls_asn1_get_bitstring_null(&pk_ptr, pk_end, &len);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ *pk_start = pk_ptr;
+ *pk_len = len;
+
+ return rc;
+}
+
+/*
+ * NOTE: This has been made internal in mbedtls 3.6.0 and the mbedtls team has
+ * advised that it's better to copy out the declaration than it would be to
+ * update to 3.5.2, where this function is exposed.
+ */
+int mbedtls_x509_get_sig_alg(const mbedtls_x509_buf *sig_oid,
+ const mbedtls_x509_buf *sig_params,
+ mbedtls_md_type_t *md_alg,
+ mbedtls_pk_type_t *pk_alg,
+ void **sig_opts);
+/*
* Verify a signature.
*
* Parameters are passed using the DER encoding format following the ASN.1
@@ -388,6 +435,20 @@
psa_set_key_type(&psa_key_attr, psa_key_type);
psa_set_key_usage_flags(&psa_key_attr, PSA_KEY_USAGE_VERIFY_MESSAGE);
+ /*
+ * Note: In the implementation of the psa_import_key function in
+ * version 3.6.0, the function expects the starting pointer of the
+ * subject public key instead of the starting point of
+ * SubjectPublicKeyInfo.
+ * This is only needed while dealing with RSASSA_PSS (RSA Signature
+ * scheme with Appendix based on Probabilistic Signature Scheme)
+ * algorithm.
+ */
+ if (pk_alg == MBEDTLS_PK_RSASSA_PSS) {
+ rc = pk_bytes_from_subpubkey((unsigned char **) &pk_ptr, &pk_len);
+ goto end2;
+ }
+
/* Get the key_id using import API */
status = psa_import_key(&psa_key_attr,
pk_ptr,
diff --git a/drivers/measured_boot/rss/dice_prot_env.c b/drivers/measured_boot/rse/dice_prot_env.c
similarity index 98%
rename from drivers/measured_boot/rss/dice_prot_env.c
rename to drivers/measured_boot/rse/dice_prot_env.c
index 81a21d1..8e9185a 100644
--- a/drivers/measured_boot/rss/dice_prot_env.c
+++ b/drivers/measured_boot/rse/dice_prot_env.c
@@ -13,7 +13,7 @@
#include <common/debug.h>
#include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
#include <lib/cassert.h>
#include <lib/psa/dice_protection_environment.h>
diff --git a/drivers/measured_boot/rss/dice_prot_env.mk b/drivers/measured_boot/rse/dice_prot_env.mk
similarity index 91%
rename from drivers/measured_boot/rss/dice_prot_env.mk
rename to drivers/measured_boot/rse/dice_prot_env.mk
index c5a35e0..7c83307 100644
--- a/drivers/measured_boot/rss/dice_prot_env.mk
+++ b/drivers/measured_boot/rse/dice_prot_env.mk
@@ -26,4 +26,4 @@
DPE_DIGEST_SIZE \
)))
-DPE_SOURCES += drivers/measured_boot/rss/dice_prot_env.c
+DPE_SOURCES += drivers/measured_boot/rse/dice_prot_env.c
diff --git a/drivers/measured_boot/rss/qcbor.mk b/drivers/measured_boot/rse/qcbor.mk
similarity index 100%
rename from drivers/measured_boot/rss/qcbor.mk
rename to drivers/measured_boot/rse/qcbor.mk
diff --git a/drivers/measured_boot/rss/rss_measured_boot.c b/drivers/measured_boot/rse/rse_measured_boot.c
similarity index 87%
rename from drivers/measured_boot/rss/rss_measured_boot.c
rename to drivers/measured_boot/rse/rse_measured_boot.c
index c44ec73..5337c3d 100644
--- a/drivers/measured_boot/rss/rss_measured_boot.c
+++ b/drivers/measured_boot/rse/rse_measured_boot.c
@@ -9,7 +9,7 @@
#include <common/debug.h>
#include <drivers/auth/crypto_mod.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
#include <lib/psa/measured_boot.h>
#include <psa/crypto_types.h>
#include <psa/crypto_values.h>
@@ -46,12 +46,12 @@
#endif /* ENABLE_ASSERTIONS */
/* Functions' declarations */
-void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr)
+void rse_measured_boot_init(struct rse_mboot_metadata *metadata_ptr)
{
assert(metadata_ptr != NULL);
/* Init the non-const members of the metadata structure */
- while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+ while (metadata_ptr->id != RSE_MBOOT_INVALID_ID) {
assert(null_arr(metadata_ptr->signer_id, MBOOT_DIGEST_SIZE));
metadata_ptr->sw_type_size =
strlen((const char *)&metadata_ptr->sw_type) + 1;
@@ -59,7 +59,7 @@
}
}
-int rss_mboot_measure_and_record(struct rss_mboot_metadata *metadata_ptr,
+int rse_mboot_measure_and_record(struct rse_mboot_metadata *metadata_ptr,
uintptr_t data_base, uint32_t data_size,
uint32_t data_id)
{
@@ -70,13 +70,13 @@
assert(metadata_ptr != NULL);
/* Get the metadata associated with this image. */
- while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) &&
+ while ((metadata_ptr->id != RSE_MBOOT_INVALID_ID) &&
(metadata_ptr->id != data_id)) {
metadata_ptr++;
}
/* If image is not present in metadata array then skip */
- if (metadata_ptr->id == RSS_MBOOT_INVALID_ID) {
+ if (metadata_ptr->id == RSE_MBOOT_INVALID_ID) {
return 0;
}
@@ -87,7 +87,7 @@
return rc;
}
- ret = rss_measured_boot_extend_measurement(
+ ret = rse_measured_boot_extend_measurement(
metadata_ptr->slot,
metadata_ptr->signer_id,
metadata_ptr->signer_id_size,
@@ -106,7 +106,7 @@
return 0;
}
-int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+int rse_mboot_set_signer_id(struct rse_mboot_metadata *metadata_ptr,
const void *pk_oid,
const void *pk_ptr,
size_t pk_len)
@@ -125,7 +125,7 @@
* The platform may decide not to measure all of the images
* in the system.
*/
- while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) {
+ while (metadata_ptr->id != RSE_MBOOT_INVALID_ID) {
/* Get the metadata associated with this key-oid */
if (metadata_ptr->pk_oid == pk_oid) {
if (hash_calc_done == false) {
diff --git a/drivers/measured_boot/rss/rss_measured_boot.mk b/drivers/measured_boot/rse/rse_measured_boot.mk
similarity index 65%
rename from drivers/measured_boot/rss/rss_measured_boot.mk
rename to drivers/measured_boot/rse/rse_measured_boot.mk
index 18ee836..1bd971f 100644
--- a/drivers/measured_boot/rss/rss_measured_boot.mk
+++ b/drivers/measured_boot/rse/rse_measured_boot.mk
@@ -6,27 +6,27 @@
# Hash algorithm for measured boot
# SHA-256 (or stronger) is required.
-MBOOT_RSS_HASH_ALG := sha256
+MBOOT_RSE_HASH_ALG := sha256
-ifeq (${MBOOT_RSS_HASH_ALG}, sha512)
+ifeq (${MBOOT_RSE_HASH_ALG}, sha512)
MBOOT_ALG_ID := MBOOT_ALG_SHA512
MBOOT_DIGEST_SIZE := 64U
-else ifeq (${MBOOT_RSS_HASH_ALG}, sha384)
+else ifeq (${MBOOT_RSE_HASH_ALG}, sha384)
MBOOT_ALG_ID := MBOOT_ALG_SHA384
MBOOT_DIGEST_SIZE := 48U
else
MBOOT_ALG_ID := MBOOT_ALG_SHA256
MBOOT_DIGEST_SIZE := 32U
-endif #MBOOT_RSS_HASH_ALG
+endif #MBOOT_RSE_HASH_ALG
# Set definitions for Measured Boot driver.
$(eval $(call add_defines,\
$(sort \
MBOOT_ALG_ID \
MBOOT_DIGEST_SIZE \
- MBOOT_RSS_BACKEND \
+ MBOOT_RSE_BACKEND \
)))
-MEASURED_BOOT_SRC_DIR := drivers/measured_boot/rss/
+MEASURED_BOOT_SRC_DIR := drivers/measured_boot/rse/
-MEASURED_BOOT_SOURCES += ${MEASURED_BOOT_SRC_DIR}rss_measured_boot.c
+MEASURED_BOOT_SOURCES += ${MEASURED_BOOT_SRC_DIR}rse_measured_boot.c
diff --git a/drivers/nxp/console/console.mk b/drivers/nxp/console/console.mk
index 6174650..5f3c6e3 100644
--- a/drivers/nxp/console/console.mk
+++ b/drivers/nxp/console/console.mk
@@ -1,5 +1,5 @@
#
-# Copyright 2021 NXP
+# Copyright 2021-2024 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -28,8 +28,13 @@
CONSOLE_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
${PLAT_DRIVERS_PATH}/console/console_pl011.c
else
+ifeq ($(CONSOLE), LINFLEX)
+CONSOLE_SOURCES := ${PLAT_DRIVERS_PATH}/console/linflex_console.S
+else
$(error -> CONSOLE not set!)
endif
+
+endif
endif
ifeq (${BL_COMM_CONSOLE_NEEDED},yes)
diff --git a/drivers/nxp/console/linflex_console.S b/drivers/nxp/console/linflex_console.S
new file mode 100644
index 0000000..abcbb59
--- /dev/null
+++ b/drivers/nxp/console/linflex_console.S
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/libc/errno.h>
+
+#include <asm_macros.S>
+#include <console_macros.S>
+#include <lib/utils_def.h>
+
+#define LDIV_MULTIPLIER U(16)
+
+#define LINFLEX_LINCR1 (0x0)
+#define LINCR1_INIT BIT_32(0)
+#define LINCR1_MME BIT_32(4)
+
+#define LINFLEX_LINSR (0x8)
+#define LINSR_LINS_INITMODE (0x00001000)
+#define LINSR_LINS_MASK (0x0000F000)
+
+#define LINFLEX_UARTCR (0x10)
+#define UARTCR_ROSE BIT_32(23)
+
+#define LINFLEX_UARTSR (0x14)
+#define LINFLEX_LINIBRR (0x28)
+#define LINFLEX_LINFBRR (0x24)
+#define LINFLEX_BDRL (0x38)
+#define LINFLEX_UARTPTO (0x50)
+
+#define UARTCR_UART BIT_32(0)
+#define UARTCR_WL0 BIT_32(1)
+#define UARTCR_PC0 BIT_32(3)
+#define UARTCR_TXEN BIT_32(4)
+#define UARTCR_RXEN BIT_32(5)
+#define UARTCR_PC1 BIT_32(6)
+#define UARTCR_TFBM BIT_32(8)
+#define UARTCR_RFBM BIT_32(9)
+#define UARTCR_OSR_SHIFT U(24)
+#define UARTCR_OSR_WIDTH U(4)
+
+#define UARTSR_DTF BIT_32(1)
+
+/*
+ * "core" functions are low-level implementations that do not require
+ * writable memory and are thus safe to call in BL1 crash context.
+ */
+.globl console_linflex_core_init
+.globl console_linflex_core_putc
+
+.globl console_linflex_register
+.globl console_linflex_putc
+
+/**
+ * uint32_t get_ldiv_mult(uintptr_t baseaddr, uint32_t clock,
+ * uint32_t baud, console_t *console,);
+ *
+ * Clobber list : x0 - x6
+ * Out x4: LDIV multiplier
+ */
+func get_ldiv_mult
+ ldr w4, [x0, LINFLEX_UARTCR]
+ mov w5, w4
+
+ /* Prepare choices in w5 and w6 */
+ ubfx x5, x5, #UARTCR_OSR_SHIFT, #UARTCR_OSR_WIDTH
+ mov w6, #LDIV_MULTIPLIER
+
+ and w4, w4, #UARTCR_ROSE
+ cmp w4, #0x0
+ csel w4, w5, w6, ne
+ ret
+endfunc get_ldiv_mult
+
+/*
+ * void linflex_set_brg(uintptr_t baseaddr, uint32_t clock
+ * uint32_t baud, console_t *console);
+ *
+ * Clobber list : x0 - x7, x13
+ */
+func linflex_set_brg
+ mov x13, x30
+ bl get_ldiv_mult
+ mov x30, x13
+
+ /* (x4) dividr = baudrate * ldiv_mult */
+ mul x4, x4, x2
+ /* (x5) divisr = clock rate */
+ mov x5, x1
+ /* (x6) ibr = divisr / dividr */
+ udiv x6, x5, x4
+ /* (x7) fbr = divisr % dividr */
+ msub x7, x6, x4, x5
+ /* fbr *= 16 / dividr */
+ lsl x7, x7, #4
+ udiv x7, x7, x4
+ /* fbr &= 0xf */
+ and w7, w7, #0xf
+ str w6, [x0, LINFLEX_LINIBRR]
+ str w7, [x0, LINFLEX_LINFBRR]
+ ret
+endfunc linflex_set_brg
+
+/**
+ * int console_linflex_core_init(uintptr_t baseaddr, uint32_t clock,
+ * uint32_t baud);
+ *
+ * In: x0 - Linflex base address
+ * x1 - clock frequency
+ * x2 - baudrate
+ * Out: x0 - 1 on success, 0 on error
+ * Clobber list : x0 - x7, x13 - x14
+ */
+func console_linflex_core_init
+ /* Set master mode and init mode */
+ mov w4, #(LINCR1_INIT)
+ str w4, [x0, LINFLEX_LINCR1]
+ mov w4, #(LINCR1_MME | LINCR1_INIT)
+ str w4, [x0, LINFLEX_LINCR1]
+
+ /* wait for init mode entry */
+wait_init_entry:
+ ldr w4, [x0, LINFLEX_LINSR]
+ and w4, w4, #LINSR_LINS_MASK
+ cmp w4, #LINSR_LINS_INITMODE
+ b.ne wait_init_entry
+
+ /* Set UART bit */
+ mov w4, #UARTCR_UART
+ str w4, [x0, LINFLEX_UARTCR]
+
+ mov x14, x30
+ bl linflex_set_brg
+ mov x30, x14
+
+ /* Set preset timeout register value. */
+ mov w4, #0xf
+ str w4, [x0, LINFLEX_UARTPTO]
+
+ /* 8-bit data, no parity, Tx/Rx enabled, UART mode */
+ mov w4, #(UARTCR_PC1 | UARTCR_RXEN | UARTCR_TXEN | UARTCR_PC0 | \
+ UARTCR_WL0 | UARTCR_UART | UARTCR_RFBM | UARTCR_TFBM)
+ str w4, [x0, LINFLEX_UARTCR]
+
+ /* End init mode */
+ ldr w4, [x0, LINFLEX_LINCR1]
+ bic w4, w4, #LINCR1_INIT
+ str w4, [x0, LINFLEX_LINCR1]
+ ret
+endfunc console_linflex_core_init
+
+/**
+ * int console_linflex_register(uintptr_t baseaddr, uint32_t clock,
+ * uint32_t clock, uint32_t baud);
+ *
+ * Function to initialize and register the console.
+ * The caller needs to pass an empty console_linflex_t
+ * structure in which *MUST* be allocated in
+ * persistent memory (e.g. a global or static local
+ * variable, *NOT* on the stack).
+ * In: x0 - Linflex base address
+ * x1 - clock frequency
+ * x2 - baudrate
+ * x3 - pointer to empty console_t structure
+ * Out: x0 - 1 on success, 0 on error
+ * Clobber list : x0 - x7, x13 - x15
+ */
+func console_linflex_register
+ mov x15, x30
+ bl console_linflex_core_init
+ mov x30, x15
+
+ /* Populate the base address */
+ str x0, [x3, #CONSOLE_T_BASE]
+
+ mov x0, x3
+ finish_console_register linflex, putc=1, getc=0, flush=0
+endfunc console_linflex_register
+
+/**
+ * int console_linflex_core_putc(int c, uintptr_t baseaddr);
+
+ * Out: w0 - printed character on success, < 0 on error.
+ * Clobber list : x0 - x3
+ */
+func console_linflex_core_putc
+ cbz x1, putc_error
+
+ cmp w0, #'\n'
+ b.ne print_char
+
+ /* Print '\r\n' for each '\n' */
+ mov x0, #'\r'
+ mov x14, x30
+ bl console_linflex_core_putc
+ mov x30, x14
+ mov x0, #'\n'
+
+print_char:
+ ldr w2, [x1, LINFLEX_UARTCR]
+ and w2, w2, #UARTCR_TFBM
+ cmp w2, #0x0
+ b.eq buffer_mode
+
+fifo_mode:
+ /* UART is in FIFO mode */
+ ldr w2, [x1, LINFLEX_UARTSR]
+ and w2, w2, #UARTSR_DTF
+ cmp w2, #0
+ b.ne fifo_mode
+
+ strb w0, [x1, LINFLEX_BDRL]
+ b no_error
+
+buffer_mode:
+ strb w0, [x1, LINFLEX_BDRL]
+
+buffer_loop:
+ ldr w2, [x1, LINFLEX_UARTSR]
+ and w3, w2, #UARTSR_DTF
+ cmp w3, #0
+ b.eq buffer_loop
+
+ /**
+ * In Buffer Mode the DTFTFF bit of UARTSR register
+ * has to be set in software
+ */
+ mov w2, #UARTSR_DTF
+ str w2, [x1, LINFLEX_UARTSR]
+
+no_error:
+ mov x0, #0
+ ret
+
+putc_error:
+ mov x0, #-EINVAL
+ ret
+endfunc console_linflex_core_putc
+
+/**
+ * int console_linflex_putc(int c, console_t *console);
+ *
+ * Function to output a character over the console. It
+ * returns the character printed on success or -EINVAL on error.
+ * In : w0 - character to be printed
+ * x1 - pointer to console_t struct
+ * Out: w0 - printed character on success, < 0 on error.
+ * Clobber list : x0 - x3, x15
+ */
+func console_linflex_putc
+ cbz x1, putc_error
+ ldr x1, [x1, #CONSOLE_T_BASE]
+
+ b console_linflex_core_putc
+puct_error:
+ mov x0, #-EINVAL
+ ret
+endfunc console_linflex_putc
diff --git a/drivers/st/bsec/bsec2.c b/drivers/st/bsec/bsec2.c
index a6e5220..db07d1c 100644
--- a/drivers/st/bsec/bsec2.c
+++ b/drivers/st/bsec/bsec2.c
@@ -166,11 +166,13 @@
struct dt_node_info bsec_info;
if (fdt_get_address(&fdt) == 0) {
+ EARLY_ERROR("%s: DT not found\n", __func__);
panic();
}
node = bsec_get_dt_node(&bsec_info);
if (node < 0) {
+ EARLY_ERROR("%s: BSEC node not found\n", __func__);
panic();
}
@@ -226,13 +228,21 @@
*/
uint32_t bsec_probe(void)
{
+ uint32_t version;
+ uint32_t id;
+
if (is_otp_invalid_mode()) {
+ EARLY_ERROR("%s: otp_invalid_mod\n", __func__);
return BSEC_ERROR;
}
- if (((bsec_get_version() != BSEC_IP_VERSION_1_1) &&
- (bsec_get_version() != BSEC_IP_VERSION_2_0)) ||
- (bsec_get_id() != BSEC_IP_ID_2)) {
+ version = bsec_get_version();
+ id = bsec_get_id();
+
+ if (((version != BSEC_IP_VERSION_1_1) &&
+ (version != BSEC_IP_VERSION_2_0)) ||
+ (id != BSEC_IP_ID_2)) {
+ EARLY_ERROR("%s: version = 0x%x, id = 0x%x\n", __func__, version, id);
panic();
}
diff --git a/drivers/st/bsec/bsec3.c b/drivers/st/bsec/bsec3.c
index a803a3a..3fdaf16 100644
--- a/drivers/st/bsec/bsec3.c
+++ b/drivers/st/bsec/bsec3.c
@@ -188,7 +188,7 @@
uint32_t id = bsec_get_id();
if ((version != BSEC_IP_VERSION_1_0) || (id != BSEC_IP_ID_3)) {
- ERROR("%s: version = 0x%x, id = 0x%x\n", __func__, version, id);
+ EARLY_ERROR("%s: version = 0x%x, id = 0x%x\n", __func__, version, id);
panic();
}
diff --git a/fdts/tc.dts b/fdts/tc-base.dtsi
similarity index 70%
rename from fdts/tc.dts
rename to fdts/tc-base.dtsi
index 63f6c3d..e32d215 100644
--- a/fdts/tc.dts
+++ b/fdts/tc-base.dtsi
@@ -4,15 +4,37 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-/dts-v1/;
+/* If SCMI power domain control is enabled */
+#if TC_SCMI_PD_CTRL_EN
+#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1)
+#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
+#endif /* TC_SCMI_PD_CTRL_EN */
+
+/* Use SCMI controlled clocks */
+#if TC_DPU_USE_SCMI_CLK
+#define DPU_CLK_ATTR1 \
+ clocks = <&scmi_clk 0>; \
+ clock-names = "aclk"
+
+#define DPU_CLK_ATTR2 \
+ clocks = <&scmi_clk 1>; \
+ clock-names = "pxclk"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include "platform_def.h"
-#include "tc_vers.dtsi"
-#if TARGET_FLAVOUR_FVP
-#include "tc_fvp.dtsi"
-#endif /* TARGET_FLAVOUR_FVP */
+#define DPU_CLK_ATTR3 \
+ clocks = <&scmi_clk 2>; \
+ clock-names = "pxclk" \
+/* Use fixed clocks */
+#else /* !TC_DPU_USE_SCMI_CLK */
+#define DPU_CLK_ATTR1 \
+ clocks = <&dpu_aclk>; \
+ clock-names = "aclk"
+
+#define DPU_CLK_ATTR2 \
+ clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \
+ clock-names = "pxclk", "aclk"
+
+#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
+#endif /* !TC_DPU_USE_SCMI_CLK */
/ {
compatible = "arm,tc";
@@ -25,7 +47,6 @@
};
chosen {
- stdout-path = STDOUT_PATH;
/*
* Add some dummy entropy for Linux so it
* doesn't delay the boot waiting for it.
@@ -70,26 +91,6 @@
core7 {
cpu = <&CPU7>;
};
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- core8 {
- cpu = <&CPU8>;
- };
- core9 {
- cpu = <&CPU9>;
- };
- core10 {
- cpu = <&CPU10>;
- };
- core11 {
- cpu = <&CPU11>;
- };
- core12 {
- cpu = <&CPU12>;
- };
- core13 {
- cpu = <&CPU13>;
- };
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
};
@@ -170,13 +171,6 @@
reg = <0x200>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
-#elif TARGET_PLATFORM == 3
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -187,13 +181,6 @@
reg = <0x300>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 0>;
- capacity-dmips-mhz = <LIT_CAPACITY>;
-#elif TARGET_PLATFORM == 3
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -228,13 +215,6 @@
reg = <0x600>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#elif TARGET_PLATFORM == 3
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
-#endif /* TARGET_PLATFORM == 3 */
amu = <&amu>;
supports-mpmm;
};
@@ -245,84 +225,9 @@
reg = <0x700>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
-#else
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
amu = <&amu>;
supports-mpmm;
};
-
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- CPU8:cpu@800 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x800>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- capacity-dmips-mhz = <MID_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU9:cpu@900 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x900>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU10:cpu@A00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xA00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU11:cpu@B00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xB00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 2>;
- capacity-dmips-mhz = <BIG2_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU12:cpu@C00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xC00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-
- CPU13:cpu@D00 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0xD00>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 3>;
- capacity-dmips-mhz = <BIG_CAPACITY>;
- amu = <&amu>;
- supports-mpmm;
- };
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
};
reserved-memory {
@@ -363,13 +268,6 @@
cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
- <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- ,<&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
- <&CPU12>, <&CPU13>
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
- ;
};
sram: sram@6000000 {
@@ -386,52 +284,50 @@
};
};
- mbox_db_rx: mhu@MHU_RX_ADDR() {
+ mbox_db_rx: mhu@MHU_RX_ADDR {
compatible = "arm,mhuv2-rx","arm,primecell";
- reg = <0x0 MHU_RX_ADDR(0x) 0x0 0x1000>;
+ reg = <0x0 ADDRESSIFY(MHU_RX_ADDR) 0x0 0x1000>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupts = <GIC_SPI INT_MBOX_RX IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mhu_rx";
- mhu-protocol = "doorbell";
- arm,mhuv2-protocols = <0 1>;
};
- mbox_db_tx: mhu@MHU_TX_ADDR() {
+ mbox_db_tx: mhu@MHU_TX_ADDR {
compatible = "arm,mhuv2-tx","arm,primecell";
- reg = <0x0 MHU_TX_ADDR(0x) 0x0 0x1000>;
+ reg = <0x0 ADDRESSIFY(MHU_TX_ADDR) 0x0 0x1000>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
#mbox-cells = <2>;
interrupt-names = "mhu_tx";
- mhu-protocol = "doorbell";
- arm,mhuv2-protocols = <0 1>;
};
- scmi {
- compatible = "arm,scmi";
- mbox-names = "tx", "rx";
- mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
- shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
- #address-cells = <1>;
- #size-cells = <0>;
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mbox-names = "tx", "rx";
+ mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
+ shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#if TC_SCMI_PD_CTRL_EN
- scmi_devpd: protocol@11 {
- reg = <0x11>;
- #power-domain-cells = <1>;
- };
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
#endif /* TC_SCMI_PD_CTRL_EN */
- scmi_dvfs: protocol@13 {
- reg = <0x13>;
- #clock-cells = <1>;
- };
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
};
};
@@ -485,6 +381,22 @@
clock-names = "uartclk", "apb_pclk";
status = "okay";
};
+
+#if !TC_DPU_USE_SCMI_CLK
+ dpu_aclk: dpu_aclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <VENCODER_TIMING_CLK>;
+ clock-output-names = "fpga:dpu_aclk";
+ };
+
+ dpu_pixel_clk: dpu-pixel-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <VENCODER_TIMING_CLK>;
+ clock-output-names = "pxclk";
+ };
+#endif /* !TC_DPU_USE_SCMI_CLK */
vencoder {
compatible = "drm,virtual-encoder";
@@ -502,13 +414,10 @@
};
- ethernet@18000000 {
- compatible = ETH_COMPATIBLE;
+ ethernet: ethernet@18000000 {
reg = <0x0 0x18000000 0x0 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- /* FPGA only but will work on FVP. Keep for simplicity */
- phy-mode = "mii";
reg-io-width = <2>;
smsc,irq-push-pull;
};
@@ -536,12 +445,11 @@
regulator-always-on;
};
- mmci@1c050000 {
+ mmci: mmci@1c050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- MMC_REMOVABLE;
wp-gpios = <&sysreg 1 0>;
bus-width = <4>;
max-frequency = <25000000>;
@@ -606,20 +514,17 @@
};
#endif /* TC_IOMMU_EN */
- dp0: display@DPU_ADDR() {
+ dp0: display@DPU_ADDR {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
- reg = <HI(DPU_ADDR(0x)) LO(DPU_ADDR(0x)) 0 0x20000>;
+ reg = <HI(ADDRESSIFY(DPU_ADDR)) LO(ADDRESSIFY(DPU_ADDR)) 0 0x20000>;
interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DPU";
DPU_CLK_ATTR1;
#if TC_IOMMU_EN
iommus = <&smmu_700 0x100>;
#endif /* TC_IOMMU_EN */
-#if TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3)
- power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
-#endif /* TC_SCMI_PD_CTRL_EN && (TARGET_PLATFORM != 3) */
pl0: pipeline@0 {
reg = <0>;
@@ -699,38 +604,6 @@
compatible = "arm,embedded-trace-extension";
cpu = <&CPU7>;
};
-
-#if TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2
- ete8 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU8>;
- };
-
- ete9 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU9>;
- };
-
- ete10 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU10>;
- };
-
- ete11 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU11>;
- };
-
- ete12 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU12>;
- };
-
- ete13 {
- compatible = "arm,embedded-trace-extension";
- cpu = <&CPU13>;
- };
-#endif /* TARGET_FLAVOUR_FPGA && TARGET_PLATFORM <= 2 */
trbe {
compatible = "arm,trace-buffer-extension";
diff --git a/fdts/tc-common.dtsi b/fdts/tc-common.dtsi
new file mode 100644
index 0000000..c331193
--- /dev/null
+++ b/fdts/tc-common.dtsi
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define PASTER(x, y) x ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/fdts/tc-fpga.dtsi b/fdts/tc-fpga.dtsi
new file mode 100644
index 0000000..73f4743
--- /dev/null
+++ b/fdts/tc-fpga.dtsi
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define GIC_CTRL_ADDR 30000000
+#define GIC_GICR_OFFSET 0x1000000
+#define UART_OFFSET 0x10000
+/* 1440x3200@120 framebuffer */
+#define VENCODER_TIMING_CLK 836000000
+#define VENCODER_TIMING \
+ clock-frequency = <VENCODER_TIMING_CLK>; \
+ hactive = <1440>; \
+ vactive = <3200>; \
+ hfront-porch = <136>; \
+ hback-porch = <296>; \
+ hsync-len = <160>; \
+ vfront-porch = <3>; \
+ vback-porch = <217>; \
+ vsync-len = <10>
+
+/ {
+ chosen {
+ stdout-path = "serial0:38400n8";
+ };
+
+ ethernet: ethernet@18000000 {
+ compatible = "smsc,lan9115";
+ phy-mode = "mii";
+ };
+
+ mmci: mmci@1c050000 {
+ non-removable;
+ };
+};
diff --git a/fdts/tc_fvp.dtsi b/fdts/tc-fvp.dtsi
similarity index 62%
rename from fdts/tc_fvp.dtsi
rename to fdts/tc-fvp.dtsi
index 42f3818..46b0e81 100644
--- a/fdts/tc_fvp.dtsi
+++ b/fdts/tc-fvp.dtsi
@@ -4,7 +4,34 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#define GIC_CTRL_ADDR 2c010000
+#define GIC_GICR_OFFSET 0x200000
+#define UART_OFFSET 0x1000
+#define VENCODER_TIMING_CLK 25175000
+#define VENCODER_TIMING \
+ clock-frequency = <VENCODER_TIMING_CLK>; \
+ hactive = <640>; \
+ vactive = <480>; \
+ hfront-porch = <16>; \
+ hback-porch = <48>; \
+ hsync-len = <96>; \
+ vfront-porch = <10>; \
+ vback-porch = <33>; \
+ vsync-len = <2>
+
/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ethernet: ethernet@18000000 {
+ compatible = "smsc,lan91c111";
+ };
+
+ mmci: mmci@1c050000 {
+ cd-gpios = <&sysreg 0 0>;
+ };
+
rtc@1c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
new file mode 100644
index 0000000..288b40f
--- /dev/null
+++ b/fdts/tc2.dts
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <platform_def.h>
+
+#if TARGET_FLAVOUR_FVP
+#define LIT_CAPACITY 406
+#define MID_CAPACITY 912
+#else /* TARGET_FLAVOUR_FPGA */
+#define LIT_CAPACITY 280
+#define MID_CAPACITY 775
+/* this is an area optimized configuration of the big core */
+#define BIG2_CAPACITY 930
+#endif /* TARGET_FLAVOUR_FPGA */
+#define BIG_CAPACITY 1024
+
+#define INT_MBOX_RX 317
+#define MHU_TX_ADDR 45000000 /* hex */
+#define MHU_RX_ADDR 45010000 /* hex */
+#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
+#define UARTCLK_FREQ 5000000
+
+#define DPU_ADDR 2cc00000
+#define DPU_IRQ 69
+
+#include "tc-common.dtsi"
+#if TARGET_FLAVOUR_FVP
+#include "tc-fvp.dtsi"
+#else
+#include "tc-fpga.dtsi"
+#endif /* TARGET_FLAVOUR_FVP */
+#include "tc-base.dtsi"
+
+/ {
+ cpus {
+#if TARGET_FLAVOUR_FPGA
+ cpu-map {
+ cluster0 {
+ core8 {
+ cpu = <&CPU8>;
+ };
+ core9 {
+ cpu = <&CPU9>;
+ };
+ core10 {
+ cpu = <&CPU10>;
+ };
+ core11 {
+ cpu = <&CPU11>;
+ };
+ core12 {
+ cpu = <&CPU12>;
+ };
+ core13 {
+ cpu = <&CPU13>;
+ };
+ };
+ };
+#endif
+
+ CPU2:cpu@200 {
+ clocks = <&scmi_dvfs 0>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
+ };
+
+ CPU3:cpu@300 {
+ clocks = <&scmi_dvfs 0>;
+ capacity-dmips-mhz = <LIT_CAPACITY>;
+ };
+
+ CPU6:cpu@600 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+ CPU7:cpu@700 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+#if TARGET_FLAVOUR_FPGA
+ CPU8:cpu@800 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x800>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU9:cpu@900 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x900>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU10:cpu@A00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xA00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU11:cpu@B00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xB00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG2_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU12:cpu@C00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xC00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 3>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+
+ CPU13:cpu@D00 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0xD00>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 3>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ amu = <&amu>;
+ supports-mpmm;
+ };
+#endif
+ };
+
+#if TARGET_FLAVOUR_FPGA
+ ete8 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU8>;
+ };
+
+ ete9 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU9>;
+ };
+
+ ete10 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU10>;
+ };
+
+ ete11 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU11>;
+ };
+
+ ete12 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU12>;
+ };
+
+ ete13 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&CPU13>;
+ };
+#endif /* TARGET_FLAVOUR_FPGA */
+
+ cpu-pmu {
+#if TARGET_FLAVOUR_FPGA
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>,
+ <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>,
+ <&CPU12>, <&CPU13>;
+#else
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+#endif
+ };
+
+ cmn-pmu {
+ compatible = "arm,ci-700";
+ reg = <0x0 0x50000000 0x0 0x10000000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ mbox_db_rx: mhu@MHU_RX_ADDR {
+ arm,mhuv2-protocols = <0 1>;
+ };
+
+ mbox_db_tx: mhu@MHU_TX_ADDR {
+ arm,mhuv2-protocols = <0 1>;
+ };
+
+ dp0: display@DPU_ADDR {
+#if TC_SCMI_PD_CTRL_EN
+ power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
+#endif
+ };
+};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
new file mode 100644
index 0000000..52b0856
--- /dev/null
+++ b/fdts/tc3.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <platform_def.h>
+
+#define LIT_CAPACITY 239
+#define MID_CAPACITY 686
+#define BIG_CAPACITY 1024
+
+#define INT_MBOX_RX 300
+#define MHU_TX_ADDR 46040000 /* hex */
+#define MHU_RX_ADDR 46140000 /* hex */
+#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
+#define UARTCLK_FREQ 3750000
+
+#if TARGET_FLAVOUR_FVP
+#define DPU_ADDR 4000000000
+#define DPU_IRQ 579
+#elif TARGET_FLAVOUR_FPGA
+#define DPU_ADDR 2cc00000
+#define DPU_IRQ 69
+#endif
+
+#include "tc-common.dtsi"
+#if TARGET_FLAVOUR_FVP
+#include "tc-fvp.dtsi"
+#else
+#include "tc-fpga.dtsi"
+#endif /* TARGET_FLAVOUR_FVP */
+#include "tc-base.dtsi"
+
+/ {
+ cpus {
+ CPU2:cpu@200 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+ CPU3:cpu@300 {
+ clocks = <&scmi_dvfs 1>;
+ capacity-dmips-mhz = <MID_CAPACITY>;
+ };
+
+ CPU6:cpu@600 {
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ };
+
+ CPU7:cpu@700 {
+ clocks = <&scmi_dvfs 2>;
+ capacity-dmips-mhz = <BIG_CAPACITY>;
+ };
+ };
+
+ cpu-pmu {
+ interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+ };
+};
diff --git a/fdts/tc_vers.dtsi b/fdts/tc_vers.dtsi
deleted file mode 100644
index 43fafd5..0000000
--- a/fdts/tc_vers.dtsi
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/* If SCMI power domain control is enabled */
-#if TC_SCMI_PD_CTRL_EN
-#define GPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 1)
-#define DPU_SCMI_PD_IDX (PLAT_MAX_CPUS_PER_CLUSTER + 2)
-#endif /* TC_SCMI_PD_CTRL_EN */
-
-/* All perf is normalized against the big core */
-#define BIG_CAPACITY 1024
-
-#if TARGET_PLATFORM <= 2
-#if TARGET_FLAVOUR_FVP
-#define LIT_CAPACITY 406
-#define MID_CAPACITY 912
-#else /* TARGET_FLAVOUR_FPGA */
-#define LIT_CAPACITY 280
-#define MID_CAPACITY 775
-/* this is an area optimized configuration of the big core */
-#define BIG2_CAPACITY 930
-#endif /* TARGET_FLAVOUR_FPGA */
-
-#define INT_MBOX_RX 317
-#define MHU_TX_ADDR(pref) pref##45000000 /* hex */
-#define MHU_RX_ADDR(pref) pref##45010000 /* hex */
-#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
-#define UARTCLK_FREQ 5000000
-#elif TARGET_PLATFORM == 3
-
-#define LIT_CAPACITY 239
-#define MID_CAPACITY 686
-
-#define INT_MBOX_RX 300
-#define MHU_TX_ADDR(pref) pref##46040000 /* hex */
-#define MHU_RX_ADDR(pref) pref##46140000 /* hex */
-#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
-#define UARTCLK_FREQ 3750000
-#endif /* TARGET_PLATFORM == 3 */
-
-#if TARGET_FLAVOUR_FVP
-#define STDOUT_PATH "serial0:115200n8"
-#define GIC_CTRL_ADDR 2c010000
-#define GIC_GICR_OFFSET 0x200000
-#define UART_OFFSET 0x1000
-#define VENCODER_TIMING_CLK 25175000
-#define VENCODER_TIMING \
- clock-frequency = <VENCODER_TIMING_CLK>; \
- hactive = <640>; \
- vactive = <480>; \
- hfront-porch = <16>; \
- hback-porch = <48>; \
- hsync-len = <96>; \
- vfront-porch = <10>; \
- vback-porch = <33>; \
- vsync-len = <2>
-#define ETH_COMPATIBLE "smsc,lan91c111"
-#define MMC_REMOVABLE cd-gpios = <&sysreg 0 0>
-#if TARGET_PLATFORM <= 2
-#define DPU_ADDR(pref) pref##2cc00000
-#define DPU_IRQ 69
-#else /* TARGET_PLATFORM >= 3 */
-#define DPU_ADDR(pref) pref##4000000000
-#define DPU_IRQ 579
-#endif /* TARGET_PLATFORM >= 3 */
-
-#else /* TARGET_FLAVOUR_FPGA */
-
-#define STDOUT_PATH "serial0:38400n8"
-#define GIC_CTRL_ADDR 30000000
-#define GIC_GICR_OFFSET 0x1000000
-#define UART_OFFSET 0x10000
-/* 1440x3200@120 framebuffer */
-#define VENCODER_TIMING_CLK 836000000
-#define VENCODER_TIMING \
- clock-frequency = <VENCODER_TIMING_CLK>; \
- hactive = <1440>; \
- vactive = <3200>; \
- hfront-porch = <136>; \
- hback-porch = <296>; \
- hsync-len = <160>; \
- vfront-porch = <3>; \
- vback-porch = <217>; \
- vsync-len = <10>
-#define ETH_COMPATIBLE "smsc,lan9115"
-#define MMC_REMOVABLE non-removable
-#define DPU_ADDR(pref) pref##2cc00000
-#define DPU_IRQ 69
-#endif /* TARGET_FLAVOUR_FPGA */
-
-/* Use SCMI controlled clocks */
-#if TC_DPU_USE_SCMI_CLK
-#define DPU_CLK_ATTR1 \
- clocks = <&scmi_clk 0>; \
- clock-names = "aclk"
-
-#define DPU_CLK_ATTR2 \
- clocks = <&scmi_clk 1>; \
- clock-names = "pxclk"
-
-#define DPU_CLK_ATTR3 \
- clocks = <&scmi_clk 2>; \
- clock-names = "pxclk" \
-/* Use fixed clocks */
-#else /* !TC_DPU_USE_SCMI_CLK */
-#define DPU_CLK_ATTR1 \
- clocks = <&dpu_aclk>; \
- clock-names = "aclk"
-
-#define DPU_CLK_ATTR2 \
- clocks = <&dpu_pixel_clk>, <&dpu_aclk>; \
- clock-names = "pxclk", "aclk"
-
-#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
-#endif /* !TC_DPU_USE_SCMI_CLK */
-
-/ {
-#if TARGET_PLATFORM <= 2
- cmn-pmu {
- compatible = "arm,ci-700";
- reg = <0x0 0x50000000 0x0 0x10000000>;
- interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
- };
-#endif /* TARGET_PLATFORM <= 2 */
-
-#if !TC_DPU_USE_SCMI_CLK
- dpu_aclk: dpu_aclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <VENCODER_TIMING_CLK>;
- clock-output-names = "fpga:dpu_aclk";
- };
-
- dpu_pixel_clk: dpu-pixel-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <VENCODER_TIMING_CLK>;
- clock-output-names = "pxclk";
- };
-#endif /* !TC_DPU_USE_SCMI_CLK */
-};
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 7e759d81..d32ead4 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -111,18 +111,18 @@
#define ID_DFR0_PERFMON_PMUV3P5 U(6)
#define ID_DFR0_COPTRC_SHIFT U(12)
#define ID_DFR0_COPTRC_MASK U(0xf)
-#define ID_DFR0_COPTRC_SUPPORTED U(1)
+#define COPTRC_IMPLEMENTED U(1)
#define ID_DFR0_COPTRC_LENGTH U(4)
#define ID_DFR0_TRACEFILT_SHIFT U(28)
#define ID_DFR0_TRACEFILT_MASK U(0xf)
-#define ID_DFR0_TRACEFILT_SUPPORTED U(1)
+#define TRACEFILT_IMPLEMENTED U(1)
#define ID_DFR0_TRACEFILT_LENGTH U(4)
/* ID_DFR1_EL1 definitions */
#define ID_DFR1_MTPMU_SHIFT U(0)
#define ID_DFR1_MTPMU_MASK U(0xf)
-#define ID_DFR1_MTPMU_SUPPORTED U(1)
-#define ID_DFR1_MTPMU_DISABLED U(15)
+#define MTPMU_IMPLEMENTED U(1)
+#define MTPMU_NOT_IMPLEMENTED U(15)
/* ID_MMFR3 definitions */
#define ID_MMFR3_PAN_SHIFT U(16)
@@ -141,14 +141,13 @@
#define ID_PFR0_AMU_SHIFT U(20)
#define ID_PFR0_AMU_LENGTH U(4)
#define ID_PFR0_AMU_MASK U(0xf)
-#define ID_PFR0_AMU_NOT_SUPPORTED U(0x0)
#define ID_PFR0_AMU_V1 U(0x1)
#define ID_PFR0_AMU_V1P1 U(0x2)
#define ID_PFR0_DIT_SHIFT U(24)
#define ID_PFR0_DIT_LENGTH U(4)
#define ID_PFR0_DIT_MASK U(0xf)
-#define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
+#define DIT_IMPLEMENTED (U(1) << ID_PFR0_DIT_SHIFT)
/* ID_PFR1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@@ -166,7 +165,7 @@
/* ID_PFR2 definitions */
#define ID_PFR2_SSBS_SHIFT U(4)
#define ID_PFR2_SSBS_MASK U(0xf)
-#define SSBS_UNAVAILABLE U(0)
+#define SSBS_NOT_IMPLEMENTED U(0)
/* SCTLR definitions */
#define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
@@ -796,7 +795,21 @@
/*******************************************************************************
* Definitions for DynamicIQ Shared Unit registers
******************************************************************************/
-#define CLUSTERPWRDN p15, 0, c15, c3, 6
+#define CLUSTERPWRDN p15, 0, c15, c3, 6
+#define CLUSTERPMCR p15, 0, c15, c5, 0
+#define CLUSTERPMCNTENSET p15, 0, c15, c5, 1
+#define CLUSTERPMCCNTR p15, 0, c15, c6, 0
+#define CLUSTERPMOVSSET p15, 0, c15, c5, 3
+#define CLUSTERPMOVSCLR p15, 0, c15, c5, 4
+#define CLUSTERPMSELR p15, 0, c15, c5, 5
+#define CLUSTERPMXEVTYPER p15, 0, c15, c6, 1
+#define CLUSTERPMXEVCNTR p15, 0, c15, c6, 2
+
+/* CLUSTERPMCR register definitions */
+#define CLUSTERPMCR_E_BIT BIT(0)
+#define CLUSTERPMCR_N_SHIFT U(11)
+#define CLUSTERPMCR_N_MASK U(0x1f)
+
/* CLUSTERPWRDN register definitions */
#define DSU_CLUSTER_PWR_OFF 0
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index b52e4d0..8e39529 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -12,132 +12,112 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
-#define ISOLATE_FIELD(reg, feat) \
- ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK)))
+#define ISOLATE_FIELD(reg, feat, mask) \
+ ((unsigned int)(((reg) >> (feat)) & mask))
-static inline bool is_armv7_gentimer_present(void)
-{
- return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER) != 0U;
-}
-
-static inline bool is_armv8_2_ttcnp_present(void)
-{
- return ISOLATE_FIELD(read_id_mmfr4(), ID_MMFR4_CNP) != 0U;
-}
-
-static unsigned int read_feat_amu_id_field(void)
-{
- return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_AMU);
-}
-
-static inline bool is_feat_amu_supported(void)
-{
- if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_amu_id_field() >= ID_PFR0_AMU_V1;
+#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
+static inline bool is_ ## name ## _supported(void) \
+{ \
+ if ((guard) == FEAT_STATE_DISABLED) { \
+ return false; \
+ } \
+ if ((guard) == FEAT_STATE_ALWAYS) { \
+ return true; \
+ } \
+ return read_func(); \
}
-static inline bool is_feat_amuv1p1_supported(void)
-{
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_amu_id_field() >= ID_PFR0_AMU_V1P1;
+#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+static inline bool is_ ## name ## _present(void) \
+{ \
+ return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
+ ? true : false; \
}
-static inline unsigned int read_feat_trf_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_TRACEFILT);
-}
-
-static inline bool is_feat_trf_supported(void)
-{
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
+CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
- if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
- return read_feat_trf_id_field() != 0U;
-}
-
-static inline unsigned int read_feat_coptrc_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_COPTRC);
-}
+/*
+ * +----------------------------+
+ * | Features supported |
+ * +----------------------------+
+ * | GENTIMER |
+ * +----------------------------+
+ * | FEAT_TTCNP |
+ * +----------------------------+
+ * | FEAT_AMU |
+ * +----------------------------+
+ * | FEAT_AMUV1P1 |
+ * +----------------------------+
+ * | FEAT_TRF |
+ * +----------------------------+
+ * | FEAT_SYS_REG_TRACE |
+ * +----------------------------+
+ * | FEAT_DIT |
+ * +----------------------------+
+ * | FEAT_PAN |
+ * +----------------------------+
+ * | FEAT_SSBS |
+ * +----------------------------+
+ * | FEAT_PMUV3 |
+ * +----------------------------+
+ * | FEAT_MTPMU |
+ * +----------------------------+
+ */
-static inline bool is_feat_sys_reg_trace_supported(void)
+/* GENTIMER */
+static inline bool is_armv7_gentimer_present(void)
{
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- return read_feat_coptrc_id_field() != 0U;
+ return ISOLATE_FIELD(read_id_pfr1(), ID_PFR1_GENTIMER_SHIFT,
+ ID_PFR1_GENTIMER_MASK) != 0U;
}
-static inline unsigned int read_feat_dit_id_field(void)
-{
- return ISOLATE_FIELD(read_id_pfr0(), ID_PFR0_DIT);
-}
+/* FEAT_TTCNP: Translation table common not private */
+CREATE_FEATURE_PRESENT(feat_ttcnp, id_mmfr4, ID_MMFR4_CNP_SHIFT,
+ ID_MMFR4_CNP_MASK, 1U)
-static inline bool is_feat_dit_supported(void)
-{
- if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_AMU: Activity Monitors Extension */
+CREATE_FEATURE_FUNCS(feat_amu, id_pfr0, ID_PFR0_AMU_SHIFT,
+ ID_PFR0_AMU_MASK, ID_PFR0_AMU_V1, ENABLE_FEAT_AMU)
- if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_AMUV1P1: AMU Extension v1.1 */
+CREATE_FEATURE_FUNCS(feat_amuv1p1, id_pfr0, ID_PFR0_AMU_SHIFT,
+ ID_PFR0_AMU_MASK, ID_PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
- return read_feat_dit_id_field() != 0U;
-}
+/* FEAT_TRF: Tracefilter */
+CREATE_FEATURE_FUNCS(feat_trf, id_dfr0, ID_DFR0_TRACEFILT_SHIFT,
+ ID_DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
-static inline unsigned int read_feat_pan_id_field(void)
-{
- return ISOLATE_FIELD(read_id_mmfr3(), ID_MMFR3_PAN);
-}
+/* FEAT_SYS_REG_TRACE */
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_dfr0, ID_DFR0_COPTRC_SHIFT,
+ ID_DFR0_COPTRC_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
-static inline bool is_feat_pan_supported(void)
-{
- if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) {
- return false;
- }
+/* FEAT_DIT: Data independent timing */
+CREATE_FEATURE_FUNCS(feat_dit, id_pfr0, ID_PFR0_DIT_SHIFT,
+ ID_PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
- if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) {
- return true;
- }
+/* FEAT_PAN: Privileged access never */
+CREATE_FEATURE_FUNCS(feat_pan, id_mmfr3, ID_MMFR3_PAN_SHIFT,
+ ID_MMFR3_PAN_MASK, 1U, ENABLE_FEAT_PAN)
- return read_feat_pan_id_field() != 0U;
-}
+/* FEAT_SSBS: Speculative store bypass safe */
+CREATE_FEATURE_PRESENT(feat_ssbs, id_pfr2, ID_PFR2_SSBS_SHIFT,
+ ID_PFR2_SSBS_MASK, 1U)
-static inline bool is_feat_pan_present(void)
-{
- return read_feat_pan_id_field() != 0U;
-}
+/* FEAT_PMUV3 */
+CREATE_FEATURE_PRESENT(feat_pmuv3, id_dfr0, ID_DFR0_PERFMON_SHIFT,
+ ID_DFR0_PERFMON_MASK, 3U)
-static inline unsigned int is_feat_ssbs_present(void)
+/* FEAT_MTPMU */
+static inline bool is_feat_mtpmu_present(void)
{
- return ((read_id_pfr2() >> ID_PFR2_SSBS_SHIFT) &
- ID_PFR2_SSBS_MASK) != SSBS_UNAVAILABLE;
+ unsigned int mtpmu = ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU_SHIFT,
+ ID_DFR1_MTPMU_MASK);
+ return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
}
+CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
/*
* TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch
@@ -179,29 +159,4 @@
static inline bool is_feat_ebep_present(void) { return false; }
static inline bool is_feat_sebep_present(void) { return false; }
-static inline unsigned int read_feat_pmuv3_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_PERFMON);
-}
-
-static inline unsigned int read_feat_mtpmu_id_field(void)
-{
- return ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU);
-}
-
-static inline bool is_feat_mtpmu_supported(void)
-{
- if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- unsigned int mtpmu = read_feat_mtpmu_id_field();
-
- return mtpmu != 0U && mtpmu != ID_DFR1_MTPMU_DISABLED;
-}
-
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index 3244d3b..adc96ae 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
* Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -354,6 +354,14 @@
* DynamIQ Shared Unit power management
*/
DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN)
+DEFINE_COPROCR_RW_FUNCS(clusterpmcr, CLUSTERPMCR)
+DEFINE_COPROCR_RW_FUNCS(clusterpmcntenset, CLUSTERPMCNTENSET)
+DEFINE_COPROCR_RW_FUNCS(clusterpmccntr, CLUSTERPMCCNTR)
+DEFINE_COPROCR_RW_FUNCS(clusterpmovsset, CLUSTERPMOVSSET)
+DEFINE_COPROCR_RW_FUNCS(clusterpmovsclr, CLUSTERPMOVSCLR)
+DEFINE_COPROCR_RW_FUNCS(clusterpmselr, CLUSTERPMSELR)
+DEFINE_COPROCR_RW_FUNCS(clusterpmxevcntr, CLUSTERPMXEVCNTR)
+DEFINE_COPROCR_RW_FUNCS(clusterpmxevtyper, CLUSTERPMXEVTYPER)
/*
* RNDR is AArch64 only, so just provide a placeholder here to make the
diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S
index 3ba86e9..bccd2a7 100644
--- a/include/arch/aarch32/asm_macros.S
+++ b/include/arch/aarch32/asm_macros.S
@@ -241,4 +241,13 @@
cmp \temp, \bot
bhs div2
.endm
+
+ /*
+ * Helper macro to instruction adr <reg>, <symbol> where <symbol> is
+ * within the range +/- 4 GB.
+ */
+ .macro adr_l, dst, sym
+ adrp \dst, \sym
+ add \dst, \dst, :lo12:\sym
+ .endm
#endif /* ASM_MACROS_S */
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 697eb82..41eeabb 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -76,7 +76,7 @@
orr r0, r0, #(NSACR_RESET_VAL | NSACR_ENABLE_FP_ACCESS)
ldcopr r1, ID_DFR0
ubfx r1, r1, #ID_DFR0_COPTRC_SHIFT, #ID_DFR0_COPTRC_LENGTH
- cmp r1, #ID_DFR0_COPTRC_SUPPORTED
+ cmp r1, #COPTRC_IMPLEMENTED
bne 1f
orr r0, r0, #NSTRCDIS_BIT
1:
@@ -143,7 +143,7 @@
SDCR_SCCD_BIT) & ~SDCR_TTRF_BIT)
ldcopr r1, ID_DFR0
ubfx r1, r1, #ID_DFR0_TRACEFILT_SHIFT, #ID_DFR0_TRACEFILT_LENGTH
- cmp r1, #ID_DFR0_TRACEFILT_SUPPORTED
+ cmp r1, #TRACEFILT_IMPLEMENTED
bne 1f
orr r0, r0, #SDCR_TTRF_BIT
1:
@@ -182,7 +182,7 @@
*/
ldcopr r0, ID_PFR0
and r0, r0, #(ID_PFR0_DIT_MASK << ID_PFR0_DIT_SHIFT)
- cmp r0, #ID_PFR0_DIT_SUPPORTED
+ cmp r0, #DIT_IMPLEMENTED
bne 1f
mrs r0, cpsr
orr r0, r0, #CPSR_DIT_BIT
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 5508ebb..4eb54ed 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -179,7 +179,6 @@
#define ID_AA64PFR0_AMU_SHIFT U(44)
#define ID_AA64PFR0_AMU_MASK ULL(0xf)
-#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
#define ID_AA64PFR0_AMU_V1 ULL(0x1)
#define ID_AA64PFR0_AMU_V1P1 U(0x2)
@@ -191,8 +190,8 @@
#define ID_AA64PFR0_SVE_SHIFT U(32)
#define ID_AA64PFR0_SVE_MASK ULL(0xf)
-#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
#define ID_AA64PFR0_SVE_LENGTH U(4)
+#define SVE_IMPLEMENTED ULL(0x1)
#define ID_AA64PFR0_SEL2_SHIFT U(36)
#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
@@ -203,23 +202,21 @@
#define ID_AA64PFR0_DIT_SHIFT U(48)
#define ID_AA64PFR0_DIT_MASK ULL(0xf)
#define ID_AA64PFR0_DIT_LENGTH U(4)
-#define ID_AA64PFR0_DIT_SUPPORTED U(1)
+#define DIT_IMPLEMENTED ULL(1)
#define ID_AA64PFR0_CSV2_SHIFT U(56)
#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
#define ID_AA64PFR0_CSV2_LENGTH U(4)
-#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
-#define ID_AA64PFR0_CSV2_3_SUPPORTED ULL(0x3)
+#define CSV2_2_IMPLEMENTED ULL(0x2)
+#define CSV2_3_IMPLEMENTED ULL(0x3)
#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
-#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
-#define ID_AA64PFR0_FEAT_RME_V1 U(1)
+#define RME_NOT_IMPLEMENTED ULL(0)
#define ID_AA64PFR0_RAS_SHIFT U(28)
#define ID_AA64PFR0_RAS_MASK ULL(0xf)
-#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR0_RAS_LENGTH U(4)
/* Exception level handling */
@@ -230,12 +227,13 @@
/* ID_AA64DFR0_EL1.TraceVer definitions */
#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
-#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
+
#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
-#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
+#define TRACEFILT_IMPLEMENTED ULL(1)
+
#define ID_AA64DFR0_PMUVER_LENGTH U(4)
#define ID_AA64DFR0_PMUVER_SHIFT U(8)
#define ID_AA64DFR0_PMUVER_MASK U(0xf)
@@ -251,24 +249,24 @@
/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
#define ID_AA64DFR0_PMS_SHIFT U(32)
#define ID_AA64DFR0_PMS_MASK ULL(0xf)
-#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
-#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
+#define SPE_IMPLEMENTED ULL(0x1)
+#define SPE_NOT_IMPLEMENTED ULL(0x0)
/* ID_AA64DFR0_EL1.TraceBuffer definitions */
#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
-#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
+#define TRACEBUFFER_IMPLEMENTED ULL(1)
/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
#define ID_AA64DFR0_MTPMU_SHIFT U(48)
#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
-#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
-#define ID_AA64DFR0_MTPMU_DISABLED ULL(15)
+#define MTPMU_IMPLEMENTED ULL(1)
+#define MTPMU_NOT_IMPLEMENTED ULL(15)
/* ID_AA64DFR0_EL1.BRBE definitions */
#define ID_AA64DFR0_BRBE_SHIFT U(52)
#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
-#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
+#define BRBE_IMPLEMENTED ULL(1)
/* ID_AA64DFR1_EL1 definitions */
#define ID_AA64DFR1_EBEP_SHIFT U(48)
@@ -294,8 +292,8 @@
#define ID_AA64ISAR1_SB_SHIFT U(36)
#define ID_AA64ISAR1_SB_MASK ULL(0xf)
-#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
-#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
+#define SB_IMPLEMENTED ULL(0x1)
+#define SB_NOT_IMPLEMENTED ULL(0x0)
/* ID_AA64ISAR2_EL1 definitions */
#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
@@ -323,52 +321,41 @@
#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
+#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
+#define ECV_IMPLEMENTED ULL(0x1)
#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
+#define FGT_IMPLEMENTED ULL(0x1)
+#define FGT_NOT_IMPLEMENTED ULL(0x0)
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
-#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2)
+#define TGRAN16_IMPLEMENTED ULL(0x1)
/* ID_AA64MMFR1_EL1 definitions */
#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
-#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
+#define TWED_IMPLEMENTED ULL(0x1)
#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
-#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
-#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
+#define PAN_IMPLEMENTED ULL(0x1)
+#define PAN2_IMPLEMENTED ULL(0x2)
+#define PAN3_IMPLEMENTED ULL(0x3)
#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
-#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
+#define HCX_IMPLEMENTED ULL(0x1)
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -388,9 +375,7 @@
#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
-#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
-#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
+#define NV2_IMPLEMENTED ULL(0x2)
/* ID_AA64MMFR3_EL1 definitions */
#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
@@ -414,11 +399,11 @@
#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
-#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
+#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
-#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
+#define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */
#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
@@ -434,8 +419,7 @@
#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
#define GCS_IMPLEMENTED ULL(1)
-#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
-#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
+#define RNG_TRAP_IMPLEMENTED ULL(0x1)
/* ID_AA64PFR2_EL1 definitions */
#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0)
@@ -468,9 +452,9 @@
#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
-#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
-#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
-#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
+#define SME_IMPLEMENTED ULL(0x1)
+#define SME2_IMPLEMENTED ULL(0x2)
+#define SME_NOT_IMPLEMENTED ULL(0x0)
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@@ -1102,11 +1086,11 @@
/* ID_AA64SMFR0_EL1 definitions */
#define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63)
#define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1)
-#define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1)
+#define SME_FA64_IMPLEMENTED U(0x1)
#define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55)
#define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf)
-#define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0)
-#define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1)
+#define SME_INST_IMPLEMENTED ULL(0x0)
+#define SME2_INST_IMPLEMENTED ULL(0x1)
/* SMCR_ELx definitions */
#define SMCR_ELX_LEN_SHIFT U(0)
@@ -1498,4 +1482,17 @@
/* alternative system register encoding for the "sb" speculation barrier */
#define SYSREG_SB S0_3_C3_C0_7
+#define CLUSTERPMCR_EL1 S3_0_C15_C5_0
+#define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1
+#define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0
+#define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3
+#define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4
+#define CLUSTERPMSELR_EL1 S3_0_C15_C5_5
+#define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1
+#define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2
+
+#define CLUSTERPMCR_E_BIT BIT(0)
+#define CLUSTERPMCR_N_SHIFT U(11)
+#define CLUSTERPMCR_N_MASK U(0x1f)
+
#endif /* ARCH_H */
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 7582fc6..ddc1c80 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -12,27 +12,125 @@
#include <arch_helpers.h>
#include <common/feat_detect.h>
-#define ISOLATE_FIELD(reg, feat) \
- ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
+#define ISOLATE_FIELD(reg, feat, mask) \
+ ((unsigned int)(((reg) >> (feat)) & mask))
-#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
-static inline bool is_ ## name ## _supported(void) \
-{ \
- if ((guard) == FEAT_STATE_DISABLED) { \
- return false; \
- } \
- if ((guard) == FEAT_STATE_ALWAYS) { \
- return true; \
- } \
- return read_func() >= (idvalue); \
+#define CREATE_FEATURE_SUPPORTED(name, read_func, guard) \
+static inline bool is_ ## name ## _supported(void) \
+{ \
+ if ((guard) == FEAT_STATE_DISABLED) { \
+ return false; \
+ } \
+ if ((guard) == FEAT_STATE_ALWAYS) { \
+ return true; \
+ } \
+ return read_func(); \
}
-#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
-static unsigned int read_ ## name ## _id_field(void) \
-{ \
- return ISOLATE_FIELD(read_ ## idreg(), idfield); \
-} \
-CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
+#define CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+static inline bool is_ ## name ## _present(void) \
+{ \
+ return (ISOLATE_FIELD(read_ ## idreg(), idfield, mask) >= idval) \
+ ? true : false; \
+}
+
+#define CREATE_FEATURE_FUNCS(name, idreg, idfield, mask, idval, guard) \
+CREATE_FEATURE_PRESENT(name, idreg, idfield, mask, idval) \
+CREATE_FEATURE_SUPPORTED(name, is_ ## name ## _present, guard)
+
+
+/* +----------------------------+
+ * | Features supported |
+ * +----------------------------+
+ * | GENTIMER |
+ * +----------------------------+
+ * | FEAT_PAN |
+ * +----------------------------+
+ * | FEAT_VHE |
+ * +----------------------------+
+ * | FEAT_TTCNP |
+ * +----------------------------+
+ * | FEAT_UAO |
+ * +----------------------------+
+ * | FEAT_PACQARMA3 |
+ * +----------------------------+
+ * | FEAT_PAUTH |
+ * +----------------------------+
+ * | FEAT_TTST |
+ * +----------------------------+
+ * | FEAT_BTI |
+ * +----------------------------+
+ * | FEAT_MTE2 |
+ * +----------------------------+
+ * | FEAT_SSBS |
+ * +----------------------------+
+ * | FEAT_NMI |
+ * +----------------------------+
+ * | FEAT_GCS |
+ * +----------------------------+
+ * | FEAT_EBEP |
+ * +----------------------------+
+ * | FEAT_SEBEP |
+ * +----------------------------+
+ * | FEAT_SEL2 |
+ * +----------------------------+
+ * | FEAT_TWED |
+ * +----------------------------+
+ * | FEAT_FGT |
+ * +----------------------------+
+ * | FEAT_EC/ECV2 |
+ * +----------------------------+
+ * | FEAT_RNG |
+ * +----------------------------+
+ * | FEAT_TCR2 |
+ * +----------------------------+
+ * | FEAT_S2POE |
+ * +----------------------------+
+ * | FEAT_S1POE |
+ * +----------------------------+
+ * | FEAT_S2PIE |
+ * +----------------------------+
+ * | FEAT_S1PIE |
+ * +----------------------------+
+ * | FEAT_AMU/AMUV1P1 |
+ * +----------------------------+
+ * | FEAT_MPAM |
+ * +----------------------------+
+ * | FEAT_HCX |
+ * +----------------------------+
+ * | FEAT_RNG_TRAP |
+ * +----------------------------+
+ * | FEAT_RME |
+ * +----------------------------+
+ * | FEAT_SB |
+ * +----------------------------+
+ * | FEAT_CSV2/CSV3 |
+ * +----------------------------+
+ * | FEAT_SPE |
+ * +----------------------------+
+ * | FEAT_SVE |
+ * +----------------------------+
+ * | FEAT_RAS |
+ * +----------------------------+
+ * | FEAT_DIT |
+ * +----------------------------+
+ * | FEAT_SYS_REG_TRACE |
+ * +----------------------------+
+ * | FEAT_TRF |
+ * +----------------------------+
+ * | FEAT_NV/NV2 |
+ * +----------------------------+
+ * | FEAT_BRBE |
+ * +----------------------------+
+ * | FEAT_TRBE |
+ * +----------------------------+
+ * | FEAT_SME/SME2 |
+ * +----------------------------+
+ * | FEAT_PMUV3 |
+ * +----------------------------+
+ * | FEAT_MTPMU |
+ * +----------------------------+
+ */
static inline bool is_armv7_gentimer_present(void)
{
@@ -40,38 +138,28 @@
return true;
}
+/* FEAT_PAN: Privileged access never */
CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
- ENABLE_FEAT_PAN)
-static inline bool is_feat_pan_present(void)
-{
- return read_feat_pan_id_field() != 0U;
-}
+ ID_AA64MMFR1_EL1_PAN_MASK, 1U, ENABLE_FEAT_PAN)
+/* FEAT_VHE: Virtualization Host Extensions */
CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
- ENABLE_FEAT_VHE)
+ ID_AA64MMFR1_EL1_VHE_MASK, 1U, ENABLE_FEAT_VHE)
-static inline bool is_armv8_2_ttcnp_present(void)
-{
- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
- ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
-}
+/* FEAT_TTCNP: Translation table common not private */
+CREATE_FEATURE_PRESENT(feat_ttcnp, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_CNP_SHIFT,
+ ID_AA64MMFR2_EL1_CNP_MASK, 1U)
-static inline bool is_feat_uao_present(void)
-{
- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_UAO_SHIFT) &
- ID_AA64MMFR2_EL1_UAO_MASK) != 0U;
-}
-
-static inline bool is_feat_pacqarma3_present(void)
-{
- uint64_t mask_id_aa64isar2 =
- (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
- (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
+/* FEAT_UAO: User access override */
+CREATE_FEATURE_PRESENT(feat_uao, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_UAO_SHIFT,
+ ID_AA64MMFR2_EL1_UAO_MASK, 1U)
- /* If any of the fields is not zero, QARMA3 algorithm is present */
- return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
-}
+/* If any of the fields is not zero, QARMA3 algorithm is present */
+CREATE_FEATURE_PRESENT(feat_pacqarma3, id_aa64isar2_el1, 0,
+ ((ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
+ (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT)), 1U)
+/* PAUTH */
static inline bool is_armv8_3_pauth_present(void)
{
uint64_t mask_id_aa64isar1 =
@@ -88,89 +176,81 @@
is_feat_pacqarma3_present());
}
-static inline bool is_armv8_4_ttst_present(void)
-{
- return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
- ID_AA64MMFR2_EL1_ST_MASK) == 1U;
-}
+/* FEAT_TTST: Small translation tables */
+CREATE_FEATURE_PRESENT(feat_ttst, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_ST_SHIFT,
+ ID_AA64MMFR2_EL1_ST_MASK, 1U)
-static inline bool is_armv8_5_bti_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
- ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
-}
-
-static inline unsigned int get_armv8_5_mte_support(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
- ID_AA64PFR1_EL1_MTE_MASK);
-}
-static inline unsigned int is_feat_mte2_present(void)
-{
- return get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX;
-}
+/* FEAT_BTI: Branch target identification */
+CREATE_FEATURE_PRESENT(feat_bti, id_aa64pfr1_el1, ID_AA64PFR1_EL1_BT_SHIFT,
+ ID_AA64PFR1_EL1_BT_MASK, BTI_IMPLEMENTED)
-static inline bool is_feat_ssbs_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
- ID_AA64PFR1_EL1_SSBS_MASK) != SSBS_UNAVAILABLE;
-}
+/* FEAT_MTE2: Memory tagging extension */
+CREATE_FEATURE_FUNCS(feat_mte2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_MTE_SHIFT,
+ ID_AA64PFR1_EL1_MTE_MASK, MTE_IMPLEMENTED_ELX, ENABLE_FEAT_MTE2)
-static inline bool is_feat_nmi_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_NMI_SHIFT) &
- ID_AA64PFR1_EL1_NMI_MASK) == NMI_IMPLEMENTED;
-}
+/* FEAT_SSBS: Speculative store bypass safe */
+CREATE_FEATURE_PRESENT(feat_ssbs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SSBS_SHIFT,
+ ID_AA64PFR1_EL1_SSBS_MASK, 1U)
-static inline bool is_feat_gcs_present(void)
-{
- return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_GCS_SHIFT) &
- ID_AA64PFR1_EL1_GCS_MASK) == GCS_IMPLEMENTED;
-}
+/* FEAT_NMI: Non-maskable interrupts */
+CREATE_FEATURE_PRESENT(feat_nmi, id_aa64pfr1_el1, ID_AA64PFR1_EL1_NMI_SHIFT,
+ ID_AA64PFR1_EL1_NMI_MASK, NMI_IMPLEMENTED)
-static inline bool is_feat_ebep_present(void)
-{
- return ((read_id_aa64dfr1_el1() >> ID_AA64DFR1_EBEP_SHIFT) &
- ID_AA64DFR1_EBEP_MASK) == EBEP_IMPLEMENTED;
-}
+/* FEAT_EBEP */
+CREATE_FEATURE_PRESENT(feat_ebep, id_aa64dfr1_el1, ID_AA64DFR1_EBEP_SHIFT,
+ ID_AA64DFR1_EBEP_MASK, EBEP_IMPLEMENTED)
-static inline bool is_feat_sebep_present(void)
-{
- return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_SEBEP_SHIFT) &
- ID_AA64DFR0_SEBEP_MASK) == SEBEP_IMPLEMENTED;
-}
+/* FEAT_SEBEP */
+CREATE_FEATURE_PRESENT(feat_sebep, id_aa64dfr0_el1, ID_AA64DFR0_SEBEP_SHIFT,
+ ID_AA64DFR0_SEBEP_MASK, SEBEP_IMPLEMENTED)
-CREATE_FEATURE_FUNCS_VER(feat_mte2, get_armv8_5_mte_support, MTE_IMPLEMENTED_ELX,
- ENABLE_FEAT_MTE2)
+/* FEAT_SEL2: Secure EL2 */
CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
- ENABLE_FEAT_SEL2)
+ ID_AA64PFR0_SEL2_MASK, 1U, ENABLE_FEAT_SEL2)
+
+/* FEAT_TWED: Delayed trapping of WFE */
CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
- ENABLE_FEAT_TWED)
+ ID_AA64MMFR1_EL1_TWED_MASK, 1U, ENABLE_FEAT_TWED)
+
+/* FEAT_FGT: Fine-grained traps */
CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
- ENABLE_FEAT_FGT)
+ ID_AA64MMFR0_EL1_FGT_MASK, 1U, ENABLE_FEAT_FGT)
+
+/* FEAT_ECV: Enhanced Counter Virtualization */
CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
- ENABLE_FEAT_ECV)
-CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
- ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
+ ID_AA64MMFR0_EL1_ECV_MASK, 1U, ENABLE_FEAT_ECV)
+CREATE_FEATURE_FUNCS(feat_ecv_v2, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
+ ID_AA64MMFR0_EL1_ECV_MASK, ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
+/* FEAT_RNG: Random number generator */
CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
- ENABLE_FEAT_RNG)
+ ID_AA64ISAR0_RNDR_MASK, 1U, ENABLE_FEAT_RNG)
+
+/* FEAT_TCR2: Support TCR2_ELx regs */
CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
- ENABLE_FEAT_TCR2)
+ ID_AA64MMFR3_EL1_TCRX_MASK, 1U, ENABLE_FEAT_TCR2)
+/* FEAT_S2POE */
CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
- ENABLE_FEAT_S2POE)
+ ID_AA64MMFR3_EL1_S2POE_MASK, 1U, ENABLE_FEAT_S2POE)
+
+/* FEAT_S1POE */
CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
- ENABLE_FEAT_S1POE)
+ ID_AA64MMFR3_EL1_S1POE_MASK, 1U, ENABLE_FEAT_S1POE)
+
static inline bool is_feat_sxpoe_supported(void)
{
return is_feat_s1poe_supported() || is_feat_s2poe_supported();
}
+/* FEAT_S2PIE */
CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
- ENABLE_FEAT_S2PIE)
+ ID_AA64MMFR3_EL1_S2PIE_MASK, 1U, ENABLE_FEAT_S2PIE)
+
+/* FEAT_S1PIE */
CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
- ENABLE_FEAT_S1PIE)
+ ID_AA64MMFR3_EL1_S1PIE_MASK, 1U, ENABLE_FEAT_S1PIE)
+
static inline bool is_feat_sxpie_supported(void)
{
return is_feat_s1pie_supported() || is_feat_s2pie_supported();
@@ -178,13 +258,15 @@
/* FEAT_GCS: Guarded Control Stack */
CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
- ENABLE_FEAT_GCS)
+ ID_AA64PFR1_EL1_GCS_MASK, 1U, ENABLE_FEAT_GCS)
/* FEAT_AMU: Activity Monitors Extension */
CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
- ENABLE_FEAT_AMU)
-CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
- ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
+ ID_AA64PFR0_AMU_MASK, 1U, ENABLE_FEAT_AMU)
+
+/* FEAT_AMUV1P1: AMU Extension v1.1 */
+CREATE_FEATURE_FUNCS(feat_amuv1p1, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
+ ID_AA64PFR0_AMU_MASK, ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
/*
* Return MPAM version:
@@ -195,46 +277,32 @@
* 0x11: v1.1 Armv8.4 or later
*
*/
-static inline unsigned int read_feat_mpam_version(void)
+static inline bool is_feat_mpam_present(void)
{
- return (unsigned int)((((read_id_aa64pfr0_el1() >>
+ unsigned int ret = (unsigned int)((((read_id_aa64pfr0_el1() >>
ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
- ((read_id_aa64pfr1_el1() >>
- ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
+ ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_MPAM_FRAC_SHIFT)
+ & ID_AA64PFR1_MPAM_FRAC_MASK));
+ return ret;
}
-CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
- ENABLE_FEAT_MPAM)
+CREATE_FEATURE_SUPPORTED(feat_mpam, is_feat_mpam_present, ENABLE_FEAT_MPAM)
/* FEAT_HCX: Extended Hypervisor Configuration Register */
CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
- ENABLE_FEAT_HCX)
+ ID_AA64MMFR1_EL1_HCX_MASK, 1U, ENABLE_FEAT_HCX)
-static inline bool is_feat_rng_trap_present(void)
-{
- return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
- ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
- == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED);
-}
+/* FEAT_RNG_TRAP: Trapping support */
+CREATE_FEATURE_PRESENT(feat_rng_trap, id_aa64pfr1_el1, ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
+ ID_AA64PFR1_EL1_RNDR_TRAP_MASK, RNG_TRAP_IMPLEMENTED)
-static inline unsigned int get_armv9_2_feat_rme_support(void)
-{
- /*
- * Return the RME version, zero if not supported. This function can be
- * used as both an integer value for the RME version or compared to zero
- * to detect RME presence.
- */
- return (unsigned int)(read_id_aa64pfr0_el1() >>
- ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
-}
+/* Return the RME version, zero if not supported. */
+CREATE_FEATURE_FUNCS(feat_rme, id_aa64pfr0_el1, ID_AA64PFR0_FEAT_RME_SHIFT,
+ ID_AA64PFR0_FEAT_RME_MASK, 1U, ENABLE_RME)
-/*********************************************************************************
- * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
- ********************************************************************************/
-static inline unsigned int read_feat_sb_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
-}
+/* FEAT_SB: Speculation barrier instruction */
+CREATE_FEATURE_PRESENT(feat_sb, id_aa64isar1_el1, ID_AA64ISAR1_SB_SHIFT,
+ ID_AA64ISAR1_SB_MASK, 1U)
/*
* FEAT_CSV2: Cache Speculation Variant 2. This checks bit fields[56-59]
@@ -248,109 +316,94 @@
* implemented.
* 0b0011 - Feature FEAT_CSV2_3 is implemented.
*/
-static inline unsigned int read_feat_csv2_id_field(void)
-{
- return (unsigned int)(read_id_aa64pfr0_el1() >>
- ID_AA64PFR0_CSV2_SHIFT) & ID_AA64PFR0_CSV2_MASK;
-}
-CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
- ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
-CREATE_FEATURE_FUNCS_VER(feat_csv2_3, read_feat_csv2_id_field,
- ID_AA64PFR0_CSV2_3_SUPPORTED, ENABLE_FEAT_CSV2_3)
+CREATE_FEATURE_FUNCS(feat_csv2_2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
+ ID_AA64PFR0_CSV2_MASK, CSV2_2_IMPLEMENTED, ENABLE_FEAT_CSV2_2)
+CREATE_FEATURE_FUNCS(feat_csv2_3, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT,
+ ID_AA64PFR0_CSV2_MASK, CSV2_3_IMPLEMENTED, ENABLE_FEAT_CSV2_3)
/* FEAT_SPE: Statistical Profiling Extension */
CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
- ENABLE_SPE_FOR_NS)
+ ID_AA64DFR0_PMS_MASK, 1U, ENABLE_SPE_FOR_NS)
/* FEAT_SVE: Scalable Vector Extension */
CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
- ENABLE_SVE_FOR_NS)
+ ID_AA64PFR0_SVE_MASK, 1U, ENABLE_SVE_FOR_NS)
/* FEAT_RAS: Reliability, Accessibility, Serviceability */
-CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
- ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
+CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, ID_AA64PFR0_RAS_SHIFT,
+ ID_AA64PFR0_RAS_MASK, 1U, ENABLE_FEAT_RAS)
/* FEAT_DIT: Data Independent Timing instructions */
-CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
- ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
+CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, ID_AA64PFR0_DIT_SHIFT,
+ ID_AA64PFR0_DIT_MASK, 1U, ENABLE_FEAT_DIT)
-CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
- ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
+/* FEAT_SYS_REG_TRACE */
+CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, ID_AA64DFR0_TRACEVER_SHIFT,
+ ID_AA64DFR0_TRACEVER_MASK, 1U, ENABLE_SYS_REG_TRACE_FOR_NS)
/* FEAT_TRF: TraceFilter */
CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
- ENABLE_TRF_FOR_NS)
+ ID_AA64DFR0_TRACEFILT_MASK, 1U, ENABLE_TRF_FOR_NS)
/* FEAT_NV2: Enhanced Nested Virtualization */
-CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
-CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
- ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
+CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
+ ID_AA64MMFR2_EL1_NV_MASK, 1U, 0U)
+CREATE_FEATURE_FUNCS(feat_nv2, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT,
+ ID_AA64MMFR2_EL1_NV_MASK, NV2_IMPLEMENTED, CTX_INCLUDE_NEVE_REGS)
/* FEAT_BRBE: Branch Record Buffer Extension */
CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
- ENABLE_BRBE_FOR_NS)
+ ID_AA64DFR0_BRBE_MASK, 1U, ENABLE_BRBE_FOR_NS)
/* FEAT_TRBE: Trace Buffer Extension */
CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
- ENABLE_TRBE_FOR_NS)
+ ID_AA64DFR0_TRACEBUFFER_MASK, 1U, ENABLE_TRBE_FOR_NS)
-static inline unsigned int read_feat_sme_fa64_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
- ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
-}
+/* FEAT_SME_FA64: Full A64 Instruction support in streaming SVE mode */
+CREATE_FEATURE_PRESENT(feat_sme_fa64, id_aa64smfr0_el1, ID_AA64SMFR0_EL1_SME_FA64_SHIFT,
+ ID_AA64SMFR0_EL1_SME_FA64_MASK, 1U)
+
/* FEAT_SMEx: Scalar Matrix Extension */
CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
- ENABLE_SME_FOR_NS)
-CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
- ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
+ ID_AA64PFR1_EL1_SME_MASK, 1U, ENABLE_SME_FOR_NS)
+
+CREATE_FEATURE_FUNCS(feat_sme2, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
+ ID_AA64PFR1_EL1_SME_MASK, SME2_IMPLEMENTED, ENABLE_SME2_FOR_NS)
/*******************************************************************************
* Function to get hardware granularity support
******************************************************************************/
-static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
+static inline bool is_feat_tgran4K_present(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
+ unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN4_SHIFT, ID_REG_FIELD_MASK);
+ return (tgranx < 8U);
}
-static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
-}
+CREATE_FEATURE_PRESENT(feat_tgran16K, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
+ ID_AA64MMFR0_EL1_TGRAN16_MASK, TGRAN16_IMPLEMENTED)
-static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
+static inline bool is_feat_tgran64K_present(void)
{
- return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
- ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
+ unsigned int tgranx = ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
+ ID_AA64MMFR0_EL1_TGRAN64_SHIFT, ID_REG_FIELD_MASK);
+ return (tgranx < 8U);
}
-static inline unsigned int read_feat_pmuv3_id_field(void)
-{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
-}
+/* FEAT_PMUV3 */
+CREATE_FEATURE_PRESENT(feat_pmuv3, id_aa64dfr0_el1, ID_AA64DFR0_PMUVER_SHIFT,
+ ID_AA64DFR0_PMUVER_MASK, 1U)
-static inline unsigned int read_feat_mtpmu_id_field(void)
+/* FEAT_MTPMU */
+static inline bool is_feat_mtpmu_present(void)
{
- return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
+ unsigned int mtpmu = ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
+ ID_AA64DFR0_MTPMU_MASK);
+ return (mtpmu != 0U) && (mtpmu != MTPMU_NOT_IMPLEMENTED);
}
-static inline bool is_feat_mtpmu_supported(void)
-{
- if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
- return false;
- }
-
- if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
- return true;
- }
-
- unsigned int mtpmu = read_feat_mtpmu_id_field();
-
- return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED);
-}
+CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
#endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 57dbc06..1e2f84b 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -663,8 +663,16 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
-/* DynamIQ Shared Unit power management */
+/* DynamIQ Control registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcr_el1, CLUSTERPMCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcntenset_el1, CLUSTERPMCNTENSET_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmccntr_el1, CLUSTERPMCCNTR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsset_el1, CLUSTERPMOVSSET_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsclr_el1, CLUSTERPMOVSCLR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmselr_el1, CLUSTERPMSELR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevcntr_el1, CLUSTERPMXEVCNTR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevtyper_el1, CLUSTERPMXEVTYPER_EL1)
/* CPU Power/Performance Management registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3)
@@ -799,15 +807,6 @@
TLBIRPALOS(addr, TLBI_SZ_512M);
}
-/*
- * Invalidate TLBs of GPT entries by Physical address, last level.
- *
- * @pa: the starting address for the range
- * of invalidation
- * @size: size of the range of invalidation
- */
-void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
-
/* Previously defined accessor functions with incomplete register names */
#define read_current_el() read_CurrentEl()
@@ -827,8 +826,32 @@
#define read_cpacr() read_cpacr_el1()
#define write_cpacr(_v) write_cpacr_el1(_v)
+#define read_clusterpwrdn() read_clusterpwrdn_el1()
+#define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
+
+#define read_clusterpmcr() read_clusterpmcr_el1()
+#define write_clusterpmcr(_v) write_clusterpmcr_el1(_v)
+
+#define read_clusterpmcntenset() read_clusterpmcntenset_el1()
+#define write_clusterpmcntenset(_v) write_clusterpmcntenset_el1(_v)
+
+#define read_clusterpmccntr() read_clusterpmccntr_el1()
+#define write_clusterpmccntr(_v) write_clusterpmccntr_el1(_v)
+
+#define read_clusterpmovsset() read_clusterpmovsset_el1()
+#define write_clusterpmovsset(_v) write_clusterpmovsset_el1(_v)
+
+#define read_clusterpmovsclr() read_clusterpmovsclr_el1()
+#define write_clusterpmovsclr(_v) write_clusterpmovsclr_el1(_v)
+
+#define read_clusterpmselr() read_clusterpmselr_el1()
+#define write_clusterpmselr(_v) write_clusterpmselr_el1(_v)
+
+#define read_clusterpmxevcntr() read_clusterpmxevcntr_el1()
+#define write_clusterpmxevcntr(_v) write_clusterpmxevcntr_el1(_v)
+
-#define read_clusterpwrdn() read_clusterpwrdn_el1()
-#define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
+#define read_clusterpmxevtyper() read_clusterpmxevtyper_el1()
+#define write_clusterpmxevtyper(_v) write_clusterpmxevtyper_el1(_v)
#if ERRATA_SPECULATIVE_AT
/*
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index d09ad0f..ec2acd5 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -317,4 +317,12 @@
#endif
.endm
+ /*
+ * Helper macro to instruction adr <reg>, <symbol> where <symbol> is
+ * within the range +/- 4 GB.
+ */
+ .macro adr_l, dst, sym
+ adrp \dst, \sym
+ add \dst, \dst, :lo12:\sym
+ .endm
#endif /* ASM_MACROS_S */
diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S
index 9609c0d..9f82399 100644
--- a/include/arch/aarch64/el2_common_macros.S
+++ b/include/arch/aarch64/el2_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -157,7 +157,7 @@
*/
mrs x0, id_aa64pfr0_el1
ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
- cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
+ cmp x0, #DIT_IMPLEMENTED
bne 1f
mov x0, #DIT_BIT
msr DIT, x0
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 26c7578..1a3e9b6 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -133,7 +133,7 @@
#if ENABLE_FEAT_DIT > 1
cbz x0, 1f
#else
- cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
+ cmp x0, #DIT_IMPLEMENTED
ASM_ASSERT(eq)
#endif
diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h
index 7cd7e72..3ab88de 100644
--- a/include/bl1/bl1.h
+++ b/include/bl1/bl1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -94,9 +94,5 @@
(FWU_SMC_FID_END - FWU_SMC_FID_START + 1),
assert_FWU_NUM_SMC_CALLS_mismatch);
-/* Utility functions */
-void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout);
-
#endif /* __ASSEMBLER__ */
#endif /* BL1_H */
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 4c8a17c..647ae85 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -180,8 +180,6 @@
void dyn_disable_auth(void);
#endif
-extern const char build_message[];
-extern const char version_string[];
const char *get_version(void);
void print_entry_point_info(const entry_point_info_t *ep_info);
diff --git a/include/common/build_message.h b/include/common/build_message.h
new file mode 100644
index 0000000..b7c2f72
--- /dev/null
+++ b/include/common/build_message.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BUILD_MESSAGE_H
+#define BUILD_MESSAGE_H
+
+static const char build_message[] = "Built : " BUILD_MESSAGE_TIMESTAMP;
+static const char build_version_string[] = BUILD_MESSAGE_VERSION_STRING;
+static const char build_version[] = BUILD_MESSAGE_VERSION;
+
+#endif /* BUILD_MESSAGE_H */
diff --git a/include/common/debug.h b/include/common/debug.h
index 5ea541d..0ddb400 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -91,6 +91,12 @@
# define VERBOSE(...) no_tf_log(LOG_MARKER_VERBOSE __VA_ARGS__)
#endif
+#if EARLY_CONSOLE
+#define EARLY_ERROR(...) ERROR(__VA_ARGS__)
+#else /* !EARLY_CONSOLE */
+#define EARLY_ERROR(...) no_tf_log(LOG_MARKER_ERROR __VA_ARGS__)
+#endif /* EARLY_CONSOLE */
+
const char *get_el_str(unsigned int el);
#if ENABLE_BACKTRACE
diff --git a/include/drivers/arm/css/dsu.h b/include/drivers/arm/css/dsu.h
new file mode 100644
index 0000000..4d7822b
--- /dev/null
+++ b/include/drivers/arm/css/dsu.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DSU_H
+#define DSU_H
+
+#define PMCR_N_MAX 0x1f
+
+#define save_pmu_reg(state, reg) state->reg = read_##reg()
+
+#define restore_pmu_reg(context, reg) write_##reg(context->reg)
+
+typedef struct cluster_pmu_state{
+ uint64_t clusterpmcr;
+ uint64_t clusterpmcntenset;
+ uint64_t clusterpmccntr;
+ uint64_t clusterpmovsset;
+ uint64_t clusterpmselr;
+ uint64_t clusterpmsevtyper;
+ uint64_t counter_val[PMCR_N_MAX];
+ uint64_t counter_type[PMCR_N_MAX];
+} cluster_pmu_state_t;
+
+static inline unsigned int read_cluster_eventctr_num(void)
+{
+ return ((read_clusterpmcr() >> CLUSTERPMCR_N_SHIFT) &
+ CLUSTERPMCR_N_MASK);
+}
+
+
+void save_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
+
+void restore_dsu_pmu_state(cluster_pmu_state_t *cluster_pmu_context);
+
+void cluster_on_dsu_pmu_context_restore(void);
+
+void cluster_off_dsu_pmu_context_save(void);
+
+#endif /* DSU_H */
diff --git a/include/drivers/arm/rse_comms.h b/include/drivers/arm/rse_comms.h
new file mode 100644
index 0000000..e4169a5
--- /dev/null
+++ b/include/drivers/arm/rse_comms.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef RSE_COMMS_H
+#define RSE_COMMS_H
+
+#include <stdint.h>
+
+int rse_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base);
+
+#endif /* RSE_COMMS_H */
diff --git a/include/drivers/arm/rss_comms.h b/include/drivers/arm/rss_comms.h
deleted file mode 100644
index b96c79f..0000000
--- a/include/drivers/arm/rss_comms.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#ifndef RSS_COMMS_H
-#define RSS_COMMS_H
-
-#include <stdint.h>
-
-int rss_comms_init(uintptr_t mhu_sender_base, uintptr_t mhu_receiver_base);
-
-#endif /* RSS_COMMS_H */
diff --git a/include/drivers/auth/mbedtls/mbedtls_config-3.h b/include/drivers/auth/mbedtls/mbedtls_config-3.h
index 923fc54..37a9288 100644
--- a/include/drivers/auth/mbedtls/mbedtls_config-3.h
+++ b/include/drivers/auth/mbedtls/mbedtls_config-3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -128,7 +128,6 @@
#ifndef __ASSEMBLER__
/* System headers required to build mbed TLS with the current configuration */
#include <stdlib.h>
-#include <mbedtls/check_config.h>
#endif
/*
diff --git a/include/drivers/auth/mbedtls/psa_mbedtls_config.h b/include/drivers/auth/mbedtls/psa_mbedtls_config.h
index ad825f0..1001d89 100644
--- a/include/drivers/auth/mbedtls/psa_mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/psa_mbedtls_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Ltd. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include "mbedtls_config-3.h"
#define MBEDTLS_PSA_CRYPTO_C
+#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS
/*
* Using PSA crypto API requires an RNG right now. If we don't define the macro
diff --git a/include/drivers/measured_boot/rss/dice_prot_env.h b/include/drivers/measured_boot/rse/dice_prot_env.h
similarity index 100%
rename from include/drivers/measured_boot/rss/dice_prot_env.h
rename to include/drivers/measured_boot/rse/dice_prot_env.h
diff --git a/include/drivers/measured_boot/rss/rss_measured_boot.h b/include/drivers/measured_boot/rse/rse_measured_boot.h
similarity index 65%
rename from include/drivers/measured_boot/rss/rss_measured_boot.h
rename to include/drivers/measured_boot/rse/rse_measured_boot.h
index 38f7d4e..2f605d7 100644
--- a/include/drivers/measured_boot/rss/rss_measured_boot.h
+++ b/include/drivers/measured_boot/rse/rse_measured_boot.h
@@ -4,17 +4,17 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef RSS_MEASURED_BOOT_H
-#define RSS_MEASURED_BOOT_H
+#ifndef RSE_MEASURED_BOOT_H
+#define RSE_MEASURED_BOOT_H
#include <stdint.h>
#include <common/debug.h>
#include <drivers/measured_boot/metadata.h>
-#define RSS_MBOOT_INVALID_ID UINT32_MAX
+#define RSE_MBOOT_INVALID_ID UINT32_MAX
-struct rss_mboot_metadata {
+struct rse_mboot_metadata {
unsigned int id;
uint8_t slot;
uint8_t signer_id[SIGNER_ID_MAX_SIZE];
@@ -28,13 +28,13 @@
};
/* Functions' declarations */
-void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr);
-int rss_mboot_measure_and_record(struct rss_mboot_metadata *metadata_ptr,
+void rse_measured_boot_init(struct rse_mboot_metadata *metadata_ptr);
+int rse_mboot_measure_and_record(struct rse_mboot_metadata *metadata_ptr,
uintptr_t data_base, uint32_t data_size,
uint32_t data_id);
-int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr,
+int rse_mboot_set_signer_id(struct rse_mboot_metadata *metadata_ptr,
const void *pk_oid, const void *pk_ptr,
size_t pk_len);
-#endif /* RSS_MEASURED_BOOT_H */
+#endif /* RSE_MEASURED_BOOT_H */
diff --git a/include/drivers/nxp/console/linflex.h b/include/drivers/nxp/console/linflex.h
new file mode 100644
index 0000000..2b4e0d7
--- /dev/null
+++ b/include/drivers/nxp/console/linflex.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef LINFLEX_H
+#define LINFLEX_H
+
+#ifndef __ASSEMBLER__
+#include <drivers/console.h>
+
+int console_linflex_core_init(uintptr_t baseaddr, uint32_t clock,
+ uint32_t baud);
+int console_linflex_register(uintptr_t baseaddr, uint32_t clock,
+ uint32_t baud, console_t *console);
+#endif
+
+#endif /* LINFLEX_H */
diff --git a/include/lib/cpus/aarch64/neoverse_hermes.h b/include/lib/cpus/aarch64/neoverse_hermes.h
deleted file mode 100644
index 22492c3..0000000
--- a/include/lib/cpus/aarch64/neoverse_hermes.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NEOVERSE_HERMES_H
-#define NEOVERSE_HERMES_H
-
-#define NEOVERSE_HERMES_MIDR U(0x410FD8E0)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_HERMES_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_HERMES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* NEOVERSE_HERMES_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n3.h b/include/lib/cpus/aarch64/neoverse_n3.h
new file mode 100644
index 0000000..9196330
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n3.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N3_H
+#define NEOVERSE_N3_H
+
+#define NEOVERSE_N3_MIDR U(0x410FD8E0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_N3_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_N3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* NEOVERSE_N3_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h
index 39a6607..1171e95 100644
--- a/include/lib/cpus/aarch64/neoverse_v2.h
+++ b/include/lib/cpus/aarch64/neoverse_v2.h
@@ -16,6 +16,7 @@
* CPU Extended Control register specific definitions
******************************************************************************/
#define NEOVERSE_V2_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
/*******************************************************************************
* CPU Power Control register specific definitions
diff --git a/include/lib/debugfs.h b/include/lib/debugfs.h
index 8ed237a..1fdccb6 100644
--- a/include/lib/debugfs.h
+++ b/include/lib/debugfs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,11 +61,23 @@
/* Debugfs version returned through SMC interface */
#define DEBUGFS_VERSION (0x000000001U)
-/* Function ID for accessing the debugfs interface */
-#define DEBUGFS_FID_VALUE (0x30U)
+/* Function ID for accessing the debugfs interface from
+ * Vendor-Specific EL3 Range.
+ */
+#define DEBUGFS_FID_VALUE (0x10U)
+
+#define is_debugfs_fid(_fid) \
+ (GET_SMC_NUM(_fid) == DEBUGFS_FID_VALUE)
+
+
+/* Function ID for accessing the debugfs interface from arm sip.
+ * This is now deprecated FID and will be removed after 2.12 release.
+ */
+#define DEBUGFS_FID_VALUE_DEPRECATED (0x30U)
+
+#define is_debugfs_fid_deprecated(_fid) \
+ (GET_SMC_NUM(_fid) == DEBUGFS_FID_VALUE_DEPRECATED)
-#define is_debugfs_fid(_fid) \
- (((_fid) & FUNCID_NUM_MASK) == DEBUGFS_FID_VALUE)
/* Error code for debugfs SMC interface failures */
#define DEBUGFS_E_INVALID_PARAMS (-2)
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h
index 9d901e2..41bf7fc 100644
--- a/include/lib/pmf/pmf.h
+++ b/include/lib/pmf/pmf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,19 +36,36 @@
#define PMF_NO_CACHE_MAINT U(0)
/*
- * Defines for PMF SMC function ids.
+ * Defines for PMF SMC function ids used with arm-sip
+ * range, this is now deprecated and will be removed.
*/
-#define PMF_SMC_GET_TIMESTAMP_32 U(0x82000010)
-#define PMF_SMC_GET_TIMESTAMP_64 U(0xC2000010)
+#define PMF_SMC_GET_TIMESTAMP_32_DEP U(0x82000010)
+#define PMF_SMC_GET_TIMESTAMP_64_DEP U(0xC2000010)
+
+#define PMF_FID_VALUE_DEPRECATED U(0x10)
+#define is_pmf_fid_deprecated(_fid) \
+ (GET_SMC_NUM(_fid) == PMF_FID_VALUE_DEPRECATED)
+
+/*
+ * Defines for PMF SMC function ids used with Vendor-Specific
+ * EL3 range.
+ */
+#define PMF_SMC_GET_TIMESTAMP_32 U(0x87000020)
+#define PMF_SMC_GET_TIMESTAMP_64 U(0xC7000020)
#define PMF_NUM_SMC_CALLS 2
+#define PMF_SMC_GET_VERSION_32 U(0x87000021)
+#define PMF_SMC_GET_VERSION_64 U(0xC7000021)
+
+#define PMF_SMC_VERSION U(0x00000001)
+
/*
* The macros below are used to identify
* PMF calls from the SMC function ID.
*/
-#define PMF_FID_MASK U(0xffe0)
-#define PMF_FID_VALUE U(0)
-#define is_pmf_fid(_fid) (((_fid) & PMF_FID_MASK) == PMF_FID_VALUE)
+#define PMF_FID_VALUE U(0x20)
+#define PMF_ID_MASK (FUNCID_NUM_MASK & ~(0xf))
+#define is_pmf_fid(_fid) ((GET_SMC_NUM(_fid) & PMF_ID_MASK) == PMF_FID_VALUE)
/* Following are the supported PMF service IDs */
#define PMF_PSCI_STAT_SVC_ID 0
diff --git a/include/lib/psa/delegated_attestation.h b/include/lib/psa/delegated_attestation.h
index 7aaceb3..ec49f5d 100644
--- a/include/lib/psa/delegated_attestation.h
+++ b/include/lib/psa/delegated_attestation.h
@@ -15,9 +15,9 @@
#include "psa/error.h"
-/* RSS Delegated Attestation message types that distinguish its services. */
-#define RSS_DELEGATED_ATTEST_GET_DELEGATED_KEY 1001U
-#define RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN 1002U
+/* RSE Delegated Attestation message types that distinguish its services. */
+#define RSE_DELEGATED_ATTEST_GET_DELEGATED_KEY 1001U
+#define RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN 1002U
/**
* The aim of these APIs to get a derived signing key (private only) for the
@@ -28,13 +28,13 @@
* key is bind to the platform token (details below).
*
* Expected usage model:
- * - First rss_delegated_attest_get_delegated_key() API need to be called to
+ * - First rse_delegated_attest_get_delegated_key() API need to be called to
* obtain the private part of the delegated attestation key. The public part
* of key is computed by the cryptographic library when the key is
* registered.
- * - Secondly the rss_delegated_attest_get_token() must be called to obtain
+ * - Secondly the rse_delegated_attest_get_token() must be called to obtain
* platform attestation token. The hash of the public key (computed by
- * the hash_algo indicated in the rss_delegated_attest_get_delegated_key()
+ * the hash_algo indicated in the rse_delegated_attest_get_delegated_key()
* call) must be the input of this call. This ensures that nothing but the
* previously derived delegated key is bindable to the platform token.
*/
@@ -74,7 +74,7 @@
* platform attestation token as they are cryptographically linked together.
*/
psa_status_t
-rss_delegated_attest_get_delegated_key(uint8_t ecc_curve,
+rse_delegated_attest_get_delegated_key(uint8_t ecc_curve,
uint32_t key_bits,
uint8_t *key_buf,
size_t key_buf_size,
@@ -100,7 +100,7 @@
* code will be returned.
*/
psa_status_t
-rss_delegated_attest_get_token(const uint8_t *dak_pub_hash,
+rse_delegated_attest_get_token(const uint8_t *dak_pub_hash,
size_t dak_pub_hash_size,
uint8_t *token_buf,
size_t token_buf_size,
diff --git a/include/lib/psa/dice_protection_environment.h b/include/lib/psa/dice_protection_environment.h
index 61b6482..5351451 100644
--- a/include/lib/psa/dice_protection_environment.h
+++ b/include/lib/psa/dice_protection_environment.h
@@ -14,7 +14,7 @@
#include <dice.h>
-/* Additional defines for max size limit. These limits are set by DPE in RSS. */
+/* Additional defines for max size limit. These limits are set by DPE in RSE. */
#define DICE_AUTHORITY_DESCRIPTOR_MAX_SIZE 64
#define DICE_CONFIG_DESCRIPTOR_MAX_SIZE 64
#define DICE_CODE_DESCRIPTOR_MAX_SIZE 32
@@ -28,7 +28,7 @@
#define DPE_ARGUMENT_NOT_SUPPORTED ((dpe_error_t)4)
#define DPE_SESSION_EXHAUSTED ((dpe_error_t)5)
-/* Custom values in RSS based DPE implementation */
+/* Custom values in RSE based DPE implementation */
#define DPE_INSUFFICIENT_MEMORY ((dpe_error_t)128)
#define DPE_ERR_CBOR_FORMATTING ((dpe_error_t)129)
diff --git a/include/lib/psa/measured_boot.h b/include/lib/psa/measured_boot.h
index 79cdfa0..3cc6c95 100644
--- a/include/lib/psa/measured_boot.h
+++ b/include/lib/psa/measured_boot.h
@@ -43,11 +43,11 @@
* - When the requested slot is not accessible to the caller.
*/
-/* Not a standard PSA API, just an extension therefore use the 'rss_' prefix
+/* Not a standard PSA API, just an extension therefore use the 'rse_' prefix
* rather than the usual 'psa_'.
*/
psa_status_t
-rss_measured_boot_extend_measurement(uint8_t index,
+rse_measured_boot_extend_measurement(uint8_t index,
const uint8_t *signer_id,
size_t signer_id_size,
const uint8_t *version,
@@ -92,7 +92,7 @@
* PSA_ERROR_DOES_NOT_EXIST
* - The requested slot is empty, does not contain a measurement.
*/
-psa_status_t rss_measured_boot_read_measurement(uint8_t index,
+psa_status_t rse_measured_boot_read_measurement(uint8_t index,
uint8_t *signer_id,
size_t signer_id_size,
size_t *signer_id_len,
diff --git a/include/lib/psa/psa_manifest/sid.h b/include/lib/psa/psa_manifest/sid.h
index 6c15656..bb8abe4 100644
--- a/include/lib/psa/psa_manifest/sid.h
+++ b/include/lib/psa/psa_manifest/sid.h
@@ -8,19 +8,19 @@
#ifndef PSA_MANIFEST_SID_H
#define PSA_MANIFEST_SID_H
-/******** RSS_SP_CRYPTO ********/
-#define RSS_CRYPTO_HANDLE (0x40000100U)
+/******** RSE_SP_CRYPTO ********/
+#define RSE_CRYPTO_HANDLE (0x40000100U)
-/******** RSS_SP_PLATFORM ********/
-#define RSS_PLATFORM_SERVICE_HANDLE (0x40000105U)
+/******** RSE_SP_PLATFORM ********/
+#define RSE_PLATFORM_SERVICE_HANDLE (0x40000105U)
/******** PSA_SP_MEASURED_BOOT ********/
-#define RSS_MEASURED_BOOT_HANDLE (0x40000110U)
+#define RSE_MEASURED_BOOT_HANDLE (0x40000110U)
/******** PSA_SP_DELEGATED_ATTESTATION ********/
-#define RSS_DELEGATED_SERVICE_HANDLE (0x40000111U)
+#define RSE_DELEGATED_SERVICE_HANDLE (0x40000111U)
/******** PSA_SP_DICE_PROTECTION_ENVIRONMENT ********/
-#define RSS_DPE_SERVICE_HANDLE (0x40000112U)
+#define RSE_DPE_SERVICE_HANDLE (0x40000112U)
#endif /* PSA_MANIFEST_SID_H */
diff --git a/include/lib/psa/rss_crypto_defs.h b/include/lib/psa/rse_crypto_defs.h
similarity index 68%
rename from include/lib/psa/rss_crypto_defs.h
rename to include/lib/psa/rse_crypto_defs.h
index 301dc05..44936b8 100644
--- a/include/lib/psa/rss_crypto_defs.h
+++ b/include/lib/psa/rse_crypto_defs.h
@@ -5,8 +5,8 @@
*
*/
-#ifndef RSS_CRYPTO_DEFS_H
-#define RSS_CRYPTO_DEFS_H
+#ifndef RSE_CRYPTO_DEFS_H
+#define RSE_CRYPTO_DEFS_H
/* Declares types that encode errors, algorithms, key types, policies, etc. */
#include "psa/crypto_types.h"
@@ -16,31 +16,31 @@
* to the corresponding API implementation in the Crypto service backend.
*
*/
-#define RSS_CRYPTO_EXPORT_PUBLIC_KEY_SID (uint16_t)(0x701)
+#define RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID (uint16_t)(0x701)
/*
- * The persistent key identifiers for RSS builtin keys.
+ * The persistent key identifiers for RSE builtin keys.
*/
-enum rss_key_id_builtin_t {
- RSS_BUILTIN_KEY_ID_HOST_S_ROTPK = 0x7FFF816Cu,
- RSS_BUILTIN_KEY_ID_HOST_NS_ROTPK,
- RSS_BUILTIN_KEY_ID_HOST_CCA_ROTPK,
+enum rse_key_id_builtin_t {
+ RSE_BUILTIN_KEY_ID_HOST_S_ROTPK = 0x7FFF816Cu,
+ RSE_BUILTIN_KEY_ID_HOST_NS_ROTPK,
+ RSE_BUILTIN_KEY_ID_HOST_CCA_ROTPK,
};
/*
- * This type is used to overcome a limitation within RSS firmware in the number of maximum
+ * This type is used to overcome a limitation within RSE firmware in the number of maximum
* IOVECs it can use especially in psa_aead_encrypt and psa_aead_decrypt.
*/
-#define RSS_CRYPTO_MAX_NONCE_LENGTH (16u)
-struct rss_crypto_aead_pack_input {
- uint8_t nonce[RSS_CRYPTO_MAX_NONCE_LENGTH];
+#define RSE_CRYPTO_MAX_NONCE_LENGTH (16u)
+struct rse_crypto_aead_pack_input {
+ uint8_t nonce[RSE_CRYPTO_MAX_NONCE_LENGTH];
uint32_t nonce_length;
};
/*
* Structure used to pack non-pointer types in a call to PSA Crypto APIs
*/
-struct rss_crypto_pack_iovec {
+struct rse_crypto_pack_iovec {
psa_key_id_t key_id; /* !< Key id */
psa_algorithm_t alg; /* !< Algorithm */
uint32_t op_handle; /*
@@ -56,7 +56,7 @@
* AEAD
*/
- struct rss_crypto_aead_pack_input aead_in; /*
+ struct rse_crypto_aead_pack_input aead_in; /*
* !< Packs AEAD-related
* inputs
*/
@@ -64,7 +64,7 @@
uint16_t function_id; /*
* !< Used to identify the function in the
* API dispatcher to the service backend
- * See rss_crypto_func_sid for detail
+ * See rse_crypto_func_sid for detail
*/
uint16_t step; /* !< Key derivation step */
union {
@@ -76,4 +76,4 @@
};
};
-#endif /* RSS_CRYPTO_DEFS_H */
+#endif /* RSE_CRYPTO_DEFS_H */
diff --git a/include/lib/psa/rss_platform_api.h b/include/lib/psa/rse_platform_api.h
similarity index 75%
rename from include/lib/psa/rss_platform_api.h
rename to include/lib/psa/rse_platform_api.h
index 8f74a51..535001b 100644
--- a/include/lib/psa/rss_platform_api.h
+++ b/include/lib/psa/rse_platform_api.h
@@ -5,16 +5,16 @@
*
*/
-#ifndef RSS_PLATFORM_API_H
-#define RSS_PLATFORM_API_H
+#ifndef RSE_PLATFORM_API_H
+#define RSE_PLATFORM_API_H
#include <stdint.h>
#include "psa/error.h"
-#include <rss_crypto_defs.h>
+#include <rse_crypto_defs.h>
-#define RSS_PLATFORM_API_ID_NV_READ (1010)
-#define RSS_PLATFORM_API_ID_NV_INCREMENT (1011)
+#define RSE_PLATFORM_API_ID_NV_READ (1010)
+#define RSE_PLATFORM_API_ID_NV_INCREMENT (1011)
/*
* Increments the given non-volatile (NV) counter by one
@@ -25,7 +25,7 @@
* it returns a PSA_ERROR.
*/
psa_status_t
-rss_platform_nv_counter_increment(uint32_t counter_id);
+rse_platform_nv_counter_increment(uint32_t counter_id);
/*
* Reads the given non-volatile (NV) counter
@@ -39,7 +39,7 @@
* it returns a PSA_ERROR.
*/
psa_status_t
-rss_platform_nv_counter_read(uint32_t counter_id,
+rse_platform_nv_counter_read(uint32_t counter_id,
uint32_t size, uint8_t *val);
/*
@@ -54,7 +54,7 @@
* it returns a PSA_ERROR.
*/
psa_status_t
-rss_platform_key_read(enum rss_key_id_builtin_t key, uint8_t *data,
+rse_platform_key_read(enum rse_key_id_builtin_t key, uint8_t *data,
size_t data_size, size_t *data_length);
-#endif /* RSS_PLATFORM_API_H */
+#endif /* RSE_PLATFORM_API_H */
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index c493105..775c2b2 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,7 +20,7 @@
SMCCC_VERSION_MINOR_SHIFT))
#define SMCCC_MAJOR_VERSION U(1)
-#define SMCCC_MINOR_VERSION U(4)
+#define SMCCC_MINOR_VERSION U(5)
/*******************************************************************************
* Bit definitions inside the function id as per the SMC calling convention
@@ -95,6 +95,8 @@
#define OEN_STD_HYP_END U(5)
#define OEN_VEN_HYP_START U(6) /* Vendor Hypervisor Service calls */
#define OEN_VEN_HYP_END U(6)
+#define OEN_VEN_EL3_START U(7) /* Vendor Specific EL3 Monitor Calls */
+#define OEN_VEN_EL3_END U(7)
#define OEN_TAP_START U(48) /* Trusted Applications */
#define OEN_TAP_END U(49)
#define OEN_TOS_START U(50) /* Trusted OS */
diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h
index c5df22b..5bea270 100644
--- a/include/lib/transfer_list.h
+++ b/include/lib/transfer_list.h
@@ -44,6 +44,8 @@
TL_TAG_OPTEE_PAGABLE_PART = 0x100,
TL_TAG_DT_SPMC_MANIFEST = 0x101,
TL_TAG_EXEC_EP_INFO64 = 0x102,
+ TL_TAG_TB_FW_CONFIG = 0x103,
+ TL_TAG_SRAM_LAYOUT64 = 0x104,
};
enum transfer_list_ops {
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index c3a88e7..ec5f90b 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -411,6 +411,8 @@
#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
V2M_FLASH_BLOCK_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
+
+#if !TRANSFER_LIST
/*
* Map the region for device tree configuration with read and write permissions
*/
@@ -418,6 +420,8 @@
(ARM_FW_CONFIGS_LIMIT \
- ARM_BL_RAM_BASE), \
MT_MEMORY | MT_RW | EL3_PAS)
+#endif
+
/*
* Map L0_GPT with read and write permissions
*/
@@ -505,6 +509,14 @@
*/
#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+/* Define memory configuration for trusted boot device tree files. */
+#ifdef PLAT_ARM_TB_FW_CONFIG_SIZE
+#define ARM_TB_FW_CONFIG_MAX_SIZE PLAT_ARM_TB_FW_CONFIG_SIZE
+#else
+#define ARM_TB_FW_CONFIG_MAX_SIZE U(0x400)
+#endif
+
+#if !TRANSFER_LIST
/*
* To enable FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space of BL2 meminfo.
@@ -526,6 +538,7 @@
*/
#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
+#endif
#if ENABLE_RME
/*
diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h
index a6fd42b..bca224d 100644
--- a/include/plat/arm/common/arm_sip_svc.h
+++ b/include/plat/arm/common/arm_sip_svc.h
@@ -16,12 +16,14 @@
/* U(0x8200ff02) is reserved */
#define ARM_SIP_SVC_VERSION U(0x8200ff03)
+/* Deprecated FID's Range and will be removed */
/* PMF_SMC_GET_TIMESTAMP_32 0x82000010 */
/* PMF_SMC_GET_TIMESTAMP_64 0xC2000010 */
/* Function ID for requesting state switch of lower EL */
#define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020)
+/* Deprecated FID's Range and will be removed */
/* DEBUGFS_SMC_32 0x82000030U */
/* DEBUGFS_SMC_64 0xC2000030U */
@@ -32,8 +34,8 @@
*/
/* ARM SiP Service Calls version numbers */
-#define ARM_SIP_SVC_VERSION_MAJOR U(0x0)
-#define ARM_SIP_SVC_VERSION_MINOR U(0x2)
+#define ARM_SIP_SVC_VERSION_MAJOR U(0x1)
+#define ARM_SIP_SVC_VERSION_MINOR U(0x0)
/*
* Arm SiP SMC calls that are primarily used for testing purposes.
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index a43e13c..d778201 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -9,12 +9,14 @@
#include <stdbool.h>
#include <stdint.h>
+#include <common/desc_image_load.h>
#include <drivers/arm/tzc_common.h>
#include <lib/bakery_lock.h>
#include <lib/cassert.h>
#include <lib/el3_runtime/cpu_data.h>
#include <lib/gpt_rme/gpt_rme.h>
#include <lib/spinlock.h>
+#include <lib/transfer_list.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
@@ -151,11 +153,10 @@
#define ARM_LOCAL_PSTATE_WIDTH 4
#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
-#if PSCI_OS_INIT_MODE
+/* Last in Level for the OS-initiated */
#define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \
(ARM_LOCAL_PSTATE_WIDTH * \
(PLAT_MAX_PWR_LVL + 1)))
-#endif /* __PSCI_OS_INIT_MODE__ */
/* Macros to construct the composite power state */
@@ -254,6 +255,7 @@
int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
int arm_bl2_handle_post_image_load(unsigned int image_id);
struct bl_params *arm_get_next_bl_params(void);
+void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node);
/* BL2 at EL3 functions */
void arm_bl2_el3_early_platform_setup(void);
@@ -266,12 +268,25 @@
void arm_bl2u_plat_arch_setup(void);
/* BL31 utility functions */
+#if TRANSFER_LIST
+void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3);
+#else
void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
uintptr_t hw_config, void *plat_params_from_bl2);
+#endif
void arm_bl31_platform_setup(void);
void arm_bl31_plat_runtime_setup(void);
void arm_bl31_plat_arch_setup(void);
+/* Firmware Handoff utility functions */
+void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl);
+void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node,
+ struct transfer_list_header *secure_tl,
+ struct transfer_list_header *ns_tl);
+void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl,
+ struct transfer_list_header *ns_tl);
+
/* TSP utility functions */
void arm_tsp_early_platform_setup(void);
@@ -368,6 +383,8 @@
unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
#endif
+unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr);
+
/*
* This function is called after loading SCP_BL2 image and it is used to perform
* any platform-specific actions required to handle the SCP firmware.
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 0aea548..6203937 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -58,12 +58,12 @@
INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_LEVEL), \
- INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
#define CSS_G1S_IRQ_PROPS(grp) \
CSS_G1S_INT_PROPS(grp), \
+ INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 4fe3620..ce5e8e0 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -184,6 +184,14 @@
}
#endif /* MEASURED_BOOT */
+#if EARLY_CONSOLE
+void plat_setup_early_console(void);
+#else
+static inline void plat_setup_early_console(void)
+{
+}
+#endif /* EARLY_CONSOLE */
+
/*******************************************************************************
* Mandatory BL1 functions
******************************************************************************/
@@ -243,7 +251,11 @@
int bl1_plat_handle_pre_image_load(unsigned int image_id);
int bl1_plat_handle_post_image_load(unsigned int image_id);
-#if (MEASURED_BOOT || DICE_PROTECTION_ENVIRONMENT)
+/* Utility functions */
+void bl1_plat_calc_bl2_layout(const meminfo_t *bl1_mem_layout,
+ meminfo_t *bl2_mem_layout);
+
+#if MEASURED_BOOT
void bl1_plat_mboot_init(void);
void bl1_plat_mboot_finish(void);
#else
diff --git a/include/services/ven_el3_svc.h b/include/services/ven_el3_svc.h
new file mode 100644
index 0000000..e030b68
--- /dev/null
+++ b/include/services/ven_el3_svc.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef VEN_EL3_SVC_H
+#define VEN_EL3_SVC_H
+
+/*
+ * Function Identifier value ranges for Vendor-Specific
+ * EL3 Monitor Service Calls.
+ */
+/* VEN_EL3_SMC_32 0x87000000U */
+/* VEN_EL3_SMC_64 0xC7000000U */
+
+
+/* Function Identifier values of general queries */
+#define VEN_EL3_SVC_UID 0x8700ff01
+/* 0x8700ff02 is reserved */
+#define VEN_EL3_SVC_VERSION 0x8700ff03
+
+#define VEN_EL3_SVC_VERSION_MAJOR 1
+#define VEN_EL3_SVC_VERSION_MINOR 0
+
+/* DEBUGFS_SMC_32 0x87000010U */
+/* DEBUGFS_SMC_64 0xC7000010U */
+
+/* PMF_SMC_GET_TIMESTAMP_32 0x87000020U */
+/* PMF_SMC_GET_TIMESTAMP_64 0xC7000020U */
+
+#endif /* VEN_EL3_SVC_H */
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index f9c4baf..93771df 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,6 @@
.globl zero_normalmem
.globl zeromem
.globl memcpy16
- .globl gpt_tlbi_by_pa_ll
.globl disable_mmu_el1
.globl disable_mmu_el3
@@ -594,20 +593,3 @@
b.lo 1b
ret
endfunc fixup_gdt_reloc
-
-/*
- * TODO: Currently only supports size of 4KB,
- * support other sizes as well.
- */
-func gpt_tlbi_by_pa_ll
-#if ENABLE_ASSERTIONS
- cmp x1, #PAGE_SIZE_4KB
- ASM_ASSERT(eq)
- tst x0, #(PAGE_SIZE_MASK)
- ASM_ASSERT(eq)
-#endif
- lsr x0, x0, #FOUR_KB_SHIFT /* 4KB size encoding is zero */
- sys #6, c8, c4, #7, x0 /* TLBI RPALOS, <Xt> */
- dsb sy
- ret
-endfunc gpt_tlbi_by_pa_ll
diff --git a/lib/compiler-rt/builtins/assembly.h b/lib/compiler-rt/builtins/assembly.h
index 169d496..8c42fc7 100644
--- a/lib/compiler-rt/builtins/assembly.h
+++ b/lib/compiler-rt/builtins/assembly.h
@@ -260,9 +260,10 @@
.globl name SEPARATOR \
SYMBOL_IS_FUNC(name) SEPARATOR \
DECLARE_SYMBOL_VISIBILITY_UNMANGLED(name) SEPARATOR \
- CFI_START SEPARATOR \
DECLARE_FUNC_ENCODING \
- name: SEPARATOR BTI_C
+ name: \
+ SEPARATOR CFI_START \
+ SEPARATOR BTI_C
#define DEFINE_COMPILERRT_FUNCTION_ALIAS(name, target) \
.globl SYMBOL_NAME(name) SEPARATOR \
diff --git a/lib/compiler-rt/builtins/int_lib.h b/lib/compiler-rt/builtins/int_lib.h
index 04ea2d9..f6c1b7c 100644
--- a/lib/compiler-rt/builtins/int_lib.h
+++ b/lib/compiler-rt/builtins/int_lib.h
@@ -119,14 +119,14 @@
#if defined(_MSC_VER) && !defined(__clang__)
#include <intrin.h>
-int __inline __builtin_ctz(uint32_t value) {
+static int __inline __builtin_ctz(uint32_t value) {
unsigned long trailing_zero = 0;
if (_BitScanForward(&trailing_zero, value))
return trailing_zero;
return 32;
}
-int __inline __builtin_clz(uint32_t value) {
+static int __inline __builtin_clz(uint32_t value) {
unsigned long leading_zero = 0;
if (_BitScanReverse(&leading_zero, value))
return 31 - leading_zero;
@@ -134,14 +134,14 @@
}
#if defined(_M_ARM) || defined(_M_X64)
-int __inline __builtin_clzll(uint64_t value) {
+static int __inline __builtin_clzll(uint64_t value) {
unsigned long leading_zero = 0;
if (_BitScanReverse64(&leading_zero, value))
return 63 - leading_zero;
return 64;
}
#else
-int __inline __builtin_clzll(uint64_t value) {
+static int __inline __builtin_clzll(uint64_t value) {
if (value == 0)
return 64;
uint32_t msh = (uint32_t)(value >> 32);
@@ -154,7 +154,7 @@
#define __builtin_clzl __builtin_clzll
-bool __inline __builtin_sadd_overflow(int x, int y, int *result) {
+static bool __inline __builtin_sadd_overflow(int x, int y, int *result) {
if ((x < 0) != (y < 0)) {
*result = x + y;
return false;
diff --git a/lib/compiler-rt/builtins/int_types.h b/lib/compiler-rt/builtins/int_types.h
index 18bf0a7..48862f3 100644
--- a/lib/compiler-rt/builtins/int_types.h
+++ b/lib/compiler-rt/builtins/int_types.h
@@ -107,8 +107,8 @@
static __inline ti_int make_ti(di_int h, di_int l) {
twords r;
- r.s.high = h;
- r.s.low = l;
+ r.s.high = (du_int)h;
+ r.s.low = (du_int)l;
return r.all;
}
@@ -139,7 +139,6 @@
udwords u;
double f;
} double_bits;
-#endif
typedef struct {
#if _YUGA_LITTLE_ENDIAN
@@ -190,12 +189,16 @@
#define CRT_LDBL_IEEE_F128
#endif
#define TF_C(x) x##L
-#elif __LDBL_MANT_DIG__ == 113
-// Use long double instead of __float128 if it matches the IEEE 128-bit format.
+#elif __LDBL_MANT_DIG__ == 113 || \
+ (__FLT_RADIX__ == 16 && __LDBL_MANT_DIG__ == 28)
+// Use long double instead of __float128 if it matches the IEEE 128-bit format
+// or the IBM hexadecimal format.
#define CRT_LDBL_128BIT
#define CRT_HAS_F128
+#if __LDBL_MANT_DIG__ == 113
#define CRT_HAS_IEEE_TF
#define CRT_LDBL_IEEE_F128
+#endif
typedef long double tf_float;
#define TF_C(x) x##L
#elif defined(__FLOAT128__) || defined(__SIZEOF_FLOAT128__)
@@ -220,7 +223,6 @@
#define CRT_HAS_TF_MODE
#endif
-#if CRT_HAS_FLOATING_POINT
#if __STDC_VERSION__ >= 199901L
typedef float _Complex Fcomplex;
typedef double _Complex Dcomplex;
@@ -270,5 +272,5 @@
#define COMPLEXTF_IMAGINARY(x) (x).imaginary
#endif
-#endif
+#endif // CRT_HAS_FLOATING_POINT
#endif // INT_TYPES_H
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S
index dc704f2..8870019 100644
--- a/lib/cpus/aarch64/cortex_gelas.S
+++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,7 +42,7 @@
mrs x0, ID_AA64PFR1_EL1
ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
#ID_AA64PFR1_EL1_SME_WIDTH
- cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
+ cmp x0, #SME_NOT_IMPLEMENTED
b.eq 1f
msr CORTEX_GELAS_SVCRSM, xzr
msr CORTEX_GELAS_SVCRZA, xzr
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 1ae3180..3aa4f15 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -165,13 +165,13 @@
and w2, w2, w3
/* Get the cpu_ops end location */
- adr x5, (__CPU_OPS_END__ + CPU_MIDR)
+ adr_l x5, (__CPU_OPS_END__ + CPU_MIDR)
/* Initialize the return parameter */
mov x0, #0
1:
/* Get the cpu_ops start location */
- adr x4, (__CPU_OPS_START__ + CPU_MIDR)
+ adr_l x4, (__CPU_OPS_START__ + CPU_MIDR)
2:
/* Check if we have reached end of list */
diff --git a/lib/cpus/aarch64/neoverse_hermes.S b/lib/cpus/aarch64/neoverse_hermes.S
deleted file mode 100644
index cb90b71..0000000
--- a/lib/cpus/aarch64/neoverse_hermes.S
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <neoverse_hermes.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Neoverse Hermes must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Neoverse Hermes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-cpu_reset_func_start neoverse_hermes
- /* Disable speculative loads */
- msr SSBS, xzr
-cpu_reset_func_end neoverse_hermes
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func neoverse_hermes_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- sysreg_bit_set NEOVERSE_HERMES_CPUPWRCTLR_EL1, NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- isb
- ret
-endfunc neoverse_hermes_core_pwr_dwn
-
-errata_report_shim neoverse_hermes
-
- /* ---------------------------------------------
- * This function provides Neoverse Hermes specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.neoverse_hermes_regs, "aS"
-neoverse_hermes_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func neoverse_hermes_cpu_reg_dump
- adr x6, neoverse_hermes_regs
- mrs x8, NEOVERSE_HERMES_CPUECTLR_EL1
- ret
-endfunc neoverse_hermes_cpu_reg_dump
-
-declare_cpu_ops neoverse_hermes, NEOVERSE_HERMES_MIDR, \
- neoverse_hermes_reset_func, \
- neoverse_hermes_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_n3.S b/lib/cpus/aarch64/neoverse_n3.S
new file mode 100644
index 0000000..0b33b7e
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_n3.S
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_n3.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start neoverse_n3
+ /* Disable speculative loads */
+ msr SSBS, xzr
+
+#if NEOVERSE_Nx_EXTERNAL_LLC
+ /* Some systems may have External LLC, core needs to be made aware */
+ sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT
+#endif
+cpu_reset_func_end neoverse_n3
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func neoverse_n3_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
+ ret
+endfunc neoverse_n3_core_pwr_dwn
+
+errata_report_shim neoverse_n3
+
+ /* ---------------------------------------------
+ * This function provides Neoverse-N3 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_n3_regs, "aS"
+neoverse_n3_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_n3_cpu_reg_dump
+ adr x6, neoverse_n3_regs
+ mrs x8, NEOVERSE_N3_CPUECTLR_EL1
+ ret
+endfunc neoverse_n3_cpu_reg_dump
+
+declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \
+ neoverse_n3_reset_func, \
+ neoverse_n3_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index d4b3a96..3179918 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -109,6 +109,11 @@
cpu_reset_func_start neoverse_v2
/* Disable speculative loads */
msr SSBS, xzr
+
+#if NEOVERSE_Vx_EXTERNAL_LLC
+ /* Some systems may have External LLC, core needs to be made aware */
+ sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT
+#endif
cpu_reset_func_end neoverse_v2
errata_report_shim neoverse_v2
diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S
index 2abefe9..ba06f55 100644
--- a/lib/cpus/aarch64/travis.S
+++ b/lib/cpus/aarch64/travis.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,7 +38,7 @@
mrs x0, ID_AA64PFR1_EL1
ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
#ID_AA64PFR1_EL1_SME_WIDTH
- cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
+ cmp x0, #SME_NOT_IMPLEMENTED
b.eq 1f
msr TRAVIS_SVCRSM, xzr
msr TRAVIS_SVCRZA, xzr
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 301c60c..132888c 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -149,7 +149,7 @@
trf_init_el3();
}
- if (read_feat_pmuv3_id_field() >= 3U) {
+ if (is_feat_pmuv3_present()) {
pmuv3_init_el3();
}
#endif /* IMAGE_BL32 */
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index b1409b9..98d57e9 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -53,7 +53,7 @@
* using SMCR_EL2 and SMCR_EL1.
*/
smcr_el3 = SMCR_ELX_LEN_MAX;
- if (read_feat_sme_fa64_id_field() != 0U) {
+ if (is_feat_sme_fa64_present()) {
VERBOSE("[SME] FA64 enabled\n");
smcr_el3 |= SMCR_ELX_FA64_BIT;
}
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index 72e905e..4d80373 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -57,6 +57,13 @@
*/
static const gpt_p_val_e gpt_p_lookup[] = {PGS_4KB_P, PGS_64KB_P, PGS_16KB_P};
+static void shatter_2mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+static void shatter_32mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+static void shatter_512mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+
/*
* This structure contains GPT configuration data
*/
@@ -70,11 +77,188 @@
static gpt_config_t gpt_config;
+/*
+ * Number of L1 entries in 2MB, depending on GPCCR_EL3.PGS:
+ * +-------+------------+
+ * | PGS | L1 entries |
+ * +-------+------------+
+ * | 4KB | 32 |
+ * +-------+------------+
+ * | 16KB | 8 |
+ * +-------+------------+
+ * | 64KB | 2 |
+ * +-------+------------+
+ */
+static unsigned int gpt_l1_cnt_2mb;
+
+/*
+ * Mask for the L1 index field, depending on
+ * GPCCR_EL3.L0GPTSZ and GPCCR_EL3.PGS:
+ * +---------+-------------------------------+
+ * | | PGS |
+ * +---------+----------+----------+---------+
+ * | L0GPTSZ | 4KB | 16KB | 64KB |
+ * +---------+----------+----------+---------+
+ * | 1GB | 0x3FFF | 0xFFF | 0x3FF |
+ * +---------+----------+----------+---------+
+ * | 16GB | 0x3FFFF | 0xFFFF | 0x3FFF |
+ * +---------+----------+----------+---------+
+ * | 64GB | 0xFFFFF | 0x3FFFF | 0xFFFF |
+ * +---------+----------+----------+---------+
+ * | 512GB | 0x7FFFFF | 0x1FFFFF | 0x7FFFF |
+ * +---------+----------+----------+---------+
+ */
+static uint64_t gpt_l1_index_mask;
+
+/* Number of 128-bit L1 entries in 2MB, 32MB and 512MB */
+#define L1_QWORDS_2MB (gpt_l1_cnt_2mb / 2U)
+#define L1_QWORDS_32MB (L1_QWORDS_2MB * 16U)
+#define L1_QWORDS_512MB (L1_QWORDS_32MB * 16U)
+
+/* Size in bytes of L1 entries in 2MB, 32MB */
+#define L1_BYTES_2MB (gpt_l1_cnt_2mb * sizeof(uint64_t))
+#define L1_BYTES_32MB (L1_BYTES_2MB * 16U)
+
+/* Get the index into the L1 table from a physical address */
+#define GPT_L1_INDEX(_pa) \
+ (((_pa) >> (unsigned int)GPT_L1_IDX_SHIFT(gpt_config.p)) & gpt_l1_index_mask)
+
/* These variables are used during initialization of the L1 tables */
-static unsigned int gpt_next_l1_tbl_idx;
static uintptr_t gpt_l1_tbl;
+/* These variable is used during runtime */
+#if (RME_GPT_BITLOCK_BLOCK == 0)
+/*
+ * The GPTs are protected by a global spinlock to ensure
+ * that multiple CPUs do not attempt to change the descriptors at once.
+ */
+static spinlock_t gpt_lock;
+#else
+
+/* Bitlocks base address */
+static bitlock_t *gpt_bitlock_base;
+#endif
+
+/* Lock/unlock macros for GPT entries */
+#if (RME_GPT_BITLOCK_BLOCK == 0)
+/*
+ * Access to GPT is controlled by a global lock to ensure
+ * that no more than one CPU is allowed to make changes at any
+ * given time.
+ */
+#define GPT_LOCK spin_lock(&gpt_lock)
+#define GPT_UNLOCK spin_unlock(&gpt_lock)
+#else
+/*
+ * Access to a block of memory is controlled by a bitlock.
+ * Size of block = RME_GPT_BITLOCK_BLOCK * 512MB.
+ */
+#define GPT_LOCK bit_lock(gpi_info.lock, gpi_info.mask)
+#define GPT_UNLOCK bit_unlock(gpi_info.lock, gpi_info.mask)
+#endif
+
+static void tlbi_page_dsbosh(uintptr_t base)
+{
+ /* Look-up table for invalidation TLBs for 4KB, 16KB and 64KB pages */
+ static const gpt_tlbi_lookup_t tlbi_page_lookup[] = {
+ { tlbirpalos_4k, ~(SZ_4K - 1UL) },
+ { tlbirpalos_64k, ~(SZ_64K - 1UL) },
+ { tlbirpalos_16k, ~(SZ_16K - 1UL) }
+ };
+
+ tlbi_page_lookup[gpt_config.pgs].function(
+ base & tlbi_page_lookup[gpt_config.pgs].mask);
+ dsbosh();
+}
+
/*
+ * Helper function to fill out GPI entries in a single L1 table
+ * with Granules or Contiguous descriptor.
+ *
+ * Parameters
+ * l1 Pointer to 2MB, 32MB or 512MB aligned L1 table entry to fill out
+ * l1_desc GPT Granules or Contiguous descriptor set this range to
+ * cnt Number of double 128-bit L1 entries to fill
+ *
+ */
+static void fill_desc(uint64_t *l1, uint64_t l1_desc, unsigned int cnt)
+{
+ uint128_t *l1_quad = (uint128_t *)l1;
+ uint128_t l1_quad_desc = (uint128_t)l1_desc | ((uint128_t)l1_desc << 64);
+
+ VERBOSE("GPT: %s(%p 0x%"PRIx64" %u)\n", __func__, l1, l1_desc, cnt);
+
+ for (unsigned int i = 0U; i < cnt; i++) {
+ *l1_quad++ = l1_quad_desc;
+ }
+}
+
+static void shatter_2mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ unsigned long idx = GPT_L1_INDEX(ALIGN_2MB(base));
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n",
+ __func__, base, l1_desc);
+
+ /* Convert 2MB Contiguous block to Granules */
+ fill_desc(&gpi_info->gpt_l1_addr[idx], l1_desc, L1_QWORDS_2MB);
+}
+
+static void shatter_32mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ unsigned long idx = GPT_L1_INDEX(ALIGN_2MB(base));
+ const uint64_t *l1_gran = &gpi_info->gpt_l1_addr[idx];
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB);
+ uint64_t *l1;
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n",
+ __func__, base, l1_desc);
+
+ /* Get index corresponding to 32MB aligned address */
+ idx = GPT_L1_INDEX(ALIGN_32MB(base));
+ l1 = &gpi_info->gpt_l1_addr[idx];
+
+ /* 16 x 2MB blocks in 32MB */
+ for (unsigned int i = 0U; i < 16U; i++) {
+ /* Fill with Granules or Contiguous descriptors */
+ fill_desc(l1, (l1 == l1_gran) ? l1_desc : l1_cont_desc,
+ L1_QWORDS_2MB);
+ l1 = (uint64_t *)((uintptr_t)l1 + L1_BYTES_2MB);
+ }
+}
+
+static void shatter_512mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ unsigned long idx = GPT_L1_INDEX(ALIGN_32MB(base));
+ const uint64_t *l1_32mb = &gpi_info->gpt_l1_addr[idx];
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB);
+ uint64_t *l1;
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n",
+ __func__, base, l1_desc);
+
+ /* Get index corresponding to 512MB aligned address */
+ idx = GPT_L1_INDEX(ALIGN_512MB(base));
+ l1 = &gpi_info->gpt_l1_addr[idx];
+
+ /* 16 x 32MB blocks in 512MB */
+ for (unsigned int i = 0U; i < 16U; i++) {
+ if (l1 == l1_32mb) {
+ /* Shatter this 32MB block */
+ shatter_32mb(base, gpi_info, l1_desc);
+ } else {
+ /* Fill 32MB with Contiguous descriptors */
+ fill_desc(l1, l1_cont_desc, L1_QWORDS_32MB);
+ }
+
+ l1 = (uint64_t *)((uintptr_t)l1 + L1_BYTES_32MB);
+ }
+}
+
+/*
* This function checks to see if a GPI value is valid.
*
* These are valid GPI values.
@@ -213,10 +397,11 @@
* to see if this PAS would fall into one that has already been
* initialized.
*/
- for (unsigned int i = GPT_L0_IDX(pas_regions[idx].base_pa);
- i <= GPT_L0_IDX(pas_regions[idx].base_pa +
- pas_regions[idx].size - 1UL);
- i++) {
+ for (unsigned int i =
+ (unsigned int)GPT_L0_IDX(pas_regions[idx].base_pa);
+ i <= GPT_L0_IDX(pas_regions[idx].base_pa +
+ pas_regions[idx].size - 1UL);
+ i++) {
if ((GPT_L0_TYPE(l0_desc[i]) == GPT_L0_TYPE_BLK_DESC) &&
(GPT_L0_BLKD_GPI(l0_desc[i]) == GPT_GPI_ANY)) {
/* This descriptor is unused so continue */
@@ -227,7 +412,7 @@
* This descriptor has been initialized in a previous
* call to this function so cannot be initialized again.
*/
- ERROR("GPT: PAS[%u] overlaps with previous L0[%d]!\n",
+ ERROR("GPT: PAS[%u] overlaps with previous L0[%u]!\n",
idx, i);
return -EFAULT;
}
@@ -318,7 +503,7 @@
static int validate_l0_params(gpccr_pps_e pps, uintptr_t l0_mem_base,
size_t l0_mem_size)
{
- size_t l0_alignment;
+ size_t l0_alignment, locks_size = 0;
/*
* Make sure PPS is valid and then store it since macros need this value
@@ -344,12 +529,28 @@
return -EFAULT;
}
- /* Check size */
- if (l0_mem_size < GPT_L0_TABLE_SIZE(gpt_config.t)) {
- ERROR("%sL0%s\n", "GPT: Inadequate ", " memory\n");
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /*
+ * Size of bitlocks in bytes for the protected address space
+ * with RME_GPT_BITLOCK_BLOCK * 512MB per bitlock.
+ */
+ locks_size = GPT_PPS_ACTUAL_SIZE(gpt_config.t) /
+ (RME_GPT_BITLOCK_BLOCK * SZ_512M * 8U);
+
+ /*
+ * If protected space size is less than the size covered
+ * by 'bitlock' structure, check for a single bitlock.
+ */
+ if (locks_size < LOCK_SIZE) {
+ locks_size = LOCK_SIZE;
+ }
+#endif
+ /* Check size for L0 tables and bitlocks */
+ if (l0_mem_size < (GPT_L0_TABLE_SIZE(gpt_config.t) + locks_size)) {
+ ERROR("GPT: Inadequate L0 memory\n");
ERROR(" Expected 0x%lx bytes, got 0x%lx bytes\n",
- GPT_L0_TABLE_SIZE(gpt_config.t),
- l0_mem_size);
+ GPT_L0_TABLE_SIZE(gpt_config.t) + locks_size,
+ l0_mem_size);
return -ENOMEM;
}
@@ -397,9 +598,10 @@
/* Make sure enough space was supplied */
if (l1_mem_size < l1_gpt_mem_sz) {
- ERROR("%sL1 GPTs%s", "GPT: Inadequate ", " memory\n");
+ ERROR("%sL1 GPTs%s", (const char *)"GPT: Inadequate ",
+ (const char *)" memory\n");
ERROR(" Expected 0x%lx bytes, got 0x%lx bytes\n",
- l1_gpt_mem_sz, l1_mem_size);
+ l1_gpt_mem_sz, l1_mem_size);
return -ENOMEM;
}
@@ -418,8 +620,7 @@
static void generate_l0_blk_desc(pas_region_t *pas)
{
uint64_t gpt_desc;
- unsigned int end_idx;
- unsigned int idx;
+ unsigned long idx, end_idx;
uint64_t *l0_gpt_arr;
assert(gpt_config.plat_gpt_l0_base != 0U);
@@ -448,7 +649,7 @@
/* Generate the needed block descriptors */
for (; idx < end_idx; idx++) {
l0_gpt_arr[idx] = gpt_desc;
- VERBOSE("GPT: L0 entry (BLOCK) index %u [%p]: GPI = 0x%"PRIx64" (0x%"PRIx64")\n",
+ VERBOSE("GPT: L0 entry (BLOCK) index %lu [%p]: GPI = 0x%"PRIx64" (0x%"PRIx64")\n",
idx, &l0_gpt_arr[idx],
(gpt_desc >> GPT_L0_BLK_DESC_GPI_SHIFT) &
GPT_L0_BLK_DESC_GPI_MASK, l0_gpt_arr[idx]);
@@ -482,54 +683,202 @@
return end_pa;
}
- return (cur_idx + 1U) << GPT_L0_IDX_SHIFT;
+ return (cur_idx + 1UL) << GPT_L0_IDX_SHIFT;
}
/*
- * Helper function to fill out GPI entries in a single L1 table. This function
- * fills out entire L1 descriptors at a time to save memory writes.
+ * Helper function to fill out GPI entries from 'first' granule address of
+ * the specified 'length' in a single L1 table with 'l1_desc' Contiguous
+ * descriptor.
*
* Parameters
- * gpi GPI to set this range to
* l1 Pointer to L1 table to fill out
- * first Address of first granule in range.
- * last Address of last granule in range (inclusive).
+ * first Address of first granule in range
+ * length Length of the range in bytes
+ * gpi GPI set this range to
+ *
+ * Return
+ * Address of next granule in range.
*/
-static void fill_l1_tbl(uint64_t gpi, uint64_t *l1, uintptr_t first,
- uintptr_t last)
+static uintptr_t fill_l1_cont_desc(uint64_t *l1, uintptr_t first,
+ size_t length, unsigned int gpi)
{
- uint64_t gpi_field = GPT_BUILD_L1_DESC(gpi);
- uint64_t gpi_mask = ULONG_MAX;
+ /*
+ * Look up table for contiguous blocks and descriptors.
+ * Entries should be defined in descending block sizes:
+ * 512MB, 32MB and 2MB.
+ */
+ static const gpt_fill_lookup_t gpt_fill_lookup[] = {
+#if (RME_GPT_MAX_BLOCK == 512)
+ { SZ_512M, GPT_L1_CONT_DESC_512MB },
+#endif
+#if (RME_GPT_MAX_BLOCK >= 32)
+ { SZ_32M, GPT_L1_CONT_DESC_32MB },
+#endif
+#if (RME_GPT_MAX_BLOCK != 0)
+ { SZ_2M, GPT_L1_CONT_DESC_2MB }
+#endif
+ };
- assert(first <= last);
- assert((first & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) == 0U);
- assert((last & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) == 0U);
- assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
- assert(l1 != NULL);
+ /*
+ * Iterate through all block sizes (512MB, 32MB and 2MB)
+ * starting with maximum supported.
+ */
+ for (unsigned long i = 0UL; i < ARRAY_SIZE(gpt_fill_lookup); i++) {
+ /* Calculate index */
+ unsigned long idx = GPT_L1_INDEX(first);
+
+ /* Contiguous block size */
+ size_t cont_size = gpt_fill_lookup[i].size;
+
+ if (GPT_REGION_IS_CONT(length, first, cont_size)) {
+
+ /* Generate Contiguous descriptor */
+ uint64_t l1_desc = GPT_L1_GPI_CONT_DESC(gpi,
+ gpt_fill_lookup[i].desc);
+
+ /* Number of 128-bit L1 entries in block */
+ unsigned int cnt;
+
+ switch (cont_size) {
+ case SZ_512M:
+ cnt = L1_QWORDS_512MB;
+ break;
+ case SZ_32M:
+ cnt = L1_QWORDS_32MB;
+ break;
+ default: /* SZ_2MB */
+ cnt = L1_QWORDS_2MB;
+ }
+
+ VERBOSE("GPT: Contiguous descriptor 0x%"PRIxPTR" %luMB\n",
+ first, cont_size / SZ_1M);
+
+ /* Fill Contiguous descriptors */
+ fill_desc(&l1[idx], l1_desc, cnt);
+ first += cont_size;
+ length -= cont_size;
+
+ if (length == 0UL) {
+ break;
+ }
+ }
+ }
+
+ return first;
+}
+
+/* Build Granules descriptor with the same 'gpi' for every GPI entry */
+static uint64_t build_l1_desc(unsigned int gpi)
+{
+ uint64_t l1_desc = (uint64_t)gpi | ((uint64_t)gpi << 4);
+
+ l1_desc |= (l1_desc << 8);
+ l1_desc |= (l1_desc << 16);
+ return (l1_desc | (l1_desc << 32));
+}
+
+/*
+ * Helper function to fill out GPI entries from 'first' to 'last' granule
+ * address in a single L1 table with 'l1_desc' Granules descriptor.
+ *
+ * Parameters
+ * l1 Pointer to L1 table to fill out
+ * first Address of first granule in range
+ * last Address of last granule in range (inclusive)
+ * gpi GPI set this range to
+ *
+ * Return
+ * Address of next granule in range.
+ */
+static uintptr_t fill_l1_gran_desc(uint64_t *l1, uintptr_t first,
+ uintptr_t last, unsigned int gpi)
+{
+ uint64_t gpi_mask;
+ unsigned long i;
+
+ /* Generate Granules descriptor */
+ uint64_t l1_desc = build_l1_desc(gpi);
/* Shift the mask if we're starting in the middle of an L1 entry */
- gpi_mask = gpi_mask << (GPT_L1_GPI_IDX(gpt_config.p, first) << 2);
+ gpi_mask = ULONG_MAX << (GPT_L1_GPI_IDX(gpt_config.p, first) << 2);
/* Fill out each L1 entry for this region */
- for (unsigned int i = GPT_L1_IDX(gpt_config.p, first);
- i <= GPT_L1_IDX(gpt_config.p, last); i++) {
+ for (i = GPT_L1_INDEX(first); i <= GPT_L1_INDEX(last); i++) {
+
/* Account for stopping in the middle of an L1 entry */
- if (i == GPT_L1_IDX(gpt_config.p, last)) {
+ if (i == GPT_L1_INDEX(last)) {
gpi_mask &= (gpi_mask >> ((15U -
GPT_L1_GPI_IDX(gpt_config.p, last)) << 2));
}
+ assert((l1[i] & gpi_mask) == (GPT_L1_ANY_DESC & gpi_mask));
+
/* Write GPI values */
- assert((l1[i] & gpi_mask) ==
- (GPT_BUILD_L1_DESC(GPT_GPI_ANY) & gpi_mask));
- l1[i] = (l1[i] & ~gpi_mask) | (gpi_mask & gpi_field);
+ l1[i] = (l1[i] & ~gpi_mask) | (l1_desc & gpi_mask);
/* Reset mask */
gpi_mask = ULONG_MAX;
}
+
+ return last + GPT_PGS_ACTUAL_SIZE(gpt_config.p);
}
/*
+ * Helper function to fill out GPI entries in a single L1 table.
+ * This function fills out an entire L1 table with either Contiguous
+ * or Granules descriptors depending on region length and alignment.
+ *
+ * Parameters
+ * l1 Pointer to L1 table to fill out
+ * first Address of first granule in range
+ * last Address of last granule in range (inclusive)
+ * gpi GPI set this range to
+ */
+static void fill_l1_tbl(uint64_t *l1, uintptr_t first, uintptr_t last,
+ unsigned int gpi)
+{
+ assert(l1 != NULL);
+ assert(first <= last);
+ assert((first & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) == 0UL);
+ assert((last & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) == 0UL);
+ assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
+
+ while (first < last) {
+ /* Region length */
+ size_t length = last - first + GPT_PGS_ACTUAL_SIZE(gpt_config.p);
+
+ if (length < SZ_2M) {
+ /*
+ * Fill with Granule descriptor in case of
+ * region length < 2MB.
+ */
+ first = fill_l1_gran_desc(l1, first, last, gpi);
+
+ } else if ((first & (SZ_2M - UL(1))) == UL(0)) {
+ /*
+ * For region length >= 2MB and at least 2MB aligned
+ * call to fill_l1_cont_desc will iterate through
+ * all block sizes (512MB, 32MB and 2MB) supported and
+ * fill corresponding Contiguous descriptors.
+ */
+ first = fill_l1_cont_desc(l1, first, length, gpi);
+ } else {
+ /*
+ * For not aligned region >= 2MB fill with Granules
+ * descriptors up to the next 2MB aligned address.
+ */
+ uintptr_t new_last = ALIGN_2MB(first + SZ_2M) -
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p);
+
+ first = fill_l1_gran_desc(l1, first, new_last, gpi);
+ }
+ }
+
+ assert(first == (last + GPT_PGS_ACTUAL_SIZE(gpt_config.p)));
+}
+
+/*
* This function finds the next available unused L1 table and initializes all
* granules descriptor entries to GPI_ANY. This ensures that there are no chunks
* of GPI_NO_ACCESS (0b0000) memory floating around in the system in the
@@ -543,16 +892,14 @@
static uint64_t *get_new_l1_tbl(void)
{
/* Retrieve the next L1 table */
- uint64_t *l1 = (uint64_t *)((uint64_t)(gpt_l1_tbl) +
- (GPT_L1_TABLE_SIZE(gpt_config.p) *
- gpt_next_l1_tbl_idx));
+ uint64_t *l1 = (uint64_t *)gpt_l1_tbl;
- /* Increment L1 counter */
- gpt_next_l1_tbl_idx++;
+ /* Increment L1 GPT address */
+ gpt_l1_tbl += GPT_L1_TABLE_SIZE(gpt_config.p);
/* Initialize all GPIs to GPT_GPI_ANY */
for (unsigned int i = 0U; i < GPT_L1_ENTRY_COUNT(gpt_config.p); i++) {
- l1[i] = GPT_BUILD_L1_DESC(GPT_GPI_ANY);
+ l1[i] = GPT_L1_ANY_DESC;
}
return l1;
@@ -573,7 +920,7 @@
uintptr_t last_gran_pa;
uint64_t *l0_gpt_base;
uint64_t *l1_gpt_arr;
- unsigned int l0_idx;
+ unsigned int l0_idx, gpi;
assert(gpt_config.plat_gpt_l0_base != 0U);
assert(pas != NULL);
@@ -582,18 +929,19 @@
* Checking of PAS parameters has already been done in
* validate_pas_mappings so no need to check the same things again.
*/
-
end_pa = pas->base_pa + pas->size;
l0_gpt_base = (uint64_t *)gpt_config.plat_gpt_l0_base;
/* We start working from the granule at base PA */
cur_pa = pas->base_pa;
+ /* Get GPI */
+ gpi = GPT_PAS_ATTR_GPI(pas->attrs);
+
/* Iterate over each L0 region in this memory range */
- for (l0_idx = GPT_L0_IDX(pas->base_pa);
- l0_idx <= GPT_L0_IDX(end_pa - 1U);
+ for (l0_idx = (unsigned int)GPT_L0_IDX(pas->base_pa);
+ l0_idx <= (unsigned int)GPT_L0_IDX(end_pa - 1UL);
l0_idx++) {
-
/*
* See if the L0 entry is already a table descriptor or if we
* need to create one.
@@ -623,8 +971,7 @@
* function needs the addresses of the first granule and last
* granule in the range.
*/
- fill_l1_tbl(GPT_PAS_ATTR_GPI(pas->attrs), l1_gpt_arr,
- cur_pa, last_gran_pa);
+ fill_l1_tbl(l1_gpt_arr, cur_pa, last_gran_pa, gpi);
/* Advance cur_pa to first granule in next L0 region */
cur_pa = get_l1_end_pa(cur_pa, end_pa);
@@ -644,9 +991,9 @@
*/
static void flush_l0_for_pas_array(pas_region_t *pas, unsigned int pas_count)
{
- unsigned int idx;
- unsigned int start_idx;
- unsigned int end_idx;
+ unsigned long idx;
+ unsigned long start_idx;
+ unsigned long end_idx;
uint64_t *l0 = (uint64_t *)gpt_config.plat_gpt_l0_base;
assert(pas != NULL);
@@ -657,7 +1004,7 @@
end_idx = GPT_L0_IDX(pas[0].base_pa + pas[0].size - 1UL);
/* Find lowest and highest L0 indices used in this PAS array */
- for (idx = 1U; idx < pas_count; idx++) {
+ for (idx = 1UL; idx < pas_count; idx++) {
if (GPT_L0_IDX(pas[idx].base_pa) < start_idx) {
start_idx = GPT_L0_IDX(pas[idx].base_pa);
}
@@ -671,7 +1018,7 @@
* the end index value.
*/
flush_dcache_range((uintptr_t)&l0[start_idx],
- ((end_idx + 1U) - start_idx) * sizeof(uint64_t));
+ ((end_idx + 1UL) - start_idx) * sizeof(uint64_t));
}
/*
@@ -767,8 +1114,10 @@
int gpt_init_l0_tables(gpccr_pps_e pps, uintptr_t l0_mem_base,
size_t l0_mem_size)
{
- int ret;
uint64_t gpt_desc;
+ size_t locks_size = 0;
+ __unused bitlock_t *bit_locks;
+ int ret;
/* Ensure that MMU and Data caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
@@ -787,9 +1136,31 @@
((uint64_t *)l0_mem_base)[i] = gpt_desc;
}
- /* Flush updated L0 tables to memory */
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /* Initialise bitlocks at the end of L0 table */
+ bit_locks = (bitlock_t *)(l0_mem_base +
+ GPT_L0_TABLE_SIZE(gpt_config.t));
+
+ /* Size of bitlocks in bytes */
+ locks_size = GPT_PPS_ACTUAL_SIZE(gpt_config.t) /
+ (RME_GPT_BITLOCK_BLOCK * SZ_512M * 8U);
+
+ /*
+ * If protected space size is less than the size covered
+ * by 'bitlock' structure, initialise a single bitlock.
+ */
+ if (locks_size < LOCK_SIZE) {
+ locks_size = LOCK_SIZE;
+ }
+
+ for (size_t i = 0UL; i < (locks_size/LOCK_SIZE); i++) {
+ bit_locks[i].lock = 0U;
+ }
+#endif
+
+ /* Flush updated L0 tables and bitlocks to memory */
flush_dcache_range((uintptr_t)l0_mem_base,
- (size_t)GPT_L0_TABLE_SIZE(gpt_config.t));
+ GPT_L0_TABLE_SIZE(gpt_config.t) + locks_size);
/* Stash the L0 base address once initial setup is complete */
gpt_config.plat_gpt_l0_base = l0_mem_base;
@@ -806,7 +1177,7 @@
* This function can be called multiple times with different L1 memory ranges
* and PAS regions if it is desirable to place L1 tables in different locations
* in memory. (ex: you have multiple DDR banks and want to place the L1 tables
- * in the DDR bank that they control)
+ * in the DDR bank that they control).
*
* Parameters
* pgs PGS value to use for table generation.
@@ -822,8 +1193,7 @@
size_t l1_mem_size, pas_region_t *pas_regions,
unsigned int pas_count)
{
- int ret;
- int l1_gpt_cnt;
+ int l1_gpt_cnt, ret;
/* Ensure that MMU and Data caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
@@ -860,9 +1230,14 @@
/* Set up parameters for L1 table generation */
gpt_l1_tbl = l1_mem_base;
- gpt_next_l1_tbl_idx = 0U;
}
+ /* Number of L1 entries in 2MB depends on GPCCR_EL3.PGS value */
+ gpt_l1_cnt_2mb = (unsigned int)GPT_L1_ENTRY_COUNT_2MB(gpt_config.p);
+
+ /* Mask for the L1 index field */
+ gpt_l1_index_mask = GPT_L1_IDX_MASK(gpt_config.p);
+
INFO("GPT: Boot Configuration\n");
INFO(" PPS/T: 0x%x/%u\n", gpt_config.pps, gpt_config.t);
INFO(" PGS/P: 0x%x/%u\n", gpt_config.pgs, gpt_config.p);
@@ -894,7 +1269,7 @@
if (l1_gpt_cnt > 0) {
flush_dcache_range(l1_mem_base,
GPT_L1_TABLE_SIZE(gpt_config.p) *
- l1_gpt_cnt);
+ (size_t)l1_gpt_cnt);
}
/* Make sure that all the entries are written to the memory */
@@ -946,23 +1321,29 @@
gpt_config.pgs = (reg >> GPCCR_PGS_SHIFT) & GPCCR_PGS_MASK;
gpt_config.p = gpt_p_lookup[gpt_config.pgs];
+ /* Number of L1 entries in 2MB depends on GPCCR_EL3.PGS value */
+ gpt_l1_cnt_2mb = (unsigned int)GPT_L1_ENTRY_COUNT_2MB(gpt_config.p);
+
+ /* Mask for the L1 index field */
+ gpt_l1_index_mask = GPT_L1_IDX_MASK(gpt_config.p);
+
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /* Bitlocks at the end of L0 table */
+ gpt_bitlock_base = (bitlock_t *)(gpt_config.plat_gpt_l0_base +
+ GPT_L0_TABLE_SIZE(gpt_config.t));
+#endif
VERBOSE("GPT: Runtime Configuration\n");
VERBOSE(" PPS/T: 0x%x/%u\n", gpt_config.pps, gpt_config.t);
VERBOSE(" PGS/P: 0x%x/%u\n", gpt_config.pgs, gpt_config.p);
VERBOSE(" L0GPTSZ/S: 0x%x/%u\n", GPT_L0GPTSZ, GPT_S_VAL);
VERBOSE(" L0 base: 0x%"PRIxPTR"\n", gpt_config.plat_gpt_l0_base);
-
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ VERBOSE(" Bitlocks: 0x%"PRIxPTR"\n", (uintptr_t)gpt_bitlock_base);
+#endif
return 0;
}
/*
- * The L1 descriptors are protected by a spinlock to ensure that multiple
- * CPUs do not attempt to change the descriptors at once. In the future it
- * would be better to have separate spinlocks for each L1 descriptor.
- */
-static spinlock_t gpt_lock;
-
-/*
* A helper to write the value (target_pas << gpi_shift) to the index of
* the gpt_l1_addr.
*/
@@ -973,6 +1354,8 @@
*gpt_l1_desc &= ~(GPT_L1_GRAN_DESC_GPI_MASK << gpi_shift);
*gpt_l1_desc |= ((uint64_t)target_pas << gpi_shift);
gpt_l1_addr[idx] = *gpt_l1_desc;
+
+ dsboshst();
}
/*
@@ -982,6 +1365,7 @@
static int get_gpi_params(uint64_t base, gpi_info_t *gpi_info)
{
uint64_t gpt_l0_desc, *gpt_l0_base;
+ __unused unsigned int block_idx;
gpt_l0_base = (uint64_t *)gpt_config.plat_gpt_l0_base;
gpt_l0_desc = gpt_l0_base[GPT_L0_IDX(base)];
@@ -993,19 +1377,311 @@
/* Get the table index and GPI shift from PA */
gpi_info->gpt_l1_addr = GPT_L0_TBLD_ADDR(gpt_l0_desc);
- gpi_info->idx = GPT_L1_IDX(gpt_config.p, base);
+ gpi_info->idx = (unsigned int)GPT_L1_INDEX(base);
gpi_info->gpi_shift = GPT_L1_GPI_IDX(gpt_config.p, base) << 2;
- gpi_info->gpt_l1_desc = (gpi_info->gpt_l1_addr)[gpi_info->idx];
- gpi_info->gpi = (gpi_info->gpt_l1_desc >> gpi_info->gpi_shift) &
- GPT_L1_GRAN_DESC_GPI_MASK;
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /* Block index */
+ block_idx = (unsigned int)(base / (RME_GPT_BITLOCK_BLOCK * SZ_512M));
+
+ /* Bitlock address and mask */
+ gpi_info->lock = &gpt_bitlock_base[block_idx / LOCK_BITS];
+ gpi_info->mask = 1U << (block_idx & (LOCK_BITS - 1U));
+#endif
return 0;
}
/*
+ * Helper to retrieve the gpt_l1_desc and GPI information from gpi_info.
+ * This function is called with bitlock or spinlock acquired.
+ */
+static void read_gpi(gpi_info_t *gpi_info)
+{
+ gpi_info->gpt_l1_desc = (gpi_info->gpt_l1_addr)[gpi_info->idx];
+
+ if ((gpi_info->gpt_l1_desc & GPT_L1_TYPE_CONT_DESC_MASK) ==
+ GPT_L1_TYPE_CONT_DESC) {
+ /* Read GPI from Contiguous descriptor */
+ gpi_info->gpi = (unsigned int)GPT_L1_CONT_GPI(gpi_info->gpt_l1_desc);
+ } else {
+ /* Read GPI from Granules descriptor */
+ gpi_info->gpi = (unsigned int)((gpi_info->gpt_l1_desc >> gpi_info->gpi_shift) &
+ GPT_L1_GRAN_DESC_GPI_MASK);
+ }
+}
+
+static void flush_page_to_popa(uintptr_t addr)
+{
+ size_t size = GPT_PGS_ACTUAL_SIZE(gpt_config.p);
+
+ if (is_feat_mte2_supported()) {
+ flush_dcache_to_popa_range_mte2(addr, size);
+ } else {
+ flush_dcache_to_popa_range(addr, size);
+ }
+}
+
+/*
+ * Helper function to check if all L1 entries in 2MB block have
+ * the same Granules descriptor value.
+ *
+ * Parameters
+ * base Base address of the region to be checked
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor with all entries
+ * set to the same GPI.
+ *
+ * Return
+ * true if L1 all entries have the same descriptor value, false otherwise.
+ */
+__unused static bool check_fuse_2mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* Last L1 entry index in 2MB block */
+ unsigned int long idx = GPT_L1_INDEX(ALIGN_2MB(base)) +
+ gpt_l1_cnt_2mb - 1UL;
+
+ /* Number of L1 entries in 2MB block */
+ unsigned int cnt = gpt_l1_cnt_2mb;
+
+ /*
+ * Start check from the last L1 entry and continue until the first
+ * non-matching to the passed Granules descriptor value is found.
+ */
+ while (cnt-- != 0U) {
+ if (gpi_info->gpt_l1_addr[idx--] != l1_desc) {
+ /* Non-matching L1 entry found */
+ return false;
+ }
+ }
+
+ return true;
+}
+
+__unused static void fuse_2mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* L1 entry index of the start of 2MB block */
+ unsigned long idx_2 = GPT_L1_INDEX(ALIGN_2MB(base));
+
+ /* 2MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB);
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n", __func__, base, l1_desc);
+
+ fill_desc(&gpi_info->gpt_l1_addr[idx_2], l1_cont_desc, L1_QWORDS_2MB);
+}
+
+/*
+ * Helper function to check if all 1st L1 entries of 2MB blocks
+ * in 32MB have the same 2MB Contiguous descriptor value.
+ *
+ * Parameters
+ * base Base address of the region to be checked
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor.
+ *
+ * Return
+ * true if all L1 entries have the same descriptor value, false otherwise.
+ */
+__unused static bool check_fuse_32mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* The 1st L1 entry index of the last 2MB block in 32MB */
+ unsigned long idx = GPT_L1_INDEX(ALIGN_32MB(base)) +
+ (15UL * gpt_l1_cnt_2mb);
+
+ /* 2MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB);
+
+ /* Number of 2MB blocks in 32MB */
+ unsigned int cnt = 16U;
+
+ /* Set the first L1 entry to 2MB Contiguous descriptor */
+ gpi_info->gpt_l1_addr[GPT_L1_INDEX(ALIGN_2MB(base))] = l1_cont_desc;
+
+ /*
+ * Start check from the 1st L1 entry of the last 2MB block and
+ * continue until the first non-matching to 2MB Contiguous descriptor
+ * value is found.
+ */
+ while (cnt-- != 0U) {
+ if (gpi_info->gpt_l1_addr[idx] != l1_cont_desc) {
+ /* Non-matching L1 entry found */
+ return false;
+ }
+ idx -= gpt_l1_cnt_2mb;
+ }
+
+ return true;
+}
+
+__unused static void fuse_32mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* L1 entry index of the start of 32MB block */
+ unsigned long idx_32 = GPT_L1_INDEX(ALIGN_32MB(base));
+
+ /* 32MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB);
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n", __func__, base, l1_desc);
+
+ fill_desc(&gpi_info->gpt_l1_addr[idx_32], l1_cont_desc, L1_QWORDS_32MB);
+}
+
+/*
+ * Helper function to check if all 1st L1 entries of 32MB blocks
+ * in 512MB have the same 32MB Contiguous descriptor value.
+ *
+ * Parameters
+ * base Base address of the region to be checked
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor.
+ *
+ * Return
+ * true if all L1 entries have the same descriptor value, false otherwise.
+ */
+__unused static bool check_fuse_512mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* The 1st L1 entry index of the last 32MB block in 512MB */
+ unsigned long idx = GPT_L1_INDEX(ALIGN_512MB(base)) +
+ (15UL * 16UL * gpt_l1_cnt_2mb);
+
+ /* 32MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB);
+
+ /* Number of 32MB blocks in 512MB */
+ unsigned int cnt = 16U;
+
+ /* Set the first L1 entry to 2MB Contiguous descriptor */
+ gpi_info->gpt_l1_addr[GPT_L1_INDEX(ALIGN_32MB(base))] = l1_cont_desc;
+
+ /*
+ * Start check from the 1st L1 entry of the last 32MB block and
+ * continue until the first non-matching to 32MB Contiguous descriptor
+ * value is found.
+ */
+ while (cnt-- != 0U) {
+ if (gpi_info->gpt_l1_addr[idx] != l1_cont_desc) {
+ /* Non-matching L1 entry found */
+ return false;
+ }
+ idx -= 16UL * gpt_l1_cnt_2mb;
+ }
+
+ return true;
+}
+
+__unused static void fuse_512mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* L1 entry index of the start of 512MB block */
+ unsigned long idx_512 = GPT_L1_INDEX(ALIGN_512MB(base));
+
+ /* 512MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 512MB);
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n", __func__, base, l1_desc);
+
+ fill_desc(&gpi_info->gpt_l1_addr[idx_512], l1_cont_desc, L1_QWORDS_512MB);
+}
+
+/*
+ * Helper function to convert GPI entries in a single L1 table
+ * from Granules to Contiguous descriptor.
+ *
+ * Parameters
+ * base Base address of the region to be written
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor with all entries
+ * set to the same GPI.
+ */
+__unused static void fuse_block(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* Start with check for 2MB block */
+ if (!check_fuse_2mb(base, gpi_info, l1_desc)) {
+ /* Check for 2MB fusing failed */
+ return;
+ }
+
+#if (RME_GPT_MAX_BLOCK == 2)
+ fuse_2mb(base, gpi_info, l1_desc);
+#else
+ /* Check for 32MB block */
+ if (!check_fuse_32mb(base, gpi_info, l1_desc)) {
+ /* Check for 32MB fusing failed, fuse to 2MB */
+ fuse_2mb(base, gpi_info, l1_desc);
+ return;
+ }
+
+#if (RME_GPT_MAX_BLOCK == 32)
+ fuse_32mb(base, gpi_info, l1_desc);
+#else
+ /* Check for 512MB block */
+ if (!check_fuse_512mb(base, gpi_info, l1_desc)) {
+ /* Check for 512MB fusing failed, fuse to 32MB */
+ fuse_32mb(base, gpi_info, l1_desc);
+ return;
+ }
+
+ /* Fuse to 512MB */
+ fuse_512mb(base, gpi_info, l1_desc);
+
+#endif /* RME_GPT_MAX_BLOCK == 32 */
+#endif /* RME_GPT_MAX_BLOCK == 2 */
+}
+
+/*
+ * Helper function to convert GPI entries in a single L1 table
+ * from Contiguous to Granules descriptor. This function updates
+ * descriptor to Granules in passed 'gpt_config_t' structure as
+ * the result of shuttering.
+ *
+ * Parameters
+ * base Base address of the region to be written
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor set this range to.
+ */
+__unused static void shatter_block(uint64_t base, gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* Look-up table for 2MB, 32MB and 512MB locks shattering */
+ static const gpt_shatter_func gpt_shatter_lookup[] = {
+ shatter_2mb,
+ shatter_32mb,
+ shatter_512mb
+ };
+
+ /* Look-up table for invalidation TLBs for 2MB, 32MB and 512MB blocks */
+ static const gpt_tlbi_lookup_t tlbi_lookup[] = {
+ { tlbirpalos_2m, ~(SZ_2M - 1UL) },
+ { tlbirpalos_32m, ~(SZ_32M - 1UL) },
+ { tlbirpalos_512m, ~(SZ_512M - 1UL) }
+ };
+
+ /* Get shattering level from Contig field of Contiguous descriptor */
+ unsigned long level = GPT_L1_CONT_CONTIG(gpi_info->gpt_l1_desc) - 1UL;
+
+ /* Shatter contiguous block */
+ gpt_shatter_lookup[level](base, gpi_info, l1_desc);
+
+ tlbi_lookup[level].function(base & tlbi_lookup[level].mask);
+ dsbosh();
+
+ /*
+ * Update 'gpt_config_t' structure's descriptor to Granules to reflect
+ * the shattered GPI back to caller.
+ */
+ gpi_info->gpt_l1_desc = l1_desc;
+}
+
+/*
* This function is the granule transition delegate service. When a granule
* transition request occurs it is routed to this function to have the request,
- * if valid, fulfilled following A1.1.1 Delegate of RME supplement
+ * if valid, fulfilled following A1.1.1 Delegate of RME supplement.
*
* TODO: implement support for transitioning multiple granules at once.
*
@@ -1022,9 +1698,9 @@
int gpt_delegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
{
gpi_info_t gpi_info;
- uint64_t nse;
- int res;
+ uint64_t nse, __unused l1_desc;
unsigned int target_pas;
+ int res;
/* Ensure that the tables have been set up before taking requests */
assert(gpt_config.plat_gpt_l0_base != 0UL);
@@ -1032,10 +1708,6 @@
/* Ensure that caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
- /* Delegate request can only come from REALM or SECURE */
- assert(src_sec_state == SMC_FROM_REALM ||
- src_sec_state == SMC_FROM_SECURE);
-
/* See if this is a single or a range of granule transition */
if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
return -EINVAL;
@@ -1060,70 +1732,80 @@
return -EINVAL;
}
+ /* Delegate request can only come from REALM or SECURE */
+ if ((src_sec_state != SMC_FROM_REALM) &&
+ (src_sec_state != SMC_FROM_SECURE)) {
+ VERBOSE("GPT: Invalid caller security state 0x%x\n",
+ src_sec_state);
+ return -EINVAL;
+ }
+
- target_pas = GPT_GPI_REALM;
- if (src_sec_state == SMC_FROM_SECURE) {
+ if (src_sec_state == SMC_FROM_REALM) {
+ target_pas = GPT_GPI_REALM;
+ nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
+ l1_desc = GPT_L1_REALM_DESC;
+ } else {
target_pas = GPT_GPI_SECURE;
+ nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
+ l1_desc = GPT_L1_SECURE_DESC;
}
- /*
- * Access to L1 tables is controlled by a global lock to ensure
- * that no more than one CPU is allowed to make changes at any
- * given time.
- */
- spin_lock(&gpt_lock);
res = get_gpi_params(base, &gpi_info);
if (res != 0) {
- spin_unlock(&gpt_lock);
return res;
}
+ /*
+ * Access to GPT is controlled by a lock to ensure that no more
+ * than one CPU is allowed to make changes at any given time.
+ */
+ GPT_LOCK;
+ read_gpi(&gpi_info);
+
/* Check that the current address is in NS state */
if (gpi_info.gpi != GPT_GPI_NS) {
VERBOSE("GPT: Only Granule in NS state can be delegated.\n");
VERBOSE(" Caller: %u, Current GPI: %u\n", src_sec_state,
gpi_info.gpi);
- spin_unlock(&gpt_lock);
+ GPT_UNLOCK;
return -EPERM;
}
- if (src_sec_state == SMC_FROM_SECURE) {
- nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
- } else {
- nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
+#if (RME_GPT_MAX_BLOCK != 0)
+ /* Check for Contiguous descriptor */
+ if ((gpi_info.gpt_l1_desc & GPT_L1_TYPE_CONT_DESC_MASK) ==
+ GPT_L1_TYPE_CONT_DESC) {
+ shatter_block(base, &gpi_info, GPT_L1_NS_DESC);
}
-
+#endif
/*
* In order to maintain mutual distrust between Realm and Secure
* states, remove any data speculatively fetched into the target
- * physical address space. Issue DC CIPAPA over address range.
+ * physical address space.
+ * Issue DC CIPAPA or DC_CIGDPAPA on implementations with FEAT_MTE2.
*/
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- }
+ flush_page_to_popa(base | nse);
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
gpi_info.gpi_shift, gpi_info.idx, target_pas);
- dsboshst();
- gpt_tlbi_by_pa_ll(base, GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- dsbosh();
+ /* Ensure that all agents observe the new configuration */
+ tlbi_page_dsbosh(base);
nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ /* Ensure that the scrubbed data have made it past the PoPA */
+ flush_page_to_popa(base | nse);
+
+#if (RME_GPT_MAX_BLOCK != 0)
+ if (gpi_info.gpt_l1_desc == l1_desc) {
+ /* Try to fuse */
+ fuse_block(base, &gpi_info, l1_desc);
}
+#endif
- /* Unlock access to the L1 tables */
- spin_unlock(&gpt_lock);
+ /* Unlock the lock to GPT */
+ GPT_UNLOCK;
/*
* The isb() will be done as part of context
@@ -1155,7 +1837,7 @@
int gpt_undelegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
{
gpi_info_t gpi_info;
- uint64_t nse;
+ uint64_t nse, __unused l1_desc;
int res;
/* Ensure that the tables have been set up before taking requests */
@@ -1164,10 +1846,6 @@
/* Ensure that MMU and caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
- /* Delegate request can only come from REALM or SECURE */
- assert(src_sec_state == SMC_FROM_REALM ||
- src_sec_state == SMC_FROM_SECURE);
-
/* See if this is a single or a range of granule transition */
if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
return -EINVAL;
@@ -1192,84 +1870,80 @@
return -EINVAL;
}
- /*
- * Access to L1 tables is controlled by a global lock to ensure
- * that no more than one CPU is allowed to make changes at any
- * given time.
- */
- spin_lock(&gpt_lock);
-
res = get_gpi_params(base, &gpi_info);
if (res != 0) {
- spin_unlock(&gpt_lock);
return res;
}
+ /*
+ * Access to GPT is controlled by a lock to ensure that no more
+ * than one CPU is allowed to make changes at any given time.
+ */
+ GPT_LOCK;
+ read_gpi(&gpi_info);
+
/* Check that the current address is in the delegated state */
- if ((src_sec_state == SMC_FROM_REALM &&
- gpi_info.gpi != GPT_GPI_REALM) ||
- (src_sec_state == SMC_FROM_SECURE &&
- gpi_info.gpi != GPT_GPI_SECURE)) {
- VERBOSE("GPT: Only Granule in REALM or SECURE state can be undelegated.\n");
+ if ((src_sec_state == SMC_FROM_REALM) &&
+ (gpi_info.gpi == GPT_GPI_REALM)) {
+ l1_desc = GPT_L1_REALM_DESC;
+ nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
+ } else if ((src_sec_state == SMC_FROM_SECURE) &&
+ (gpi_info.gpi == GPT_GPI_SECURE)) {
+ l1_desc = GPT_L1_SECURE_DESC;
+ nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
+ } else {
+ VERBOSE("GPT: Only Granule in REALM or SECURE state can be undelegated\n");
VERBOSE(" Caller: %u Current GPI: %u\n", src_sec_state,
gpi_info.gpi);
- spin_unlock(&gpt_lock);
+ GPT_UNLOCK;
return -EPERM;
}
-
- /* In order to maintain mutual distrust between Realm and Secure
+#if (RME_GPT_MAX_BLOCK != 0)
+ /* Check for Contiguous descriptor */
+ if ((gpi_info.gpt_l1_desc & GPT_L1_TYPE_CONT_DESC_MASK) ==
+ GPT_L1_TYPE_CONT_DESC) {
+ shatter_block(base, &gpi_info, l1_desc);
+ }
+#endif
+ /*
+ * In order to maintain mutual distrust between Realm and Secure
* states, remove access now, in order to guarantee that writes
* to the currently-accessible physical address space will not
* later become observable.
*/
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
gpi_info.gpi_shift, gpi_info.idx, GPT_GPI_NO_ACCESS);
- dsboshst();
- gpt_tlbi_by_pa_ll(base, GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- dsbosh();
-
- if (src_sec_state == SMC_FROM_SECURE) {
- nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
- } else {
- nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
- }
+ /* Ensure that all agents observe the new NO_ACCESS configuration */
+ tlbi_page_dsbosh(base);
- /* Ensure that the scrubbed data has made it past the PoPA */
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- }
+ /* Ensure that the scrubbed data have made it past the PoPA */
+ flush_page_to_popa(base | nse);
/*
- * Remove any data loaded speculatively
- * in NS space from before the scrubbing
+ * Remove any data loaded speculatively in NS space from before
+ * the scrubbing.
*/
nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- }
+ flush_page_to_popa(base | nse);
- /* Clear existing GPI encoding and transition granule. */
+ /* Clear existing GPI encoding and transition granule */
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
gpi_info.gpi_shift, gpi_info.idx, GPT_GPI_NS);
- dsboshst();
/* Ensure that all agents observe the new NS configuration */
- gpt_tlbi_by_pa_ll(base, GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- dsbosh();
+ tlbi_page_dsbosh(base);
- /* Unlock access to the L1 tables. */
- spin_unlock(&gpt_lock);
+#if (RME_GPT_MAX_BLOCK != 0)
+ if (gpi_info.gpt_l1_desc == GPT_L1_NS_DESC) {
+ /* Try to fuse */
+ fuse_block(base, &gpi_info, GPT_L1_NS_DESC);
+ }
+#endif
+ /* Unlock the lock to GPT */
+ GPT_UNLOCK;
/*
* The isb() will be done as part of context
diff --git a/lib/gpt_rme/gpt_rme.mk b/lib/gpt_rme/gpt_rme.mk
index 60176f4..7d6b61f 100644
--- a/lib/gpt_rme/gpt_rme.mk
+++ b/lib/gpt_rme/gpt_rme.mk
@@ -1,8 +1,22 @@
#
-# Copyright (c) 2021, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
+# Process RME_GPT_BITLOCK_BLOCK value
+ifeq ($(filter 0 1 2 4 8 16 32 64 128 256 512, ${RME_GPT_BITLOCK_BLOCK}),)
+ $(error "Invalid value for RME_GPT_BITLOCK_BLOCK: ${RME_GPT_BITLOCK_BLOCK}")
+endif
+
+ifeq (${RME_GPT_BITLOCK_BLOCK},0)
+ $(warning "GPT library uses global spinlock")
+endif
+
+# Process RME_GPT_MAX_BLOCK value
+ifeq ($(filter 0 2 32 512, ${RME_GPT_MAX_BLOCK}),)
+ $(error "Invalid value for RME_GPT_MAX_BLOCK: ${RME_GPT_MAX_BLOCK}")
+endif
+
GPT_LIB_SRCS := $(addprefix lib/gpt_rme/, \
gpt_rme.c)
diff --git a/lib/gpt_rme/gpt_rme_private.h b/lib/gpt_rme/gpt_rme_private.h
index b2a5dae..31dad20 100644
--- a/lib/gpt_rme/gpt_rme_private.h
+++ b/lib/gpt_rme/gpt_rme_private.h
@@ -9,6 +9,7 @@
#include <arch.h>
#include <lib/gpt_rme/gpt_rme.h>
+#include <lib/spinlock.h>
#include <lib/utils_def.h>
/******************************************************************************/
@@ -19,7 +20,7 @@
#define GPT_L0_TYPE_MASK UL(0xF)
#define GPT_L0_TYPE_SHIFT U(0)
-/* For now, we don't support contiguous descriptors, only table and block */
+/* GPT level 0 table and block descriptors */
#define GPT_L0_TYPE_TBL_DESC UL(3)
#define GPT_L0_TYPE_BLK_DESC UL(1)
@@ -29,29 +30,63 @@
#define GPT_L0_BLK_DESC_GPI_MASK UL(0xF)
#define GPT_L0_BLK_DESC_GPI_SHIFT U(4)
-/* GPT level 1 descriptor bit definitions */
+/* GPT level 1 Contiguous descriptor */
+#define GPT_L1_TYPE_CONT_DESC_MASK UL(0xF)
+#define GPT_L1_TYPE_CONT_DESC UL(1)
+
+/* GPT level 1 Contiguous descriptor definitions */
+#define GPT_L1_CONTIG_2MB UL(1)
+#define GPT_L1_CONTIG_32MB UL(2)
+#define GPT_L1_CONTIG_512MB UL(3)
+
+#define GPT_L1_CONT_DESC_GPI_SHIFT U(4)
+#define GPT_L1_CONT_DESC_GPI_MASK UL(0xF)
+#define GPT_L1_CONT_DESC_CONTIG_SHIFT U(8)
+#define GPT_L1_CONT_DESC_CONTIG_MASK UL(3)
+
+/* GPT level 1 Granules descriptor bit definitions */
#define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF)
+/* L1 Contiguous descriptors templates */
+#define GPT_L1_CONT_DESC_2MB \
+ (GPT_L1_TYPE_CONT_DESC | \
+ (GPT_L1_CONTIG_2MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
+#define GPT_L1_CONT_DESC_32MB \
+ (GPT_L1_TYPE_CONT_DESC | \
+ (GPT_L1_CONTIG_32MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
+#define GPT_L1_CONT_DESC_512MB \
+ (GPT_L1_TYPE_CONT_DESC | \
+ (GPT_L1_CONTIG_512MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
+
+/* Create L1 Contiguous descriptor from GPI and template */
+#define GPT_L1_GPI_CONT_DESC(_gpi, _desc) \
+ ((_desc) | ((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT))
+
+/* Create L1 Contiguous descriptor from Granules descriptor and size */
+#define GPT_L1_CONT_DESC(_desc, _size) \
+ (GPT_L1_CONT_DESC_##_size | \
+ (((_desc) & GPT_L1_GRAN_DESC_GPI_MASK) << \
+ GPT_L1_CONT_DESC_GPI_SHIFT))
+
+/* Create L1 Contiguous descriptor from GPI and size */
+#define GPT_L1_CONT_DESC_SIZE(_gpi, _size) \
+ (GPT_L1_CONT_DESC_##_size | \
+ (((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT))
+
+#define GPT_L1_GPI_BYTE(_gpi) (uint64_t)((_gpi) | ((_gpi) << 4))
+#define GPT_L1_GPI_HALF(_gpi) (GPT_L1_GPI_BYTE(_gpi) | (GPT_L1_GPI_BYTE(_gpi) << 8))
+#define GPT_L1_GPI_WORD(_gpi) (GPT_L1_GPI_HALF(_gpi) | (GPT_L1_GPI_HALF(_gpi) << 16))
+
/*
- * This macro fills out every GPI entry in a granules descriptor to the same
- * value.
+ * This macro generates a Granules descriptor
+ * with the same value for every GPI entry.
*/
-#define GPT_BUILD_L1_DESC(_gpi) (((uint64_t)(_gpi) << 4*0) | \
- ((uint64_t)(_gpi) << 4*1) | \
- ((uint64_t)(_gpi) << 4*2) | \
- ((uint64_t)(_gpi) << 4*3) | \
- ((uint64_t)(_gpi) << 4*4) | \
- ((uint64_t)(_gpi) << 4*5) | \
- ((uint64_t)(_gpi) << 4*6) | \
- ((uint64_t)(_gpi) << 4*7) | \
- ((uint64_t)(_gpi) << 4*8) | \
- ((uint64_t)(_gpi) << 4*9) | \
- ((uint64_t)(_gpi) << 4*10) | \
- ((uint64_t)(_gpi) << 4*11) | \
- ((uint64_t)(_gpi) << 4*12) | \
- ((uint64_t)(_gpi) << 4*13) | \
- ((uint64_t)(_gpi) << 4*14) | \
- ((uint64_t)(_gpi) << 4*15))
+#define GPT_BUILD_L1_DESC(_gpi) (GPT_L1_GPI_WORD(_gpi) | (GPT_L1_GPI_WORD(_gpi) << 32))
+
+#define GPT_L1_SECURE_DESC GPT_BUILD_L1_DESC(GPT_GPI_SECURE)
+#define GPT_L1_NS_DESC GPT_BUILD_L1_DESC(GPT_GPI_NS)
+#define GPT_L1_REALM_DESC GPT_BUILD_L1_DESC(GPT_GPI_REALM)
+#define GPT_L1_ANY_DESC GPT_BUILD_L1_DESC(GPT_GPI_ANY)
/******************************************************************************/
/* GPT platform configuration */
@@ -106,17 +141,46 @@
PGS_64KB_P = 16U
} gpt_p_val_e;
+#define LOCK_SIZE sizeof(((bitlock_t *)NULL)->lock)
+#define LOCK_TYPE typeof(((bitlock_t *)NULL)->lock)
+#define LOCK_BITS (LOCK_SIZE * 8U)
+
/*
- * Internal structure to retrieve the values from get_gpi_info();
+ * Internal structure to retrieve the values from get_gpi_params();
*/
-typedef struct gpi_info {
+typedef struct {
uint64_t gpt_l1_desc;
uint64_t *gpt_l1_addr;
unsigned int idx;
unsigned int gpi_shift;
unsigned int gpi;
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ bitlock_t *lock;
+ LOCK_TYPE mask;
+#endif
} gpi_info_t;
+/*
+ * Look up structure for contiguous blocks and descriptors
+ */
+typedef struct {
+ size_t size;
+ unsigned int desc;
+} gpt_fill_lookup_t;
+
+typedef void (*gpt_shatter_func)(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+typedef void (*gpt_tlbi_func)(uintptr_t base);
+
+/*
+ * Look-up structure for
+ * invalidating TLBs of GPT entries by Physical address, last level.
+ */
+typedef struct {
+ gpt_tlbi_func function;
+ size_t mask;
+} gpt_tlbi_lookup_t;
+
/* Max valid value for PGS */
#define GPT_PGS_MAX (2U)
@@ -136,8 +200,8 @@
* special case we'll get a negative width value which does not make sense and
* would cause problems.
*/
-#define GPT_L0_IDX_WIDTH(_t) (((_t) > GPT_S_VAL) ? \
- ((_t) - GPT_S_VAL) : (0U))
+#define GPT_L0_IDX_WIDTH(_t) (((unsigned int)(_t) > GPT_S_VAL) ? \
+ ((unsigned int)(_t) - GPT_S_VAL) : (0U))
/* Bit shift for the L0 index field in a PA */
#define GPT_L0_IDX_SHIFT (GPT_S_VAL)
@@ -173,10 +237,11 @@
* the L0 index field above since all valid combinations of PGS (p) and L0GPTSZ
* (s) will result in a positive width value.
*/
-#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - ((_p) + 3U))
+#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - \
+ ((unsigned int)(_p) + 3U))
/* Bit shift for the L1 index field */
-#define GPT_L1_IDX_SHIFT(_p) ((_p) + 4U)
+#define GPT_L1_IDX_SHIFT(_p) ((unsigned int)(_p) + 4U)
/*
* Mask for the L1 index field, must be shifted.
@@ -196,7 +261,10 @@
#define GPT_L1_GPI_IDX_MASK (0xF)
/* Total number of entries in each L1 table */
-#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1U)
+#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1UL)
+
+/* Number of L1 entries in 2MB block */
+#define GPT_L1_ENTRY_COUNT_2MB(_p) (SZ_2M >> GPT_L1_IDX_SHIFT(_p))
/* Total size in bytes of each L1 table */
#define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U)
@@ -206,10 +274,13 @@
/******************************************************************************/
/* Protected space actual size in bytes */
-#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (_t))
+#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (unsigned int)(_t))
/* Granule actual size in bytes */
-#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (_p))
+#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (unsigned int)(_p))
+
+/* Number of granules in 2MB block */
+#define GPT_PGS_COUNT_2MB(_p) (1UL << (21U - (unsigned int)(_p)))
/* L0 GPT region size in bytes */
#define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL)
@@ -221,7 +292,8 @@
* This definition is used to determine if a physical address lies on an L0
* region boundary.
*/
-#define GPT_IS_L0_ALIGNED(_pa) (((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0))
+#define GPT_IS_L0_ALIGNED(_pa) \
+ (((_pa) & (GPT_L0_REGION_SIZE - UL(1))) == UL(0))
/* Get the type field from an L0 descriptor */
#define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \
@@ -246,16 +318,43 @@
(GPT_L0_TBL_DESC_L1ADDR_MASK << \
GPT_L0_TBL_DESC_L1ADDR_SHIFT))))
+/* Get the GPI from L1 Contiguous descriptor */
+#define GPT_L1_CONT_GPI(_desc) \
+ (((_desc) >> GPT_L1_CONT_DESC_GPI_SHIFT) & GPT_L1_CONT_DESC_GPI_MASK)
+
+/* Get the GPI from L1 Granules descriptor */
+#define GPT_L1_GRAN_GPI(_desc) ((_desc) & GPT_L1_GRAN_DESC_GPI_MASK)
+
+/* Get the Contig from L1 Contiguous descriptor */
+#define GPT_L1_CONT_CONTIG(_desc) \
+ (((_desc) >> GPT_L1_CONT_DESC_CONTIG_SHIFT) & \
+ GPT_L1_CONT_DESC_CONTIG_MASK)
+
/* Get the index into the L1 table from a physical address */
-#define GPT_L1_IDX(_p, _pa) (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \
- GPT_L1_IDX_MASK(_p))
+#define GPT_L1_IDX(_p, _pa) \
+ (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & GPT_L1_IDX_MASK(_p))
/* Get the index of the GPI within an L1 table entry from a physical address */
-#define GPT_L1_GPI_IDX(_p, _pa) (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \
- GPT_L1_GPI_IDX_MASK)
+#define GPT_L1_GPI_IDX(_p, _pa) \
+ (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & GPT_L1_GPI_IDX_MASK)
/* Determine if an address is granule-aligned */
-#define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \
- == U(0))
+#define GPT_IS_L1_ALIGNED(_p, _pa) \
+ (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - UL(1))) == UL(0))
+
+/* Get aligned addresses */
+#define ALIGN_2MB(_addr) ((_addr) & ~(SZ_2M - 1UL))
+#define ALIGN_32MB(_addr) ((_addr) & ~(SZ_32M - 1UL))
+#define ALIGN_512MB(_addr) ((_addr) & ~(SZ_512M - 1UL))
+
+/* Determine if region is contiguous */
+#define GPT_REGION_IS_CONT(_len, _addr, _size) \
+ (((_len) >= (_size)) && (((_addr) & ((_size) - UL(1))) == UL(0)))
+
+/* Get 32MB block number in 512MB block: 0-15 */
+#define GET_32MB_NUM(_addr) ((_addr >> 25) & 0xF)
+
+/* Get 2MB block number in 32MB block: 0-15 */
+#define GET_2MB_NUM(_addr) ((_addr >> 21) & 0xF)
#endif /* GPT_RME_PRIVATE_H */
diff --git a/lib/libfdt/libfdt.mk b/lib/libfdt/libfdt.mk
index 812057d..c7f5404 100644
--- a/lib/libfdt/libfdt.mk
+++ b/lib/libfdt/libfdt.mk
@@ -1,19 +1,23 @@
#
-# Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-LIBFDT_SRCS := $(addprefix lib/libfdt/, \
- fdt.c \
- fdt_addresses.c \
- fdt_empty_tree.c \
- fdt_ro.c \
- fdt_rw.c \
- fdt_strerror.c \
- fdt_sw.c \
- fdt_wip.c) \
+ifndef libfdt-mk
+ libfdt-mk := 1
-INCLUDES += -Iinclude/lib/libfdt
+ LIBFDT_SRCS := $(addprefix lib/libfdt/, \
+ fdt.c \
+ fdt_addresses.c \
+ fdt_empty_tree.c \
+ fdt_ro.c \
+ fdt_rw.c \
+ fdt_strerror.c \
+ fdt_sw.c \
+ fdt_wip.c)
+
+ INCLUDES += -Iinclude/lib/libfdt
-$(eval $(call MAKE_LIB,fdt))
+ $(eval $(call MAKE_LIB,fdt))
+endif
diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c
index f3dd112..ac7f53a 100644
--- a/lib/pmf/pmf_smc.c
+++ b/lib/pmf/pmf_smc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,7 +36,8 @@
x2 = (uint32_t)x2;
x3 = (uint32_t)x3;
- if (smc_fid == PMF_SMC_GET_TIMESTAMP_32) {
+ if (smc_fid == PMF_SMC_GET_TIMESTAMP_32 ||
+ smc_fid == PMF_SMC_GET_TIMESTAMP_32_DEP) {
/*
* Return error code and the captured
* time-stamp to the caller.
@@ -48,8 +49,13 @@
SMC_RET3(handle, rc, (uint32_t)ts_value,
(uint32_t)(ts_value >> 32));
}
+
+ if (smc_fid == PMF_SMC_GET_VERSION_32) {
+ SMC_RET2(handle, SMC_OK, PMF_SMC_VERSION);
+ }
} else {
- if (smc_fid == PMF_SMC_GET_TIMESTAMP_64) {
+ if (smc_fid == PMF_SMC_GET_TIMESTAMP_64 ||
+ smc_fid == PMF_SMC_GET_TIMESTAMP_64_DEP) {
/*
* Return error code and the captured
* time-stamp to the caller.
@@ -60,6 +66,10 @@
(unsigned int)x3, &ts_value);
SMC_RET2(handle, rc, ts_value);
}
+
+ if (smc_fid == PMF_SMC_GET_VERSION_64) {
+ SMC_RET2(handle, SMC_OK, PMF_SMC_VERSION);
+ }
}
WARN("Unimplemented PMF Call: 0x%x \n", smc_fid);
diff --git a/lib/psa/delegated_attestation.c b/lib/psa/delegated_attestation.c
index 81e2621..805a941 100644
--- a/lib/psa/delegated_attestation.c
+++ b/lib/psa/delegated_attestation.c
@@ -10,7 +10,7 @@
#include <psa_manifest/sid.h>
psa_status_t
-rss_delegated_attest_get_delegated_key(uint8_t ecc_curve,
+rse_delegated_attest_get_delegated_key(uint8_t ecc_curve,
uint32_t key_bits,
uint8_t *key_buf,
size_t key_buf_size,
@@ -31,8 +31,8 @@
return PSA_ERROR_INVALID_ARGUMENT;
}
- status = psa_call(RSS_DELEGATED_SERVICE_HANDLE,
- RSS_DELEGATED_ATTEST_GET_DELEGATED_KEY,
+ status = psa_call(RSE_DELEGATED_SERVICE_HANDLE,
+ RSE_DELEGATED_ATTEST_GET_DELEGATED_KEY,
in_vec, IOVEC_LEN(in_vec),
out_vec, IOVEC_LEN(out_vec));
if (status == PSA_SUCCESS) {
@@ -43,7 +43,7 @@
}
psa_status_t
-rss_delegated_attest_get_token(const uint8_t *dak_pub_hash,
+rse_delegated_attest_get_token(const uint8_t *dak_pub_hash,
size_t dak_pub_hash_size,
uint8_t *token_buf,
size_t token_buf_size,
@@ -61,8 +61,8 @@
return PSA_ERROR_INVALID_ARGUMENT;
}
- status = psa_call(RSS_DELEGATED_SERVICE_HANDLE,
- RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN,
+ status = psa_call(RSE_DELEGATED_SERVICE_HANDLE,
+ RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN,
in_vec, IOVEC_LEN(in_vec),
out_vec, IOVEC_LEN(out_vec));
if (status == PSA_SUCCESS) {
diff --git a/lib/psa/dice_protection_environment.c b/lib/psa/dice_protection_environment.c
index 44a5848..2145611 100644
--- a/lib/psa/dice_protection_environment.c
+++ b/lib/psa/dice_protection_environment.c
@@ -258,7 +258,7 @@
{ cmd_output, *cmd_output_size },
};
- err = psa_call(RSS_DPE_SERVICE_HANDLE, 0,
+ err = psa_call(RSE_DPE_SERVICE_HANDLE, 0,
in_vec, IOVEC_LEN(in_vec), out_vec, IOVEC_LEN(out_vec));
if (err == PSA_SUCCESS) {
diff --git a/lib/psa/measured_boot.c b/lib/psa/measured_boot.c
index ff1f45d..c66b8da 100644
--- a/lib/psa/measured_boot.c
+++ b/lib/psa/measured_boot.c
@@ -63,7 +63,7 @@
}
psa_status_t
-rss_measured_boot_extend_measurement(uint8_t index,
+rse_measured_boot_extend_measurement(uint8_t index,
const uint8_t *signer_id,
size_t signer_id_size,
const uint8_t *version,
@@ -115,13 +115,13 @@
measurement_algo, measurement_value,
measurement_value_size, lock_measurement);
- return psa_call(RSS_MEASURED_BOOT_HANDLE,
- RSS_MEASURED_BOOT_EXTEND,
+ return psa_call(RSE_MEASURED_BOOT_HANDLE,
+ RSE_MEASURED_BOOT_EXTEND,
in_vec, IOVEC_LEN(in_vec),
NULL, 0);
}
-psa_status_t rss_measured_boot_read_measurement(uint8_t index,
+psa_status_t rse_measured_boot_read_measurement(uint8_t index,
uint8_t *signer_id,
size_t signer_id_size,
size_t *signer_id_len,
@@ -158,7 +158,7 @@
{.base = measurement_value, .len = measurement_value_size}
};
- status = psa_call(RSS_MEASURED_BOOT_HANDLE, RSS_MEASURED_BOOT_READ,
+ status = psa_call(RSE_MEASURED_BOOT_HANDLE, RSE_MEASURED_BOOT_READ,
in_vec, IOVEC_LEN(in_vec),
out_vec, IOVEC_LEN(out_vec));
diff --git a/lib/psa/measured_boot_private.h b/lib/psa/measured_boot_private.h
index b8ca31d..bf2ae48 100644
--- a/lib/psa/measured_boot_private.h
+++ b/lib/psa/measured_boot_private.h
@@ -13,8 +13,8 @@
#include <drivers/measured_boot/metadata.h>
/* Measured boot message types that distinguish its services */
-#define RSS_MEASURED_BOOT_READ 1001U
-#define RSS_MEASURED_BOOT_EXTEND 1002U
+#define RSE_MEASURED_BOOT_READ 1001U
+#define RSE_MEASURED_BOOT_EXTEND 1002U
struct measured_boot_read_iovec_in_t {
uint8_t index;
diff --git a/lib/psa/rse_platform.c b/lib/psa/rse_platform.c
new file mode 100644
index 0000000..7fc2382
--- /dev/null
+++ b/lib/psa/rse_platform.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <psa/client.h>
+#include <psa_manifest/sid.h>
+#include <rse_crypto_defs.h>
+#include <rse_platform_api.h>
+
+psa_status_t
+rse_platform_nv_counter_increment(uint32_t counter_id)
+{
+ struct psa_invec in_vec[1];
+
+ in_vec[0].base = &counter_id;
+ in_vec[0].len = sizeof(counter_id);
+
+ return psa_call(RSE_PLATFORM_SERVICE_HANDLE,
+ RSE_PLATFORM_API_ID_NV_INCREMENT,
+ in_vec, 1, NULL, 0);
+}
+
+psa_status_t
+rse_platform_nv_counter_read(uint32_t counter_id,
+ uint32_t size, uint8_t *val)
+{
+ struct psa_invec in_vec[1];
+ struct psa_outvec out_vec[1];
+
+ in_vec[0].base = &counter_id;
+ in_vec[0].len = sizeof(counter_id);
+
+ out_vec[0].base = val;
+ out_vec[0].len = size;
+
+ return psa_call(RSE_PLATFORM_SERVICE_HANDLE,
+ RSE_PLATFORM_API_ID_NV_READ,
+ in_vec, 1, out_vec, 1);
+}
+
+psa_status_t
+rse_platform_key_read(enum rse_key_id_builtin_t key, uint8_t *data,
+ size_t data_size, size_t *data_length)
+{
+ psa_status_t status;
+
+ struct rse_crypto_pack_iovec iov = {
+ .function_id = RSE_CRYPTO_EXPORT_PUBLIC_KEY_SID,
+ .key_id = key,
+ };
+
+ psa_invec in_vec[] = {
+ {.base = &iov, .len = sizeof(struct rse_crypto_pack_iovec)},
+ };
+ psa_outvec out_vec[] = {
+ {.base = data, .len = data_size}
+ };
+
+ status = psa_call(RSE_CRYPTO_HANDLE, PSA_IPC_CALL,
+ in_vec, IOVEC_LEN(in_vec),
+ out_vec, IOVEC_LEN(out_vec));
+
+ *data_length = out_vec[0].len;
+
+ return status;
+}
diff --git a/lib/psa/rss_platform.c b/lib/psa/rss_platform.c
deleted file mode 100644
index 7d90bfc..0000000
--- a/lib/psa/rss_platform.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- */
-
-#include <psa/client.h>
-#include <psa_manifest/sid.h>
-#include <rss_crypto_defs.h>
-#include <rss_platform_api.h>
-
-psa_status_t
-rss_platform_nv_counter_increment(uint32_t counter_id)
-{
- struct psa_invec in_vec[1];
-
- in_vec[0].base = &counter_id;
- in_vec[0].len = sizeof(counter_id);
-
- return psa_call(RSS_PLATFORM_SERVICE_HANDLE,
- RSS_PLATFORM_API_ID_NV_INCREMENT,
- in_vec, 1, NULL, 0);
-}
-
-psa_status_t
-rss_platform_nv_counter_read(uint32_t counter_id,
- uint32_t size, uint8_t *val)
-{
- struct psa_invec in_vec[1];
- struct psa_outvec out_vec[1];
-
- in_vec[0].base = &counter_id;
- in_vec[0].len = sizeof(counter_id);
-
- out_vec[0].base = val;
- out_vec[0].len = size;
-
- return psa_call(RSS_PLATFORM_SERVICE_HANDLE,
- RSS_PLATFORM_API_ID_NV_READ,
- in_vec, 1, out_vec, 1);
-}
-
-psa_status_t
-rss_platform_key_read(enum rss_key_id_builtin_t key, uint8_t *data,
- size_t data_size, size_t *data_length)
-{
- psa_status_t status;
-
- struct rss_crypto_pack_iovec iov = {
- .function_id = RSS_CRYPTO_EXPORT_PUBLIC_KEY_SID,
- .key_id = key,
- };
-
- psa_invec in_vec[] = {
- {.base = &iov, .len = sizeof(struct rss_crypto_pack_iovec)},
- };
- psa_outvec out_vec[] = {
- {.base = data, .len = data_size}
- };
-
- status = psa_call(RSS_CRYPTO_HANDLE, PSA_IPC_CALL,
- in_vec, IOVEC_LEN(in_vec),
- out_vec, IOVEC_LEN(out_vec));
-
- *data_length = out_vec[0].len;
-
- return status;
-}
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index bd7a452..60449f6 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -665,6 +665,8 @@
}
goto exit;
}
+
+ parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
}
/*
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 62cbf3e..1293f06 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -4,7 +4,11 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := aarch64
+ifeq ($(filter-out clean,$(or $(MAKECMDGOALS),all)),)
+ toolchains :=
+else
+ toolchains := aarch64
+endif
include ../../make_helpers/toolchain.mk
diff --git a/lib/transfer_list/transfer_list.mk b/lib/transfer_list/transfer_list.mk
index 42574e8..3ec4df2 100644
--- a/lib/transfer_list/transfer_list.mk
+++ b/lib/transfer_list/transfer_list.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -15,6 +15,7 @@
BL31_SOURCES += $(TRANSFER_LIST_SOURCES)
BL2_SOURCES += $(TRANSFER_LIST_SOURCES)
+BL1_SOURCES += $(TRANSFER_LIST_SOURCES)
endif # TRANSFER_LIST
diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
index 5a2120b..b462de0 100644
--- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
+++ b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,7 +27,7 @@
{
uintptr_t ret;
- if (is_armv8_4_ttst_present()) {
+ if (is_feat_ttst_present()) {
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
} else {
ret = MIN_VIRT_ADDR_SPACE_SIZE;
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index 4dbfc11..f4195f4 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -87,7 +87,7 @@
{
uintptr_t ret;
- if (is_armv8_4_ttst_present())
+ if (is_feat_ttst_present())
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
else
ret = MIN_VIRT_ADDR_SPACE_SIZE;
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
index 920754b..b63543c 100644
--- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -248,7 +248,7 @@
/* Set TTBR0 bits as well */
ttbr0 = (uint64_t)(uintptr_t) base_table;
- if (is_armv8_2_ttcnp_present()) {
+ if (is_feat_ttcnp_present()) {
/* Enable CnP bit so as to share page tables with all PEs. */
ttbr0 |= TTBR_CNP_BIT;
}
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index bb6a35c..18e001b 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,19 +22,14 @@
*/
bool xlat_arch_is_granule_size_supported(size_t size)
{
- unsigned int tgranx;
-
if (size == PAGE_SIZE_4KB) {
- tgranx = read_id_aa64mmfr0_el0_tgran4_field();
/* MSB of TGRAN4 field will be '1' for unsupported feature */
- return (tgranx < 8U);
+ return is_feat_tgran4K_present();
} else if (size == PAGE_SIZE_16KB) {
- tgranx = read_id_aa64mmfr0_el0_tgran16_field();
- return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED);
+ return is_feat_tgran16K_present();
} else if (size == PAGE_SIZE_64KB) {
- tgranx = read_id_aa64mmfr0_el0_tgran64_field();
/* MSB of TGRAN64 field will be '1' for unsupported feature */
- return (tgranx < 8U);
+ return is_feat_tgran64K_present();
} else {
return false;
}
@@ -135,7 +130,7 @@
{
uintptr_t ret;
- if (is_armv8_4_ttst_present())
+ if (is_feat_ttst_present())
ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
else
ret = MIN_VIRT_ADDR_SPACE_SIZE;
@@ -312,7 +307,7 @@
/* Set TTBR bits as well */
ttbr0 = (uint64_t) base_table;
- if (is_armv8_2_ttcnp_present()) {
+ if (is_feat_ttcnp_present()) {
/* Enable CnP bit so as to share page tables with all PEs. */
ttbr0 |= TTBR_CNP_BIT;
}
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index 3a9c058..971dba4 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -214,7 +214,7 @@
/* Set GP bit for block and page code entries
* if BTI mechanism is implemented.
*/
- if (is_armv8_5_bti_present() &&
+ if (is_feat_bti_present() &&
((attr & (MT_TYPE_MASK | MT_RW |
MT_EXECUTE_NEVER)) == MT_CODE)) {
desc |= GP;
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 36ac126..cf4595c 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -438,11 +438,6 @@
$(notdir $(patsubst %.S,%.o,$(filter %.S,$(1))))
endef
-# Allow overriding the timestamp, for example for reproducible builds, or to
-# synchronize timestamps across multiple projects.
-# This must be set to a C string (including quotes where applicable).
-BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__
-
.PHONY: libraries
# MAKE_LIB_DIRS macro defines the target for the directory where
@@ -562,30 +557,19 @@
$(ELF): $(OBJS) $(DEFAULT_LINKER_SCRIPT) $(LINKER_SCRIPTS) | $(1)_dirs libraries $(BL_LIBS)
$$(ECHO) " LD $$@"
-ifdef MAKE_BUILD_STRINGS
- $(call MAKE_BUILD_STRINGS,$(BUILD_DIR)/build_message.o)
-else
- @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); \
- const char version_string[] = "${VERSION_STRING}"; \
- const char version[] = "${VERSION}";' | \
- $($(ARCH)-cc) $$(TF_CFLAGS) $$(CFLAGS) -xc -c - -o $(BUILD_DIR)/build_message.o
-endif
ifeq ($($(ARCH)-ld-id),arm-link)
$$(Q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) --entry=${1}_entrypoint \
--predefine="-D__LINKER__=$(__LINKER__)" \
--predefine="-DTF_CFLAGS=$(TF_CFLAGS)" \
--map --list="$(MAPFILE)" --scatter=${PLAT_DIR}/scat/${1}.scat \
- $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) \
- $(BUILD_DIR)/build_message.o $(OBJS)
+ $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) $(OBJS)
else ifeq ($($(ARCH)-ld-id),gnu-gcc)
$$(Q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Wl,-Map=$(MAPFILE) \
$(addprefix -Wl$(comma)--script$(comma),$(LINKER_SCRIPTS)) -Wl,--script,$(DEFAULT_LINKER_SCRIPT) \
- $(BUILD_DIR)/build_message.o \
$(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS)
else
$$(Q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Map=$(MAPFILE) \
$(addprefix -T ,$(LINKER_SCRIPTS)) --script $(DEFAULT_LINKER_SCRIPT) \
- $(BUILD_DIR)/build_message.o \
$(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS)
endif
ifeq ($(DISABLE_BIN_GENERATION),1)
@@ -660,12 +644,14 @@
# Dependencies of the DT compilation on its pre-compiled DTS
$(eval DTBDEP := $(patsubst %.dtb,%.d,$(DOBJ)))
-$(DOBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs
+$(DPRE): $(2) | fdt_dirs
$${ECHO} " CPP $$<"
$(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2))))
$$(Q)$($(ARCH)-cpp) -E $$(TF_CFLAGS_$(ARCH)) $$(DTC_CPPFLAGS) -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$<
+
+$(DOBJ): $(DPRE) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs
$${ECHO} " DTC $$<"
- $$(Q)$($(ARCH)-dtc) $$(DTC_FLAGS) -d $(DTBDEP) -o $$@ $(DPRE)
+ $$(Q)$($(ARCH)-dtc) $$(DTC_FLAGS) -d $(DTBDEP) -o $$@ $$<
-include $(DTBDEP)
-include $(DTSDEP)
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 26d2a00..a5c78ae 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2016-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -139,6 +139,12 @@
# For Chain of Trust
GENERATE_COT := 0
+# Default number of 512 blocks per bitlock
+RME_GPT_BITLOCK_BLOCK := 1
+
+# Default maximum size of GPT contiguous block
+RME_GPT_MAX_BLOCK := 2
+
# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
# default, they are for Secure EL1.
GICV2_G0_FOR_EL3 := 0
@@ -392,3 +398,10 @@
# Enable context memory usage reporting during BL31 setup.
PLATFORM_REPORT_CTX_MEM_USE := 0
+
+# Enable early console
+EARLY_CONSOLE := 0
+
+# Allow platforms to save/restore DSU PMU registers over a power cycle.
+# Disabled by default and must be enabled by individual platforms.
+PRESERVE_DSU_PMU_REGS := 0
diff --git a/make_helpers/march.mk b/make_helpers/march.mk
index 25bb936..8e73116 100644
--- a/make_helpers/march.mk
+++ b/make_helpers/march.mk
@@ -21,7 +21,7 @@
# armv8.6-a armv8.7-a armv8.8-a armv8-r armv9-a
# [...]
#
-GCC_MARCH_OUTPUT := $(shell $($(ARCH)-cc) -march=foo -Q --help=target -v 2>&1)
+GCC_MARCH_OUTPUT := $(if $($(ARCH)-cc),$(shell $($(ARCH)-cc) -march=foo -Q --help=target -v 2>&1))
# This function is used to find the best march value supported by the given compiler.
# We try to use `GCC_MARCH_OUTPUT` which has verbose message with supported march values we filter that
diff --git a/make_helpers/toolchain.mk b/make_helpers/toolchain.mk
index 2f47647..96e43a8 100644
--- a/make_helpers/toolchain.mk
+++ b/make_helpers/toolchain.mk
@@ -8,334 +8,339 @@
# TF-A uses three toolchains:
#
# - The host toolchain (`host`) for building native tools
-# - The AArch32 toolchain (`aarch32`) for building Arm AArch32 images
+# - The AArch32 toolchain (`aarch32`) for building Arm AArch32 images
# - The AArch64 toolchain (`aarch64`) for building Arm AArch64 images
#
# In the main Makefile only one of the two Arm toolchains is enabled in any
# given build, but individual tools and libraries may need access to both.
#
-toolchains ?= host $(ARCH)
+ifndef toolchain-mk
+ toolchain-mk := $(lastword $(MAKEFILE_LIST))
-ifneq ($(filter host,$(toolchains)),)
- host-cc := $(HOSTCC)
- host-cpp := $(HOSTCPP)
+ toolchains ?= host $(ARCH)
- host-as := $(HOSTAS)
+ include $(dir $(lastword $(MAKEFILE_LIST)))build_env.mk
+ include $(dir $(lastword $(MAKEFILE_LIST)))utilities.mk
- host-ld := $(HOSTLD)
- host-oc := $(HOSTOC)
- host-od := $(HOSTOD)
- host-ar := $(HOSTAR)
+ include $(addprefix $(dir $(lastword $(MAKEFILE_LIST)))toolchains/, \
+ $(addsuffix .mk,$(toolchains)))
- host-dtc := $(HOSTDTC)
-endif
+ #
+ # Configure tool classes that we recognize.
+ #
+ # In the context of this build system, a tool class identifies a
+ # specific role or type of tool in the toolchain.
+ #
-ifneq ($(filter aarch32,$(toolchains)),)
- aarch32-cc := $(if $(filter-out default,$(origin CC)),$(CC))
- aarch32-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
+ tool-classes := cc
+ tool-class-name-cc := C compiler
- aarch32-as := $(if $(filter-out default,$(origin AS)),$(AS))
+ tool-classes += cpp
+ tool-class-name-cpp := C preprocessor
- aarch32-ld := $(if $(filter-out default,$(origin LD)),$(LD))
- aarch32-oc := $(if $(filter-out default,$(origin OC)),$(OC))
- aarch32-od := $(if $(filter-out default,$(origin OD)),$(OD))
- aarch32-ar := $(if $(filter-out default,$(origin AR)),$(AR))
+ tool-classes += as
+ tool-class-name-as := assembler
- aarch32-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
-endif
+ tool-classes += ld
+ tool-class-name-ld := linker
-ifneq ($(filter aarch64,$(toolchains)),)
- aarch64-cc := $(if $(filter-out default,$(origin CC)),$(CC))
- aarch64-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
+ tool-classes += oc
+ tool-class-name-oc := object copier
- aarch64-as := $(if $(filter-out default,$(origin AS)),$(AS))
+ tool-classes += od
+ tool-class-name-od := object dumper
- aarch64-ld := $(if $(filter-out default,$(origin LD)),$(LD))
- aarch64-oc := $(if $(filter-out default,$(origin OC)),$(OC))
- aarch64-od := $(if $(filter-out default,$(origin OD)),$(OD))
- aarch64-ar := $(if $(filter-out default,$(origin AR)),$(AR))
+ tool-classes += ar
+ tool-class-name-ar := archiver
- aarch64-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
-endif
+ tool-classes += dtc
+ tool-class-name-dtc := device tree compiler
-include $(dir $(lastword $(MAKEFILE_LIST)))build_env.mk
-include $(dir $(lastword $(MAKEFILE_LIST)))utilities.mk
+ #
+ # Configure tools that we recognize.
+ #
+ # Here we declare the list of specific toolchain tools that we know how
+ # to interact with. We don't organize these into tool classes yet - that
+ # happens further down.
+ #
-include $(addprefix $(dir $(lastword $(MAKEFILE_LIST)))toolchains/, \
- $(addsuffix .mk,$(toolchains)))
+ # Arm® Compiler for Embedded
+ tools := arm-clang
+ tool-name-arm-clang := Arm® Compiler for Embedded `armclang`
-#
-# Configure tool classes that we recognize.
-#
-# In the context of this build system, a tool class identifies a specific role
-# or type of tool in the toolchain.
-#
+ tools += arm-link
+ tool-name-arm-link := Arm® Compiler for Embedded `armlink`
-# C-related tools
-tool-classes := cc # C compilers
-tool-classes += cpp # C preprocessors
+ tools += arm-ar
+ tool-name-arm-ar := Arm® Compiler for Embedded `armar`
-# Assembly-related tools
-tool-classes += as # Assemblers
+ tools += arm-fromelf
+ tool-name-arm-fromelf := Arm® Compiler for Embedded `fromelf`
-# Linking and object-handling tools
-tool-classes += ld # Linkers
-tool-classes += oc # Object copiers
-tool-classes += od # Object dumpers
-tool-classes += ar # Archivers
+ # LLVM Project
+ tools += llvm-clang
+ tool-name-llvm-clang := LLVM Clang (`clang`)
-# Other tools
-tool-classes += dtc # Device tree compilers
+ tools += llvm-lld
+ tool-name-llvm-lld := LLVM LLD (`lld`)
-#
-# Configure tools that we recognize.
-#
-# Here we declare the list of specific toolchain tools that we know how to
-# interact with. We don't organize these into tool classes yet - that happens
-# further down.
-#
+ tools += llvm-objcopy
+ tool-name-llvm-objcopy := LLVM `llvm-objcopy`
-# Arm Compiler for Embedded
-tools := arm-clang # armclang
-tools += arm-link # armlink
-tools += arm-ar # armar
-tools += arm-fromelf # fromelf
+ tools += llvm-objdump
+ tool-name-llvm-objdump := LLVM `llvm-objdump`
-# LLVM Project
-tools += llvm-clang # clang
-tools += llvm-lld # lld
-tools += llvm-objcopy # llvm-objcopy
-tools += llvm-objdump # llvm-objdump
-tools += llvm-ar # llvm-ar
+ tools += llvm-ar
+ tool-name-llvm-ar := LLVM `llvm-ar`
-# GNU Compiler Collection & GNU Binary Utilities
-tools += gnu-gcc # gcc
-tools += gnu-ld # ld
-tools += gnu-objcopy # objcopy
-tools += gnu-objdump # objdump
-tools += gnu-ar # gcc-ar
+ # GNU Compiler Collection & GNU Binary Utilities
+ tools += gnu-gcc
+ tool-name-gnu-gcc := GNU GCC (`gcc`)
-# Other tools
-tools += dtc # Device Tree Compiler
+ tools += gnu-ld
+ tool-name-gnu-ld := GNU LD (`ld.bfd`)
-#
-# Assign tools to tool classes.
-#
-# Multifunctional tools, i.e. tools which can perform multiple roles in a
-# toolchain, may be specified in multiple tool class lists. For example, a C
-# compiler which can also perform the role of a linker may be placed in both
-# `tools-cc` and `tools-ld`.
-#
+ tools += gnu-objcopy
+ tool-name-gnu-objcopy := GNU `objcopy`
-# C-related tools
-tools-cc := arm-clang llvm-clang gnu-gcc # C compilers
-tools-cpp := arm-clang llvm-clang gnu-gcc # C preprocessors
+ tools += gnu-objdump
+ tool-name-gnu-objdump := GNU `objdump`
-# Assembly-related tools
-tools-as := arm-clang llvm-clang gnu-gcc # Assemblers
+ tools += gnu-ar
+ tool-name-gnu-ar := GNU `ar`
-# Linking and object-handling tools
-tools-ld := arm-clang arm-link llvm-clang llvm-lld gnu-gcc gnu-ld # Linkers
-tools-oc := arm-fromelf llvm-objcopy gnu-objcopy # Object copiers
-tools-od := arm-fromelf llvm-objdump gnu-objdump # Object dumpers
-tools-ar := arm-ar llvm-ar gnu-ar # Archivers
+ # Other tools
+ tools += generic-dtc
+ tool-name-generic-dtc := Device Tree Compiler (`dtc`)
-# Other tools
-tools-dtc := dtc # Device tree compilers
+ #
+ # Assign tools to tool classes.
+ #
+ # Multifunctional tools, i.e. tools which can perform multiple roles in
+ # a toolchain, may be specified in multiple tool class lists. For
+ # example, a C compiler which can also perform the role of a linker may
+ # be placed in both `tools-cc` and `tools-ld`.
+ #
-define check-tool-class-tools
- $(eval tool-class := $(1))
+ # C-related tools
+ tools-cc := arm-clang llvm-clang gnu-gcc # C compilers
+ tools-cpp := arm-clang llvm-clang gnu-gcc # C preprocessors
- ifndef tools-$(tool-class)
- $$(error no tools registered to handle tool class `$(tool-class)`)
- endif
-endef
+ # Assembly-related tools
+ tools-as := arm-clang llvm-clang gnu-gcc # Assemblers
-$(foreach tool-class,$(tool-classes), \
- $(eval $(call check-tool-class-tools,$(tool-class))))
+ # Linking and object-handling tools
+ tools-ld := arm-clang arm-link llvm-clang llvm-lld gnu-gcc gnu-ld # Linkers
+ tools-oc := arm-fromelf llvm-objcopy gnu-objcopy # Object copiers
+ tools-od := arm-fromelf llvm-objdump gnu-objdump # Object dumpers
+ tools-ar := arm-ar llvm-ar gnu-ar # Archivers
-#
-# Default tools for each toolchain.
-#
-# Toolchains can specify a default path to any given tool with a tool class.
-# These values are used in the absence of user-specified values, and are
-# configured by the makefile for each toolchain using variables of the form:
-#
-# - $(toolchain)-$(tool-class)-default
-#
-# For example, the default C compiler for the AArch32 and AArch64 toolchains
-# could be configured with:
-#
-# - aarch32-cc-default
-# - aarch64-cc-default
-#
+ # Other tools
+ tools-dtc := generic-dtc # Device tree compilers
-define check-toolchain-tool-class-default
- $(eval toolchain := $(1))
- $(eval tool-class := $(2))
+ define check-tool-class-tools
+ $(eval tool-class := $(1))
- ifndef $(toolchain)-$(tool-class)-default
- $$(error no default value specified for tool class `$(tool-class)` of toolchain `$(toolchain)`)
- endif
-endef
-
-define check-toolchain-tool-class-defaults
- $(eval toolchain := $(1))
+ ifndef tools-$(tool-class)
+ $$(error no tools registered to handle tool class `$(tool-class)`)
+ endif
+ endef
$(foreach tool-class,$(tool-classes), \
- $(eval $(call check-toolchain-tool-class-default,$(toolchain),$(tool-class))))
-endef
+ $(eval $(call check-tool-class-tools,$(tool-class))))
-$(foreach toolchain,$(toolchains), \
- $(eval $(call check-toolchain-tool-class-defaults,$(toolchain))))
+ #
+ # Default tools for each toolchain.
+ #
+ # Toolchains can specify a default path to any given tool with a tool
+ # class. These values are used in the absence of user-specified values,
+ # and are configured by the makefile for each toolchain using variables
+ # of the form:
+ #
+ # - $(toolchain)-$(tool-class)-default
+ #
+ # For example, the default C compiler for the AArch32 and AArch64
+ # toolchains could be configured with:
+ #
+ # - aarch32-cc-default
+ # - aarch64-cc-default
+ #
-#
-# Helper functions to identify toolchain tools.
-#
-# The functions defined in this section return a tool identifier when given a
-# path to a binary. We generally check a help or version string to more reliably
-# identify tools than by looking at the path alone (e.g. `gcc` on macOS is
-# actually Apple Clang).
-#
-# Each tool-guessing function (`guess-tool-$(tool)`) takes a single argument
-# giving the path to the tool to guess, and returns a non-empty value if the
-# tool corresponds to the tool identifier `$(tool)`:
-#
-# $(call guess-tool-llvm-clang,aarch64-none-elf-gcc) # <empty>
-# $(call guess-tool-gnu-gcc,aarch64-none-elf-gcc) # <non-empty>
-#
-# The `guess-tool` function tries to find the corresponding tool identifier
-# for a tool given its path. It takes two arguments:
-#
-# - $(1): a list of candidate tool identifiers to check
-# - $(2): the path to the tool to identify
-#
-# If any of the guess functions corresponding to candidate tool identifiers
-# return a non-empty value then the tool identifier of the first function to do
-# so is returned:
-#
-# $(call guess-tool,gnu-gcc llvm-clang,armclang) # <empty>
-# $(call guess-tool,gnu-gcc llvm-clang,clang-14) # llvm-clang
-# $(call guess-tool,gnu-gcc llvm-clang,aarch64-none-elf-gcc-12) # gnu-gcc
-#
-# Tools are checked in the order that they appear in `tools-$(tool-class)`, and
-# the first match is returned.
-#
+ define check-toolchain-tool-class-default
+ $(eval toolchain := $(1))
+ $(eval tool-class := $(2))
-# Arm Compiler for Embedded
-guess-tool-arm-clang = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Tool: armclang")
-guess-tool-arm-link = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "Tool: armlink")
-guess-tool-arm-fromelf = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "Tool: fromelf")
-guess-tool-arm-ar = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Tool: armar")
+ ifndef $(toolchain)-$(tool-class)-default
+ $$(error no default value specified for tool class `$(tool-class)` of toolchain `$(toolchain)`)
+ endif
+ endef
-# LLVM Project
-guess-tool-llvm-clang = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "clang version")
-guess-tool-llvm-lld = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "OVERVIEW: lld")
-guess-tool-llvm-objcopy = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "llvm-objcopy tool")
-guess-tool-llvm-objdump = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "llvm object file dumper")
-guess-tool-llvm-ar = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "LLVM Archiver")
+ define check-toolchain-tool-class-defaults
+ $(eval toolchain := $(1))
-# GNU Compiler Collection & GNU Binary Utilities
-guess-tool-gnu-gcc = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "gcc version")
-guess-tool-gnu-ld = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "GNU ld")
-guess-tool-gnu-objcopy = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU objcopy")
-guess-tool-gnu-objdump = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU objdump")
-guess-tool-gnu-ar = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU ar")
+ $(foreach tool-class,$(tool-classes), \
+ $(eval $(call check-toolchain-tool-class-default,$(toolchain),$(tool-class))))
+ endef
-# Other tools
-guess-tool-dtc = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Version: DTC")
+ $(foreach toolchain,$(toolchains), \
+ $(eval $(call check-toolchain-tool-class-defaults,$(toolchain))))
-guess-tool = $(firstword $(foreach candidate,$(1), \
- $(if $(call guess-tool-$(candidate),$(2)),$(candidate))))
+ #
+ # Helper functions to identify toolchain tools.
+ #
+ # The functions defined in this section return a tool identifier when
+ # given a path to a binary. We generally check a help or version string
+ # to more reliably identify tools than by looking at the path alone
+ # (e.g. `gcc` on macOS is actually Apple Clang).
+ #
+ # Each tool-guessing function (`guess-tool-$(tool)`) takes a single
+ # argument giving the path to the tool to guess, and returns a non-empty
+ # value if the tool corresponds to the tool identifier `$(tool)`:
+ #
+ # $(call guess-tool-llvm-clang,aarch64-none-elf-gcc) # <empty>
+ # $(call guess-tool-gnu-gcc,aarch64-none-elf-gcc) # <non-empty>
+ #
+ # The `guess-tool` function tries to find the corresponding tool
+ # identifier for a tool given its path. It takes two arguments:
+ #
+ # - $(1): a list of candidate tool identifiers to check
+ # - $(2): the path to the tool to identify
+ #
+ # If any of the guess functions corresponding to candidate tool
+ # identifiers return a non-empty value then the tool identifier of the
+ # first function to do so is returned:
+ #
+ # $(call guess-tool,gnu-gcc llvm-clang,armclang) # <empty>
+ # $(call guess-tool,gnu-gcc llvm-clang,clang-14) # llvm-clang
+ # $(call guess-tool,gnu-gcc llvm-clang,aarch64-none-elf-gcc-12) # gnu-gcc
+ #
+ # Tools are checked in the order that they appear in
+ # `tools-$(tool-class)`, and the first match is returned.
+ #
-#
-# Locate and identify tools belonging to each toolchain.
-#
-# Each tool class in each toolchain receives a variable of the form
-# `$(toolchain)-$(tool)` giving the associated path to the program. For example:
-#
-# - `aarch64-ld` gives the linker for the AArch64 toolchain,
-# - `aarch32-oc` gives the object copier for the AArch32 toolchain, and
-# - `host-cc` gives the C compiler for the host toolchain.
-#
-# For each of these variables, if no program path is explicitly provided by the
-# parent Makefile then the C compiler is queried (if supported) for its
-# location. This is done via the `guess-$(tool)-$(tool-class)` set of functions.
-# For example:
-#
-# - `guess-arm-clang-ld` guesses the linker via Arm Clang,
-# - `guess-llvm-clang-as` guesses the assembler via LLVM Clang, and
-# - `guess-gnu-gcc-od` guesses the object dumper via GNU GCC.
-#
-# If the C compiler cannot provide the location (or the tool class is the C
-# compiler), then it is assigned the value of the `$(toolchain)-$(tool)-default`
-# variable.
-#
+ # Arm Compiler for Embedded
+ guess-tool-arm-clang = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armclang")
+ guess-tool-arm-link = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: armlink")
+ guess-tool-arm-fromelf = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: fromelf")
+ guess-tool-arm-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armar")
-guess-arm-clang-cpp = $(1)
-guess-arm-clang-as = $(1)
-guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
-guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
-guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
-guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
+ # LLVM Project
+ guess-tool-llvm-clang = $(shell $(1) -v 2>&1 <$(nul) | grep -o "clang version")
+ guess-tool-llvm-lld = $(shell $(1) --help 2>&1 <$(nul) | grep -o "OVERVIEW: lld")
+ guess-tool-llvm-objcopy = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm-objcopy tool")
+ guess-tool-llvm-objdump = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm object file dumper")
+ guess-tool-llvm-ar = $(shell $(1) --help 2>&1 <$(nul) | grep -o "LLVM Archiver")
-guess-llvm-clang-cpp = $(1)
-guess-llvm-clang-as = $(1)
-guess-llvm-clang-ld = $(shell $(call escape-shell,$(1)) --print-prog-name ld.lld 2>$(nul))
-guess-llvm-clang-oc = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-objcopy 2>$(nul))
-guess-llvm-clang-od = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-objdump 2>$(nul))
-guess-llvm-clang-ar = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-ar 2>$(nul))
+ # GNU Compiler Collection & GNU Binary Utilities
+ guess-tool-gnu-gcc = $(shell $(1) -v 2>&1 <$(nul) | grep -o "gcc version")
+ guess-tool-gnu-ld = $(shell $(1) -v 2>&1 <$(nul) | grep -o "GNU ld")
+ guess-tool-gnu-objcopy = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objcopy")
+ guess-tool-gnu-objdump = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objdump")
+ guess-tool-gnu-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU ar")
-guess-gnu-gcc-cpp = $(1)
-guess-gnu-gcc-as = $(1)
-guess-gnu-gcc-ld = $(1)
-guess-gnu-gcc-oc = $(shell $(call escape-shell,$(1)) --print-prog-name objcopy 2>$(nul))
-guess-gnu-gcc-od = $(shell $(call escape-shell,$(1)) --print-prog-name objdump 2>$(nul))
-guess-gnu-gcc-ar = $(call which,$(call decompat-path,$(patsubst %$(call file-name,$(1)),%$(subst gcc,gcc-ar,$(call file-name,$(1))),$(call compat-path,$(1)))))
+ # Other tools
+ guess-tool-generic-dtc = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Version: DTC")
-define locate-toolchain-tool-cc
- $(eval toolchain := $(1))
+ guess-tool = $(firstword $(foreach candidate,$(1), \
+ $(if $(call guess-tool-$(candidate),$(2)),$(candidate))))
- $(toolchain)-cc := $$(or $$($(toolchain)-cc),$$($(toolchain)-cc-default))
- $(toolchain)-cc-id := $$(call guess-tool,$$(tools-cc),$$($(toolchain)-cc))
-endef
+ #
+ # Locate and identify tools belonging to each toolchain.
+ #
+ # Each tool class in each toolchain receives a variable of the form
+ # `$(toolchain)-$(tool)` giving the associated path to the program. For
+ # example:
+ #
+ # - `aarch64-ld` gives the linker for the AArch64 toolchain,
+ # - `aarch32-oc` gives the object copier for the AArch32 toolchain, and
+ # - `host-cc` gives the C compiler for the host toolchain.
+ #
+ # For each of these variables, if no program path is explicitly provided
+ # by the parent Makefile then the C compiler is queried (if supported)
+ # for its location. This is done via the `guess-$(tool)-$(tool-class)`
+ # set of functions. For example:
+ #
+ # - `guess-arm-clang-ld` guesses the linker via Arm Clang,
+ # - `guess-llvm-clang-as` guesses the assembler via LLVM Clang, and
+ # - `guess-gnu-gcc-od` guesses the object dumper via GNU GCC.
+ #
+ # If the C compiler cannot provide the location (or the tool class is
+ # the C compiler), then it is assigned the value of the
+ # `$(toolchain)-$(tool)-default` variable.
+ #
-define locate-toolchain-tool
- $(eval toolchain := $(1))
- $(eval tool-class := $(2))
+ guess-arm-clang-cpp = $(1)
+ guess-arm-clang-as = $(1)
+ guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
+ guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
+ guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
+ guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
- ifndef $(toolchain)-$(tool-class)
- $(toolchain)-$(tool-class) := $$(call guess-$$($(toolchain)-cc-id)-$(tool-class),$$($(toolchain)-cc-path))
+ guess-llvm-clang-cpp = $(1)
+ guess-llvm-clang-as = $(1)
+ guess-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
+ guess-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
+ guess-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
+ guess-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
- ifeq ($$($(toolchain)-$(tool-class)),)
- $(toolchain)-$(tool-class) := $$($(toolchain)-$(tool-class)-default)
- endif
- endif
+ guess-gnu-gcc-cpp = $(1)
+ guess-gnu-gcc-as = $(1)
+ guess-gnu-gcc-ld = $(1)
+ guess-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
+ guess-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
+ guess-gnu-gcc-ar = $(call which,$(call decompat-path,$(patsubst %$(call file-name,$(1)),%$(subst gcc,gcc-ar,$(call file-name,$(1))),$(call compat-path,$(1)))))
- $(toolchain)-$(tool-class)-id := $$(call guess-tool,$$(tools-$(tool-class)),$$($$(toolchain)-$(tool-class)))
-endef
+ define toolchain-warn-unrecognized
+ $$(warning )
+ $$(warning The configured $$($(1)-name) $$(tool-class-name-$(2)) could not be identified and may not be supported:)
+ $$(warning )
+ $$(warning $$(space) $$($(1)-$(2)))
+ $$(warning )
+ $$(warning The default $$($(1)-name) $$(tool-class-name-$(2)) is:)
+ $$(warning )
+ $$(warning $$(space) $$($(1)-$(2)-default))
+ $$(warning )
+ $$(warning The following tools are supported:)
+ $$(warning )
-define canonicalize-toolchain-tool-path
- $(eval toolchain := $(1))
- $(eval tool-class := $(2))
+ $$(foreach tool,$$(tools-$(2)), \
+ $$(warning $$(space) - $$(tool-name-$$(tool))))
- $(toolchain)-$(tool-class)-path := $$(call absolute-path,$$(call which,$$($(toolchain)-$(tool-class))))
- $(toolchain)-$(tool-class)-path := $$(or $$($(toolchain)-$(tool-class)-path),$$($(toolchain)-$(tool-class)))
+ $$(warning )
+ $$(warning The build system will treat this $$(tool-class-name-$(2)) as $$(tool-name-$$($(1)-$(2)-id-default)).)
+ $$(warning )
+ endef
- $(toolchain)-$(tool-class) := $(call escape-shell,$$($(toolchain)-$(tool-class)-path))
-endef
+ define toolchain-determine-tool
+ $(1)-$(2)-guess = $$(if $$(filter-out cc,$(2)),$\
+ $$(call guess-$$($(1)-cc-id)-$(2),$$($(1)-cc)))
-define locate-toolchain
- $(eval toolchain := $(1))
+ $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-guess))
+ $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-default))
- $$(eval $$(call locate-toolchain-tool-cc,$(toolchain)))
- $$(eval $$(call canonicalize-toolchain-tool-path,$(toolchain),cc))
+ ifneq ($$(call which,$$($(1)-$(2))),)
+ # If we can resolve this tool to a program on the `PATH`
+ # then escape it for use in a shell, which allows us to
+ # preserve spaces.
+
+ $(1)-$(2) := $$(call escape-shell,$$($(1)-$(2)))
+ endif
- $$(foreach tool-class,$$(filter-out cc,$$(tool-classes)), \
- $$(eval $$(call locate-toolchain-tool,$(toolchain),$$(tool-class))) \
- $$(eval $$(call canonicalize-toolchain-tool-path,$(toolchain),$$(tool-class))))
-endef
+ $(1)-$(2)-id := $$(call guess-tool,$$(tools-$(2)),$$($(1)-$(2)))
-$(foreach toolchain,$(toolchains), \
- $(eval $(call locate-toolchain,$(toolchain))))
+ ifndef $(1)-$(2)-id
+ $(1)-$(2)-id := $$($(1)-$(2)-id-default)
+
+ $$(eval $$(call toolchain-warn-unrecognized,$(1),$(2)))
+ endif
+ endef
+
+ define toolchain-determine
+ $$(foreach tool-class,$$(tool-classes), \
+ $$(eval $$(call toolchain-determine-tool,$(1),$$(tool-class))))
+ endef
+
+ $(foreach toolchain,$(toolchains), \
+ $(eval $(call toolchain-determine,$(toolchain))))
+endif
diff --git a/make_helpers/toolchains/aarch32.mk b/make_helpers/toolchains/aarch32.mk
index 3475c91..ff00a53 100644
--- a/make_helpers/toolchains/aarch32.mk
+++ b/make_helpers/toolchains/aarch32.mk
@@ -4,11 +4,36 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+aarch32-name := AArch32
+
+aarch32-cc := $(if $(filter-out default,$(origin CC)),$(CC))
aarch32-cc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
+aarch32-cc-id-default := gnu-gcc
+
+aarch32-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
aarch32-cpp-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
+aarch32-cpp-id-default := gnu-gcc
+
+aarch32-as := $(if $(filter-out default,$(origin AS)),$(AS))
aarch32-as-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
+aarch32-as-id-default := gnu-gcc
+
+aarch32-ld := $(if $(filter-out default,$(origin LD)),$(LD))
aarch32-ld-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc
+aarch32-ld-id-default := gnu-gcc
+
+aarch32-oc := $(if $(filter-out default,$(origin OC)),$(OC))
aarch32-oc-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objcopy
+aarch32-oc-id-default := gnu-objcopy
+
+aarch32-od := $(if $(filter-out default,$(origin OD)),$(OD))
aarch32-od-default := $(or $(CROSS_COMPILE),arm-none-eabi-)objdump
+aarch32-od-id-default := gnu-objdump
+
+aarch32-ar := $(if $(filter-out default,$(origin AR)),$(AR))
aarch32-ar-default := $(or $(CROSS_COMPILE),arm-none-eabi-)gcc-ar
+aarch32-ar-id-default := gnu-ar
+
+aarch32-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
aarch32-dtc-default := dtc
+aarch32-dtc-id-default := generic-dtc
diff --git a/make_helpers/toolchains/aarch64.mk b/make_helpers/toolchains/aarch64.mk
index d83d918..407f068 100644
--- a/make_helpers/toolchains/aarch64.mk
+++ b/make_helpers/toolchains/aarch64.mk
@@ -4,11 +4,36 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+aarch64-name := AArch64
+
+aarch64-cc := $(if $(filter-out default,$(origin CC)),$(CC))
aarch64-cc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
+aarch64-cc-id-default := gnu-gcc
+
+aarch64-cpp := $(if $(filter-out default,$(origin CPP)),$(CPP))
aarch64-cpp-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
+aarch64-cpp-id-default := gnu-gcc
+
+aarch64-as := $(if $(filter-out default,$(origin AS)),$(AS))
aarch64-as-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
+aarch64-as-id-default := gnu-gcc
+
+aarch64-ld := $(if $(filter-out default,$(origin LD)),$(LD))
aarch64-ld-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc
+aarch64-ld-id-default := gnu-gcc
+
+aarch64-oc := $(if $(filter-out default,$(origin OC)),$(OC))
aarch64-oc-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objcopy
+aarch64-oc-id-default := gnu-objcopy
+
+aarch64-od := $(if $(filter-out default,$(origin OD)),$(OD))
aarch64-od-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)objdump
+aarch64-od-id-default := gnu-objdump
+
+aarch64-ar := $(if $(filter-out default,$(origin AR)),$(AR))
aarch64-ar-default := $(or $(CROSS_COMPILE),aarch64-none-elf-)gcc-ar
+aarch64-ar-id-default := gnu-ar
+
+aarch64-dtc := $(if $(filter-out default,$(origin DTC)),$(DTC))
aarch64-dtc-default := dtc
+aarch64-dtc-id-default := generic-dtc
diff --git a/make_helpers/toolchains/host.mk b/make_helpers/toolchains/host.mk
index fe3fc1c..733c289 100644
--- a/make_helpers/toolchains/host.mk
+++ b/make_helpers/toolchains/host.mk
@@ -1,14 +1,39 @@
#
-# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
+host-name := host
+
+host-cc := $(HOSTCC)
host-cc-default := gcc
+host-cc-id-default := gnu-gcc
+
+host-cpp := $(HOSTCPP)
host-cpp-default := gcc
+host-cpp-id-default := gnu-gcc
+
+host-as := $(HOSTAS)
host-as-default := gcc
+host-as-id-default := gnu-gcc
+
+host-ld := $(HOSTLD)
host-ld-default := gcc
+host-ld-id-default := gnu-gcc
+
+host-oc := $(HOSTOC)
host-oc-default := objcopy
+host-oc-id-default := gnu-objcopy
+
+host-od := $(HOSTOD)
host-od-default := objdump
+host-od-id-default := gnu-objdump
+
+host-ar := $(HOSTAR)
host-ar-default := gcc-ar
+host-ar-id-default := gnu-ar
+
+host-dtc := $(HOSTDTC)
host-dtc-default := dtc
+host-dtc-id-default := generic-dtc
diff --git a/make_helpers/toolchains/rk3399-m0.mk b/make_helpers/toolchains/rk3399-m0.mk
index f57d658..92309f1 100644
--- a/make_helpers/toolchains/rk3399-m0.mk
+++ b/make_helpers/toolchains/rk3399-m0.mk
@@ -4,11 +4,28 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+rk3399-m0-name := RK3399 M0
+
rk3399-m0-cc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
+rk3399-m0-cc-id-default := gnu-gcc
+
rk3399-m0-cpp-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
+rk3399-m0-cpp-id-default := gnu-gcc
+
rk3399-m0-as-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
+rk3399-m0-as-id-default := gnu-gcc
+
rk3399-m0-ld-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc
+rk3399-m0-ld-id-default := gnu-gcc
+
rk3399-m0-oc-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objcopy
+rk3399-m0-oc-id-default := gnu-objcopy
+
rk3399-m0-od-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)objdump
+rk3399-m0-od-id-default := gnu-objdump
+
rk3399-m0-ar-default := $(or $(M0_CROSS_COMPILE),arm-none-eabi-)gcc-ar
+rk3399-m0-ar-id-default := gnu-ar
+
rk3399-m0-dtc-default := dtc
+rk3399-m0-dtc-id-default := generic-dtc
diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk
index a75a740..de34eaf 100644
--- a/make_helpers/windows.mk
+++ b/make_helpers/windows.mk
@@ -79,16 +79,4 @@
# This can be overridden from the command line or environment.
BUILD_STRING ?= development build
-# The DOS echo shell command does not strip ' characters from the command
-# parameters before printing. We therefore use an alternative method invoked
-# by defining the MAKE_BUILD_STRINGS macro.
-BUILT_TIME_DATE_STRING = const char build_message[] = "Built : "${BUILD_MESSAGE_TIMESTAMP};
-VERSION_STRING_MESSAGE = const char version_string[] = "${VERSION_STRING}";
-VERSION_MESSAGE = const char version[] = "${VERSION}";
-define MAKE_BUILD_STRINGS
- $$(file >$1.in,$$(TF_CFLAGS) $$(CFLAGS))
- @echo $$(BUILT_TIME_DATE_STRING) $$(VERSION_STRING_MESSAGE) $$(VERSION_MESSAGE) | \
- $($(ARCH)-cc) @$1.in -x c -c - -o $1
-endef
-
MSVC_NMAKE := nmake.exe
diff --git a/package-lock.json b/package-lock.json
index e60c44e..a6bb905 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,12 +1,12 @@
{
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"lockfileVersion": 3,
"requires": true,
"packages": {
"": {
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"license": "BSD-3-Clause",
"devDependencies": {
"@commitlint/cli": "^19.0.0",
diff --git a/package.json b/package.json
index 7ad5c58..e4c6475 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
{
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"license": "BSD-3-Clause",
"type": "module",
"private": true,
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index 1863292..24edd79 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -186,9 +186,6 @@
{
/* Change the DTB if the configuration requires so. */
sunxi_prepare_dtb(fdt);
-
- console_flush();
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index 30f1760..9fba4af 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -92,8 +92,9 @@
memory@1 {
device_type = "ns-memory";
- reg = <0x00008800 0x80000000 0x0 0x7f000000>,
- <0x0 0x88000000 0x0 0x10000000>;
+ reg = <0x0 0x80000000 0x0 0x7c000000>,
+ <0x8 0x80000000 0x1 0x80000000>,
+ <0x00008800 0x80000000 0x0 0x7f000000>;
};
memory@2 {
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index 97d000e..ebdd80d 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -20,8 +20,6 @@
#include "fvp_private.h"
-static struct transfer_list_header *ns_tl __unused;
-
#if ENABLE_RME
/*
* The GPT library might modify the gpt regions structure to optimize
@@ -50,6 +48,11 @@
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
{
+ struct transfer_list_entry *te __unused;
+
+#if TRANSFER_LIST
+ arg0 = arg3;
+#endif
arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
/* Initialize the platform config for future decision making */
@@ -60,10 +63,6 @@
{
arm_bl2_platform_setup();
-#if TRANSFER_LIST
- ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE);
- assert(ns_tl != NULL);
-#endif
/* Initialize System level generic or SP804 timer */
fvp_timer_init();
}
@@ -81,16 +80,15 @@
struct bl_params *plat_get_next_bl_params(void)
{
struct bl_params *arm_bl_params;
- const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
- struct transfer_list_entry *te __unused;
bl_mem_params_node_t *param_node __unused;
+ const struct dyn_cfg_dtb_info_t *fw_config_info __unused;
+ const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
+ entry_point_info_t *ep __unused;
+ uint32_t next_exe_img_id __unused;
+ uintptr_t fw_config_base __unused;
arm_bl_params = arm_get_next_bl_params();
-#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
- const struct dyn_cfg_dtb_info_t *fw_config_info;
- uintptr_t fw_config_base = 0UL;
-
#if __aarch64__
/* Get BL31 image node */
param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
@@ -100,6 +98,15 @@
#endif /* __aarch64__ */
assert(param_node != NULL);
+#if TRANSFER_LIST
+ arm_bl_params->head = ¶m_node->params_node_mem;
+ arm_bl_params->head->ep_info = ¶m_node->ep_info;
+ arm_bl_params->head->image_id = param_node->image_id;
+
+ arm_bl2_setup_next_ep_info(param_node);
+#elif !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
+ fw_config_base = 0UL;
+
/* Update the next image's ep info with the FW config address */
fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
assert(fw_config_info != NULL);
@@ -113,49 +120,29 @@
param_node = get_bl_mem_params_node(BL33_IMAGE_ID);
assert(param_node != NULL);
-#if TRANSFER_LIST
- /* Update BL33's ep info with NS HW config address */
- te = transfer_list_find(ns_tl, TL_TAG_FDT);
- assert(te != NULL);
-
- param_node->ep_info.args.arg1 = TRANSFER_LIST_SIGNATURE |
- REGISTER_CONVENTION_VERSION_MASK;
- param_node->ep_info.args.arg2 = 0;
- param_node->ep_info.args.arg3 = (uintptr_t)ns_tl;
- param_node->ep_info.args.arg0 =
- te ? (uintptr_t)transfer_list_entry_data(te) : 0;
-#else
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
assert(hw_config_info != NULL);
param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr;
#endif /* TRANSFER_LIST */
-#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */
return arm_bl_params;
}
int bl2_plat_handle_post_image_load(unsigned int image_id)
{
-#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
+#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST
if (image_id == HW_CONFIG_ID) {
- const struct dyn_cfg_dtb_info_t *hw_config_info;
+ const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
struct transfer_list_entry *te __unused;
+ bl_mem_params_node_t *param_node __unused;
- const bl_mem_params_node_t *param_node =
- get_bl_mem_params_node(image_id);
+ param_node = get_bl_mem_params_node(image_id);
assert(param_node != NULL);
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
assert(hw_config_info != NULL);
-#if TRANSFER_LIST
- /* Update BL33's ep info with NS HW config address */
- te = transfer_list_add(ns_tl, TL_TAG_FDT,
- param_node->image_info.image_size,
- (void *)hw_config_info->config_addr);
- assert(te != NULL);
-#else
memcpy((void *)hw_config_info->secondary_config_addr,
(void *)hw_config_info->config_addr,
(size_t)param_node->image_info.image_size);
@@ -166,9 +153,8 @@
*/
flush_dcache_range(hw_config_info->secondary_config_addr,
param_node->image_info.image_size);
-#endif /* TRANSFER_LIST */
}
-#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */
+#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE && !TRANSFER_LIST*/
return arm_bl2_plat_handle_post_image_load(image_id);
}
diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index 93289b6..e087565 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -5,12 +5,15 @@
*/
#include <assert.h>
+
+#include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/smmu_v3.h>
#include <fconf_hw_config_getter.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/mmio.h>
+
#include <plat/arm/common/arm_config.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
@@ -25,6 +28,9 @@
/* Initialize the console to provide early debug support */
arm_console_boot_init();
+#if TRANSFER_LIST
+ arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
+#else
#if !RESET_TO_BL31 && !RESET_TO_BL2
const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
@@ -48,8 +54,8 @@
assert(hw_config_info->secondary_config_addr != 0UL);
arg2 = hw_config_info->secondary_config_addr;
#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 */
-
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+#endif /* TRANSFER_LIST */
/* Initialize the platform config for future decision making */
fvp_config_setup();
@@ -88,6 +94,7 @@
}
}
+#if !TRANSFER_LIST
void __init bl31_plat_arch_setup(void)
{
int rc __unused;
@@ -142,6 +149,7 @@
}
#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1 */
}
+#endif /* TRANSFER_LIST */
unsigned int plat_get_syscnt_freq2(void)
{
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 8cbf10e..5557d59 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -81,10 +81,15 @@
#if TRANSFER_LIST
#ifdef FW_NS_HANDOFF_BASE
-#define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, \
- FW_HANDOFF_SIZE, \
- MT_MEMORY | MT_RW | MT_NS)
+#define MAP_FW_NS_HANDOFF \
+ MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
#endif
+#ifdef PLAT_ARM_EL3_FW_HANDOFF_BASE
+#define MAP_EL3_FW_HANDOFF \
+ MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \
+ PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS)
+#endif
#endif
/*
@@ -165,7 +170,10 @@
ARM_MAP_OPTEE_CORE_MEM,
ARM_OPTEE_PAGEABLE_LOAD_MEM,
#endif
- {0}
+#ifdef MAP_EL3_FW_HANDOFF
+ MAP_EL3_FW_HANDOFF,
+#endif
+ { 0 }
};
#endif
#ifdef IMAGE_BL2U
@@ -202,7 +210,10 @@
#ifdef MAP_FW_NS_HANDOFF
MAP_FW_NS_HANDOFF,
#endif
- {0}
+#ifdef MAP_EL3_FW_HANDOFF
+ MAP_EL3_FW_HANDOFF,
+#endif
+ { 0 }
};
#if defined(IMAGE_BL31) && SPM_MM
diff --git a/plat/arm/board/fvp/fvp_common_measured_boot.c b/plat/arm/board/fvp/fvp_common_measured_boot.c
index d56f510..605f0ff 100644
--- a/plat/arm/board/fvp/fvp_common_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_common_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,12 +9,10 @@
#include <common/desc_image_load.h>
#include <drivers/measured_boot/event_log/event_log.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
extern event_log_metadata_t fvp_event_log_metadata[];
-extern struct rss_mboot_metadata fvp_rss_mboot_metadata[];
int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
{
diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c
index 5fb3141..f5bd722 100644
--- a/plat/arm/board/fvp/fvp_plat_attest_token.c
+++ b/plat/arm/board/fvp/fvp_plat_attest_token.c
@@ -98,7 +98,7 @@
/*
* Get the hardcoded platform attestation token as FVP does not support
- * RSS.
+ * RSE.
*/
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
uintptr_t hash, size_t hash_size)
diff --git a/plat/arm/board/fvp/fvp_realm_attest_key.c b/plat/arm/board/fvp/fvp_realm_attest_key.c
index fe0cde7..150608d 100644
--- a/plat/arm/board/fvp/fvp_realm_attest_key.c
+++ b/plat/arm/board/fvp/fvp_realm_attest_key.c
@@ -19,7 +19,7 @@
/*
* Get the hardcoded delegated realm attestation key as FVP
- * does not support RSS.
+ * does not support RSE.
*/
int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
unsigned int type)
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index ab1b07f..56de8b8 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -143,8 +143,14 @@
#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
#if TRANSFER_LIST
-#define FW_HANDOFF_SIZE 0x4000
-#define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - FW_HANDOFF_SIZE)
+#define PLAT_ARM_FW_HANDOFF_SIZE U(0x5000)
+
+#define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE)
+#define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE
+#define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE
+
+#else
+#define PLAT_ARM_FW_HANDOFF_SIZE U(0)
#endif
/*
@@ -269,9 +275,15 @@
* BL2 and BL1-RW.
* Size of the BL31 PROGBITS increases as the SRAM size increases.
*/
+#if TRANSFER_LIST
+#define PLAT_ARM_MAX_BL31_SIZE \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \
+ PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE)
+#else
#define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
ARM_SHARED_RAM_SIZE - \
ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE)
+#endif /* TRANSFER_LIST */
#endif /* RESET_TO_BL31 */
#ifndef __aarch64__
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 8fa01ff..033eb7c 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -7,70 +7,53 @@
include common/fdt_wrappers.mk
# Use the GICv3 driver on the FVP by default
-FVP_USE_GIC_DRIVER := FVP_GICV3
+FVP_USE_GIC_DRIVER := FVP_GICV3
# Default cluster count for FVP
-FVP_CLUSTER_COUNT := 2
+FVP_CLUSTER_COUNT := 2
# Default number of CPUs per cluster on FVP
FVP_MAX_CPUS_PER_CLUSTER := 4
# Default number of threads per CPU on FVP
-FVP_MAX_PE_PER_CPU := 1
+FVP_MAX_PE_PER_CPU := 1
# Disable redistributor frame of inactive/fused CPU cores by marking it as read
# only; enable redistributor frames of all CPU cores by default.
-FVP_GICR_REGION_PROTECTION := 0
+FVP_GICR_REGION_PROTECTION := 0
-FVP_DT_PREFIX := fvp-base-gicv3-psci
+FVP_DT_PREFIX := fvp-base-gicv3-psci
-# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
+# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
# the FVP platform. This option defaults to 256.
-FVP_TRUSTED_SRAM_SIZE := 256
+FVP_TRUSTED_SRAM_SIZE := 256
# Macro to enable helpers for running SPM tests. Disabled by default.
PLAT_TEST_SPM := 0
-# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's
-# progbits limit. We need a way to build all useful configurations while waiting
-# on the fvp to increase its SRAM size. The problem is twofild:
-# 1. the cleanup that introduced these enables cleaned up tf-a a little too
-# well and things that previously (incorrectly) were enabled, no longer are.
-# A bunch of CI configs build subtly incorrectly and this combo makes it
-# necessary to forcefully and unconditionally enable them here.
-# 2. the progbits limit is exceeded only when the tsp is involved. However,
-# there are tsp CI configs that run on very high architecture revisions so
-# disabling everything isn't an option.
-# The fix is to enable everything, as before. When the tsp is included, though,
-# we need to slim the size down. In that case, disable all optional features,
-# that will not be present in CI when the tsp is.
-# Similarly, DRTM support is only tested on v8.0 models. Disable everything just
-# for it.
-# TODO: make all of this unconditional (or only base the condition on
-# ARM_ARCH_* when the makefile supports it).
-ifneq (${DRTM_SUPPORT}, 1)
-ifneq (${SPD}, tspd)
- ENABLE_FEAT_AMU := 2
- ENABLE_FEAT_AMUv1p1 := 2
- ENABLE_FEAT_HCX := 2
- ENABLE_FEAT_RNG := 2
- ENABLE_FEAT_TWED := 2
- ENABLE_FEAT_GCS := 2
+# By default dont build CPUs with no FVP model.
+BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0
+
+ENABLE_FEAT_AMU := 2
+ENABLE_FEAT_AMUv1p1 := 2
+ENABLE_FEAT_HCX := 2
+ENABLE_FEAT_RNG := 2
+ENABLE_FEAT_TWED := 2
+ENABLE_FEAT_GCS := 2
+
ifeq (${ARCH}, aarch64)
+
ifeq (${SPM_MM}, 0)
ifeq (${CTX_INCLUDE_FPREGS}, 0)
- ENABLE_SME_FOR_NS := 2
- ENABLE_SME2_FOR_NS := 2
-endif
-endif
+ ENABLE_SME_FOR_NS := 2
+ ENABLE_SME2_FOR_NS := 2
endif
endif
-# enable unconditionally for all builds
-ifeq (${ARCH}, aarch64)
- ENABLE_BRBE_FOR_NS := 2
- ENABLE_TRBE_FOR_NS := 2
+ ENABLE_BRBE_FOR_NS := 2
+ ENABLE_TRBE_FOR_NS := 2
endif
+
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_CSV2_3 := 2
@@ -87,7 +70,6 @@
ENABLE_FEAT_S1PIE := 2
ENABLE_FEAT_S2POE := 2
ENABLE_FEAT_S1POE := 2
-endif
# The FVP platform depends on this macro to build with correct GIC driver.
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
@@ -211,16 +193,21 @@
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/cortex_x2.S \
- lib/cpus/aarch64/cortex_x4.S \
- lib/cpus/aarch64/cortex_gelas.S \
- lib/cpus/aarch64/nevis.S \
- lib/cpus/aarch64/travis.S
+ lib/cpus/aarch64/cortex_x4.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a75.S
endif
+#Build AArch64-only CPUs with no FVP model yet.
+ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
+ FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
+ lib/cpus/aarch64/cortex_gelas.S \
+ lib/cpus/aarch64/nevis.S \
+ lib/cpus/aarch64/travis.S
+endif
+
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
lib/cpus/aarch32/cortex_a57.S \
@@ -330,9 +317,23 @@
BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c
endif
+ifeq (${TRANSFER_LIST}, 1)
+include lib/transfer_list/transfer_list.mk
+endif
+
# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env)
ifdef UNIX_MK
+FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts
+
+FDT_SOURCES += ${FVP_HW_CONFIG_DTS}
+$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
+
+ifeq (${TRANSFER_LIST}, 1)
+FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \
+ ${PLAT}_tb_fw_config.dts \
+ )
+else
FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \
${PLAT}_fw_config.dts \
${PLAT}_tb_fw_config.dts \
@@ -341,7 +342,6 @@
)
FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb
FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
@@ -353,10 +353,6 @@
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG}))
endif
-ifeq (${TRANSFER_LIST}, 1)
-include lib/transfer_list/transfer_list.mk
-endif
-
ifeq (${SPD},spmd)
ifeq ($(ARM_SPMC_MANIFEST_DTS),)
@@ -372,16 +368,14 @@
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG}))
# Add the NT_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG}))
-
-FDT_SOURCES += ${FVP_HW_CONFIG_DTS}
-$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
+endif
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG}))
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
endif
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_main.c b/plat/arm/board/fvp_r/fvp_r_bl1_main.c
index 252fc31..6fe2b5b 100644
--- a/plat/arm/board/fvp_r/fvp_r_bl1_main.c
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,7 @@
#include <arch_helpers.h>
#include <bl1/bl1.h>
#include <common/bl_common.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
#include <drivers/console.h>
@@ -92,27 +93,6 @@
}
/*******************************************************************************
- * Helper utility to calculate the BL2 memory layout taking into consideration
- * the BL1 RW data assuming that it is at the top of the memory layout.
- ******************************************************************************/
-void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
-
- /*
- * Remove BL1 RW data from the scope of memory visible to BL2.
- * This is assuming BL1 RW data is at the top of bl1_mem_layout.
- */
- assert(bl1_mem_layout->total_base < BL1_RW_BASE);
- bl2_mem_layout->total_base = bl1_mem_layout->total_base;
- bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
-
- flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
-}
-
-/*******************************************************************************
* This function prepares for entry to BL33
******************************************************************************/
void bl1_prepare_next_image(unsigned int image_id)
@@ -182,7 +162,7 @@
/* Announce our arrival */
NOTICE(FIRMWARE_WELCOME_STR);
- NOTICE("BL1: %s\n", version_string);
+ NOTICE("BL1: %s\n", build_version_string);
NOTICE("BL1: %s\n", build_message);
INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
@@ -265,4 +245,3 @@
NOTICE("BL1: Please connect the debugger to continue\n");
}
#endif
-
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
index 6a7c0c8..dcf5e04 100644
--- a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -235,7 +235,7 @@
*/
bl33_secram_layout = (meminfo_t *) bl1_secram_layout->total_base;
- bl1_calc_bl2_mem_layout(bl1_secram_layout, bl33_secram_layout);
+ bl1_plat_calc_bl2_layout(bl1_secram_layout, bl33_secram_layout);
ep_info->args.arg1 = (uintptr_t)bl33_secram_layout;
diff --git a/plat/arm/board/morello/morello_image_load.c b/plat/arm/board/morello/morello_image_load.c
index cfe8bee..b959031 100644
--- a/plat/arm/board/morello/morello_image_load.c
+++ b/plat/arm/board/morello/morello_image_load.c
@@ -5,6 +5,7 @@
*/
#include <arch_helpers.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <drivers/arm/css/sds.h>
@@ -142,7 +143,7 @@
return -1;
}
- err = fdt_setprop_string(fdt, nodeoffset_fw, "tfa-fw-version", version_string);
+ err = fdt_setprop_string(fdt, nodeoffset_fw, "tfa-fw-version", build_version_string);
if (err < 0) {
WARN("NT_FW_CONFIG: Unable to set tfa-fw-version\n");
}
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 3897096..dcae95f 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -168,17 +168,9 @@
* Size of cacheable stacks
*/
#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
-# else
-# define PLATFORM_STACK_SIZE 0x440
-# endif
#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
-# else
-# define PLATFORM_STACK_SIZE 0x400
-# endif
#elif defined(IMAGE_BL2U)
# define PLATFORM_STACK_SIZE 0x400
#elif defined(IMAGE_BL31)
@@ -193,11 +185,11 @@
/*
* In the current implementation the RoT Service request that requires the
- * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The
+ * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The
* maximum required buffer size is calculated based on the platform-specific
* needs of this request.
*/
-#define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500
+#define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE 0x500
#define TC_DEVICE_BASE 0x21000000
#define TC_DEVICE_SIZE 0x5f000000
@@ -279,13 +271,13 @@
/* Index of SDS region used in the communication with SCP */
#define SDS_SCP_AP_REGION_ID U(0)
-/* Index of SDS region used in the communication with RSS */
-#define SDS_RSS_AP_REGION_ID U(1)
+/* Index of SDS region used in the communication with RSE */
+#define SDS_RSE_AP_REGION_ID U(1)
/*
- * Memory region for RSS's shared data storage (SDS)
+ * Memory region for RSE's shared data storage (SDS)
* It is placed right after the SCMI payload area.
*/
-#define PLAT_ARM_RSS_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \
+#define PLAT_ARM_RSE_AP_SDS_MEM_BASE (CSS_SCMI_PAYLOAD_BASE + \
CSS_SCMI_PAYLOAD_SIZE_MAX)
#define PLAT_ARM_CLUSTER_COUNT U(1)
@@ -306,9 +298,9 @@
#endif /* TARGET_PLATFORM == 3 */
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-/* TC2: AP<->RSS MHUs */
-#define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000)
-#define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000)
+/* TC2: AP<->RSE MHUs */
+#define PLAT_RSE_AP_SND_MHU_BASE UL(0x2A840000)
+#define PLAT_RSE_AP_RCV_MHU_BASE UL(0x2A850000)
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h
index a6b2b0d..6ba4694 100644
--- a/plat/arm/board/tc/include/tc_plat.h
+++ b/plat/arm/board/tc/include/tc_plat.h
@@ -8,7 +8,7 @@
#define TC_PLAT_H
#ifdef PLATFORM_TEST_ROTPK
-#include <rss_crypto_defs.h>
+#include <rse_crypto_defs.h>
#endif
void tc_bl31_common_platform_setup(void);
@@ -23,7 +23,7 @@
#ifdef PLATFORM_TEST_ROTPK
struct key_id_info {
- enum rss_key_id_builtin_t key_id;
+ enum rse_key_id_builtin_t key_id;
const char *key_id_name;
};
diff --git a/plat/arm/board/tc/nv_counter_test.c b/plat/arm/board/tc/nv_counter_test.c
index 179ec4b..9025569 100644
--- a/plat/arm/board/tc/nv_counter_test.c
+++ b/plat/arm/board/tc/nv_counter_test.c
@@ -7,9 +7,9 @@
#include <stdint.h>
#include <stdio.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
#include <plat/common/platform.h>
-#include "rss_platform_api.h"
+#include "rse_platform_api.h"
#include <platform_def.h>
@@ -20,30 +20,30 @@
uint32_t new_val;
uint32_t id;
- status = rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
+ status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
if (status != PSA_SUCCESS) {
- printf("Failed to initialize RSS communication channel - psa_status = %d\n", status);
+ printf("Failed to initialize RSE communication channel - psa_status = %d\n", status);
return -1;
}
for (id = 0; id < 3; id++) {
- status = rss_platform_nv_counter_read(id, sizeof(old_val), (uint8_t *)&old_val);
+ status = rse_platform_nv_counter_read(id, sizeof(old_val), (uint8_t *)&old_val);
if (status != PSA_SUCCESS) {
- printf("Failed during first id=(%d) rss_platform_nv_counter_read - psa_status = %d\n",
+ printf("Failed during first id=(%d) rse_platform_nv_counter_read - psa_status = %d\n",
id, status);
return -1;
}
- status = rss_platform_nv_counter_increment(id);
+ status = rse_platform_nv_counter_increment(id);
if (status != PSA_SUCCESS) {
- printf("Failed during id=(%d) rss_platform_nv_counter_increment - psa_status = %d\n",
+ printf("Failed during id=(%d) rse_platform_nv_counter_increment - psa_status = %d\n",
id, status);
return -1;
}
- status = rss_platform_nv_counter_read(id, sizeof(new_val), (uint8_t *)&new_val);
+ status = rse_platform_nv_counter_read(id, sizeof(new_val), (uint8_t *)&new_val);
if (status != PSA_SUCCESS) {
- printf("Failed during second id=(%d) rss_platform_nv_counter_read - psa_status = %d\n",
+ printf("Failed during second id=(%d) rse_platform_nv_counter_read - psa_status = %d\n",
id, status);
return -1;
}
diff --git a/plat/arm/board/tc/plat_def_fip_uuid.h b/plat/arm/board/tc/plat_def_fip_uuid.h
index 631f7c9..46a455c 100644
--- a/plat/arm/board/tc/plat_def_fip_uuid.h
+++ b/plat/arm/board/tc/plat_def_fip_uuid.h
@@ -10,28 +10,28 @@
#include "uuid.h"
-#define UUID_RSS_FIRMWARE_BL1_2 \
+#define UUID_RSE_FIRMWARE_BL1_2 \
{{0x0a, 0xa5, 0xb1, 0xbe}, {0xe7, 0x84}, {0x41, 0xc5}, 0x81, 0xb8, {0x4a, 0x41, 0xcb, 0x4a, 0xd2, 0xdf}}
-#define UUID_RSS_FIRMWARE_BL2 \
+#define UUID_RSE_FIRMWARE_BL2 \
{{0xa3, 0xb3, 0xb3, 0x0d}, {0xeb, 0xc9}, {0x40, 0x48}, 0xb4, 0x80, {0x15, 0x53, 0x61, 0xc1, 0x70, 0x48}}
-#define UUID_RSS_FIRMWARE_SCP_BL1 \
+#define UUID_RSE_FIRMWARE_SCP_BL1 \
{{0xbf, 0xd5, 0x09, 0x8d}, {0xa7, 0x07}, {0x4f, 0x15}, 0x89, 0x1c, {0x37, 0x22, 0x10, 0xcb, 0x51, 0xe2}}
-#define UUID_RSS_FIRMWARE_AP_BL1 \
+#define UUID_RSE_FIRMWARE_AP_BL1 \
{{0x12, 0x4c, 0x50, 0xe0}, {0xf2, 0xda}, {0x45, 0xe9}, 0x85, 0xc8, {0xda, 0xd9, 0x60, 0x9b, 0x7a, 0x11}}
-#define UUID_RSS_FIRMWARE_NS \
+#define UUID_RSE_FIRMWARE_NS \
{{0x8d, 0x95, 0x9f, 0x72}, {0xb8, 0xb1}, {0x42, 0x11}, 0x9a, 0xe6, {0x4b, 0x80, 0x97, 0x47, 0x5a, 0xd9}}
-#define UUID_RSS_FIRMWARE_S \
+#define UUID_RSE_FIRMWARE_S \
{{0x22, 0xea, 0x33, 0x85}, {0xf8, 0x6e}, {0x47, 0x93}, 0x96, 0x8a, {0x2f, 0xe3, 0xdd, 0x50, 0x33, 0xcc}}
-#define UUID_RSS_SIC_TABLES_NS \
+#define UUID_RSE_SIC_TABLES_NS \
{{0xd9, 0x10, 0x00, 0x72}, {0x6a, 0x28}, {0x4b, 0xec}, 0xb0, 0xd6, {0x8c, 0xed, 0xc4, 0x15, 0x7c, 0xe0}}
-#define UUID_RSS_SIC_TABLES_S \
+#define UUID_RSE_SIC_TABLES_S \
{{0xc7, 0x38, 0xd0, 0xde}, {0x8c, 0x26}, {0x48, 0x51}, 0x93, 0x36, {0xf3, 0xdb, 0xe2, 0x96, 0x65, 0x18}}
#endif /* __PLAT_DEF_FIP_UUID__ */
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index b30e40c..37ca4c6 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -40,6 +40,7 @@
ifeq (${SPD},spmd)
SPMD_SPM_AT_SEL2 := 1
+ ENABLE_FEAT_MTE2 := 1
CTX_INCLUDE_PAUTH_REGS := 1
endif
@@ -67,6 +68,9 @@
CSS_LOAD_SCP_IMAGES := 1
+# Save DSU PMU registers on cluster off and restore them on cluster on
+PRESERVE_DSU_PMU_REGS := 1
+
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -127,6 +131,7 @@
${TC_BASE}/tc_topology.c \
lib/fconf/fconf.c \
lib/fconf/fconf_dyn_cfg_getter.c \
+ drivers/arm/css/dsu/dsu.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
@@ -162,7 +167,7 @@
endif
#Device tree
-TC_HW_CONFIG_DTS := fdts/tc.dts
+TC_HW_CONFIG_DTS := fdts/${PLAT}${TARGET_PLATFORM}.dts
TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
FDT_SOURCES += ${TC_HW_CONFIG_DTS}
$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS)))
@@ -173,20 +178,20 @@
# Include Measured Boot makefile before any Crypto library makefile.
# Crypto library makefile may need default definitions of Measured Boot build
# flags present in Measured Boot makefile.
-$(info Including rss_comms.mk)
+$(info Including rse_comms.mk)
ifeq (${MEASURED_BOOT},1)
- $(info Including rss_comms.mk)
- include drivers/arm/rss/rss_comms.mk
+ $(info Including rse_comms.mk)
+ include drivers/arm/rse/rse_comms.mk
- BL1_SOURCES += ${RSS_COMMS_SOURCES}
- BL2_SOURCES += ${RSS_COMMS_SOURCES}
+ BL1_SOURCES += ${RSE_COMMS_SOURCES}
+ BL2_SOURCES += ${RSE_COMMS_SOURCES}
PLAT_INCLUDES += -Iinclude/lib/psa
ifeq (${DICE_PROTECTION_ENVIRONMENT},1)
$(info Including qcbor.mk)
- include drivers/measured_boot/rss/qcbor.mk
+ include drivers/measured_boot/rse/qcbor.mk
$(info Including dice_prot_env.mk)
- include drivers/measured_boot/rss/dice_prot_env.mk
+ include drivers/measured_boot/rse/dice_prot_env.mk
BL1_SOURCES += ${QCBOR_SOURCES} \
${DPE_SOURCES} \
@@ -206,8 +211,8 @@
PLAT_INCLUDES += -I${QCBOR_INCLUDES} \
-Iinclude/lib/dice
else
- $(info Including rss_measured_boot.mk)
- include drivers/measured_boot/rss/rss_measured_boot.mk
+ $(info Including rse_measured_boot.mk)
+ include drivers/measured_boot/rse/rse_measured_boot.mk
BL1_SOURCES += ${MEASURED_BOOT_SOURCES} \
plat/arm/board/tc/tc_common_measured_boot.c \
diff --git a/plat/arm/board/tc/platform_test.mk b/plat/arm/board/tc/platform_test.mk
index 4e81b2c..8d39325 100644
--- a/plat/arm/board/tc/platform_test.mk
+++ b/plat/arm/board/tc/platform_test.mk
@@ -5,42 +5,42 @@
$(eval $(call add_define,PLATFORM_TESTS))
-ifeq (${PLATFORM_TEST},rss-nv-counters)
- include drivers/arm/rss/rss_comms.mk
+ifeq (${PLATFORM_TEST},rse-nv-counters)
+ include drivers/arm/rse/rse_comms.mk
# Test code.
BL31_SOURCES += plat/arm/board/tc/nv_counter_test.c
# Code under testing.
- BL31_SOURCES += lib/psa/rss_platform.c \
- ${RSS_COMMS_SOURCES}
+ BL31_SOURCES += lib/psa/rse_platform.c \
+ ${RSE_COMMS_SOURCES}
PLAT_INCLUDES += -Iinclude/lib/psa
$(eval $(call add_define,PLATFORM_TEST_NV_COUNTERS))
-else ifeq (${PLATFORM_TEST},rss-rotpk)
- include drivers/arm/rss/rss_comms.mk
+else ifeq (${PLATFORM_TEST},rse-rotpk)
+ include drivers/arm/rse/rse_comms.mk
# Test code.
BL31_SOURCES += plat/arm/board/tc/rotpk_test.c
# Code under testing.
- BL31_SOURCES += lib/psa/rss_platform.c \
- ${RSS_COMMS_SOURCES}
+ BL31_SOURCES += lib/psa/rse_platform.c \
+ ${RSE_COMMS_SOURCES}
PLAT_INCLUDES += -Iinclude/lib/psa
$(eval $(call add_define,PLATFORM_TEST_ROTPK))
else ifeq (${PLATFORM_TEST},tfm-testsuite)
- include drivers/arm/rss/rss_comms.mk
+ include drivers/arm/rse/rse_comms.mk
# The variables need to be set to compile the platform test:
ifeq (${TF_M_TESTS_PATH},)
- # Example: ../rss/tf-m-tests
+ # Example: ../rse/tf-m-tests
$(error Error: TF_M_TESTS_PATH not set)
endif
ifeq (${TF_M_EXTRAS_PATH},)
- # Example: ../rss/tf-m-extras
+ # Example: ../rse/tf-m-extras
$(error Error: TF_M_EXTRAS_PATH not set)
endif
ifeq (${MEASUREMENT_VALUE_SIZE},)
@@ -61,18 +61,19 @@
hmac_drbg.c \
psa_crypto.c \
psa_crypto_client.c \
- psa_crypto_driver_wrappers.c \
+ psa_crypto_driver_wrappers_no_static.c \
psa_crypto_hash.c \
psa_crypto_rsa.c \
psa_crypto_ecp.c \
psa_crypto_slot_management.c \
+ psa_util.c \
)
- BL31_SOURCES += ${RSS_COMMS_SOURCES} \
+ BL31_SOURCES += ${RSE_COMMS_SOURCES} \
plat/arm/common/arm_dyn_cfg.c \
- ${TC_BASE}/rss_ap_tests.c \
- ${TC_BASE}/rss_ap_testsuites.c \
- ${TC_BASE}/rss_ap_test_stubs.c \
+ ${TC_BASE}/rse_ap_tests.c \
+ ${TC_BASE}/rse_ap_testsuites.c \
+ ${TC_BASE}/rse_ap_test_stubs.c \
$(TF_M_TESTS_PATH)/tests_reg/test/framework/test_framework.c \
$(MEASURED_BOOT_TESTS_PATH)/measured_boot_common.c \
$(MEASURED_BOOT_TESTS_PATH)/measured_boot_tests_common.c \
diff --git a/plat/arm/board/tc/rotpk_test.c b/plat/arm/board/tc/rotpk_test.c
index ed56c31..2178f69 100644
--- a/plat/arm/board/tc/rotpk_test.c
+++ b/plat/arm/board/tc/rotpk_test.c
@@ -7,9 +7,9 @@
#include <stdint.h>
#include <stdio.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
#include <plat/common/platform.h>
-#include <rss_platform_api.h>
+#include <rse_platform_api.h>
#include <tc_plat.h>
static void print_hex(const char *key_id_name, size_t key_size, const uint8_t *key_buf)
@@ -28,19 +28,19 @@
size_t key_size;
struct key_id_info key_ids[3] = {
- {.key_id = RSS_BUILTIN_KEY_ID_HOST_S_ROTPK, .key_id_name = "Secure-ROTPK"},
- {.key_id = RSS_BUILTIN_KEY_ID_HOST_NS_ROTPK, .key_id_name = "NS-ROTPK"},
- {.key_id = RSS_BUILTIN_KEY_ID_HOST_CCA_ROTPK, .key_id_name = "CCA-ROTPK"}
+ {.key_id = RSE_BUILTIN_KEY_ID_HOST_S_ROTPK, .key_id_name = "Secure-ROTPK"},
+ {.key_id = RSE_BUILTIN_KEY_ID_HOST_NS_ROTPK, .key_id_name = "NS-ROTPK"},
+ {.key_id = RSE_BUILTIN_KEY_ID_HOST_CCA_ROTPK, .key_id_name = "CCA-ROTPK"}
};
- status = rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
+ status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
if (status != PSA_SUCCESS) {
- printf("Failed to initialize RSS communication channel - psa_status = %d\n", status);
+ printf("Failed to initialize RSE communication channel - psa_status = %d\n", status);
return -1;
}
for (int i = 0; i < ARRAY_SIZE(key_ids); i++) {
- status = rss_platform_key_read(key_ids[i].key_id, key_buf,
+ status = rse_platform_key_read(key_ids[i].key_id, key_buf,
sizeof(key_buf), &key_size);
if (status != PSA_SUCCESS) {
printf("Failed to retrieve %s - psa_status = %d\n", key_ids[i].key_id_name, status);
diff --git a/plat/arm/board/tc/rss_ap_test_stubs.c b/plat/arm/board/tc/rse_ap_test_stubs.c
similarity index 92%
rename from plat/arm/board/tc/rss_ap_test_stubs.c
rename to plat/arm/board/tc/rse_ap_test_stubs.c
index aa97476..cf79181 100644
--- a/plat/arm/board/tc/rss_ap_test_stubs.c
+++ b/plat/arm/board/tc/rse_ap_test_stubs.c
@@ -26,7 +26,7 @@
size_t measurement_value_size,
bool lock_measurement)
{
- return rss_measured_boot_extend_measurement(index,
+ return rse_measured_boot_extend_measurement(index,
signer_id,
signer_id_size,
version,
@@ -56,7 +56,7 @@
size_t *measurement_value_len,
bool *is_locked)
{
- return rss_measured_boot_read_measurement(index,
+ return rse_measured_boot_read_measurement(index,
signer_id,
signer_id_size,
signer_id_len,
@@ -80,7 +80,7 @@
size_t token_buf_size,
size_t *token_size)
{
- return rss_delegated_attest_get_token(dak_pub_hash,
+ return rse_delegated_attest_get_token(dak_pub_hash,
dak_pub_hash_size,
token_buf,
token_buf_size,
@@ -95,7 +95,7 @@
size_t *key_size,
uint32_t hash_algo)
{
- return rss_delegated_attest_get_delegated_key(ecc_curve,
+ return rse_delegated_attest_get_delegated_key(ecc_curve,
key_bits,
key_buf,
key_buf_size,
diff --git a/plat/arm/board/tc/rss_ap_tests.c b/plat/arm/board/tc/rse_ap_tests.c
similarity index 94%
rename from plat/arm/board/tc/rss_ap_tests.c
rename to plat/arm/board/tc/rse_ap_tests.c
index ea90ac3..3ca628a 100644
--- a/plat/arm/board/tc/rss_ap_tests.c
+++ b/plat/arm/board/tc/rse_ap_tests.c
@@ -10,9 +10,9 @@
#include <mbedtls_common.h>
#include <plat/common/platform.h>
#include <psa/crypto.h>
-#include <rss_comms.h>
+#include <rse_comms.h>
-#include "rss_ap_testsuites.h"
+#include "rse_ap_testsuites.h"
static struct test_suite_t test_suites[] = {
{.freg = register_testsuite_delegated_attest},
@@ -32,7 +32,7 @@
size_t i;
/* Initialize test environment. */
- rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
+ rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
mbedtls_init();
status = psa_crypto_init();
if (status != PSA_SUCCESS) {
diff --git a/plat/arm/board/tc/rss_ap_testsuites.c b/plat/arm/board/tc/rse_ap_testsuites.c
similarity index 93%
rename from plat/arm/board/tc/rss_ap_testsuites.c
rename to plat/arm/board/tc/rse_ap_testsuites.c
index aa47d4c..5f4dc16 100644
--- a/plat/arm/board/tc/rss_ap_testsuites.c
+++ b/plat/arm/board/tc/rse_ap_testsuites.c
@@ -11,7 +11,7 @@
* necessary because both files define the function `extra_tests_init`, so a
* linker error occurs when both are linked to BL31. This file defines a macro
* that renames the colliding function names to something unique.
- * `plat/arm/board/tc/rss_ap_tests.c` can call the test init functions with
+ * `plat/arm/board/tc/rse_ap_tests.c` can call the test init functions with
* their new name.
*/
diff --git a/plat/arm/board/tc/rss_ap_testsuites.h b/plat/arm/board/tc/rse_ap_testsuites.h
similarity index 76%
rename from plat/arm/board/tc/rss_ap_testsuites.h
rename to plat/arm/board/tc/rse_ap_testsuites.h
index 58502ab..9bb42f5 100644
--- a/plat/arm/board/tc/rss_ap_testsuites.h
+++ b/plat/arm/board/tc/rse_ap_testsuites.h
@@ -5,12 +5,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef RSS_AP_TESTSUITES_H
-#define RSS_AP_TESTSUITES_H
+#ifndef RSE_AP_TESTSUITES_H
+#define RSE_AP_TESTSUITES_H
#include <test_framework.h>
void register_testsuite_measured_boot(struct test_suite_t *p_test_suite);
void register_testsuite_delegated_attest(struct test_suite_t *p_test_suite);
-#endif /* RSS_AP_TESTSUITES_H */
+#endif /* RSE_AP_TESTSUITES_H */
diff --git a/plat/arm/board/tc/tc_bl1_dpe.c b/plat/arm/board/tc/tc_bl1_dpe.c
index dc60fb6..432a163 100644
--- a/plat/arm/board/tc/tc_bl1_dpe.c
+++ b/plat/arm/board/tc/tc_bl1_dpe.c
@@ -8,11 +8,11 @@
#include <common/debug.h>
#include <drivers/arm/css/sds.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
#include <drivers/delay_timer.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -53,7 +53,7 @@
};
/* Effective timeout of 10000 ms */
-#define RSS_DPE_BOOT_10US_RETRIES 1000000
+#define RSE_DPE_BOOT_10US_RETRIES 1000000
#define TC2_SDS_DPE_CTX_HANDLE_STRUCT_ID 0x0000000A
/* Context handle is meant to be used by BL2. Sharing it via TB_FW_CONFIG */
@@ -66,20 +66,20 @@
void plat_dpe_get_context_handle(int *ctx_handle)
{
- int retry = RSS_DPE_BOOT_10US_RETRIES;
+ int retry = RSE_DPE_BOOT_10US_RETRIES;
int ret;
/* Initialize System level generic or SP804 timer */
generic_delay_timer_init();
- /* Check the initialization of the Shared Data Storage area between RSS
- * and AP. Since AP_BL1 is executed first then a bit later the RSS
+ /* Check the initialization of the Shared Data Storage area between RSE
+ * and AP. Since AP_BL1 is executed first then a bit later the RSE
* runtime, which initialize this area, therefore AP needs to check it
- * in a loop until it gets written by RSS Secure Runtime.
+ * in a loop until it gets written by RSE Secure Runtime.
*/
- VERBOSE("Waiting for DPE service initialization in RSS Secure Runtime\n");
+ VERBOSE("Waiting for DPE service initialization in RSE Secure Runtime\n");
while (retry > 0) {
- ret = sds_init(SDS_RSS_AP_REGION_ID);
+ ret = sds_init(SDS_RSE_AP_REGION_ID);
if (ret != SDS_OK) {
udelay(10);
retry--;
@@ -93,11 +93,11 @@
plat_panic_handler();
} else {
VERBOSE("DPE init succeeded in %dms.\n",
- (RSS_DPE_BOOT_10US_RETRIES - retry) / 100);
+ (RSE_DPE_BOOT_10US_RETRIES - retry) / 100);
}
/* TODO: call this in a loop to avoid reading unfinished data */
- ret = sds_struct_read(SDS_RSS_AP_REGION_ID,
+ ret = sds_struct_read(SDS_RSE_AP_REGION_ID,
TC2_SDS_DPE_CTX_HANDLE_STRUCT_ID,
0,
ctx_handle,
@@ -113,9 +113,9 @@
void bl1_plat_mboot_init(void)
{
- /* Initialize the communication channel between AP and RSS */
- (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
- PLAT_RSS_AP_RCV_MHU_BASE);
+ /* Initialize the communication channel between AP and RSE */
+ (void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+ PLAT_RSE_AP_RCV_MHU_BASE);
dpe_init(tc_dpe_metadata);
}
diff --git a/plat/arm/board/tc/tc_bl1_measured_boot.c b/plat/arm/board/tc/tc_bl1_measured_boot.c
index 2e58954..28a1e31 100644
--- a/plat/arm/board/tc/tc_bl1_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl1_measured_boot.c
@@ -6,9 +6,9 @@
#include <stdint.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
#include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
#include <tools_share/zero_oid.h>
#include <plat/arm/common/plat_arm.h>
@@ -17,7 +17,7 @@
/* Table with platform specific image IDs and metadata. Intentionally not a
* const struct, some members might set by bootloaders during trusted boot.
*/
-struct rss_mboot_metadata tc_rss_mboot_metadata[] = {
+struct rse_mboot_metadata tc_rse_mboot_metadata[] = {
{
.id = FW_CONFIG_ID,
.slot = U(6),
@@ -41,16 +41,16 @@
.lock_measurement = true },
{
- .id = RSS_MBOOT_INVALID_ID }
+ .id = RSE_MBOOT_INVALID_ID }
};
void bl1_plat_mboot_init(void)
{
- /* Initialize the communication channel between AP and RSS */
- (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
- PLAT_RSS_AP_RCV_MHU_BASE);
+ /* Initialize the communication channel between AP and RSE */
+ (void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+ PLAT_RSE_AP_RCV_MHU_BASE);
- rss_measured_boot_init(tc_rss_mboot_metadata);
+ rse_measured_boot_init(tc_rse_mboot_metadata);
}
void bl1_plat_mboot_finish(void)
diff --git a/plat/arm/board/tc/tc_bl2_dpe.c b/plat/arm/board/tc/tc_bl2_dpe.c
index e50508f..50cdbf8 100644
--- a/plat/arm/board/tc/tc_bl2_dpe.c
+++ b/plat/arm/board/tc/tc_bl2_dpe.c
@@ -7,9 +7,9 @@
#include <stdint.h>
#include <common/debug.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
#include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -211,9 +211,9 @@
void bl2_plat_mboot_init(void)
{
- /* Initialize the communication channel between AP and RSS */
- (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
- PLAT_RSS_AP_RCV_MHU_BASE);
+ /* Initialize the communication channel between AP and RSE */
+ (void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+ PLAT_RSE_AP_RCV_MHU_BASE);
dpe_init(tc_dpe_metadata);
}
diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c
index fd80fdc..add871c 100644
--- a/plat/arm/board/tc/tc_bl2_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl2_measured_boot.c
@@ -6,9 +6,9 @@
#include <stdint.h>
-#include <drivers/arm/rss_comms.h>
+#include <drivers/arm/rse_comms.h>
#include <drivers/measured_boot/metadata.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
#include <tools_share/tbbr_oid.h>
#include <plat/common/common_def.h>
@@ -17,7 +17,7 @@
/* TC specific table with image IDs and metadata. Intentionally not a
* const struct, some members might set by bootloaders during trusted boot.
*/
-struct rss_mboot_metadata tc_rss_mboot_metadata[] = {
+struct rse_mboot_metadata tc_rse_mboot_metadata[] = {
{
.id = BL31_IMAGE_ID,
.slot = U(9),
@@ -40,16 +40,16 @@
.pk_oid = SOC_FW_CONFIG_KEY_OID,
.lock_measurement = true },
{
- .id = RSS_MBOOT_INVALID_ID }
+ .id = RSE_MBOOT_INVALID_ID }
};
void bl2_plat_mboot_init(void)
{
- /* Initialize the communication channel between AP and RSS */
- (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE,
- PLAT_RSS_AP_RCV_MHU_BASE);
+ /* Initialize the communication channel between AP and RSE */
+ (void)rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE,
+ PLAT_RSE_AP_RCV_MHU_BASE);
- rss_measured_boot_init(tc_rss_mboot_metadata);
+ rse_measured_boot_init(tc_rse_mboot_metadata);
}
void bl2_plat_mboot_finish(void)
diff --git a/plat/arm/board/tc/tc_common_dpe.c b/plat/arm/board/tc/tc_common_dpe.c
index 42b5468..72ac673 100644
--- a/plat/arm/board/tc/tc_common_dpe.c
+++ b/plat/arm/board/tc/tc_common_dpe.c
@@ -9,7 +9,7 @@
#include <stdint.h>
#include <common/desc_image_load.h>
-#include <drivers/measured_boot/rss/dice_prot_env.h>
+#include <drivers/measured_boot/rse/dice_prot_env.h>
extern struct dpe_metadata tc_dpe_metadata[];
@@ -17,7 +17,7 @@
{
int err;
- /* Calculate image hash and record it in the DPE service in RSS. */
+ /* Calculate image hash and record it in the DPE service in RSE. */
err = dpe_measure_and_record(tc_dpe_metadata,
image_data->image_base,
image_data->image_size,
diff --git a/plat/arm/board/tc/tc_common_measured_boot.c b/plat/arm/board/tc/tc_common_measured_boot.c
index 925a411..6b8d41a 100644
--- a/plat/arm/board/tc/tc_common_measured_boot.c
+++ b/plat/arm/board/tc/tc_common_measured_boot.c
@@ -8,22 +8,22 @@
#include <stdint.h>
#include <common/desc_image_load.h>
-#include <drivers/measured_boot/rss/rss_measured_boot.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
-extern struct rss_mboot_metadata tc_rss_mboot_metadata[];
+extern struct rse_mboot_metadata tc_rse_mboot_metadata[];
int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
{
int err;
- /* Calculate image hash and record data in RSS */
- err = rss_mboot_measure_and_record(tc_rss_mboot_metadata,
+ /* Calculate image hash and record data in RSE */
+ err = rse_mboot_measure_and_record(tc_rse_mboot_metadata,
image_data->image_base,
image_data->image_size,
image_id);
if (err != 0) {
ERROR("%s%s image id %u (%i)\n",
- "Failed to ", "record in RSS", image_id, err);
+ "Failed to ", "record in RSE", image_id, err);
}
return err;
@@ -31,6 +31,6 @@
int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
{
- return rss_mboot_set_signer_id(tc_rss_mboot_metadata, pk_oid, pk_ptr,
+ return rse_mboot_set_signer_id(tc_rse_mboot_metadata, pk_oid, pk_ptr,
pk_len);
}
diff --git a/plat/arm/board/tc/tc_dpe_cert.h b/plat/arm/board/tc/tc_dpe_cert.h
index 25855ec..d0632e8 100644
--- a/plat/arm/board/tc/tc_dpe_cert.h
+++ b/plat/arm/board/tc/tc_dpe_cert.h
@@ -20,10 +20,10 @@
* RoT Cert. | | | +->TOS_FW_CONF | | |
* +------------+ | +->SCP_BL1 +-----+-----+-->FW_CONF +->AP_BL32 | | +->PVMFW |
* | | | | | | | | | | | |
- * | RSS_BL1_2--+-----+-->RSS_BL2------->AP_BL1--+-----+------------->AP_BL2------------+-----+-->AP_BL33 |
+ * | RSE_BL1_2--+-----+-->RSE_BL2------->AP_BL1--+-----+------------->AP_BL2------------+-----+-->AP_BL33 |
* | | | | | | | | | | | |
- * +------------+ | +->RSS_S +-----+-----+-->TB_FW_CONF +->AP_BL31 | | +->HYPERVISOR |
- * | +->RSS_NS | | +->SCP_BL2 | | |
+ * +------------+ | +->RSE_S +-----+-----+-->TB_FW_CONF +->AP_BL31 | | +->HYPERVISOR |
+ * | +->RSE_NS | | +->SCP_BL2 | | |
* | | | +->HW_CONF | | |
* +--------------------------+ | +---------------+-----+-->NT_FW_CONF |
* | | | |
diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index e5d05c4..fed14f7 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c
@@ -165,7 +165,7 @@
static sds_region_desc_t tc_sds_regions[] = {
{ .base = PLAT_ARM_SDS_MEM_BASE },
- { .base = PLAT_ARM_RSS_AP_SDS_MEM_BASE },
+ { .base = PLAT_ARM_RSE_AP_SDS_MEM_BASE },
};
sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
diff --git a/plat/arm/board/tc/tc_topology.c b/plat/arm/board/tc/tc_topology.c
index cc0dcc2..7631873 100644
--- a/plat/arm/board/tc/tc_topology.c
+++ b/plat/arm/board/tc/tc_topology.c
@@ -65,3 +65,11 @@
return PLAT_MAX_PE_PER_CPU;
}
#endif
+
+/******************************************************************************
+ * Return the cluster ID of current CPU
+ *****************************************************************************/
+unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr)
+{
+ return MPIDR_AFFLVL2_VAL(mpidr);
+}
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index feff691..f043f59 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,9 @@
#include <common/debug.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
+#if TRANSFER_LIST
+#include <lib/transfer_list.h>
+#endif
#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/arm/common/plat_arm.h>
@@ -61,6 +64,10 @@
/* Boolean variable to hold condition whether firmware update needed or not */
static bool is_fwu_needed;
+#if TRANSFER_LIST
+static struct transfer_list_header *secure_tl;
+#endif
+
struct meminfo *bl1_plat_sec_mem_layout(void)
{
return &bl1_tzram_layout;
@@ -144,9 +151,13 @@
*/
void arm_bl1_platform_setup(void)
{
- const struct dyn_cfg_dtb_info_t *fw_config_info;
+ const struct dyn_cfg_dtb_info_t *config_info __unused;
+ uint32_t fw_config_max_size __unused;
+ image_info_t config_image_info __unused;
+ struct transfer_list_entry *te __unused;
+
image_desc_t *desc;
- uint32_t fw_config_max_size;
+
int err = -1;
/* Initialise the IO layer and register platform IO devices */
@@ -159,6 +170,37 @@
return;
}
+#if TRANSFER_LIST
+ secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
+ PLAT_ARM_FW_HANDOFF_SIZE);
+
+ if (secure_tl == NULL) {
+ ERROR("Secure transfer list initialisation failed!\n");
+ panic();
+ }
+
+ te = transfer_list_add(secure_tl, TL_TAG_TB_FW_CONFIG,
+ ARM_TB_FW_CONFIG_MAX_SIZE, NULL);
+ assert(te != NULL);
+
+ /*
+ * Set the load address of TB_FW_CONFIG in the data section of the TE just
+ * allocated in the secure transfer list.
+ */
+ SET_PARAM_HEAD(&config_image_info, PARAM_IMAGE_BINARY, VERSION_2, 0);
+ config_image_info.image_base = (uintptr_t)transfer_list_entry_data(te);
+ config_image_info.image_max_size = te->data_size;
+
+ VERBOSE("FCONF: Loading config with image ID: %u\n", TB_FW_CONFIG_ID);
+ err = load_auth_image(TB_FW_CONFIG_ID, &config_image_info);
+ if (err != 0) {
+ VERBOSE("Failed to load config %u\n", TB_FW_CONFIG_ID);
+ plat_error_handler(err);
+ }
+
+ transfer_list_update_checksum(secure_tl);
+ fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te));
+#else
/* Set global DTB info for fixed fw_config information */
fw_config_max_size = ARM_FW_CONFIG_LIMIT - ARM_FW_CONFIG_BASE;
set_config_info(ARM_FW_CONFIG_BASE, ~0UL, fw_config_max_size, FW_CONFIG_ID);
@@ -174,13 +216,14 @@
* FW_CONFIG loaded successfully. If FW_CONFIG device tree parsing
* is successful then load TB_FW_CONFIG device tree.
*/
- fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
- if (fw_config_info != NULL) {
- err = fconf_populate_dtb_registry(fw_config_info->config_addr);
+ config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+ if (config_info != NULL) {
+ err = fconf_populate_dtb_registry(config_info->config_addr);
if (err < 0) {
ERROR("Parsing of FW_CONFIG failed %d\n", err);
plat_error_handler(err);
}
+
/* load TB_FW_CONFIG */
err = fconf_load_config(TB_FW_CONFIG_ID);
if (err < 0) {
@@ -191,11 +234,17 @@
ERROR("Invalid FW_CONFIG address\n");
plat_error_handler(err);
}
+#endif /* TRANSFER_LIST */
- /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
+
+#if TRANSFER_LIST
+ transfer_list_set_handoff_args(secure_tl, &desc->ep_info);
+#else
+ /* The BL2 ep_info arg0 is modified to point to FW_CONFIG */
assert(desc != NULL);
- desc->ep_info.args.arg0 = fw_config_info->config_addr;
+ desc->ep_info.args.arg0 = config_info->config_addr;
+#endif /* TRANSFER_LIST */
#if CRYPTO_SUPPORT
/* Share the Mbed TLS heap info with other images */
@@ -250,3 +299,32 @@
{
return is_fwu_needed ? NS_BL1U_IMAGE_ID : BL2_IMAGE_ID;
}
+
+// Use the default implementation of this function when Firmware Handoff is
+// disabled to avoid duplicating its logic.
+#if TRANSFER_LIST
+int bl1_plat_handle_post_image_load(unsigned int image_id)
+{
+ image_desc_t *image_desc __unused;
+
+ assert(image_id == BL2_IMAGE_ID);
+ struct transfer_list_entry *te;
+
+ /* Convey this information to BL2 via its TL. */
+ te = transfer_list_add(secure_tl, TL_TAG_SRAM_LAYOUT64,
+ sizeof(meminfo_t), NULL);
+ assert(te != NULL);
+
+ bl1_plat_calc_bl2_layout(&bl1_tzram_layout,
+ (meminfo_t *)transfer_list_entry_data(te));
+
+ transfer_list_update_checksum(secure_tl);
+
+ /**
+ * Before exiting make sure the contents of the TL are flushed in case there's no
+ * support for hardware cache coherency.
+ */
+ flush_dcache_range((uintptr_t)secure_tl, secure_tl->size);
+ return 0;
+}
+#endif /* TRANSFER_LIST*/
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 30d0647..58a14ab 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -19,6 +19,9 @@
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <lib/gpt_rme/gpt_rme.h>
+#if TRANSFER_LIST
+#include <lib/transfer_list.h>
+#endif
#ifdef SPD_opteed
#include <lib/optee_utils.h>
#endif
@@ -30,13 +33,18 @@
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
/* Base address of fw_config received from BL1 */
-static uintptr_t config_base;
+static uintptr_t config_base __unused;
/*
* Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
* for `meminfo_t` data structure and fw_configs passed from BL1.
*/
+#if TRANSFER_LIST
+CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE,
+ assert_bl2_base_overflows);
+#else
CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
+#endif /* TRANSFER_LIST */
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl2_early_platform_setup2
@@ -58,6 +66,9 @@
#pragma weak arm_bl2_plat_handle_post_image_load
+static struct transfer_list_header *secure_tl __unused;
+static struct transfer_list_header *ns_tl __unused;
+
/*******************************************************************************
* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
@@ -66,16 +77,28 @@
void arm_bl2_early_platform_setup(uintptr_t fw_config,
struct meminfo *mem_layout)
{
+ struct transfer_list_entry *te __unused;
int __maybe_unused ret;
/* Initialize the console to provide early debug support */
arm_console_boot_init();
- /* Setup the BL2 memory layout */
- bl2_tzram_layout = *mem_layout;
+#if TRANSFER_LIST
+ // TODO: modify the prototype of this function fw_config != bl2_tl
+ secure_tl = (struct transfer_list_header *)fw_config;
+ te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT64);
+ assert(te != NULL);
+
+ bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te);
+ transfer_list_rem(secure_tl, te);
+#else
config_base = fw_config;
+ /* Setup the BL2 memory layout */
+ bl2_tzram_layout = *mem_layout;
+#endif
+
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
@@ -103,7 +126,22 @@
*/
void bl2_plat_preload_setup(void)
{
+#if TRANSFER_LIST
+/* Assume the secure TL hasn't been initialised if BL2 is running at EL3. */
+#if RESET_TO_BL2
+ secure_tl = transfer_list_init((void *)PLAT_ARM_EL3_FW_HANDOFF_BASE,
+ PLAT_ARM_FW_HANDOFF_SIZE);
+
+ if (secure_tl == NULL) {
+ ERROR("Secure transfer list initialisation failed!\n");
+ panic();
+ }
+#endif
+
+ arm_transfer_list_dyn_cfg_init(secure_tl);
+#else
arm_bl2_dyn_cfg_init();
+#endif
#if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
/* Always use the FIP from bank 0 */
@@ -124,6 +162,16 @@
#if defined(PLAT_ARM_MEM_PROT_ADDR)
arm_nor_psci_do_static_mem_protect();
#endif
+
+#if TRANSFER_LIST
+ ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE,
+ PLAT_ARM_FW_HANDOFF_SIZE);
+
+ if (ns_tl == NULL) {
+ ERROR("Non-secure transfer list initialisation failed!");
+ panic();
+ }
+#endif
}
void bl2_platform_setup(void)
@@ -151,11 +199,13 @@
ARM_MAP_ROMLIB_CODE,
ARM_MAP_ROMLIB_DATA,
#endif
+#if !TRANSFER_LIST
ARM_MAP_BL_CONFIG_REGION,
+#endif /* TRANSFER_LIST */
#if ENABLE_RME
ARM_MAP_L0_GPT_REGION,
#endif
- {0}
+ { 0 }
};
#if ENABLE_RME
@@ -167,7 +217,7 @@
#ifdef __aarch64__
#if ENABLE_RME
/* BL2 runs in EL3 when RME enabled. */
- assert(get_armv9_2_feat_rme_support() != 0U);
+ assert(is_feat_rme_present());
enable_mmu_el3(0);
/* Initialise and enable granule protection after MMU. */
@@ -184,10 +234,17 @@
void bl2_plat_arch_setup(void)
{
- const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
-
+ const struct dyn_cfg_dtb_info_t *tb_fw_config_info __unused;
+ struct transfer_list_entry *te __unused;
arm_bl2_plat_arch_setup();
+#if TRANSFER_LIST
+ te = transfer_list_find(secure_tl, TL_TAG_TB_FW_CONFIG);
+ assert(te != NULL);
+
+ fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te));
+ transfer_list_rem(secure_tl, te);
+#else
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", config_base);
@@ -196,6 +253,7 @@
assert(tb_fw_config_info != NULL);
fconf_populate("TB_FW", tb_fw_config_info->config_addr);
+#endif
}
int arm_bl2_handle_post_image_load(unsigned int image_id)
@@ -265,5 +323,20 @@
return 0;
}
#endif
+
+#if TRANSFER_LIST
+ if (image_id == HW_CONFIG_ID) {
+ arm_transfer_list_copy_hw_config(secure_tl, ns_tl);
+ }
+#endif /* TRANSFER_LIST */
+
return arm_bl2_handle_post_image_load(image_id);
}
+
+void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node)
+{
+ assert(transfer_list_set_handoff_args(
+ secure_tl, &next_param_node->ep_info) != NULL);
+
+ arm_transfer_list_populate_ep_info(next_param_node, secure_tl, ns_tl);
+}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 33043b7..b7941ec 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -13,13 +13,18 @@
#include <drivers/console.h>
#include <lib/debugfs.h>
#include <lib/extensions/ras.h>
+#include <lib/fconf/fconf.h>
#include <lib/gpt_rme/gpt_rme.h>
#include <lib/mmio.h>
+#if TRANSFER_LIST
+#include <lib/transfer_list.h>
+#endif
#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
+static struct transfer_list_header *secure_tl __unused;
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@@ -35,8 +40,12 @@
* Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
* is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
*/
+#if TRANSFER_LIST
+CASSERT(BL31_BASE >= PLAT_ARM_EL3_FW_HANDOFF_LIMIT, assert_bl31_base_overflows);
+#else
CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
-#endif
+#endif /* TRANSFER_LIST */
+#endif /* RESET_TO_BL31 */
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak bl31_early_platform_setup2
@@ -115,6 +124,44 @@
* while creating page tables. BL2 has flushed this information to memory, so
* we are guaranteed to pick up good data.
******************************************************************************/
+#if TRANSFER_LIST
+void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ struct transfer_list_entry *te = NULL;
+ struct entry_point_info *ep;
+
+ secure_tl = (struct transfer_list_header *)arg3;
+
+ /*
+ * Populate the global entry point structures used to execute subsequent
+ * images.
+ */
+ while ((te = transfer_list_next(secure_tl, te)) != NULL) {
+ ep = transfer_list_entry_data(te);
+
+ if (te->tag_id == TL_TAG_EXEC_EP_INFO64) {
+ switch (GET_SECURITY_STATE(ep->h.attr)) {
+ case NON_SECURE:
+ bl33_image_ep_info = *ep;
+ break;
+#if ENABLE_RME
+ case REALM:
+ rmm_image_ep_info = *ep;
+ break;
+#endif
+ case SECURE:
+ bl32_image_ep_info = *ep;
+ break;
+ default:
+ ERROR("Unrecognized Image Security State %lu\n",
+ GET_SECURITY_STATE(ep->h.attr));
+ panic();
+ }
+ }
+ }
+}
+#else
void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
uintptr_t hw_config, void *plat_params_from_bl2)
{
@@ -258,11 +305,16 @@
bl33_image_ep_info.args.arg3 = 0U;
# endif
}
+#endif
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+#if TRANSFER_LIST
+ arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
+#else
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+#endif
/*
* Initialize Interconnect for this cluster during cold boot.
@@ -391,9 +443,6 @@
void bl31_plat_runtime_setup(void)
{
arm_bl31_plat_runtime_setup();
-
- console_flush();
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/*******************************************************************************
@@ -448,5 +497,15 @@
void __init bl31_plat_arch_setup(void)
{
+ struct transfer_list_entry *te __unused;
+
arm_bl31_plat_arch_setup();
+
+#if TRANSFER_LIST && !RESET_TO_BL2
+ te = transfer_list_find(secure_tl, TL_TAG_FDT);
+ assert(te != NULL);
+
+ /* Populate HW_CONFIG device tree with the mapped address */
+ fconf_populate("HW_CONFIG", (uintptr_t)transfer_list_entry_data(te));
+#endif
}
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 5084ea9..7ab39eb 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -299,6 +299,10 @@
plat/arm/common/arm_topology.c \
plat/common/plat_psci_common.c
+ifeq (${TRANSFER_LIST}, 1)
+ TRANSFER_LIST_SOURCES += plat/arm/common/arm_transfer_list.c
+endif
+
ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
ARM_SVC_HANDLER_SRCS :=
diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c
index c411c6c..2525266 100644
--- a/plat/arm/common/arm_image_load.c
+++ b/plat/arm/common/arm_image_load.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +17,10 @@
#pragma weak plat_get_bl_image_load_info
#pragma weak plat_get_next_bl_params
-static bl_params_t *next_bl_params_cpy_ptr;
+#if TRANSFER_LIST
+static bl_params_t next_bl_params_cpy;
+#endif
+bl_params_t *next_bl_params_cpy_ptr;
/*******************************************************************************
* This function flushes the data structures so that they are visible
@@ -96,9 +99,15 @@
******************************************************************************/
struct bl_params *arm_get_next_bl_params(void)
{
- bl_mem_params_node_t *bl2_mem_params_descs_cpy
- = (bl_mem_params_node_t *)ARM_BL2_MEM_DESC_BASE;
- const bl_params_t *next_bl_params;
+ bl_mem_params_node_t *bl2_mem_params_descs_cpy __unused;
+ const bl_params_t *next_bl_params __unused;
+
+#if TRANSFER_LIST
+ next_bl_params_cpy_ptr = &next_bl_params_cpy;
+ SET_PARAM_HEAD(next_bl_params_cpy_ptr, PARAM_BL_PARAMS, VERSION_2, 0U);
+#else
+ bl2_mem_params_descs_cpy =
+ (bl_mem_params_node_t *)ARM_BL2_MEM_DESC_BASE;
next_bl_params_cpy_ptr =
(bl_params_t *)(ARM_BL2_MEM_DESC_BASE +
@@ -127,6 +136,7 @@
(sizeof(bl_params_t)));
populate_next_bl_params_config(next_bl_params_cpy_ptr);
+#endif /* TRANSFER_LIST */
return next_bl_params_cpy_ptr;
}
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index 055ab36..498dedf 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -79,12 +79,8 @@
* search if the number of entries justify the additional complexity.
*/
for (i = 0; !!arm_pm_idle_states[i]; i++) {
-#if PSCI_OS_INIT_MODE
if ((power_state & ~ARM_LAST_AT_PLVL_MASK) ==
arm_pm_idle_states[i])
-#else
- if (power_state == arm_pm_idle_states[i])
-#endif /* __PSCI_OS_INIT_MODE__ */
break;
}
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index 09226f4..18e9381 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,9 +22,11 @@
static int arm_sip_setup(void)
{
+#if ENABLE_PMF
if (pmf_setup() != 0) {
return 1;
}
+#endif /* ENABLE_PMF */
#if USE_DEBUGFS
@@ -60,12 +62,13 @@
int call_count = 0;
#if ENABLE_PMF
-
/*
* Dispatch PMF calls to PMF SMC handler and return its return
* value
*/
- if (is_pmf_fid(smc_fid)) {
+ if (is_pmf_fid_deprecated(smc_fid)) {
+ NOTICE("PMF Interface usage from arm-sip range is deprecated. \
+ Please migrate smc call to Vendor-specific el3 range.\n");
return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
@@ -73,8 +76,9 @@
#endif /* ENABLE_PMF */
#if USE_DEBUGFS
-
- if (is_debugfs_fid(smc_fid)) {
+ if (is_debugfs_fid_deprecated(smc_fid)) {
+ NOTICE("Debugfs Interface usage from arm-sip range is deprecated. \
+ Please migrate smc call to vendor-specific el3 range.\n");
return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
diff --git a/plat/arm/common/arm_transfer_list.c b/plat/arm/common/arm_transfer_list.c
new file mode 100644
index 0000000..d144bbb
--- /dev/null
+++ b/plat/arm/common/arm_transfer_list.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl)
+{
+ struct transfer_list_entry *te;
+ bl_mem_params_node_t *next_param_node =
+ get_bl_mem_params_node(HW_CONFIG_ID);
+ assert(next_param_node != NULL);
+
+ /*
+ * The HW_CONFIG needs to be authenticated via the normal loading
+ * mechanism. Pre-allocate a TE for the configuration and update the
+ * load information so the configuration is loaded directly into the TE.
+ */
+ te = transfer_list_add(secure_tl, TL_TAG_FDT, PLAT_ARM_HW_CONFIG_SIZE,
+ NULL);
+ assert(te != NULL);
+
+ next_param_node->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
+ next_param_node->image_info.image_max_size = PLAT_ARM_HW_CONFIG_SIZE;
+ next_param_node->image_info.image_base =
+ (uintptr_t)transfer_list_entry_data(te);
+}
+
+void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node,
+ struct transfer_list_header *secure_tl,
+ struct transfer_list_header *ns_tl)
+{
+ uint32_t next_exe_img_id;
+ entry_point_info_t *ep;
+ struct transfer_list_entry *te;
+
+ assert(next_param_node != NULL);
+
+ while ((next_exe_img_id = next_param_node->next_handoff_image_id) !=
+ INVALID_IMAGE_ID) {
+ next_param_node =
+ &bl_mem_params_desc_ptr[get_bl_params_node_index(
+ next_exe_img_id)];
+ assert(next_param_node != NULL);
+
+ te = transfer_list_add(secure_tl, TL_TAG_EXEC_EP_INFO64,
+ sizeof(entry_point_info_t),
+ &next_param_node->ep_info);
+ assert(te != NULL);
+
+ ep = transfer_list_entry_data(te);
+
+ if (next_exe_img_id == BL33_IMAGE_ID) {
+ ep = transfer_list_set_handoff_args(ns_tl, ep);
+ assert(ep != NULL);
+ } else if ((next_exe_img_id == BL32_IMAGE_ID) && SPMC_AT_EL3) {
+ /*
+ * Populate the BL32 image base, size and max limit in
+ * the entry point information, since there is no
+ * platform function to retrieve them in generic
+ * code. We choose arg2, arg3 and arg4 since the generic
+ * code uses arg1 for stashing the SP manifest size. The
+ * SPMC setup uses these arguments to update SP manifest
+ * with actual SP's base address and it size.
+ */
+ ep->args.arg2 = next_param_node->image_info.image_base;
+ ep->args.arg3 = next_param_node->image_info.image_size;
+ ep->args.arg4 =
+ next_param_node->image_info.image_base +
+ next_param_node->image_info.image_max_size;
+ }
+
+ next_exe_img_id = next_param_node->next_handoff_image_id;
+ }
+
+ flush_dcache_range((uintptr_t)secure_tl, secure_tl->size);
+}
+
+void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl,
+ struct transfer_list_header *ns_tl)
+{
+ struct transfer_list_entry *te =
+ transfer_list_find(secure_tl, TL_TAG_FDT);
+ assert(te != NULL);
+
+ /* Refresh the now stale checksum following loading of HW_CONFIG into the TL. */
+ transfer_list_update_checksum(secure_tl);
+
+ /* Copy the hardware configuration to the non-secure TL. */
+ te = transfer_list_add(ns_tl, TL_TAG_FDT, te->data_size,
+ transfer_list_entry_data(te));
+ assert(te != NULL);
+}
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index f15c137..4cd514b 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,10 +68,6 @@
arm_console_boot_init();
#if RESET_TO_SP_MIN
- /* There are no parameters from BL2 if SP_MIN is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
-
/* Populate entry point information for BL33 */
SET_PARAM_HEAD(&bl33_image_ep_info,
PARAM_EP,
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index bb64e73..db4a169 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -12,6 +12,7 @@
#include <bl31/interrupt_mgmt.h>
#include <common/debug.h>
#include <drivers/arm/css/css_scp.h>
+#include <drivers/arm/css/dsu.h>
#include <lib/cassert.h>
#include <plat/arm/common/plat_arm.h>
@@ -82,8 +83,12 @@
* Perform the common cluster specific operations i.e enable coherency
* if this cluster was off.
*/
- if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
+ if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+#if PRESERVE_DSU_PMU_REGS
+ cluster_on_dsu_pmu_context_restore();
+#endif
plat_arm_interconnect_enter_coherency();
+ }
}
/*******************************************************************************
@@ -131,8 +136,12 @@
plat_arm_gic_cpuif_disable();
/* Cluster is to be turned off, so disable coherency */
- if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
+ if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+#if PRESERVE_DSU_PMU_REGS
+ cluster_off_dsu_pmu_context_save();
+#endif
plat_arm_interconnect_exit_coherency();
+ }
}
/*******************************************************************************
diff --git a/plat/brcm/common/brcm_bl31_setup.c b/plat/brcm/common/brcm_bl31_setup.c
index d3fa83d..6eef1d4 100644
--- a/plat/brcm/common/brcm_bl31_setup.c
+++ b/plat/brcm/common/brcm_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -235,8 +235,6 @@
******************************************************************************/
void brcm_bl31_plat_runtime_setup(void)
{
- console_switch_state(CONSOLE_FLAG_RUNTIME);
-
/* Initialize the runtime console */
bcm_console_runtime_init();
}
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 19c4e48..54f2a03 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -35,8 +35,6 @@
void bl31_plat_runtime_setup(void)
{
- console_flush();
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/*
diff --git a/plat/common/plat_bl1_common.c b/plat/common/plat_bl1_common.c
index bcf9f89..ff0e082 100644
--- a/plat/common/plat_bl1_common.c
+++ b/plat/common/plat_bl1_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -80,10 +80,8 @@
*/
int bl1_plat_handle_post_image_load(unsigned int image_id)
{
- meminfo_t *bl2_secram_layout;
- meminfo_t *bl1_secram_layout;
+ meminfo_t *bl1_tzram_layout;
image_desc_t *image_desc;
- entry_point_info_t *ep_info;
if (image_id != BL2_IMAGE_ID)
return 0;
@@ -92,26 +90,41 @@
image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
assert(image_desc != NULL);
- /* Get the entry point info */
- ep_info = &image_desc->ep_info;
-
/* Find out how much free trusted ram remains after BL1 load */
- bl1_secram_layout = bl1_plat_sec_mem_layout();
+ bl1_tzram_layout = bl1_plat_sec_mem_layout();
/*
- * Create a new layout of memory for BL2 as seen by BL1 i.e.
- * tell it the amount of total and free memory available.
- * This layout is created at the first free address visible
- * to BL2. BL2 will read the memory layout before using its
- * memory for other purposes.
+ * Convey this information to BL2 by storing the layout at the first free
+ * address visible to BL2.
*/
- bl2_secram_layout = (meminfo_t *) bl1_secram_layout->total_base;
+ bl1_plat_calc_bl2_layout(bl1_tzram_layout,
+ (meminfo_t *)bl1_tzram_layout->total_base);
- bl1_calc_bl2_mem_layout(bl1_secram_layout, bl2_secram_layout);
-
- ep_info->args.arg1 = (uintptr_t)bl2_secram_layout;
+ image_desc->ep_info.args.arg1 = (uintptr_t)bl1_tzram_layout->total_base;
VERBOSE("BL1: BL2 memory layout address = %p\n",
- (void *) bl2_secram_layout);
+ (void *)image_desc->ep_info.args.arg1);
+
return 0;
}
+
+/*******************************************************************************
+ * Helper utility to calculate the BL2 memory layout taking into consideration
+ * the BL1 RW data assuming that it is at the top of the memory layout.
+ ******************************************************************************/
+void bl1_plat_calc_bl2_layout(const meminfo_t *bl1_mem_layout,
+ meminfo_t *bl2_mem_layout)
+{
+ assert(bl1_mem_layout != NULL);
+ assert(bl2_mem_layout != NULL);
+
+ /*
+ * Remove BL1 RW data from the scope of memory visible to BL2.
+ * This is assuming BL1 RW data is at the top of bl1_mem_layout.
+ */
+ assert(BL1_RW_BASE > bl1_mem_layout->total_base);
+ bl2_mem_layout->total_base = bl1_mem_layout->total_base;
+ bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
+
+ flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
+}
diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c
index 7d008e7..55b425c 100644
--- a/plat/hisilicon/hikey/hikey_bl31_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -149,7 +149,3 @@
hisi_ipc_init();
hisi_pwrc_setup();
}
-
-void bl31_plat_runtime_setup(void)
-{
-}
diff --git a/plat/hisilicon/hikey960/hikey960_bl31_setup.c b/plat/hisilicon/hikey960/hikey960_bl31_setup.c
index 159eee9..6e80347 100644
--- a/plat/hisilicon/hikey960/hikey960_bl31_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c
index fe60ddc..5f4a18a 100644
--- a/plat/hisilicon/poplar/bl31_plat_setup.c
+++ b/plat/hisilicon/poplar/bl31_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -118,11 +118,6 @@
hisi_tzpc_sec_init();
}
-void bl31_plat_runtime_setup(void)
-{
- /* do nothing */
-}
-
void bl31_plat_arch_setup(void)
{
plat_configure_mmu_el3(BL31_BASE,
diff --git a/plat/imx/common/imx_sip_handler.c b/plat/imx/common/imx_sip_handler.c
index 5d29186..49fdacf 100644
--- a/plat/imx/common/imx_sip_handler.c
+++ b/plat/imx/common/imx_sip_handler.c
@@ -9,9 +9,10 @@
#include <stdint.h>
#include <services/std_svc.h>
#include <string.h>
-#include <platform_def.h>
+#include <common/build_message.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <platform_def.h>
#include <imx_sip_svc.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/mmio.h>
@@ -261,7 +262,7 @@
u_register_t x4)
{
/* Parse the version_string */
- char *parse = (char *)version_string;
+ char *parse = (char *)build_version_string;
uint64_t hash = 0;
do {
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index bd7896a..4c63740 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -408,8 +408,3 @@
{
return COUNTER_FREQUENCY;
}
-
-void bl31_plat_runtime_setup(void)
-{
- return;
-}
diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c
index 13e80fb..08bf8f3 100644
--- a/plat/imx/imx8qx/imx8qx_bl31_setup.c
+++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -386,8 +386,3 @@
{
return COUNTER_FREQUENCY;
}
-
-void bl31_plat_runtime_setup(void)
-{
- return;
-}
diff --git a/plat/imx/imx93/imx93_bl31_setup.c b/plat/imx/imx93/imx93_bl31_setup.c
index 6c9e1fd..d997e9a 100644
--- a/plat/imx/imx93/imx93_bl31_setup.c
+++ b/plat/imx/imx93/imx93_bl31_setup.c
@@ -140,11 +140,6 @@
plat_gic_init();
}
-void bl31_plat_runtime_setup(void)
-{
- console_switch_state(CONSOLE_FLAG_RUNTIME);
-}
-
entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
{
if (type == NON_SECURE) {
diff --git a/plat/marvell/armada/common/marvell_bl31_setup.c b/plat/marvell/armada/common/marvell_bl31_setup.c
index 26ba906..b3641e3 100644
--- a/plat/marvell/armada/common/marvell_bl31_setup.c
+++ b/plat/marvell/armada/common/marvell_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2024 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -181,8 +181,6 @@
*/
void marvell_bl31_plat_runtime_setup(void)
{
- console_switch_state(CONSOLE_FLAG_RUNTIME);
-
/* Initialize the runtime console */
marvell_console_runtime_init();
}
diff --git a/plat/mediatek/common/mtk_bl31_setup.c b/plat/mediatek/common/mtk_bl31_setup.c
index 7c9db8b..0d264b9 100644
--- a/plat/mediatek/common/mtk_bl31_setup.c
+++ b/plat/mediatek/common/mtk_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2022-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -166,7 +166,6 @@
void bl31_plat_runtime_setup(void)
{
mtk_init_one_level(MTK_INIT_LVL_PLAT_RUNTIME);
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
unsigned int plat_get_syscnt_freq2(void)
diff --git a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
index 86c4b81..cb57668 100644
--- a/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
+++ b/plat/mediatek/drivers/apusys/apusys_rv/2.0/apusys_rv.c
@@ -37,18 +37,8 @@
int apusys_kernel_apusys_rv_setup_reviser(void)
{
- static bool apusys_rv_setup_reviser_called;
-
spin_lock(&apusys_rv_lock);
- if (apusys_rv_setup_reviser_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_setup_reviser_called = true;
-
mmio_write_32(USERFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
mmio_write_32(SECUREFW_CTXT, CFG_4GB_SEL_EN | CFG_4GB_SEL);
@@ -74,18 +64,8 @@
int apusys_kernel_apusys_rv_reset_mp(void)
{
- static bool apusys_rv_reset_mp_called;
-
spin_lock(&apusys_rv_lock);
- if (apusys_rv_reset_mp_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_reset_mp_called = true;
-
mmio_write_32(MD32_SYS_CTRL, MD32_SYS_CTRL_RST);
dsb();
@@ -106,18 +86,8 @@
int apusys_kernel_apusys_rv_setup_boot(void)
{
- static bool apusys_rv_setup_boot_called;
-
spin_lock(&apusys_rv_lock);
- if (apusys_rv_setup_boot_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_setup_boot_called = true;
-
mmio_write_32(MD32_BOOT_CTRL, APU_SEC_FW_IOVA);
mmio_write_32(MD32_PRE_DEFINE, (PREDEFINE_CACHE_TCM << PREDEF_1G_OFS) |
@@ -130,55 +100,17 @@
int apusys_kernel_apusys_rv_start_mp(void)
{
- static bool apusys_rv_start_mp_called;
-
spin_lock(&apusys_rv_lock);
-
- if (apusys_rv_start_mp_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_start_mp_called = true;
-
mmio_write_32(MD32_RUNSTALL, MD32_RUN);
-
spin_unlock(&apusys_rv_lock);
return 0;
}
-static bool watch_dog_is_timeout(void)
-{
- if (mmio_read_32(WDT_INT) != WDT_INT_W1C) {
- ERROR(MODULE_TAG "%s: WDT does not timeout\n", __func__);
- return false;
- }
- return true;
-}
-
int apusys_kernel_apusys_rv_stop_mp(void)
{
- static bool apusys_rv_stop_mp_called;
-
spin_lock(&apusys_rv_lock);
-
- if (apusys_rv_stop_mp_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- if (watch_dog_is_timeout() == false) {
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_stop_mp_called = true;
-
mmio_write_32(MD32_RUNSTALL, MD32_STALL);
-
spin_unlock(&apusys_rv_lock);
return 0;
@@ -186,19 +118,10 @@
int apusys_kernel_apusys_rv_setup_sec_mem(void)
{
- static bool apusys_rv_setup_sec_mem_called;
int ret;
spin_lock(&apusys_rv_lock);
- if (apusys_rv_setup_sec_mem_called) {
- WARN(MODULE_TAG "%s: already initialized\n", __func__);
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
- apusys_rv_setup_sec_mem_called = true;
-
ret = set_apu_emi_mpu_region();
if (ret != 0) {
ERROR(MODULE_TAG "%s: set emimpu protection failed\n", __func__);
@@ -230,12 +153,6 @@
int apusys_kernel_apusys_rv_cg_gating(void)
{
spin_lock(&apusys_rv_lock);
-
- if (watch_dog_is_timeout() == false) {
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_DIS);
spin_unlock(&apusys_rv_lock);
@@ -245,12 +162,6 @@
int apusys_kernel_apusys_rv_cg_ungating(void)
{
spin_lock(&apusys_rv_lock);
-
- if (watch_dog_is_timeout() == false) {
- spin_unlock(&apusys_rv_lock);
- return -1;
- }
-
mmio_write_32(MD32_CLK_CTRL, MD32_CLK_EN);
spin_unlock(&apusys_rv_lock);
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
index da5242a..f4ff763 100644
--- a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
@@ -271,15 +271,8 @@
int apusys_devapc_rcx_init(void)
{
- static bool apusys_devapc_rcx_init_called;
enum apusys_apc_err_status ret;
- if (apusys_devapc_rcx_init_called == true) {
- INFO(MODULE_TAG "%s: init more than once!\n", __func__);
- return -1;
- }
- apusys_devapc_rcx_init_called = true;
-
apusys_devapc_init("APUAPC_CTRL_RCX", APU_CTRL_DAPC_RCX_BASE);
apusys_devapc_init("APUAPC_NOC_RCX", APU_NOC_DAPC_RCX_BASE);
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
index e8882f0..7de6620 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
@@ -16,7 +16,7 @@
/* SCP core0 DRAM */
region_info.start = 0x50000000ULL;
- region_info.end = 0x528FFFFFULL;
+ region_info.end = 0x507FFFFFULL;
region_info.region = 2;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -27,7 +27,7 @@
/* SCP core1 DRAM */
region_info.start = 0x70000000ULL;
- region_info.end = 0x729FFFFFULL;
+ region_info.end = 0x79FFFFFFULL;
region_info.region = 3;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -114,4 +114,4 @@
emi_mpu_set_protection(®ion_info);
return 0;
-}
\ No newline at end of file
+}
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index e3068b6..09eda84 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
diff --git a/plat/nxp/s32/s32g274ardb2/include/plat_console.h b/plat/nxp/s32/s32g274ardb2/include/plat_console.h
new file mode 100644
index 0000000..43c2bfd
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/include/plat_console.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_CONSOLE_H
+#define PLAT_CONSOLE_H
+
+void console_s32g2_register(void);
+
+#endif
diff --git a/plat/nxp/s32/s32g274ardb2/include/plat_helpers.h b/plat/nxp/s32/s32g274ardb2/include/plat_helpers.h
new file mode 100644
index 0000000..18582ec
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/include/plat_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_HELPERS_H
+#define PLAT_HELPERS_H
+
+unsigned int s32g2_core_pos_by_mpidr(u_register_t mpidr);
+
+#endif /* PLAT_HELPERS_H */
diff --git a/plat/nxp/s32/s32g274ardb2/include/plat_io_storage.h b/plat/nxp/s32/s32g274ardb2/include/plat_io_storage.h
new file mode 100644
index 0000000..ea01300
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/include/plat_io_storage.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_IO_STORAGE_H
+#define PLAT_IO_STORAGE_H
+
+void plat_s32g2_io_setup(void);
+
+#endif
diff --git a/plat/nxp/s32/s32g274ardb2/include/plat_macros.S b/plat/nxp/s32/s32g274ardb2/include/plat_macros.S
new file mode 100644
index 0000000..8f0c472
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/include/plat_macros.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+/* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant GIC and CCI registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * Clobbers: x0 - x10, x16, x17, sp
+ * ---------------------------------------------
+ */
+.macro plat_crash_print_regs
+.endm
+
+#endif /* PLAT_MACROS_S */
+
diff --git a/plat/nxp/s32/s32g274ardb2/include/platform_def.h b/plat/nxp/s32/s32g274ardb2/include/platform_def.h
new file mode 100644
index 0000000..bdfeee2
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/include/platform_def.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat/common/common_def.h>
+
+#define PLATFORM_STACK_SIZE U(0x1000)
+
+/* Caches */
+#define CACHE_WRITEBACK_SHIFT U(6)
+#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
+
+/* CPU Topology */
+#define PLATFORM_CORE_COUNT U(4)
+#define PLATFORM_SYSTEM_COUNT U(1)
+#define PLATFORM_CLUSTER_COUNT U(2)
+#define PLATFORM_PRIMARY_CPU U(0)
+#define PLATFORM_MPIDR_CPU_MASK_BITS U(1)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
+
+/* Power Domains */
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
+ PLATFORM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_OFF_STATE U(2)
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_PWR_LVL_STATES U(2)
+
+/* BL2 stage */
+#define BL2_BASE UL(0x34078000)
+#define BL2_LIMIT UL(0x34100000)
+
+/* BL31 stage */
+#define BL31_BASE UL(0x34200000)
+#define BL31_LIMIT UL(0x34300000)
+
+/* It is a dummy value for now, given the missing DDR */
+#define BL33_BASE UL(0x34500000)
+#define BL33_LIMIT UL(0x345FF000)
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36)
+/* We'll be doing a 1:1 mapping anyway */
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 36)
+
+#define MAX_MMAP_REGIONS U(8)
+#define MAX_XLAT_TABLES U(32)
+
+/* Console settings */
+#define UART_BASE UL(0x401C8000)
+#define UART_BAUDRATE U(115200)
+/* FIRC clock */
+#define UART_CLOCK_HZ U(48000000)
+
+#define S32G_FIP_BASE UL(0x34100000)
+#define S32G_FIP_SIZE UL(0x100000)
+
+#define MAX_IO_HANDLES U(2)
+#define MAX_IO_DEVICES U(2)
+
+/* GIC settings */
+#define S32G_GIC_BASE UL(0x50800000)
+#define PLAT_GICD_BASE S32G_GIC_BASE
+#define PLAT_GICR_BASE (S32G_GIC_BASE + UL(0x80000))
+
+/* Generic timer frequency; this goes directly into CNTFRQ_EL0.
+ * Its end-value is 5MHz; this is based on the assumption that
+ * GPR00[CA53_COUNTER_CLK_DIV_VAL] contains the reset value of 0x7, hence
+ * producing a divider value of 8, applied to the FXOSC frequency of 40MHz.
+ */
+#define COUNTER_FREQUENCY U(5000000)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
new file mode 100644
index 0000000..f265d95
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_el3_setup.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/desc_image_load.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <plat_console.h>
+#include <plat_io_storage.h>
+
+#define SIUL2_PC09_MSCR UL(0x4009C2E4)
+#define SIUL2_PC10_MSCR UL(0x4009C2E8)
+#define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40)
+
+#define LIN0_TX_MSCR_CFG U(0x00214001)
+#define LIN0_RX_MSCR_CFG U(0x00094000)
+#define LIN0_RX_IMCR_CFG U(0x00000002)
+
+struct bl_load_info *plat_get_bl_image_load_info(void)
+{
+ return get_bl_load_info_from_mem_params_desc();
+}
+
+struct bl_params *plat_get_next_bl_params(void)
+{
+ return get_next_bl_params_from_mem_params_desc();
+}
+
+void plat_flush_next_bl_params(void)
+{
+ flush_bl_params_desc();
+}
+
+void bl2_platform_setup(void)
+{
+}
+
+static void linflex_config_pinctrl(void)
+{
+ /* set PC09 - MSCR[41] - for UART0 TXD */
+ mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG);
+ /* set PC10 - MSCR[42] - for UART0 RXD */
+ mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG);
+ /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */
+ mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
+}
+
+void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ linflex_config_pinctrl();
+ console_s32g2_register();
+
+ plat_s32g2_io_setup();
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+}
+
diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl2_image_desc.c b/plat/nxp/s32/s32g274ardb2/plat_bl2_image_desc.c
new file mode 100644
index 0000000..1fc7794
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/plat_bl2_image_desc.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/desc_image_load.h>
+#include <plat/common/platform.h>
+
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+ .ep_info.pc = BL31_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+ .image_info.image_base = BL31_BASE,
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+ {
+ .image_id = BL33_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ NON_SECURE | EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, 0),
+ .image_info.image_max_size = BL33_LIMIT - BL33_BASE,
+ .image_info.image_base = BL33_BASE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c b/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c
new file mode 100644
index 0000000..03bf35c
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/plat_bl31_setup.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv3.h>
+#include <plat/common/platform.h>
+#include <plat_console.h>
+
+static entry_point_info_t bl33_image_ep_info;
+
+static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr);
+
+static uint32_t get_spsr_for_bl33_entry(void)
+{
+ unsigned long mode = MODE_EL1;
+ uint32_t spsr;
+
+ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+
+ return spsr;
+}
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ console_s32g2_register();
+
+ SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
+ bl33_image_ep_info.pc = BL33_BASE;
+ bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+}
+
+void bl31_plat_arch_setup(void)
+{
+}
+
+struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ return &bl33_image_ep_info;
+}
+
+void bl31_platform_setup(void)
+{
+ static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+ static gicv3_driver_data_t plat_gic_data = {
+ .gicd_base = PLAT_GICD_BASE,
+ .gicr_base = PLAT_GICR_BASE,
+ .rdistif_num = PLATFORM_CORE_COUNT,
+ .rdistif_base_addrs = rdistif_base_addrs,
+ .mpidr_to_core_pos = s32g2_mpidr_to_core_pos,
+ };
+
+ unsigned int pos = plat_my_core_pos();
+
+ gicv3_driver_init(&plat_gic_data);
+ gicv3_distif_init();
+ gicv3_rdistif_init(pos);
+ gicv3_cpuif_enable(pos);
+}
+
+static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr)
+{
+ int core;
+
+ core = plat_core_pos_by_mpidr(mpidr);
+ if (core < 0) {
+ return 0;
+ }
+
+ return (unsigned int)core;
+}
+
diff --git a/plat/nxp/s32/s32g274ardb2/plat_console.c b/plat/nxp/s32/s32g274ardb2/plat_console.c
new file mode 100644
index 0000000..27cae12
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/plat_console.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <linflex.h>
+#include <plat_console.h>
+#include <platform_def.h>
+
+void console_s32g2_register(void)
+{
+ static console_t s32g2_console;
+ int ret;
+
+ (void)memset(&s32g2_console, 0, sizeof(s32g2_console));
+
+ ret = console_linflex_register(UART_BASE, UART_CLOCK_HZ,
+ UART_BAUDRATE, &s32g2_console);
+ if (ret == 0) {
+ panic();
+ }
+
+ console_set_scope(&s32g2_console,
+ CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
+ CONSOLE_FLAG_TRANSLATE_CRLF);
+}
diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
new file mode 100644
index 0000000..193c884
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <platform_def.h>
+
+#define S32G_NCORE_CAIU0_BASE_ADDR UL(0x50400000)
+#define S32G_NCORE_CAIUTC_OFF U(0x0)
+#define S32G_NCORE_CAIUTC_ISOLEN_SHIFT U(1)
+
+.globl plat_crash_console_flush
+.globl plat_crash_console_init
+.globl plat_crash_console_putc
+.globl plat_is_my_cpu_primary
+.globl plat_my_core_pos
+.globl plat_reset_handler
+.globl plat_secondary_cold_boot_setup
+.globl platform_mem_init
+.globl s32g2_core_pos_by_mpidr
+
+/* int plat_crash_console_init(void); */
+func plat_crash_console_init
+ mov_imm x0, UART_BASE
+ mov_imm x1, UART_CLOCK_HZ
+ mov_imm x2, UART_BAUDRATE
+ b console_linflex_core_init
+endfunc plat_crash_console_init
+
+/* int plat_crash_console_putc(int); */
+func plat_crash_console_putc
+ mov_imm x1, UART_BASE
+ b console_linflex_core_putc
+ ret
+endfunc plat_crash_console_putc
+
+/* void plat_crash_console_flush(void); */
+func plat_crash_console_flush
+ ret
+endfunc plat_crash_console_flush
+
+/**
+ * unsigned int s32g2_core_pos_by_mpidr(u_register_t mpidr);
+ *
+ * In: x0 - MPIDR_EL1
+ * Out: x0
+ * Clobber list: x0, x1
+ */
+func s32g2_core_pos_by_mpidr
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ lsr x0, x0, #MPIDR_AFF1_SHIFT
+ add x0, x1, x0, lsl #PLATFORM_MPIDR_CPU_MASK_BITS
+ ret
+endfunc s32g2_core_pos_by_mpidr
+
+/**
+ * unsigned int plat_my_core_pos(void);
+ *
+ * Out: x0
+ * Clobber list: x0, x1, x8
+ */
+func plat_my_core_pos
+ mov x8, x30
+ mrs x0, mpidr_el1
+ bl s32g2_core_pos_by_mpidr
+ mov x30, x8
+ ret
+endfunc plat_my_core_pos
+
+/**
+ * unsigned int plat_is_my_cpu_primary(void);
+ *
+ * Clobber list: x0, x1, x7, x8
+ */
+func plat_is_my_cpu_primary
+ mov x7, x30
+ bl plat_my_core_pos
+ cmp x0, #PLATFORM_PRIMARY_CPU
+ cset x0, eq
+ mov x30, x7
+ ret
+endfunc plat_is_my_cpu_primary
+
+
+/**
+ * void plat_secondary_cold_boot_setup (void);
+ */
+func plat_secondary_cold_boot_setup
+ ret
+endfunc plat_secondary_cold_boot_setup
+
+/**
+ * void plat_reset_handler(void);
+ *
+ * Set the CAIUTC[IsolEn] bit for the primary A53 cluster.
+ * This is so cache invalidate operations from the early TF-A boot code
+ * won't cause Ncore to crash.
+ *
+ * Clobber list: x0, x1, x2
+ */
+func plat_reset_handler
+ mov x0, #S32G_NCORE_CAIU0_BASE_ADDR
+ ldr w1, [x0, #S32G_NCORE_CAIUTC_OFF]
+ movz w2, #1
+ lsl w2, w2, #S32G_NCORE_CAIUTC_ISOLEN_SHIFT
+ orr w1, w1, w2
+ str w1, [x0, #S32G_NCORE_CAIUTC_OFF]
+ ret
+endfunc plat_reset_handler
+
+/* void platform_mem_init(void); */
+func platform_mem_init
+ mov x10, x30
+ mov x0, #BL31_BASE
+ mov x1, #(BL31_LIMIT & 0xFFFFU)
+ movk x1, #(BL31_LIMIT >> 16), lsl #16
+ sub x1, x1, x0
+ bl zeromem
+ mov x0, #BL33_BASE
+ mov x1, #(BL33_LIMIT & 0xFFFFU)
+ movk x1, #(BL33_LIMIT >> 16), lsl #16
+ sub x1, x1, x0
+ bl zeromem
+ mov x30, x10
+ ret
+endfunc platform_mem_init
+
diff --git a/plat/nxp/s32/s32g274ardb2/plat_io_storage.c b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
new file mode 100644
index 0000000..db6bcc5
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/plat_io_storage.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_fip.h>
+#include <drivers/io/io_memmap.h>
+#include <plat/common/platform.h>
+#include <tools_share/firmware_image_package.h>
+
+#include <plat_io_storage.h>
+
+struct plat_io_policy {
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
+};
+
+static int open_memmap(const uintptr_t spec);
+static int open_fip(const uintptr_t spec);
+
+static uintptr_t fip_dev_handle;
+
+static uintptr_t memmap_dev_handle;
+
+static int open_memmap(const uintptr_t spec)
+{
+ uintptr_t temp_handle = 0U;
+ int result;
+
+ result = io_dev_init(memmap_dev_handle, (uintptr_t)0);
+ if (result != 0) {
+ return result;
+ }
+
+ result = io_open(memmap_dev_handle, spec, &temp_handle);
+ if (result == 0) {
+ (void)io_close(temp_handle);
+ }
+
+ return result;
+}
+
+static int open_fip(const uintptr_t spec)
+{
+ uintptr_t temp_handle = 0U;
+ int result;
+
+ /* See if a Firmware Image Package is available */
+ result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
+ if (result != 0) {
+ return result;
+ }
+
+ result = io_open(fip_dev_handle, spec, &temp_handle);
+ if (result == 0) {
+ (void)io_close(temp_handle);
+ }
+
+ return result;
+}
+
+void plat_s32g2_io_setup(void)
+{
+ static const io_dev_connector_t *memmap_dev_con;
+ static const io_dev_connector_t *fip_dev_con;
+
+ int result __unused;
+
+ result = register_io_dev_memmap(&memmap_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(memmap_dev_con, (uintptr_t)0,
+ &memmap_dev_handle);
+ assert(result == 0);
+
+ result = register_io_dev_fip(&fip_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(fip_dev_con, (uintptr_t)0,
+ &fip_dev_handle);
+ assert(result == 0);
+}
+
+int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec)
+{
+ static const io_block_spec_t fip_block_spec = {
+ .offset = S32G_FIP_BASE,
+ .length = S32G_FIP_SIZE,
+ };
+
+ static const io_uuid_spec_t bl31_uuid_spec = {
+ .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
+ };
+
+ static const io_uuid_spec_t bl33_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
+ };
+
+ static const struct plat_io_policy policies[BL33_IMAGE_ID + 1] = {
+ [FIP_IMAGE_ID] = {
+ .dev_handle = &memmap_dev_handle,
+ .image_spec = (uintptr_t)&fip_block_spec,
+ .check = open_memmap,
+ },
+ [BL31_IMAGE_ID] = {
+ .dev_handle = &fip_dev_handle,
+ .image_spec = (uintptr_t)&bl31_uuid_spec,
+ .check = open_fip,
+ },
+ [BL33_IMAGE_ID] = {
+ .dev_handle = &fip_dev_handle,
+ .image_spec = (uintptr_t)&bl33_uuid_spec,
+ .check = open_fip,
+ },
+ };
+ const struct plat_io_policy *policy;
+ int result;
+
+ assert(image_id < ARRAY_SIZE(policies));
+
+ policy = &policies[image_id];
+ result = policy->check(policy->image_spec);
+ assert(result == 0);
+
+ *image_spec = policy->image_spec;
+ *dev_handle = *policy->dev_handle;
+
+ return result;
+}
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
new file mode 100644
index 0000000..ee1507e
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -0,0 +1,65 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_DRIVERS_PATH := drivers/nxp
+PLAT_COMMON_PATH := plat/nxp/common
+PLAT_S32G274ARDB2 := plat/nxp/s32/s32g274ardb2
+
+CONSOLE := LINFLEX
+
+include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+
+PLAT_INCLUDES = \
+ -I${PLAT_S32G274ARDB2}/include
+
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+COLD_BOOT_SINGLE_CPU := 0
+
+ENABLE_SVE_FOR_NS := 0
+
+RESET_TO_BL2 := 1
+
+INIT_UNUSED_NS_EL2 := 1
+
+ERRATA_A53_855873 := 1
+ERRATA_A53_836870 := 1
+ERRATA_A53_1530924 := 1
+ERRATA_SPECULATIVE_AT := 1
+
+# Selecting Drivers for SoC
+$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+
+include ${PLAT_DRIVERS_PATH}/drivers.mk
+
+
+BL_COMMON_SOURCES += \
+ ${PLAT_S32G274ARDB2}/plat_console.c \
+ ${PLAT_S32G274ARDB2}/plat_helpers.S \
+
+BL2_SOURCES += \
+ ${BL_COMMON_SOURCES} \
+ ${PLAT_S32G274ARDB2}/plat_bl2_el3_setup.c \
+ ${PLAT_S32G274ARDB2}/plat_bl2_image_desc.c \
+ ${PLAT_S32G274ARDB2}/plat_io_storage.c \
+ common/desc_image_load.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ lib/cpus/aarch64/cortex_a53.S \
+
+BL31_SOURCES += \
+ ${GICV3_SOURCES} \
+ ${PLAT_S32G274ARDB2}/plat_bl31_setup.c \
+ ${PLAT_S32G274ARDB2}/s32g2_psci.c \
+ ${PLAT_S32G274ARDB2}/s32g2_soc.c \
+ ${XLAT_TABLES_LIB_SRCS} \
+ lib/cpus/aarch64/cortex_a53.S \
+ plat/common/plat_gicv3.c \
+ plat/common/plat_psci_common.c \
diff --git a/plat/nxp/s32/s32g274ardb2/s32g2_psci.c b/plat/nxp/s32/s32g274ardb2/s32g2_psci.c
new file mode 100644
index 0000000..2d02d94
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/s32g2_psci.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ static const plat_psci_ops_t s32g2_psci_ops = {
+ };
+
+ *psci_ops = &s32g2_psci_ops;
+
+ return 0;
+}
+
diff --git a/plat/nxp/s32/s32g274ardb2/s32g2_soc.c b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
new file mode 100644
index 0000000..0001352
--- /dev/null
+++ b/plat/nxp/s32/s32g274ardb2/s32g2_soc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+#include <plat_helpers.h>
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ static const unsigned char s32g_power_domain_tree_desc[] = {
+ PLATFORM_SYSTEM_COUNT,
+ PLATFORM_CLUSTER_COUNT,
+ PLATFORM_CORE_COUNT / U(2),
+ PLATFORM_CORE_COUNT / U(2),
+ };
+
+ return s32g_power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id, core_id;
+ u_register_t mpidr_priv = mpidr;
+
+ mpidr_priv &= MPIDR_AFFINITY_MASK;
+
+ if ((mpidr_priv & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) {
+ return -1;
+ }
+
+ cluster_id = MPIDR_AFFLVL1_VAL(mpidr_priv);
+ cpu_id = MPIDR_AFFLVL0_VAL(mpidr_priv);
+
+ if ((cluster_id >= PLATFORM_CLUSTER_COUNT) ||
+ (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)) {
+ return -1;
+ }
+
+ core_id = s32g2_core_pos_by_mpidr(mpidr_priv);
+ if (core_id >= PLATFORM_CORE_COUNT) {
+ return -1;
+ }
+
+ return (int)core_id;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return COUNTER_FREQUENCY;
+}
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index cd83a98..60acb25 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -217,7 +217,7 @@
#if ENABLE_RME
/* BL2 runs in EL3 when RME enabled. */
- assert(get_armv9_2_feat_rme_support() != 0U);
+ assert(is_feat_rme_present());
enable_mmu_el3(0);
/* Initialise and enable granule protection after MMU. */
diff --git a/plat/qemu/common/qemu_plat_attest_token.c b/plat/qemu/common/qemu_plat_attest_token.c
index cf3376d..f7d7e90 100644
--- a/plat/qemu/common/qemu_plat_attest_token.c
+++ b/plat/qemu/common/qemu_plat_attest_token.c
@@ -98,7 +98,7 @@
/*
* Get the hardcoded platform attestation token as QEMU does not support
- * RSS.
+ * RSE.
*/
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
uintptr_t hash, size_t hash_size)
diff --git a/plat/qemu/common/qemu_realm_attest_key.c b/plat/qemu/common/qemu_realm_attest_key.c
index abd569b..7da04d1 100644
--- a/plat/qemu/common/qemu_realm_attest_key.c
+++ b/plat/qemu/common/qemu_realm_attest_key.c
@@ -19,7 +19,7 @@
/*
* Get the hardcoded delegated realm attestation key as QEMU
- * does not support RSS.
+ * does not support RSE.
*/
int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
unsigned int type)
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 5718478..8e3f52e 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -368,9 +368,13 @@
@echo "clean bl2 and bl31 srecs"
rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
+$(SREC_PATH)/bl2.srec: $(BL2_ELF_SRC)
+ @echo "generating srec: $(SREC_PATH)/bl2.srec"
+ $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL2_ELF_SRC) $(SREC_PATH)/bl2.srec
+
+$(SREC_PATH)/bl31.srec: $(BL31_ELF_SRC)
+ @echo "generating srec: $(SREC_PATH)/bl31.srec"
+ $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL31_ELF_SRC) $(SREC_PATH)/bl31.srec
+
.PHONY: rcar_srecord
-rcar_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC)
- @echo "generating srec: ${SREC_PATH}/bl2.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec
- @echo "generating srec: ${SREC_PATH}/bl31.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec
+rcar_srecord: $(SREC_PATH)/bl2.srec $(SREC_PATH)/bl31.srec
diff --git a/plat/renesas/rzg/platform.mk b/plat/renesas/rzg/platform.mk
index 89ca227..354eada 100644
--- a/plat/renesas/rzg/platform.mk
+++ b/plat/renesas/rzg/platform.mk
@@ -266,9 +266,13 @@
@echo "clean bl2 and bl31 srecs"
rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
+$(SREC_PATH)/bl2.srec: $(BL2_ELF_SRC)
+ @echo "generating srec: $(SREC_PATH)/bl2.srec"
+ $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL2_ELF_SRC) $(SREC_PATH)/bl2.srec
+
+$(SREC_PATH)/bl31.srec: $(BL31_ELF_SRC)
+ @echo "generating srec: $(SREC_PATH)/bl31.srec"
+ $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL31_ELF_SRC) $(SREC_PATH)/bl31.srec
+
.PHONY: rzg_srecord
-rzg_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC)
- @echo "generating srec: ${SREC_PATH}/bl2.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec
- @echo "generating srec: ${SREC_PATH}/bl31.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec
+rzg_srecord: $(SREC_PATH)/bl2.srec $(SREC_PATH)/bl31.srec
diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c
index 967437b..e46d877 100644
--- a/plat/socionext/synquacer/sq_bl31_setup.c
+++ b/plat/socionext/synquacer/sq_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index b9b62c0..7ef7665 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk
@@ -6,7 +6,6 @@
RESET_TO_BL2 := 1
-STM32MP_EARLY_CONSOLE ?= 0
STM32MP_RECONFIGURE_CONSOLE ?= 0
STM32MP_UART_BAUDRATE ?= 115200
@@ -82,7 +81,6 @@
$(eval $(call assert_booleans,\
$(sort \
PLAT_XLAT_TABLES_DYNAMIC \
- STM32MP_EARLY_CONSOLE \
STM32MP_EMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
@@ -104,7 +102,6 @@
$(sort \
PLAT_XLAT_TABLES_DYNAMIC \
STM32_TF_VERSION \
- STM32MP_EARLY_CONSOLE \
STM32MP_EMMC \
STM32MP_EMMC_BOOT \
STM32MP_RAW_NAND \
diff --git a/plat/st/common/include/plat_def_fip_uuid.h b/plat/st/common/include/plat_def_fip_uuid.h
new file mode 100644
index 0000000..096fd95
--- /dev/null
+++ b/plat/st/common/include/plat_def_fip_uuid.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DEF_FIP_UUID_H
+#define PLAT_DEF_FIP_UUID_H
+
+#define UUID_DDR_FW \
+ {{0xb1, 0x12, 0x49, 0xbe}, {0x92, 0xdd}, {0x4b, 0x10}, 0x86, 0x7c, \
+ {0x2c, 0x6a, 0x4b, 0x47, 0xa7, 0xfb} }
+
+#define UUID_STM32MP_CONFIG_CERT \
+ {{0x50, 0x1d, 0x8d, 0xd2}, {0x8b, 0xce}, {0x49, 0xa5}, 0x84, 0xeb, \
+ {0x55, 0x9a, 0x9f, 0x2e, 0xae, 0xaf} }
+#endif /* PLAT_DEF_FIP_UUID_H */
+
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index a1ed1ad..41b86ae 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -77,14 +77,6 @@
/* Setup the UART console */
int stm32mp_uart_console_setup(void);
-#if STM32MP_EARLY_CONSOLE
-void stm32mp_setup_early_console(void);
-#else
-static inline void stm32mp_setup_early_console(void)
-{
-}
-#endif
-
/*
* Platform util functions for the GPIO driver
* @bank: Target GPIO bank ID as per DT bindings
diff --git a/plat/st/common/include/stm32mp_mbedtls_config-3.h b/plat/st/common/include/stm32mp_mbedtls_config-3.h
index a812671..2dbf068 100644
--- a/plat/st/common/include/stm32mp_mbedtls_config-3.h
+++ b/plat/st/common/include/stm32mp_mbedtls_config-3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -102,7 +102,6 @@
#ifndef __ASSEMBLER__
/* System headers required to build mbed TLS with the current configuration */
#include <stdlib.h>
-#include <mbedtls/check_config.h>
#endif
/*
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index a1d1c49..6f36011 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -269,8 +269,8 @@
return 0;
}
-#if STM32MP_EARLY_CONSOLE
-void stm32mp_setup_early_console(void)
+#if EARLY_CONSOLE
+void plat_setup_early_console(void)
{
#if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE
plat_crash_console_init();
@@ -278,7 +278,7 @@
set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ);
NOTICE("Early console setup\n");
}
-#endif /* STM32MP_EARLY_CONSOLE */
+#endif /* EARLY_CONSOLE */
/*****************************************************************************
* plat_is_smccc_feature_available() - This function checks whether SMCCC
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 798c033..bd3903d 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -142,8 +142,6 @@
u_register_t arg2 __unused,
u_register_t arg3 __unused)
{
- stm32mp_setup_early_console();
-
stm32mp_save_boot_ctx_address(arg0);
}
diff --git a/plat/st/stm32mp1/include/plat_def_fip_uuid.h b/plat/st/stm32mp1/include/plat_def_fip_uuid.h
deleted file mode 100644
index e5fbc2d..0000000
--- a/plat/st/stm32mp1/include/plat_def_fip_uuid.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_DEF_FIP_UUID_H
-#define PLAT_DEF_FIP_UUID_H
-
-#define UUID_STM32MP_CONFIG_CERT \
- {{0x50, 0x1d, 0x8d, 0xd2}, {0x8b, 0xce}, {0x49, 0xa5}, 0x84, 0xeb, \
- {0x55, 0x9a, 0x9f, 0x2e, 0xae, 0xaf} }
-#endif /* PLAT_DEF_FIP_UUID_H */
-
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index 245b2d3..7bfe6ba 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -116,8 +116,6 @@
bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
uintptr_t dt_addr = arg1;
- stm32mp_setup_early_console();
-
/* Imprecise aborts can be masked in NonSecure */
write_scr(read_scr() | SCR_AW_BIT);
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index a7cce62..724209a 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -18,7 +18,6 @@
u_register_t arg2 __unused,
u_register_t arg3 __unused)
{
- stm32mp_setup_early_console();
}
void bl2_platform_setup(void)
@@ -28,7 +27,7 @@
void bl2_el3_plat_arch_setup(void)
{
if (stm32_otp_probe() != 0U) {
- ERROR("OTP probe failed\n");
+ EARLY_ERROR("OTP probe failed\n");
panic();
}
}
diff --git a/plat/xilinx/common/include/pm_client.h b/plat/xilinx/common/include/pm_client.h
index a87923f..e9c36c3 100644
--- a/plat/xilinx/common/include/pm_client.h
+++ b/plat/xilinx/common/include/pm_client.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,7 +31,6 @@
#if defined(PLAT_zynqmp)
enum pm_ret_status pm_set_suspend_mode(uint32_t mode);
-const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid);
#endif /* PLAT_zynqmp */
#endif /* PM_CLIENT_H */
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index d19a263..08c0205 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
@@ -206,8 +206,6 @@
if (rc != 0) {
panic();
}
-
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/*
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 45b1f1c..4cf1ed1 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,6 +36,9 @@
}
proc = pm_get_proc((uint32_t)cpu_id);
+ if (proc == NULL) {
+ return PSCI_E_INTERN_FAIL;
+ }
/* Send request to PMC to wake up selected ACPU core */
(void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
@@ -59,6 +62,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -96,6 +103,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -190,6 +201,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 614d6d2..b38f394 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
@@ -231,8 +231,6 @@
if (rc != 0) {
panic();
}
-
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/*
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index 94cb7f5..e5a5235 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,7 +38,7 @@
}
proc = pm_get_proc(cpu_id);
- if (!proc) {
+ if (proc == NULL) {
return PSCI_E_INTERN_FAIL;
}
@@ -63,6 +63,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -143,6 +147,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -186,6 +194,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index baf6717..0a34f72 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -190,8 +190,6 @@
#endif
custom_runtime_setup();
-
- console_switch_state(CONSOLE_FLAG_RUNTIME);
}
/*
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index c6c6c4b..1e7df05 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,7 +42,11 @@
if (cpu_id == -1) {
return PSCI_E_INTERN_FAIL;
}
+
proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return PSCI_E_INTERN_FAIL;
+ }
/* Check the APU proc status before wakeup */
ret = pm_get_node_status(proc->node_id, buff);
@@ -64,6 +68,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -89,6 +97,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
@@ -121,6 +133,10 @@
uint32_t cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
+ if (proc == NULL) {
+ return;
+ }
+
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index 4afa01d..9d0e2c4 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -245,23 +245,6 @@
}
/**
- * pm_get_proc_by_node() - returns pointer to the proc structure.
- * @nid: node id of the processor.
- *
- * Return: pointer to a proc structure if proc is found, otherwise NULL.
- *
- */
-const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid)
-{
- for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
- if (nid == pm_procs_all[i].node_id) {
- return &pm_procs_all[i];
- }
- }
- return NULL;
-}
-
-/**
* pm_get_cpuid() - get the local cpu ID for a global node ID.
* @nid: node id of the processor.
*
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 6b42055..3d546b3 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -272,6 +272,11 @@
uint32_t cpuid = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpuid);
+ if (proc == NULL) {
+ WARN("Failed to get proc %d\n", cpuid);
+ return PM_RET_ERROR_INTERNAL;
+ }
+
/*
* Do client specific suspend operations
* (e.g. set powerdown request bit)
diff --git a/pyproject.toml b/pyproject.toml
index 0fe2383..7814497 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
[tool.poetry]
name = "trusted-firmware-a"
-version = "2.10.0"
+version = "2.11.0"
description = "Trusted Firmware-A (TF-A) Python dependencies."
authors = ["Arm Ltd."]
license = "BSD-3-Clause"
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c
index 57d211e..5456164 100644
--- a/services/arm_arch_svc/arm_arch_svc_setup.c
+++ b/services/arm_arch_svc/arm_arch_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,7 +54,7 @@
* If architectural SSBS is available on this PE, no firmware
* mitigation via SMCCC_ARCH_WORKAROUND_2 is required.
*/
- if (ssbs != SSBS_UNAVAILABLE)
+ if (ssbs != SSBS_NOT_IMPLEMENTED)
return 1;
/*
diff --git a/services/el3/ven_el3_svc.c b/services/el3/ven_el3_svc.c
new file mode 100644
index 0000000..32a3dc2
--- /dev/null
+++ b/services/el3/ven_el3_svc.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/debugfs.h>
+#include <lib/pmf/pmf.h>
+#include <services/ven_el3_svc.h>
+#include <tools_share/uuid.h>
+
+/* vendor-specific EL3 UUID */
+DEFINE_SVC_UUID2(ven_el3_svc_uid,
+ 0xb6011dca, 0x57c4, 0x407e, 0x83, 0xf0,
+ 0xa7, 0xed, 0xda, 0xf0, 0xdf, 0x6c);
+
+static int ven_el3_svc_setup(void)
+{
+#if USE_DEBUGFS
+ if (debugfs_smc_setup() != 0) {
+ return 1;
+ }
+#endif /* USE_DEBUGFS */
+
+#if ENABLE_PMF
+ if (pmf_setup() != 0) {
+ return 1;
+ }
+#endif /* ENABLE_PMF */
+
+ return 0;
+}
+
+/*
+ * This function handles Arm defined vendor-specific EL3 Service Calls.
+ */
+static uintptr_t ven_el3_svc_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+#if USE_DEBUGFS
+ /*
+ * Dispatch debugfs calls to debugfs SMC handler and return its
+ * return value.
+ */
+ if (is_debugfs_fid(smc_fid)) {
+ return debugfs_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+ }
+#endif /* USE_DEBUGFS */
+
+#if ENABLE_PMF
+
+ /*
+ * Dispatch PMF calls to PMF SMC handler and return its return
+ * value
+ */
+ if (is_pmf_fid(smc_fid)) {
+ return pmf_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+ }
+
+#endif /* ENABLE_PMF */
+
+ switch (smc_fid) {
+ case VEN_EL3_SVC_UID:
+ /* Return UID to the caller */
+ SMC_UUID_RET(handle, ven_el3_svc_uid);
+ break;
+ case VEN_EL3_SVC_VERSION:
+ SMC_RET2(handle, VEN_EL3_SVC_VERSION_MAJOR, VEN_EL3_SVC_VERSION_MINOR);
+ break;
+ default:
+ WARN("Unimplemented vendor-specific EL3 Service call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ break;
+ }
+}
+
+/* Define a runtime service descriptor for fast SMC calls */
+DECLARE_RT_SVC(
+ ven_el3_svc,
+ OEN_VEN_EL3_START,
+ OEN_VEN_EL3_END,
+ SMC_TYPE_FAST,
+ ven_el3_svc_setup,
+ ven_el3_svc_handler
+);
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 033e868..6ccb003 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -202,7 +202,7 @@
int rc;
/* Make sure RME is supported. */
- assert(get_armv9_2_feat_rme_support() != 0U);
+ assert(is_feat_rme_present());
rmm_ep_info = bl31_plat_get_next_image_ep_info(REALM);
if (rmm_ep_info == NULL) {
diff --git a/services/std_svc/rmmd/trp/trp_main.c b/services/std_svc/rmmd/trp/trp_main.c
index 33f2fb0..b75483c 100644
--- a/services/std_svc/rmmd/trp/trp_main.c
+++ b/services/std_svc/rmmd/trp/trp_main.c
@@ -1,9 +1,10 @@
/*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <common/build_message.h>
#include <common/debug.h>
#include <plat/common/platform.h>
#include <services/rmm_core_manifest.h>
@@ -86,7 +87,7 @@
/* Main function for TRP */
void trp_main(void)
{
- NOTICE("TRP: %s\n", version_string);
+ NOTICE("TRP: %s\n", build_version_string);
NOTICE("TRP: %s\n", build_message);
NOTICE("TRP: Supported RMM-EL3 Interface ABI: v.%u.%u\n",
TRP_RMM_EL3_ABI_VERS_MAJOR, TRP_RMM_EL3_ABI_VERS_MINOR);
diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index d0efab8..56cb21a 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json
@@ -1,6 +1,6 @@
{
"name": "conventional-changelog-tf-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"license": "BSD-3-Clause",
"private": true,
"main": "index.js",
diff --git a/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
index 903310b..792593f 100644
--- a/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
+++ b/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
@@ -13,44 +13,44 @@
toc_entry_t plat_def_toc_entries[] = {
{
- .name = "RSS Firmware BL1_2 image",
- .uuid = UUID_RSS_FIRMWARE_BL1_2,
- .cmdline_name = "rss-bl1_2"
+ .name = "RSE Firmware BL1_2 image",
+ .uuid = UUID_RSE_FIRMWARE_BL1_2,
+ .cmdline_name = "rse-bl1_2"
},
{
- .name = "RSS Firmware BL2 image",
- .uuid = UUID_RSS_FIRMWARE_BL2,
- .cmdline_name = "rss-bl2"
+ .name = "RSE Firmware BL2 image",
+ .uuid = UUID_RSE_FIRMWARE_BL2,
+ .cmdline_name = "rse-bl2"
},
{
- .name = "RSS Firmware SCP BL1 image",
- .uuid = UUID_RSS_FIRMWARE_SCP_BL1,
- .cmdline_name = "rss-scp-bl1"
+ .name = "RSE Firmware SCP BL1 image",
+ .uuid = UUID_RSE_FIRMWARE_SCP_BL1,
+ .cmdline_name = "rse-scp-bl1"
},
{
- .name = "RSS Firmware AP BL1 image",
- .uuid = UUID_RSS_FIRMWARE_AP_BL1,
- .cmdline_name = "rss-ap-bl1"
+ .name = "RSE Firmware AP BL1 image",
+ .uuid = UUID_RSE_FIRMWARE_AP_BL1,
+ .cmdline_name = "rse-ap-bl1"
},
{
- .name = "RSS Firmware non-secure image",
- .uuid = UUID_RSS_FIRMWARE_NS,
- .cmdline_name = "rss-ns"
+ .name = "RSE Firmware non-secure image",
+ .uuid = UUID_RSE_FIRMWARE_NS,
+ .cmdline_name = "rse-ns"
},
{
- .name = "RSS Firmware secure image",
- .uuid = UUID_RSS_FIRMWARE_S,
- .cmdline_name = "rss-s"
+ .name = "RSE Firmware secure image",
+ .uuid = UUID_RSE_FIRMWARE_S,
+ .cmdline_name = "rse-s"
},
{
- .name = "RSS Firmware non-secure SIC tables",
- .uuid = UUID_RSS_SIC_TABLES_NS,
- .cmdline_name = "rss-sic-tables-ns"
+ .name = "RSE Firmware non-secure SIC tables",
+ .uuid = UUID_RSE_SIC_TABLES_NS,
+ .cmdline_name = "rse-sic-tables-ns"
},
{
- .name = "RSS Firmware secure SIC tables",
- .uuid = UUID_RSS_SIC_TABLES_S,
- .cmdline_name = "rss-sic-tables-s"
+ .name = "RSE Firmware secure SIC tables",
+ .uuid = UUID_RSE_SIC_TABLES_S,
+ .cmdline_name = "rse-sic-tables-s"
},
{
diff --git a/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/st/plat_def_uuid_config.c
similarity index 71%
rename from tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
rename to tools/fiptool/plat_fiptool/st/plat_def_uuid_config.c
index 4df4144..8d3329f 100644
--- a/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
+++ b/tools/fiptool/plat_fiptool/st/plat_def_uuid_config.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,11 @@
toc_entry_t plat_def_toc_entries[] = {
{
+ .name = "DDR_FW",
+ .uuid = UUID_DDR_FW,
+ .cmdline_name = "ddr-fw"
+ },
+ {
.name = "STM32MP CONFIG CERT",
.uuid = UUID_STM32MP_CONFIG_CERT,
.cmdline_name = "stm32mp-cfg-cert"
diff --git a/tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk b/tools/fiptool/plat_fiptool/st/plat_fiptool.mk
similarity index 71%
rename from tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
rename to tools/fiptool/plat_fiptool/st/plat_fiptool.mk
index 0d69dbd..494715c 100644
--- a/tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/st/plat_fiptool.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved
+# Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,14 +9,14 @@
# in the plat_def_toc_entries[].
PLAT_DEF_UUID_FILE_NAME := plat_def_uuid_config
-INCLUDE_PATHS += -I${PLAT_DIR}/include -I./
+INCLUDE_PATHS += -I../../plat/st/common/include -I./
PLAT_DEF_UUID := yes
ifeq (${PLAT_DEF_UUID},yes)
HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-${PLAT_DEF_UUID_FILE_NAME}.o: plat_fiptool/st/stm32mp1/${PLAT_DEF_UUID_FILE_NAME}.c
+${PLAT_DEF_UUID_FILE_NAME}.o: plat_fiptool/st/${PLAT_DEF_UUID_FILE_NAME}.c
$(host-cc) -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
PLAT_OBJECTS += ${PLAT_DEF_UUID_FILE_NAME}.o
