fix(board): update spi_id max for sgi multichip platforms
According to GIC-600 TRM, 960 SPIs could be supported on a platform.
However, with the current configuration, platforms such as RD-V1-MC and
RD-N1-Edge Dual-Chip utilize a much smaller range. With commit
'a02a45dfe' gic600 driver is updated to get the max SPI id from the
GIC-600 and probe for the corresponding GIC instance for each SPI id.
Since RD-V1-MC and RD-N1-Edge Dual-Chip supports wider range, increase
SPI range for the chip 0 to max SPI range supported.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia8c02c6d999033af33d8e7a0bedc7b73c6552ab4
diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
index de01902..21d8ee0 100644
--- a/plat/arm/board/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -51,4 +51,7 @@
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x300C0000)
+#define RDN1E1_CHIP0_SPI_START U(32)
+#define RDN1E1_CHIP0_SPI_END U(991)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdn1edge/rdn1edge_plat.c b/plat/arm/board/rdn1edge/rdn1edge_plat.c
index 6da8bcd..9a87535 100644
--- a/plat/arm/board/rdn1edge/rdn1edge_plat.c
+++ b/plat/arm/board/rdn1edge/rdn1edge_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,7 +27,8 @@
(PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
},
.spi_ids = {
- {PLAT_ARM_GICD_BASE, 32, 255},
+ {PLAT_ARM_GICD_BASE, RDN1E1_CHIP0_SPI_START,
+ RDN1E1_CHIP0_SPI_END},
{0, 0, 0}
}
};
diff --git a/plat/arm/board/rdv1mc/include/platform_def.h b/plat/arm/board/rdv1mc/include/platform_def.h
index 3670904..cd13d6e 100644
--- a/plat/arm/board/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/rdv1mc/include/platform_def.h
@@ -60,4 +60,7 @@
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
#define PLAT_ARM_GICR_BASE UL(0x30140000)
+#define RDV1MC_CHIP0_SPI_START U(32)
+#define RDV1MC_CHIP0_SPI_END U(991)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdv1mc/rdv1mc_plat.c b/plat/arm/board/rdv1mc/rdv1mc_plat.c
index e4469dc..5ef9778 100644
--- a/plat/arm/board/rdv1mc/rdv1mc_plat.c
+++ b/plat/arm/board/rdv1mc/rdv1mc_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,7 +43,8 @@
#endif
},
.spi_ids = {
- {PLAT_ARM_GICD_BASE, 32, 255},
+ {PLAT_ARM_GICD_BASE, RDV1MC_CHIP0_SPI_START,
+ RDV1MC_CHIP0_SPI_END},
{0, 0, 0},
#if (CSS_SGI_CHIP_COUNT > 2)
{0, 0, 0},